Fixed sound from rt5651 on OrangePi 4 (#1870)
This commit is contained in:
Piotr Szczepanik
GitHub
parent
dd50c432f8
commit
e14a61c229
@ -15,7 +15,7 @@ new file mode 100644
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index 00000000..17010305
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/rk3399-orangepi-4.dts
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@@ -0,0 +1,1121 @@
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@@ -0,0 +1,1130 @@
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+/*
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+ * SPDX-License-Identifier: (GPL-2.0+ or MIT)
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+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
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@ -813,11 +813,14 @@ index 00000000..17010305
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+};
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+
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+&i2s1 {
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+ status = "okay";
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+ rockchip,i2s-broken-burst-len;
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+ rockchip,playback-channels = <8>;
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+ rockchip,capture-channels = <8>;
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+ assigned-clocks = <&cru SCLK_I2SOUT_SRC>;
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+ assigned-clock-parents = <&cru SCLK_I2S1_8CH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2s_8ch_mclk>,<&i2s1_2ch_bus>;
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+ rockchip,playback-channels = <2>;
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+ rockchip,capture-channels = <2>;
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+ #sound-dai-cells = <0>;
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+ status = "okay";
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+};
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+/*
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+&i2s0 {
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@ -1018,6 +1021,12 @@ index 00000000..17010305
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+ /delete-node/ hdmi-i2c-xfer;
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+ };
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+
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+ i2s1 {
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+ i2s_8ch_mclk: i2s-8ch-mclk {
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+ rockchip,pins = <4 RK_PA0 RK_FUNC_1 &pcfg_pull_none>;
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+ };
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+ };
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+
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+ pmic {
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+ pmic_int_l: pmic-int-l {
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+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
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@ -0,0 +1,60 @@
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diff --git a/sound/soc/codecs/rt5651.c b/sound/soc/codecs/rt5651.c
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index c506c9305..41a08b320 100644
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--- a/sound/soc/codecs/rt5651.c
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+++ b/sound/soc/codecs/rt5651.c
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@@ -24,6 +24,7 @@
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#include <sound/initval.h>
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#include <sound/tlv.h>
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#include <sound/jack.h>
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+#include <linux/clk.h>
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#include "rl6231.h"
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#include "rt5651.h"
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@@ -1511,6 +1512,7 @@ static int rt5651_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
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static int rt5651_set_bias_level(struct snd_soc_component *component,
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enum snd_soc_bias_level level)
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{
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+ struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
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switch (level) {
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case SND_SOC_BIAS_PREPARE:
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if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) {
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@@ -1518,6 +1520,13 @@ static int rt5651_set_bias_level(struct snd_soc_component *component,
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snd_soc_component_update_bits(component, RT5651_D_MISC,
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0xc00, 0xc00);
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}
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+ if (!IS_ERR(rt5651->mclk)){
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+ if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
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+ clk_disable_unprepare(rt5651->mclk);
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+ } else {
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+ clk_prepare_enable(rt5651->mclk);
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+ }
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+ }
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break;
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case SND_SOC_BIAS_STANDBY:
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if (SND_SOC_BIAS_OFF == snd_soc_component_get_bias_level(component)) {
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@@ -2059,6 +2068,13 @@ static int rt5651_probe(struct snd_soc_component *component)
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{
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struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
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+ /* Check if MCLK provided */
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+ rt5651->mclk = devm_clk_get(component->dev, "mclk");
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+ if (PTR_ERR(rt5651->mclk) == -EPROBE_DEFER){
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+ dev_err(component->dev, "unable to get mclk\n");
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+ return -EPROBE_DEFER;
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+ }
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+
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rt5651->component = component;
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snd_soc_component_update_bits(component, RT5651_PWR_ANLG1,
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diff --git a/sound/soc/codecs/rt5651.h b/sound/soc/codecs/rt5651.h
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index 20c33a3ec..17524fa9f 100644
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--- a/sound/soc/codecs/rt5651.h
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+++ b/sound/soc/codecs/rt5651.h
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@@ -2097,6 +2097,7 @@ struct rt5651_priv {
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int dmic_en;
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bool hp_mute;
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+ struct clk *mclk;
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};
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#endif /* __RT5651_H__ */
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@ -0,0 +1,25 @@
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diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
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index ce1d2446f..38447441b 100644
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--- a/drivers/clk/rockchip/clk-rk3399.c
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+++ b/drivers/clk/rockchip/clk-rk3399.c
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@@ -620,7 +620,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
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GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
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RK3399_CLKGATE_CON(8), 11, GFLAGS),
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- MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT,
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+ MUX(SCLK_I2SOUT_SRC, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT,
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RK3399_CLKSEL_CON(31), 0, 2, MFLAGS),
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COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT,
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RK3399_CLKSEL_CON(31), 2, 1, MFLAGS,
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diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h
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index 44e0a319f..b7b07dfda 100644
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--- a/include/dt-bindings/clock/rk3399-cru.h
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+++ b/include/dt-bindings/clock/rk3399-cru.h
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@@ -19,6 +19,7 @@
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#define ARMCLKB 9
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/* sclk gates (special clocks) */
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+#define SCLK_I2SOUT_SRC 64
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#define SCLK_I2C1 65
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#define SCLK_I2C2 66
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#define SCLK_I2C3 67
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@ -15,7 +15,7 @@ new file mode 100644
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index 00000000..17010305
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/rk3399-orangepi-4.dts
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@@ -0,0 +1,1121 @@
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@@ -0,0 +1,1130 @@
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+/*
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+ * SPDX-License-Identifier: (GPL-2.0+ or MIT)
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+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
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@ -813,11 +813,14 @@ index 00000000..17010305
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+};
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+
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+&i2s1 {
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+ status = "okay";
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+ rockchip,i2s-broken-burst-len;
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+ rockchip,playback-channels = <8>;
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+ rockchip,capture-channels = <8>;
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+ assigned-clocks = <&cru SCLK_I2SOUT_SRC>;
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+ assigned-clock-parents = <&cru SCLK_I2S1_8CH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2s_8ch_mclk>,<&i2s1_2ch_bus>;
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+ rockchip,playback-channels = <2>;
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+ rockchip,capture-channels = <2>;
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+ #sound-dai-cells = <0>;
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+ status = "okay";
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+};
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+/*
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+&i2s0 {
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@ -1018,6 +1021,12 @@ index 00000000..17010305
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+ /delete-node/ hdmi-i2c-xfer;
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+ };
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+
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+ i2s1 {
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+ i2s_8ch_mclk: i2s-8ch-mclk {
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+ rockchip,pins = <4 RK_PA0 RK_FUNC_1 &pcfg_pull_none>;
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+ };
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+ };
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+
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+ pmic {
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+ pmic_int_l: pmic-int-l {
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+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
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60
patch/kernel/rockchip64-dev/general-rt5651-add-mclk.patch
Normal file
60
patch/kernel/rockchip64-dev/general-rt5651-add-mclk.patch
Normal file
@ -0,0 +1,60 @@
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diff --git a/sound/soc/codecs/rt5651.c b/sound/soc/codecs/rt5651.c
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index c506c9305..41a08b320 100644
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--- a/sound/soc/codecs/rt5651.c
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+++ b/sound/soc/codecs/rt5651.c
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@@ -24,6 +24,7 @@
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#include <sound/initval.h>
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#include <sound/tlv.h>
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#include <sound/jack.h>
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+#include <linux/clk.h>
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#include "rl6231.h"
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#include "rt5651.h"
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@@ -1511,6 +1512,7 @@ static int rt5651_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
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static int rt5651_set_bias_level(struct snd_soc_component *component,
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enum snd_soc_bias_level level)
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{
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+ struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
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switch (level) {
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case SND_SOC_BIAS_PREPARE:
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if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) {
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@@ -1518,6 +1520,13 @@ static int rt5651_set_bias_level(struct snd_soc_component *component,
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snd_soc_component_update_bits(component, RT5651_D_MISC,
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0xc00, 0xc00);
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}
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+ if (!IS_ERR(rt5651->mclk)){
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+ if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
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+ clk_disable_unprepare(rt5651->mclk);
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+ } else {
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+ clk_prepare_enable(rt5651->mclk);
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+ }
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+ }
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break;
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case SND_SOC_BIAS_STANDBY:
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if (SND_SOC_BIAS_OFF == snd_soc_component_get_bias_level(component)) {
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@@ -2059,6 +2068,13 @@ static int rt5651_probe(struct snd_soc_component *component)
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{
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struct rt5651_priv *rt5651 = snd_soc_component_get_drvdata(component);
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+ /* Check if MCLK provided */
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+ rt5651->mclk = devm_clk_get(component->dev, "mclk");
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+ if (PTR_ERR(rt5651->mclk) == -EPROBE_DEFER){
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+ dev_err(component->dev, "unable to get mclk\n");
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+ return -EPROBE_DEFER;
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+ }
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+
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rt5651->component = component;
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snd_soc_component_update_bits(component, RT5651_PWR_ANLG1,
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diff --git a/sound/soc/codecs/rt5651.h b/sound/soc/codecs/rt5651.h
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index 20c33a3ec..17524fa9f 100644
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--- a/sound/soc/codecs/rt5651.h
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+++ b/sound/soc/codecs/rt5651.h
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@@ -2097,6 +2097,7 @@ struct rt5651_priv {
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int dmic_en;
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bool hp_mute;
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+ struct clk *mclk;
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};
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#endif /* __RT5651_H__ */
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@ -0,0 +1,25 @@
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diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
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index ce1d2446f..38447441b 100644
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--- a/drivers/clk/rockchip/clk-rk3399.c
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+++ b/drivers/clk/rockchip/clk-rk3399.c
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@@ -620,7 +620,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
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GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
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RK3399_CLKGATE_CON(8), 11, GFLAGS),
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- MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT,
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+ MUX(SCLK_I2SOUT_SRC, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT,
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RK3399_CLKSEL_CON(31), 0, 2, MFLAGS),
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COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT,
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RK3399_CLKSEL_CON(31), 2, 1, MFLAGS,
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diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h
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index 44e0a319f..b7b07dfda 100644
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--- a/include/dt-bindings/clock/rk3399-cru.h
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+++ b/include/dt-bindings/clock/rk3399-cru.h
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@@ -19,6 +19,7 @@
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#define ARMCLKB 9
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/* sclk gates (special clocks) */
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+#define SCLK_I2SOUT_SRC 64
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#define SCLK_I2C1 65
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#define SCLK_I2C2 66
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#define SCLK_I2C3 67
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