[ rockchip64 ] rk3328 change to mainline USB3

This commit is contained in:
tonymac32 2021-07-27 00:05:09 -04:00
parent 4c52601d52
commit d8dbefd618
8 changed files with 111 additions and 1697 deletions

View File

@ -129,7 +129,7 @@ case $BRANCH in
current)
KERNELBRANCH="branch:linux-5.10.y"
if [[ $BOARD == station* || $BOARD == renegade ]]; then
if [[ $BOARD == station* ]]; then
KERNELPATCHDIR='station-'$BRANCH
LINUXFAMILY=station
LINUXCONFIG='linux-station-'$BRANCH

View File

@ -1,46 +0,0 @@
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -984,24 +984,24 @@
status = "disabled";
};
- usbdrd3: usb@ff600000 {
- compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
- reg = <0x0 0xff600000 0x0 0x100000>;
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
- <&cru ACLK_USB3OTG>;
- clock-names = "ref_clk", "suspend_clk",
- "bus_clk";
- dr_mode = "otg";
- phy_type = "utmi_wide";
- snps,dis-del-phy-power-chg-quirk;
- snps,dis_enblslpm_quirk;
- snps,dis-tx-ipgap-linecheck-quirk;
- snps,dis-u2-freeclk-exists-quirk;
- snps,dis_u2_susphy_quirk;
- snps,dis_u3_susphy_quirk;
- status = "disabled";
- };
+// usbdrd3: usb@ff600000 {
+// compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
+// reg = <0x0 0xff600000 0x0 0x100000>;
+// interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+// clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
+// <&cru ACLK_USB3OTG>;
+// clock-names = "ref_clk", "suspend_clk",
+// "bus_clk";
+// dr_mode = "otg";
+// phy_type = "utmi_wide";
+// snps,dis-del-phy-power-chg-quirk;
+// snps,dis_enblslpm_quirk;
+// snps,dis-tx-ipgap-linecheck-quirk;
+// snps,dis-u2-freeclk-exists-quirk;
+// snps,dis_u2_susphy_quirk;
+// snps,dis_u3_susphy_quirk;
+// status = "disabled";
+// };
gic: interrupt-controller@ff811000 {
compatible = "arm,gic-400";

View File

@ -906,18 +906,18 @@ index 000000000..36890bb7f
+ status = "okay";
+};
+
+&u3phy {
+ vbus-supply = <&vcc_host_vbus>;
+ status = "okay";
+};
+
+&u3phy_utmi {
+ status = "okay";
+};
+
+&u3phy_pipe {
+ status = "okay";
+};
+
+
+
+
+
+
+
+
+
+
+
+&usb20_otg {
+ status = "okay";
@ -931,17 +931,17 @@ index 000000000..36890bb7f
+ status = "okay";
+};
+
+&usbdrd3 {
+ status = "okay";
+};
+
+&usbdrd_dwc3 {
+
+
+
+&usbdrd3 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dr_mode = "host";
+ r8153: device@2 {
+ compatible = "usbbda:8153";
+ compatible = "usbbda,8153";
+ reg = <2>;
+ local-mac-address = [00 00 00 00 00 00];
+ };

View File

@ -428,11 +428,11 @@ index 000000000000..b85508c12742
+ status = "okay";
+};
+
+&usbdrd3 {
+ status = "okay";
+};
+
+&usbdrd_dwc3 {
+
+
+
+&usbdrd3 {
+ dr_mode = "host";
+ status = "okay";
+};

View File

@ -421,18 +421,18 @@ index 000000000..52732643f
+ status = "okay";
+};
+
+&u3phy {
+ vbus-supply = <&vcc_host_vbus>;
+ status = "okay";
+};
+
+&u3phy_utmi {
+ status = "okay";
+};
+
+&u3phy_pipe {
+ status = "okay";
+};
+
+
+
+
+
+
+
+
+
+
+
+&uart2 {
+ status = "okay";
@ -451,11 +451,11 @@ index 000000000..52732643f
+ status = "okay";
+};
+
+&usbdrd3 {
+ status = "okay";
+};
+
+&usbdrd_dwc3 {
+
+
+
+&usbdrd3 {
+ dr_mode = "host";
+ status = "okay";
+};

View File

@ -1,113 +0,0 @@
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -346,12 +346,16 @@
power-domain@RK3328_PD_HEVC {
reg = <RK3328_PD_GPU>;
clocks = <&cru ACLK_GPU>;
- };
+ };
power-domain@RK3328_PD_HEVC {
reg = <RK3328_PD_HEVC>;
};
power-domain@RK3328_PD_VIDEO {
reg = <RK3328_PD_VIDEO>;
+ clocks = <&cru ACLK_RKVDEC>,
+ <&cru HCLK_RKVDEC>,
+ <&cru SCLK_VDEC_CABAC>,
+ <&cru SCLK_VDEC_CORE>;
};
power-domain@RK3328_PD_VPU {
reg = <RK3328_PD_VPU>;
@@ -705,6 +709,7 @@
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
+ power-domains = <&power RK3328_PD_VIDEO>;
status = "disabled";
};
@@ -935,6 +940,8 @@
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <150000000>;
+ resets = <&cru SRST_MMC0>;
+ reset-names = "reset";
status = "disabled";
};
@@ -947,6 +954,8 @@
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <150000000>;
+ resets = <&cru SRST_SDIO>;
+ reset-names = "reset";
status = "disabled";
};
@@ -959,6 +968,8 @@
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <150000000>;
+ resets = <&cru SRST_EMMC>;
+ reset-names = "reset";
status = "disabled";
};
@@ -1056,25 +1067,41 @@
status = "disabled";
};
+ sdmmc_ext: dwmmc@ff5f0000 {
+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff5f0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>,
+ <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <150000000>;
+ resets = <&cru SRST_SDMMCEXT>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
usbdrd3: usb@ff600000 {
compatible = "rockchip,rk3328-dwc3", "rockchip,rk3399-dwc3";
- clocks = <&cru SCLK_USB3OTG_REF>, <&cru ACLK_USB3OTG>,
- <&cru SCLK_USB3OTG_SUSPEND>;
- clock-names = "ref", "bus_early",
- "suspend";
+ clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
+ <&cru ACLK_USB3OTG>;
+ clock-names = "ref_clk", "suspend_clk",
+ "bus_clk";
+ resets = <&cru SRST_USB3OTG>;
+ reset-names = "usb3-otg";
#address-cells = <2>;
#size-cells = <2>;
ranges;
- clock-ranges;
status = "disabled";
usbdrd_dwc3: dwc3@ff600000 {
compatible = "snps,dwc3";
reg = <0x0 0xff600000 0x0 0x100000>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_USB3OTG_REF>, <&cru ACLK_USB3OTG>,
+ <&cru SCLK_USB3OTG_SUSPEND>;
+ clock-names = "ref", "bus_early", "suspend";
dr_mode = "otg";
- phys = <&u3phy_utmi>, <&u3phy_pipe>;
- phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
snps,dis_enblslpm_quirk;
snps,dis-u2-freeclk-exists-quirk;
@@ -1082,7 +1109,6 @@
snps,dis_u3_susphy_quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
- snps,xhci-trb-ent-quirk;
status = "disabled";
};
};

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@ -0,0 +1,77 @@
From 899a52340ee038037e690734f9607657a988c1de Mon Sep 17 00:00:00 2001
From: tonymac32 <tonymckahan@gmail.com>
Date: Sun, 25 Jul 2021 23:47:50 -0400
Subject: [PATCH] rk3328 dtsi mmc vdec
Signed-off-by: tonymac32 <tonymckahan@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 25 ++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 4233ea2a6..a576953ec 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -371,6 +371,10 @@ power-domain@RK3328_PD_HEVC {
};
power-domain@RK3328_PD_VIDEO {
reg = <RK3328_PD_VIDEO>;
+ clocks = <&cru ACLK_RKVDEC>,
+ <&cru HCLK_RKVDEC>,
+ <&cru SCLK_VDEC_CABAC>,
+ <&cru SCLK_VDEC_CORE>;
};
power-domain@RK3328_PD_VPU {
reg = <RK3328_PD_VPU>;
@@ -692,6 +696,7 @@ vepu_mmu: iommu@ff340800 {
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
+ power-domains = <&power RK3328_PD_VIDEO>;
status = "disabled";
};
@@ -914,6 +919,8 @@ sdmmc: mmc@ff500000 {
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <150000000>;
+ resets = <&cru SRST_MMC0>;
+ reset-names = "reset";
status = "disabled";
};
@@ -926,6 +933,8 @@ sdio: mmc@ff510000 {
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <150000000>;
+ resets = <&cru SRST_SDIO>;
+ reset-names = "reset";
status = "disabled";
};
@@ -938,6 +947,22 @@ emmc: mmc@ff520000 {
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <150000000>;
+ resets = <&cru SRST_EMMC>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ sdmmc_ext: dwmmc@ff5f0000 {
+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff5f0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>,
+ <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <150000000>;
+ resets = <&cru SRST_SDMMCEXT>;
+ reset-names = "reset";
status = "disabled";
};
--
Created with Armbian build tools https://github.com/armbian/build