rk322x: fix mainlined patches

This commit is contained in:
Paolo Sabatino 2021-08-09 20:15:34 +00:00
parent 86051a8e9d
commit cba37d6b47
2 changed files with 31 additions and 67 deletions

View File

@ -2460,40 +2460,6 @@ index d89c3ada8bb5..17c556183807 100644
compatible = "arm,gic-400";
#interrupt-cells = <3>;
From 9bb697a154bc838094e2dda77d345cfd09c80bde Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Mon, 10 Feb 2020 19:24:54 +0100
Subject: [PATCH] ARM64: dts: rk3328 add gpu powerdomain
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 17c556183807..656379a8e6cd 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -318,6 +318,10 @@ power: power-controller {
#address-cells = <1>;
#size-cells = <0>;
+ pd_gpu@RK3328_PD_GPU {
+ reg = <RK3328_PD_GPU>;
+ clocks = <&cru ACLK_GPU>;
+ };
pd_hevc@RK3328_PD_HEVC {
reg = <RK3328_PD_HEVC>;
};
@@ -620,6 +624,7 @@ gpu: gpu@ff300000 {
"ppmmu1";
clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
clock-names = "bus", "core";
+ power-domains = <&power RK3328_PD_GPU>;
resets = <&cru SRST_GPU_A>;
};
From a57c0fc274e83a2c40b31e66bcd009b9508d3f3c Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Tue, 11 Feb 2020 16:11:22 +0100

View File

@ -3937,17 +3937,6 @@ index f98a945c68d3..b233baeb20ef 100644
vpu_mmu: iommu@20020800 {
compatible = "rockchip,iommu";
reg = <0x20020800 0x100>;
@@ -687,8 +699,8 @@ vpu_mmu: iommu@20020800 {
interrupt-names = "vpu_mmu";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "iface";
- iommu-cells = <0>;
- status = "disabled";
+ #iommu-cells = <0>;
+ power-domains = <&power RK3228_PD_VPU>;
};
vdec_mmu: iommu@20030480 {
From 2542e122786d27dfcf4bf2a60b2d91a4ae3a48dd Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
@ -4438,17 +4427,6 @@ index b233baeb20ef..de5727e0bc94 100644
vdec_mmu: iommu@20030480 {
compatible = "rockchip,iommu";
reg = <0x20030480 0x40>, <0x200304c0 0x40>;
@@ -710,8 +731,8 @@ vdec_mmu: iommu@20030480 {
interrupt-names = "vdec_mmu";
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
clock-names = "aclk", "iface";
- iommu-cells = <0>;
- status = "disabled";
+ power-domains = <&power RK3228_PD_RKVDEC>;
+ #iommu-cells = <0>;
};
vop: vop@20050000 {
From 7123c3d575df39ea102be56374fbc82a02d59ff2 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
@ -6379,17 +6357,6 @@ index de5727e0bc94..a2012a44421d 100644
iep_mmu: iommu@20070800 {
compatible = "rockchip,iommu";
reg = <0x20070800 0x100>;
@@ -788,8 +803,8 @@ iep_mmu: iommu@20070800 {
interrupt-names = "iep_mmu";
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
- iommu-cells = <0>;
- status = "disabled";
+ #iommu-cells = <0>;
+ power-domains = <&power RK3228_PD_VIO>;
};
hdmi: hdmi@200a0000 {
From e01ddeae4d23380545603195f72054a604ef45f4 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
@ -6604,3 +6571,34 @@ index 9757976d6e8a..d7aa05d7dee7 100644
};
isp_mmu: iommu@ff914000 {
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 6b2d9ce24..2297b43bf 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -770,7 +770,7 @@ vpu_mmu: iommu@20020800 {
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
- status = "disabled";
+ power-domains = <&power RK3228_PD_VPU>;
};
vdec: video-codec@20030000 {
@@ -801,7 +801,7 @@ vdec_mmu: iommu@20030480 {
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
- status = "disabled";
+ power-domains = <&power RK3228_PD_RKVDEC>;
};
vop: vop@20050000 {
@@ -871,7 +871,7 @@ iep_mmu: iommu@20070800 {
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
- status = "disabled";
+ power-domains = <&power RK3228_PD_VIO>;
};
hdmi: hdmi@200a0000 {