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Removed some leftover Renegade patches for legacy u-boot (from -dev too)

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Piotr Szczepanik 2020-10-05 23:22:52 +02:00
parent fe1c783159
commit c8468ca633
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1 changed files with 0 additions and 37 deletions
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37
patch/u-boot/u-boot-rockchip64-dev/board_renegade/size_support_ddr4.patch
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@ -1,37 +0,0 @@
diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c
index 76dbdc8..19f7c17 100644
--- a/arch/arm/mach-rockchip/sdram_common.c
+++ b/arch/arm/mach-rockchip/sdram_common.c
@@ -14,7 +14,7 @@
DECLARE_GLOBAL_DATA_PTR;
size_t rockchip_sdram_size(phys_addr_t reg)
{
- u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
+ u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4, dbw, bg;
size_t chipsize_mb = 0;
size_t size_mb = 0;
u32 ch;
@@ -37,16 +37,20 @@ size_t rockchip_sdram_size(phys_addr_t reg)
SYS_REG_BW_MASK));
row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
SYS_REG_ROW_3_4_MASK;
+ dbw = sys_reg >> SYS_REG_DBW_SHIFT(ch) & SYS_REG_DBW_MASK;
+ /* only used by DDR4 */
+ bg = (dbw == 1) ? 1 : 2;
- chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
+ chipsize_mb = (1 << (cs0_row + col + bg + bk + bw - 20));
if (rank > 1)
chipsize_mb += chipsize_mb >> (cs0_row - cs1_row);
if (row_3_4)
chipsize_mb = chipsize_mb * 3 / 4;
size_mb += chipsize_mb;
- debug("rank %d col %d bk %d cs0_row %d bw %d row_3_4 %d\n",
- rank, col, bk, cs0_row, bw, row_3_4);
+ debug("rank %d col %d bk %d cs0_row %d bw %d row_3_4 %d dbw %d\n",
+ rank, col, bk, cs0_row, bw, row_3_4, dbw);
+
}
return (size_t)size_mb << 20;