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NanoPC-T6-collabora: dts: add pcie2 and eth

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This commit is contained in:
Thomas McKahan 2023-07-05 12:54:14 -04:00 committed by Igor
parent 23d8ce7c5c
commit bfc8271519
1 changed files with 88 additions and 0 deletions
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88
patch/kernel/rockchip-rk3588-collabora/dt/rk3588-nanopc-t6.dts
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@ -20,6 +20,8 @@
// mmc1 = &sdio; // needs SDIO patch
mmc2 = &sdhci;
serial2 = &uart2;
ethernet0 = &r8125_u10;
ethernet1 = &r8125_u12;
};
chosen {
@ -64,6 +66,40 @@
regulator-max-microvolt = <1100000>;
vin-supply = <&vcc4v0_sys>;
};
vcc_3v3_pcie20: vcc3v3-pcie20 {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_pcie20";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_3v3_s3>;
};
vdd_mpcie_3v3: vdd-mpcie-3v3 {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_m2_1_pwren>;
regulator-name = "vdd_mpcie_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
};
&combphy0_ps {
status = "okay";
};
&combphy1_ps {
status = "okay";
};
&combphy2_psu {
status = "okay";
};
&cpu_l0 {
@ -185,6 +221,48 @@
};
&pcie2x1l0 {
reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
rockchip,init-delay-ms = <100>;
vpcie3v3-supply = <&vcc_3v3_pcie20>;
status = "okay";
pcie@20 {
reg = <0x00200000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
r8125_u12: pcie@20,0 {
reg = <0x000000 0 0 0 0>;
local-mac-address = [ 00 00 00 00 00 00 ];
};
};
};
&pcie2x1l1 {
reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
rockchip,init-delay-ms = <500>;
vpcie3v3-supply = <&vdd_mpcie_3v3>;
status = "okay";
};
&pcie2x1l2 {
reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc_3v3_pcie20>;
status = "okay";
pcie@40 {
reg = <0x00400000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
r8125_u10: pcie@40,0 {
reg = <0x000000 0 0 0 0>;
local-mac-address = [ 00 00 00 00 00 00 ];
};
};
};
&pinctrl {
hym8563 {
@ -192,6 +270,16 @@
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
pcie {
pcie_m2_0_pwren: pcie-m20-pwren {
rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
pcie_m2_1_pwren: pcie-m21-pwren {
rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm1 {