Move mvebu64-current to 5.4.y, DEV to 5.6.y (#1866)

* Move mvebu64-current to 5.4.y, DEV to 5.6.y
* Adjust config

config/sources/families/mvebu64.conf

@@ -38,12 +38,12 @@ case $BRANCH in
 
 	current)
 
-		KERNELBRANCH='branch:linux-4.19.y'
+		KERNELBRANCH='branch:linux-5.4.y'
 
 	;;
 
         dev)
-		KERNELBRANCH='branch:linux-5.4.y'
+		KERNELBRANCH='branch:linux-5.6.y'
         ;;
 
 esac

patch/kernel/mvebu64-current/2001-clk_mvebu_armada-37xx-tbg_Switch_to_clk_get_and_balance_it_in_probe.patch

@@ -1,40 +0,0 @@
-From 480d99fdc3eee31a23c317927a335e9a71c2904f Mon Sep 17 00:00:00 2001
-From: Gregory CLEMENT <gregory.clement@bootlin.com>
-Date: Wed, 10 Oct 2018 20:18:38 +0200
-Subject: clk: mvebu: armada-37xx-tbg: Switch to clk_get and balance it in
- probe
-
-The parent clock is get only to have its name, and then the clock is no
-more used, so we can safely free it using clk_put. Furthermore as between
-the successful devm_clk_get() and the devm_clk_put() call we don't exit
-the probe function in error so I can use non managed version of clk_get()
-and clk_put().
-
-Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/mvebu/armada-37xx-tbg.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/clk/mvebu/armada-37xx-tbg.c b/drivers/clk/mvebu/armada-37xx-tbg.c
-index 7ff041f73b55..4de15d44a0c1 100644
---- a/drivers/clk/mvebu/armada-37xx-tbg.c
-+++ b/drivers/clk/mvebu/armada-37xx-tbg.c
-@@ -99,12 +99,13 @@ static int armada_3700_tbg_clock_probe(struct platform_device *pdev)
- 	hw_tbg_data->num = NUM_TBG;
- 	platform_set_drvdata(pdev, hw_tbg_data);
- 
--	parent = devm_clk_get(dev, NULL);
-+	parent = clk_get(dev, NULL);
- 	if (IS_ERR(parent)) {
- 		dev_err(dev, "Could get the clock parent\n");
- 		return -EINVAL;
- 	}
- 	parent_name = __clk_get_name(parent);
-+	clk_put(parent);
- 
- 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- 	reg = devm_ioremap_resource(dev, res);
--- 
-cgit 1.2-0.3.lf.el7
-

patch/kernel/mvebu64-current/2003-clk_mvebu_armada-37xx-periph_add_suspend_resume_support.patch

@@ -1,92 +0,0 @@
-From 5beb1e60dba973e0b9cfb54d9735d5d4385b9d90 Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Fri, 13 Jul 2018 15:44:46 +0200
-Subject: clk: mvebu: armada-37xx-periph: add suspend/resume support
-
-Add suspend/resume hooks in Armada 37xx peripheral clocks driver to
-handle S2RAM operations.
-
-One can think that these hooks are useless by comparing the register
-values before and after a suspend/resume cycle: they will look the same
-anyway. This is because of some scripts executed by the Cortex-M3 core
-during ATF operations to init both the clocks and the DDR. These values
-could be modified by the BL33 stage or by Linux itself and should be
-preserved.
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/mvebu/armada-37xx-periph.c | 43 ++++++++++++++++++++++++++++++++++
- 1 file changed, 43 insertions(+)
-
-diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c
-index 78048c2e3774..1f1cff428d78 100644
---- a/drivers/clk/mvebu/armada-37xx-periph.c
-+++ b/drivers/clk/mvebu/armada-37xx-periph.c
-@@ -57,6 +57,14 @@ struct clk_periph_driver_data {
- 	struct clk_hw_onecell_data *hw_data;
- 	spinlock_t lock;
- 	void __iomem *reg;
-+
-+	/* Storage registers for suspend/resume operations */
-+	u32 tbg_sel;
-+	u32 div_sel0;
-+	u32 div_sel1;
-+	u32 div_sel2;
-+	u32 clk_sel;
-+	u32 clk_dis;
- };
- 
- struct clk_double_div {
-@@ -673,6 +681,40 @@ static int armada_3700_add_composite_clk(const struct clk_periph_data *data,
- 	return PTR_ERR_OR_ZERO(*hw);
- }
- 
-+static int __maybe_unused armada_3700_periph_clock_suspend(struct device *dev)
-+{
-+	struct clk_periph_driver_data *data = dev_get_drvdata(dev);
-+
-+	data->tbg_sel = readl(data->reg + TBG_SEL);
-+	data->div_sel0 = readl(data->reg + DIV_SEL0);
-+	data->div_sel1 = readl(data->reg + DIV_SEL1);
-+	data->div_sel2 = readl(data->reg + DIV_SEL2);
-+	data->clk_sel = readl(data->reg + CLK_SEL);
-+	data->clk_dis = readl(data->reg + CLK_DIS);
-+
-+	return 0;
-+}
-+
-+static int __maybe_unused armada_3700_periph_clock_resume(struct device *dev)
-+{
-+	struct clk_periph_driver_data *data = dev_get_drvdata(dev);
-+
-+	/* Follow the same order than what the Cortex-M3 does (ATF code) */
-+	writel(data->clk_dis, data->reg + CLK_DIS);
-+	writel(data->div_sel0, data->reg + DIV_SEL0);
-+	writel(data->div_sel1, data->reg + DIV_SEL1);
-+	writel(data->div_sel2, data->reg + DIV_SEL2);
-+	writel(data->tbg_sel, data->reg + TBG_SEL);
-+	writel(data->clk_sel, data->reg + CLK_SEL);
-+
-+	return 0;
-+}
-+
-+static const struct dev_pm_ops armada_3700_periph_clock_pm_ops = {
-+	SET_SYSTEM_SLEEP_PM_OPS(armada_3700_periph_clock_suspend,
-+				armada_3700_periph_clock_resume)
-+};
-+
- static int armada_3700_periph_clock_probe(struct platform_device *pdev)
- {
- 	struct clk_periph_driver_data *driver_data;
-@@ -748,6 +790,7 @@ static struct platform_driver armada_3700_periph_clock_driver = {
- 	.driver		= {
- 		.name	= "marvell-armada-3700-periph-clock",
- 		.of_match_table = armada_3700_periph_clock_of_match,
-+		.pm	= &armada_3700_periph_clock_pm_ops,
- 	},
- };
- 
--- 
-cgit 1.2-0.3.lf.el7
-

patch/kernel/mvebu64-current/add-board-espressobinv7.patch

@@ -7,9 +7,9 @@ index ea9d49f2a911..d80da8f5d82d 100644
  dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb
  dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb
 +dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobinv7.dtb
+ dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-turris-mox.dtb
+ dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-uDPU.dtb
  dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb
- dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb
- dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb
 diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobinv7.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobinv7.dts
 new file mode 100644
 index 000000000000..6385b2488e45

patch/kernel/mvebu64-current/armada-3720-espressobin.dts.patch

@@ -1,55 +0,0 @@
-diff --git linux-4.18.7/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
-index 3ab25ad40..0f99e751c 100644
---- linux-4.18.7/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
-+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
-@@ -41,6 +41,15 @@
- 			  3300000 0x0>;
- 		enable-active-high;
- 	};
-+
-+	leds {
-+		compatible = "gpio-leds";
-+
-+		red {
-+			label = "espressobin:red:usr";
-+			gpios = <&gpionb 2 GPIO_ACTIVE_LOW>;
-+		};
-+	};
- };
- 
- /* J9 */
-@@ -68,9 +77,17 @@
- 
- 	flash@0 {
- 		reg = <0>;
--		compatible = "winbond,w25q32dw", "jedec,spi-flash";
-+		/*
-+		 * Originally "winbond,w25q32dw", but since the manufacturer is known
-+		 * to have replaced the part with "macronix,mx25u3235f" in some board
-+		 * batches, just use the generic "jedec,spi-nor" and let the actual
-+		 * chip type be probed. The partition table still depends on the chip
-+		 * being 4 MiB in size.
-+		 */
-+		compatible = "jedec,spi-nor";
- 		spi-max-frequency = <104000000>;
- 		m25p,fast-read;
-+		status = "okay";
- 
- 		partitions {
- 			compatible = "fixed-partitions";
-@@ -79,12 +96,12 @@
- 
- 			partition@0 {
- 				label = "uboot";
--				reg = <0 0x180000>;
-+				reg = <0 0x3f0000>;
- 			};
- 
--			partition@180000 {
-+			partition@3f0000 {
- 				label = "ubootenv";
--				reg = <0x180000 0x10000>;
-+				reg = <0x3f0000 0x10000>;
- 			};
- 		};
- 	};

patch/kernel/mvebu64-current/armada-37xx-cpufreq.patch.disabled

@@ -1,80 +0,0 @@
-diff --git a/drivers/cpufreq/armada-37xx-cpufreq.c b/drivers/cpufreq/armada-37xx-cpufreq.c
-index 75491fc84..c2adf380b 100644
---- a/drivers/cpufreq/armada-37xx-cpufreq.c
-+++ b/drivers/cpufreq/armada-37xx-cpufreq.c
-@@ -162,11 +162,25 @@ static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
- 	}
- 
- 	/*
--	 * Set cpu clock source, for all the level we keep the same
--	 * clock source that the one already configured. For this one
--	 * we need to use the clock framework
--	 */
-+	* Set CPU clock source, for all the level we keep the same
-+	* clock source that the one already configured with DVS
-+	* disabled. For this one we need to use the clock framewor
-+	*/
- 	parent = clk_get_parent(clk);
-+
-+	/*
-+	* Unset parent clock to force the clock framework setting again
-+	* the clock parent
-+	*/
-+	clk_set_parent(clk, NULL);
-+
-+	/*
-+	* For the Armada 37xx CPU clocks, setting the parent will
-+	* actually configure the parent when DVFS is enabled. At
-+	* hardware level it will be a different register from the one
-+	* read when doing clk_get_parent that will be set with
-+	* clk_set_parent.
-+	*/
- 	clk_set_parent(clk, parent);
- }
- 
-@@ -359,11 +373,11 @@ static int __init armada37xx_cpufreq_driver_init(void)
- 	struct armada_37xx_dvfs *dvfs;
- 	struct platform_device *pdev;
- 	unsigned long freq;
--	unsigned int cur_frequency;
-+	unsigned int cur_frequency, base_frequency;
- 	struct regmap *nb_pm_base, *avs_base;
- 	struct device *cpu_dev;
- 	int load_lvl, ret;
--	struct clk *clk;
-+	struct clk *clk, *parent;
- 
- 	nb_pm_base =
- 		syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm");
-@@ -399,6 +413,22 @@ static int __init armada37xx_cpufreq_driver_init(void)
- 		return PTR_ERR(clk);
- 	}
- 
-+	parent = clk_get_parent(clk);
-+	if (IS_ERR(parent)) {
-+		dev_err(cpu_dev, "Cannot get parent clock for CPU0\n");
-+		clk_put(clk);
-+		return PTR_ERR(parent);
-+	}
-+
-+	/* Get parent CPU frequency */
-+	base_frequency =  clk_get_rate(parent);
-+
-+	if (!base_frequency) {
-+		dev_err(cpu_dev, "Failed to get parent clock rate for CPU\n");
-+		clk_put(clk);
-+		return -EINVAL;
-+	}
-+
- 	/* Get nominal (current) CPU frequency */
- 	cur_frequency = clk_get_rate(clk);
- 	if (!cur_frequency) {
-@@ -431,7 +461,7 @@ static int __init armada37xx_cpufreq_driver_init(void)
- 	for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
- 	     load_lvl++) {
- 		unsigned long u_volt = avs_map[dvfs->avs[load_lvl]] * 1000;
--		freq = cur_frequency / dvfs->divider[load_lvl];
-+		freq = base_frequency / dvfs->divider[load_lvl];
- 		ret = dev_pm_opp_add(cpu_dev, freq, u_volt);
- 		if (ret)
- 			goto remove_opp;

patch/kernel/mvebu64-current/fix_problem_with_cpu_scaling_not_working.patch.disabled

@@ -1,57 +0,0 @@
-From 8fe9a4c4a024a6353e810a1dbb5e4bc78bff60a8 Mon Sep 17 00:00:00 2001
-From: FlashBurnGitHub <33546258+FlashBurnGitHub@users.noreply.github.com>
-Date: Wed, 6 Mar 2019 17:25:46 +0100
-Subject: [PATCH] Fix problem with cpu scaling not working
-
-This fixes a problem that the cpu scaling is not working.
-
-First one needs to first unset the parent clock, before setting the same old parent clock again. This solves the problem that the wrong TBG clock source was used for the cpu.
-
-Also one needs to multiply the current cpu frequency with the used divider so that the right cpu frequency gets calculated when applying the dividers. This was need for a 600MHz final cpu frequency to work
----
- drivers/cpufreq/armada-37xx-cpufreq.c | 11 ++++++++++-
- 1 file changed, 10 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/cpufreq/armada-37xx-cpufreq.c b/drivers/cpufreq/armada-37xx-cpufreq.c
-index 75491fc841a6..5c744092f819 100644
---- a/drivers/cpufreq/armada-37xx-cpufreq.c
-+++ b/drivers/cpufreq/armada-37xx-cpufreq.c
-@@ -167,6 +167,11 @@ static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
- 	 * we need to use the clock framework
- 	 */
- 	parent = clk_get_parent(clk);
-+	
-+	/* Unset parent clock */
-+	clk_set_parent(clk, NULL);
-+	
-+	/* set old parent; this triggers setting needed values for right CPU clock in hardware regs */
- 	clk_set_parent(clk, parent);
- }
- 
-@@ -360,6 +365,7 @@ static int __init armada37xx_cpufreq_driver_init(void)
- 	struct platform_device *pdev;
- 	unsigned long freq;
- 	unsigned int cur_frequency;
-+	unsigned int base_frequency;
- 	struct regmap *nb_pm_base, *avs_base;
- 	struct device *cpu_dev;
- 	int load_lvl, ret;
-@@ -412,6 +418,9 @@ static int __init armada37xx_cpufreq_driver_init(void)
- 		clk_put(clk);
- 		return -EINVAL;
- 	}
-+	
-+	/* Get base CPU frequency without divider */
-+	base_frequency = cur_frequency * dvfs->divider[ARMADA_37XX_DVFS_LOAD_0];
- 
- 	armada37xx_cpufreq_state = kmalloc(sizeof(*armada37xx_cpufreq_state),
- 					   GFP_KERNEL);
-@@ -431,7 +440,7 @@ static int __init armada37xx_cpufreq_driver_init(void)
- 	for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
- 	     load_lvl++) {
- 		unsigned long u_volt = avs_map[dvfs->avs[load_lvl]] * 1000;
--		freq = cur_frequency / dvfs->divider[load_lvl];
-+		freq = base_frequency / dvfs->divider[load_lvl];
- 		ret = dev_pm_opp_add(cpu_dev, freq, u_volt);
- 		if (ret)
- 			goto remove_opp;

patch/kernel/mvebu64-current/general-increasing_DMA_block_memory_allocation_to_2048.patch

@@ -1,27 +0,0 @@
-diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c
-index 3216e09..21bce28
---- a/arch/arm64/mm/dma-mapping.c
-+++ b/arch/arm64/mm/dma-mapping.c
-@@ -44,7 +44,7 @@ static pgprot_t __get_dma_pgprot(unsigned long attrs, pgprot_t prot,
-
- static struct gen_pool *atomic_pool;
-
--#define DEFAULT_DMA_COHERENT_POOL_SIZE  SZ_256K
-+#define DEFAULT_DMA_COHERENT_POOL_SIZE  SZ_2M
- static size_t atomic_pool_size __initdata = DEFAULT_DMA_COHERENT_POOL_SIZE;
-
- static int __init early_coherent_pool(char *p)
-
-diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
-index ada8eb2..8df220f
---- a/arch/arm/mm/dma-mapping.c
-+++ b/arch/arm/mm/dma-mapping.c
-@@ -381,7 +381,7 @@ static void __dma_free_remap(void *cpu_addr, size_t size)
- 			VM_ARM_DMA_CONSISTENT | VM_USERMAP);
- }
-
--#define DEFAULT_DMA_COHERENT_POOL_SIZE	SZ_256K
-+#define DEFAULT_DMA_COHERENT_POOL_SIZE	SZ_2M
- static struct gen_pool *atomic_pool __ro_after_init;
-
- static size_t atomic_pool_size __initdata = DEFAULT_DMA_COHERENT_POOL_SIZE;

patch/kernel/mvebu64-dev/2002-clk_mvebu_armada-37xx-periph_save_the_IP_base_address_in_the_driver_data.patch.disabled

@@ -1,70 +0,0 @@
-From d9d95e78cff80c3fe43e757ba90644cd766302ac Mon Sep 17 00:00:00 2001
-From: Miquel Raynal <miquel.raynal@bootlin.com>
-Date: Fri, 13 Jul 2018 15:44:45 +0200
-Subject: clk: mvebu: armada-37xx-periph: save the IP base address in the
- driver data
-
-Prepare the introduction of suspend/resume hooks by having an easy way
-to access all the registers in one go just from a device: add the IP
-base address in the driver data.
-
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/mvebu/armada-37xx-periph.c | 15 +++++++--------
- 1 file changed, 7 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c
-index 499f5962c8b0..78048c2e3774 100644
---- a/drivers/clk/mvebu/armada-37xx-periph.c
-+++ b/drivers/clk/mvebu/armada-37xx-periph.c
-@@ -56,6 +56,7 @@
- struct clk_periph_driver_data {
- 	struct clk_hw_onecell_data *hw_data;
- 	spinlock_t lock;
-+	void __iomem *reg;
- };
- 
- struct clk_double_div {
-@@ -680,7 +681,6 @@ static int armada_3700_periph_clock_probe(struct platform_device *pdev)
- 	struct device *dev = &pdev->dev;
- 	int num_periph = 0, i, ret;
- 	struct resource *res;
--	void __iomem *reg;
- 
- 	data = of_device_get_match_data(dev);
- 	if (!data)
-@@ -689,11 +689,6 @@ static int armada_3700_periph_clock_probe(struct platform_device *pdev)
- 	while (data[num_periph].name)
- 		num_periph++;
- 
--	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
--	reg = devm_ioremap_resource(dev, res);
--	if (IS_ERR(reg))
--		return PTR_ERR(reg);
--
- 	driver_data = devm_kzalloc(dev, sizeof(*driver_data), GFP_KERNEL);
- 	if (!driver_data)
- 		return -ENOMEM;
-@@ -706,12 +701,16 @@ static int armada_3700_periph_clock_probe(struct platform_device *pdev)
- 		return -ENOMEM;
- 	driver_data->hw_data->num = num_periph;
- 
-+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	driver_data->reg = devm_ioremap_resource(dev, res);
-+	if (IS_ERR(driver_data->reg))
-+		return PTR_ERR(driver_data->reg);
-+
- 	spin_lock_init(&driver_data->lock);
- 
- 	for (i = 0; i < num_periph; i++) {
- 		struct clk_hw **hw = &driver_data->hw_data->hws[i];
--
--		if (armada_3700_add_composite_clk(&data[i], reg,
-+		if (armada_3700_add_composite_clk(&data[i], driver_data->reg,
- 						  &driver_data->lock, dev, hw))
- 			dev_err(dev, "Can't register periph clock %s\n",
- 				data[i].name);
--- 
-cgit 1.2-0.3.lf.el7
-

patch/kernel/mvebu64-dev/armada-37xx-cpufreq.patch.disabled

@@ -1,80 +0,0 @@
-diff --git a/drivers/cpufreq/armada-37xx-cpufreq.c b/drivers/cpufreq/armada-37xx-cpufreq.c
-index 75491fc84..c2adf380b 100644
---- a/drivers/cpufreq/armada-37xx-cpufreq.c
-+++ b/drivers/cpufreq/armada-37xx-cpufreq.c
-@@ -162,11 +162,25 @@ static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
- 	}
- 
- 	/*
--	 * Set cpu clock source, for all the level we keep the same
--	 * clock source that the one already configured. For this one
--	 * we need to use the clock framework
--	 */
-+	* Set CPU clock source, for all the level we keep the same
-+	* clock source that the one already configured with DVS
-+	* disabled. For this one we need to use the clock framewor
-+	*/
- 	parent = clk_get_parent(clk);
-+
-+	/*
-+	* Unset parent clock to force the clock framework setting again
-+	* the clock parent
-+	*/
-+	clk_set_parent(clk, NULL);
-+
-+	/*
-+	* For the Armada 37xx CPU clocks, setting the parent will
-+	* actually configure the parent when DVFS is enabled. At
-+	* hardware level it will be a different register from the one
-+	* read when doing clk_get_parent that will be set with
-+	* clk_set_parent.
-+	*/
- 	clk_set_parent(clk, parent);
- }
- 
-@@ -359,11 +373,11 @@ static int __init armada37xx_cpufreq_driver_init(void)
- 	struct armada_37xx_dvfs *dvfs;
- 	struct platform_device *pdev;
- 	unsigned long freq;
--	unsigned int cur_frequency;
-+	unsigned int cur_frequency, base_frequency;
- 	struct regmap *nb_pm_base, *avs_base;
- 	struct device *cpu_dev;
- 	int load_lvl, ret;
--	struct clk *clk;
-+	struct clk *clk, *parent;
- 
- 	nb_pm_base =
- 		syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm");
-@@ -399,6 +413,22 @@ static int __init armada37xx_cpufreq_driver_init(void)
- 		return PTR_ERR(clk);
- 	}
- 
-+	parent = clk_get_parent(clk);
-+	if (IS_ERR(parent)) {
-+		dev_err(cpu_dev, "Cannot get parent clock for CPU0\n");
-+		clk_put(clk);
-+		return PTR_ERR(parent);
-+	}
-+
-+	/* Get parent CPU frequency */
-+	base_frequency =  clk_get_rate(parent);
-+
-+	if (!base_frequency) {
-+		dev_err(cpu_dev, "Failed to get parent clock rate for CPU\n");
-+		clk_put(clk);
-+		return -EINVAL;
-+	}
-+
- 	/* Get nominal (current) CPU frequency */
- 	cur_frequency = clk_get_rate(clk);
- 	if (!cur_frequency) {
-@@ -431,7 +461,7 @@ static int __init armada37xx_cpufreq_driver_init(void)
- 	for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
- 	     load_lvl++) {
- 		unsigned long u_volt = avs_map[dvfs->avs[load_lvl]] * 1000;
--		freq = cur_frequency / dvfs->divider[load_lvl];
-+		freq = base_frequency / dvfs->divider[load_lvl];
- 		ret = dev_pm_opp_add(cpu_dev, freq, u_volt);
- 		if (ret)
- 			goto remove_opp;

patch/kernel/mvebu64-dev/fix_problem_with_cpu_scaling_not_working.patch.disabled

@@ -1,57 +0,0 @@
-From 8fe9a4c4a024a6353e810a1dbb5e4bc78bff60a8 Mon Sep 17 00:00:00 2001
-From: FlashBurnGitHub <33546258+FlashBurnGitHub@users.noreply.github.com>
-Date: Wed, 6 Mar 2019 17:25:46 +0100
-Subject: [PATCH] Fix problem with cpu scaling not working
-
-This fixes a problem that the cpu scaling is not working.
-
-First one needs to first unset the parent clock, before setting the same old parent clock again. This solves the problem that the wrong TBG clock source was used for the cpu.
-
-Also one needs to multiply the current cpu frequency with the used divider so that the right cpu frequency gets calculated when applying the dividers. This was need for a 600MHz final cpu frequency to work
----
- drivers/cpufreq/armada-37xx-cpufreq.c | 11 ++++++++++-
- 1 file changed, 10 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/cpufreq/armada-37xx-cpufreq.c b/drivers/cpufreq/armada-37xx-cpufreq.c
-index 75491fc841a6..5c744092f819 100644
---- a/drivers/cpufreq/armada-37xx-cpufreq.c
-+++ b/drivers/cpufreq/armada-37xx-cpufreq.c
-@@ -167,6 +167,11 @@ static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
- 	 * we need to use the clock framework
- 	 */
- 	parent = clk_get_parent(clk);
-+	
-+	/* Unset parent clock */
-+	clk_set_parent(clk, NULL);
-+	
-+	/* set old parent; this triggers setting needed values for right CPU clock in hardware regs */
- 	clk_set_parent(clk, parent);
- }
- 
-@@ -360,6 +365,7 @@ static int __init armada37xx_cpufreq_driver_init(void)
- 	struct platform_device *pdev;
- 	unsigned long freq;
- 	unsigned int cur_frequency;
-+	unsigned int base_frequency;
- 	struct regmap *nb_pm_base, *avs_base;
- 	struct device *cpu_dev;
- 	int load_lvl, ret;
-@@ -412,6 +418,9 @@ static int __init armada37xx_cpufreq_driver_init(void)
- 		clk_put(clk);
- 		return -EINVAL;
- 	}
-+	
-+	/* Get base CPU frequency without divider */
-+	base_frequency = cur_frequency * dvfs->divider[ARMADA_37XX_DVFS_LOAD_0];
- 
- 	armada37xx_cpufreq_state = kmalloc(sizeof(*armada37xx_cpufreq_state),
- 					   GFP_KERNEL);
-@@ -431,7 +440,7 @@ static int __init armada37xx_cpufreq_driver_init(void)
- 	for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
- 	     load_lvl++) {
- 		unsigned long u_volt = avs_map[dvfs->avs[load_lvl]] * 1000;
--		freq = cur_frequency / dvfs->divider[load_lvl];
-+		freq = base_frequency / dvfs->divider[load_lvl];
- 		ret = dev_pm_opp_add(cpu_dev, freq, u_volt);
- 		if (ret)
- 			goto remove_opp;

patch/kernel/mvebu64-dev/need_checking/adjust-espresso-dts.patch

@@ -0,0 +1,91 @@
+diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
+index cd5fbfa38..a81391164 100644
+--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
++++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
+@@ -41,6 +41,16 @@
+ 			  3300000 0x0>;
+ 		enable-active-high;
+ 	};
++	
++	leds {
++		compatible = "gpio-leds";
++
++		red {
++			label = "espressobin:red:usr";
++			gpios = <&gpionb 2 GPIO_ACTIVE_LOW>;
++		};
++	};
++	
+ };
+ 
+ /* J9 */
+@@ -95,19 +105,35 @@
+ 
+ 	flash@0 {
+ 		reg = <0>;
++		/*
++		 * Originally "winbond,w25q32dw", but since the manufacturer is known
++		 * to have replaced the part with "macronix,mx25u3235f" in some board
++		 * batches, just use the generic "jedec,spi-nor" and let the actual
++		 * chip type be probed. The partition table still depends on the chip
++		 * being 4 MiB in size.
++		 */
+ 		compatible = "jedec,spi-nor";
+ 		spi-max-frequency = <104000000>;
+ 		m25p,fast-read;
+-	};
+-};
++		status = "okay";
++		
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
+ 
+-&sdhci0 {
+-	non-removable;
+-	bus-width = <8>;
+-	mmc-ddr-1_8v;
+-	mmc-hs400-1_8v;
+-	marvell,pad-type = "fixed-1-8v";
+-	status = "okay";
++			partition@0 {
++				label = "uboot";
++				reg = <0 0x3f0000>;
++			};
++
++			partition@180000 {
++				label = "ubootenv";
++				reg = <0x3f0000 0x10000>;
++			};
++		};
++		
++	};
+ };
+ 
+ /* Exported on the micro USB connector J5 through an FTDI */
+@@ -137,11 +163,6 @@
+ 	status = "okay";
+ };
+ 
+-/* J8 */
+-&usb2 {
+-	status = "okay";
+-};
+-
+ &mdio {
+ 	switch0: switch0@1 {
+ 		compatible = "marvell,mv88e6085";
+@@ -199,12 +220,6 @@
+ 			switch0phy2: switch0phy2@13 {
+ 				reg = <0x13>;
+ 			};
+-			
+-			partition@190000 {
+-				label = "Linux";
+-				reg = <0x190000 0xDF0000>;
+-			}; 
+-			
+ 		};
+ 	};
+ };