Cleanup old patches
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Jannis
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af05f254da
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b46ed4c46c
@ -1,196 +0,0 @@
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diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
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index 53b79c5..7980be0 100644
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--- a/drivers/pci/controller/pci-mvebu.c
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+++ b/drivers/pci/controller/pci-mvebu.c
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@@ -51,7 +51,14 @@
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PCIE_CONF_ADDR_EN)
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#define PCIE_CONF_DATA_OFF 0x18fc
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#define PCIE_MASK_OFF 0x1910
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+#define PCIE_MASK_PM_PME BIT(28)
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#define PCIE_MASK_ENABLE_INTS 0x0f000000
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+#define PCIE_MASK_ERR_COR BIT(18)
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+#define PCIE_MASK_ERR_NONFATAL BIT(17)
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+#define PCIE_MASK_ERR_FATAL BIT(16)
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+#define PCIE_MASK_FERR_DET BIT(10)
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+#define PCIE_MASK_NFERR_DET BIT(9)
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+#define PCIE_MASK_CORERR_DET BIT(8)
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#define PCIE_CTRL_OFF 0x1a00
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#define PCIE_CTRL_X1_MODE 0x0001
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#define PCIE_STAT_OFF 0x1a04
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@@ -455,6 +462,54 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
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MVEBU_MBUS_NO_REMAP);
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}
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+static void mvebu_pcie_handle_irq_change(struct mvebu_pcie_port *port)
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+{
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+ u32 reg, old;
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+ u16 devctl, rtctl;
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+
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+ /*
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+ * Errors from downstream devices:
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+ * bridge control register SERR: enables reception of errors
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+ * Errors from this device, or received errors:
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+ * command SERR: enables ERR_NONFATAL and ERR_FATAL messages
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+ * => when enabled, these conditions also flag SERR in status register
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+ * devctl CERE: enables ERR_CORR messages
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+ * devctl NFERE: enables ERR_NONFATAL messages
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+ * devctl FERE: enables ERR_FATAL messages
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+ * Enabled messages then have three paths:
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+ * 1. rtctl: enables system error indication
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+ * 2. root error status register updated
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+ * 3. root error command register: forwarding via MSI
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+ */
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+ old = mvebu_readl(port, PCIE_MASK_OFF);
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+ reg = old & ~(PCIE_MASK_PM_PME | PCIE_MASK_FERR_DET |
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+ PCIE_MASK_NFERR_DET | PCIE_MASK_CORERR_DET |
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+ PCIE_MASK_ERR_COR | PCIE_MASK_ERR_NONFATAL |
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+ PCIE_MASK_ERR_FATAL);
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+
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+ devctl = port->bridge.pcie_devctl;
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+ if (devctl & PCI_EXP_DEVCTL_FERE)
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+ reg |= PCIE_MASK_FERR_DET | PCIE_MASK_ERR_FATAL;
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+ if (devctl & PCI_EXP_DEVCTL_NFERE)
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+ reg |= PCIE_MASK_NFERR_DET | PCIE_MASK_ERR_NONFATAL;
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+ if (devctl & PCI_EXP_DEVCTL_CERE)
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+ reg |= PCIE_MASK_CORERR_DET | PCIE_MASK_ERR_COR;
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+ if (port->bridge.command & PCI_COMMAND_SERR)
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+ reg |= PCIE_MASK_FERR_DET | PCIE_MASK_NFERR_DET |
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+ PCIE_MASK_ERR_FATAL | PCIE_MASK_ERR_NONFATAL;
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+
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+ if (!(port->bridge.bridgectrl & PCI_BRIDGE_CTL_SERR))
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+ reg &= ~(PCIE_MASK_ERR_COR | PCIE_MASK_ERR_NONFATAL |
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+ PCIE_MASK_ERR_FATAL);
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+
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+ rtctl = port->bridge.pcie_rtctl;
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+ if (rtctl & PCI_EXP_RTCTL_PMEIE)
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+ reg |= PCIE_MASK_PM_PME;
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+
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+ if (old != reg)
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+ mvebu_writel(port, reg, PCIE_MASK_OFF);
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+}
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+
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/*
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* Initialize the configuration space of the PCI-to-PCI bridge
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* associated with the given PCIe interface.
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@@ -478,6 +533,7 @@ static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
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/* Add capabilities */
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bridge->status = PCI_STATUS_CAP_LIST;
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+ bridge->bridgectrl = PCI_BRIDGE_CTL_SERR;
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}
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/*
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@@ -550,7 +606,7 @@ static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
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case PCI_INTERRUPT_LINE:
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/* LINE PIN MIN_GNT MAX_LAT */
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- *value = 0;
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+ *value = bridge->bridgectrl << 16;
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break;
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case PCISWCAP_EXP_LIST_ID:
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@@ -599,6 +655,16 @@ static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
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*value = mvebu_readl(port, PCIE_RC_RTSTA);
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break;
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+ case 0x100 ... 0x128:
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+ *value = mvebu_readl(port, where & ~3);
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+ break;
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+
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+ case 0x100 + PCI_ERR_ROOT_COMMAND:
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+ case 0x100 + PCI_ERR_ROOT_STATUS:
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+ case 0x100 + PCI_ERR_ROOT_ERR_SRC:
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+ *value = 0;
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+ break;
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+
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/* PCIe requires the v2 fields to be hard-wired to zero */
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case PCISWCAP_EXP_DEVCAP2:
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case PCISWCAP_EXP_DEVCTL2:
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@@ -629,7 +695,7 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
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unsigned int where, int size, u32 value)
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{
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struct mvebu_sw_pci_bridge *bridge = &port->bridge;
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- u32 mask, reg;
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+ u32 mask, reg, old;
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int err;
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if (size == 4)
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@@ -649,8 +715,7 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
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switch (where & ~3) {
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case PCI_COMMAND:
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- {
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- u32 old = bridge->command;
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+ old = bridge->command;
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if (!mvebu_has_ioport(port))
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value &= ~PCI_COMMAND_IO;
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@@ -660,8 +725,9 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
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mvebu_pcie_handle_iobase_change(port);
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if ((old ^ bridge->command) & PCI_COMMAND_MEMORY)
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mvebu_pcie_handle_membase_change(port);
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+ if ((old ^ bridge->command) & PCI_COMMAND_SERR)
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+ mvebu_pcie_handle_irq_change(port);
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break;
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- }
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case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
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bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
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@@ -690,6 +756,17 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
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mvebu_pcie_handle_iobase_change(port);
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break;
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+ case PCI_INTERRUPT_LINE:
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+ value >>= 16;
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+ old = bridge->bridgectrl;
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+ /* PCIe only has three bits here */
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+ bridge->bridgectrl = value & (PCI_BRIDGE_CTL_BUS_RESET |
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+ PCI_BRIDGE_CTL_SERR |
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+ PCI_BRIDGE_CTL_PARITY);
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+ if ((old ^ bridge->bridgectrl) & PCI_BRIDGE_CTL_SERR)
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+ mvebu_pcie_handle_irq_change(port);
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+ break;
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+
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case PCI_PRIMARY_BUS:
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bridge->primary_bus = value & 0xff;
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bridge->secondary_bus = (value >> 8) & 0xff;
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@@ -699,6 +776,14 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
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break;
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case PCISWCAP_EXP_DEVCTL:
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+ old = bridge->pcie_devctl;
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+ bridge->pcie_devctl = value & (PCI_EXP_DEVCTL_FERE |
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+ PCI_EXP_DEVCTL_NFERE |
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+ PCI_EXP_DEVCTL_CERE |
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+ PCI_EXP_DEVCTL_URRE);
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+ if (bridge->pcie_devctl ^ old)
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+ mvebu_pcie_handle_irq_change(port);
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+
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/*
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* Armada370 data says these bits must always
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* be zero when in root complex mode.
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@@ -739,10 +824,24 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
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mvebu_writel(port, value, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
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break;
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+ case PCISWCAP_EXP_RTCTL:
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+ old = bridge->pcie_rtctl;
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+ bridge->pcie_rtctl = value & (PCI_EXP_RTCTL_SECEE |
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+ PCI_EXP_RTCTL_SENFEE |
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+ PCI_EXP_RTCTL_SEFEE |
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+ PCI_EXP_RTCTL_PMEIE);
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+ if (bridge->pcie_rtctl ^ old)
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+ mvebu_pcie_handle_irq_change(port);
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+ break;
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+
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case PCISWCAP_EXP_RTSTA:
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mvebu_writel(port, value, PCIE_RC_RTSTA);
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break;
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+ case 0x100 ... 0x128:
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+ mvebu_writel(port, value, where & ~3);
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+ break;
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+
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default:
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break;
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}
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@ -1,67 +0,0 @@
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From ae07b208fe4e228068282ad76cfd69ab9e96dc9f Mon Sep 17 00:00:00 2001
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From: Russell King <rmk+kernel@arm.linux.org.uk>
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Date: Mon, 28 Dec 2015 13:55:13 +0100
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Subject: [PATCH] implement slot capabilities (SSPL)
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---
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drivers/pci/controller/pci-mvebu.c | 22 ++++++++++++++++++++--
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1 file changed, 20 insertions(+), 2 deletions(-)
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diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
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index 7980be0..0e9b820 100644
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--- a/drivers/pci/controller/pci-mvebu.c
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+++ b/drivers/pci/controller/pci-mvebu.c
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@@ -65,6 +65,12 @@
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#define PCIE_STAT_BUS 0xff00
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#define PCIE_STAT_DEV 0x1f0000
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#define PCIE_STAT_LINK_DOWN BIT(0)
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+#define PCIE_SSPL 0x1a0c
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+#define PCIE_SSPL_MSGEN BIT(14)
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+#define PCIE_SSPL_SPLS(x) (((x) & 3) << 8)
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+#define PCIE_SSPL_SPLS_VAL(x) (((x) >> 8) & 3)
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+#define PCIE_SSPL_SPLV(x) ((x) & 0xff)
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+#define PCIE_SSPL_SPLV_VAL(x) ((x) & 0xff)
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#define PCIE_RC_RTSTA 0x1a14
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#define PCIE_DEBUG_CTRL 0x1a60
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#define PCIE_DEBUG_SOFT_RESET BIT(20)
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@@ -119,7 +125,6 @@ struct mvebu_sw_pci_bridge {
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u16 bridgectrl;
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/* PCI express capability */
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- u32 pcie_sltcap;
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u16 pcie_devctl;
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u16 pcie_rtctl;
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};
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@@ -640,8 +645,12 @@ static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
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break;
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case PCISWCAP_EXP_SLTCAP:
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- *value = bridge->pcie_sltcap;
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+ {
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+ u32 tmp = mvebu_readl(port, PCIE_SSPL);
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+ *value = PCIE_SSPL_SPLS_VAL(tmp) << 15 |
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+ PCIE_SSPL_SPLV_VAL(tmp) << 7;
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break;
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+ }
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case PCISWCAP_EXP_SLTCTL:
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*value = PCI_EXP_SLTSTA_PDS << 16;
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@@ -824,6 +833,15 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
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mvebu_writel(port, value, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
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break;
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+ case PCISWCAP_EXP_SLTCAP:
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+ {
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+ u32 sspl = PCIE_SSPL_SPLV((value & PCI_EXP_SLTCAP_SPLV) >> 7) |
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+ PCIE_SSPL_SPLS((value & PCI_EXP_SLTCAP_SPLS) >> 15) |
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+ PCIE_SSPL_MSGEN;
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+ mvebu_writel(port, sspl, PCIE_SSPL);
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+ break;
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+ }
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+
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case PCISWCAP_EXP_RTCTL:
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old = bridge->pcie_rtctl;
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bridge->pcie_rtctl = value & (PCI_EXP_RTCTL_SECEE |
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--
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1.9.1
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