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rockchip64: tidy up rk3328 patches

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* remove 0-rever-rk3328.dtsi-.patch
 * split rk3328-dtsi-mmc-vdec-usb3-tweaks.patch into different specific patches (sdmmc-ext, mmc-reset, power domains, usb3 resets)
 * split rk3328-audio-and-renegade-supplies.patch into specific roc-cc audio and supplies patch and general rk3328 spdif patch
 * add "dtsi" infix to rk3328 patches that deal with dtsi files
 * add back mali gpu operating points patch
This commit is contained in:
Paolo Sabatino 2021-09-25 15:47:30 +00:00 committed by Paolo
parent 71e6cf9ab3
commit a71ef23575
10 changed files with 266 additions and 237 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

46
patch/kernel/archive/rockchip64-5.14/need_checking/0-revert-rk3328-dtsi-.patch
View File

@ -1,46 +0,0 @@
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -984,24 +984,24 @@
status = "disabled";
};
- usbdrd3: usb@ff600000 {
- compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
- reg = <0x0 0xff600000 0x0 0x100000>;
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
- <&cru ACLK_USB3OTG>;
- clock-names = "ref_clk", "suspend_clk",
- "bus_clk";
- dr_mode = "otg";
- phy_type = "utmi_wide";
- snps,dis-del-phy-power-chg-quirk;
- snps,dis_enblslpm_quirk;
- snps,dis-tx-ipgap-linecheck-quirk;
- snps,dis-u2-freeclk-exists-quirk;
- snps,dis_u2_susphy_quirk;
- snps,dis_u3_susphy_quirk;
- status = "disabled";
- };
+// usbdrd3: usb@ff600000 {
+// compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
+// reg = <0x0 0xff600000 0x0 0x100000>;
+// interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+// clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
+// <&cru ACLK_USB3OTG>;
+// clock-names = "ref_clk", "suspend_clk",
+// "bus_clk";
+// dr_mode = "otg";
+// phy_type = "utmi_wide";
+// snps,dis-del-phy-power-chg-quirk;
+// snps,dis_enblslpm_quirk;
+// snps,dis-tx-ipgap-linecheck-quirk;
+// snps,dis-u2-freeclk-exists-quirk;
+// snps,dis_u2_susphy_quirk;
+// snps,dis_u3_susphy_quirk;
+// status = "disabled";
+// };
gic: interrupt-controller@ff811000 {
compatible = "arm,gic-400";

113
patch/kernel/archive/rockchip64-5.14/need_checking/rk3328-dtsi-mmc-vdec-usb3-tweaks.patch
View File

@ -1,113 +0,0 @@
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -346,12 +346,16 @@
power-domain@RK3328_PD_HEVC {
reg = <RK3328_PD_GPU>;
clocks = <&cru ACLK_GPU>;
- };
+ };
power-domain@RK3328_PD_HEVC {
reg = <RK3328_PD_HEVC>;
};
power-domain@RK3328_PD_VIDEO {
reg = <RK3328_PD_VIDEO>;
+ clocks = <&cru ACLK_RKVDEC>,
+ <&cru HCLK_RKVDEC>,
+ <&cru SCLK_VDEC_CABAC>,
+ <&cru SCLK_VDEC_CORE>;
};
power-domain@RK3328_PD_VPU {
reg = <RK3328_PD_VPU>;
@@ -705,6 +709,7 @@
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
+ power-domains = <&power RK3328_PD_VIDEO>;
status = "disabled";
};
@@ -935,6 +940,8 @@
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <150000000>;
+ resets = <&cru SRST_MMC0>;
+ reset-names = "reset";
status = "disabled";
};
@@ -947,6 +954,8 @@
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <150000000>;
+ resets = <&cru SRST_SDIO>;
+ reset-names = "reset";
status = "disabled";
};
@@ -959,6 +968,8 @@
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <150000000>;
+ resets = <&cru SRST_EMMC>;
+ reset-names = "reset";
status = "disabled";
};
@@ -1056,25 +1067,41 @@
status = "disabled";
};
+ sdmmc_ext: dwmmc@ff5f0000 {
+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff5f0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>,
+ <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <150000000>;
+ resets = <&cru SRST_SDMMCEXT>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
usbdrd3: usb@ff600000 {
compatible = "rockchip,rk3328-dwc3", "rockchip,rk3399-dwc3";
- clocks = <&cru SCLK_USB3OTG_REF>, <&cru ACLK_USB3OTG>,
- <&cru SCLK_USB3OTG_SUSPEND>;
- clock-names = "ref", "bus_early",
- "suspend";
+ clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
+ <&cru ACLK_USB3OTG>;
+ clock-names = "ref_clk", "suspend_clk",
+ "bus_clk";
+ resets = <&cru SRST_USB3OTG>;
+ reset-names = "usb3-otg";
#address-cells = <2>;
#size-cells = <2>;
ranges;
- clock-ranges;
status = "disabled";
usbdrd_dwc3: dwc3@ff600000 {
compatible = "snps,dwc3";
reg = <0x0 0xff600000 0x0 0x100000>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_USB3OTG_REF>, <&cru ACLK_USB3OTG>,
+ <&cru SCLK_USB3OTG_SUSPEND>;
+ clock-names = "ref", "bus_early", "suspend";
dr_mode = "otg";
- phys = <&u3phy_utmi>, <&u3phy_pipe>;
- phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
snps,dis_enblslpm_quirk;
snps,dis-u2-freeclk-exists-quirk;
@@ -1082,7 +1109,6 @@
snps,dis_u3_susphy_quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
- snps,xhci-trb-ent-quirk;
status = "disabled";
};
};

90
patch/kernel/archive/rockchip64-5.14/rk3328-audio-and-renegade-supplies.patch → patch/kernel/archive/rockchip64-5.14/rk3328-dts-roc-cc-audio-supplies.patch
View File

@ -5,7 +5,7 @@ index f4b6799a8..a1041ec3e 100644
@@ -21,33 +21,24 @@
#clock-cells = <0>;
};
- dc_12v: dc-12v {
- compatible = "regulator-fixed";
- regulator-name = "dc_12v";
@ -27,7 +27,7 @@ index f4b6799a8..a1041ec3e 100644
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_io>;
};
- vcc_sdio: sdmmcio-regulator {
+ vccio_sd: sdmmcio-regulator {
compatible = "regulator-gpio";
@ -49,7 +49,7 @@ index f4b6799a8..a1041ec3e 100644
regulator-max-microvolt = <5000000>;
- vin-supply = <&dc_12v>;
};
vcc_phy: vcc-phy-regulator {
@@ -82,7 +71,24 @@
regulator-always-on;
@ -88,7 +88,7 @@ index f4b6799a8..a1041ec3e 100644
@@ -152,6 +156,10 @@
status = "okay";
};
+&gpu {
+ mali-supply = <&vdd_logic>;
+};
@ -99,14 +99,14 @@ index f4b6799a8..a1041ec3e 100644
@@ -160,6 +168,10 @@
status = "okay";
};
+&hdmi_sound {
+ status = "okay";
+};
+
&i2c1 {
status = "okay";
@@ -187,8 +199,9 @@
regulators {
vdd_logic: DCDC_REG1 {
@ -120,7 +120,7 @@ index f4b6799a8..a1041ec3e 100644
regulator-boot-on;
regulator-state-mem {
@@ -199,8 +212,9 @@
vdd_arm: DCDC_REG2 {
regulator-name = "vdd_arm";
- regulator-min-microvolt = <712500>;
@ -134,7 +134,7 @@ index f4b6799a8..a1041ec3e 100644
@@ -269,12 +283,20 @@
};
};
+&i2s0 {
+ status = "okay";
+};
@ -145,7 +145,7 @@ index f4b6799a8..a1041ec3e 100644
+
&io_domains {
status = "okay";
vccio1-supply = <&vcc_io>;
vccio2-supply = <&vcc18_emmc>;
- vccio3-supply = <&vcc_sdio>;
@ -155,7 +155,7 @@ index f4b6799a8..a1041ec3e 100644
vccio6-supply = <&vcc_io>;
@@ -282,6 +304,12 @@
};
&pinctrl {
+ ir {
+ ir_int: ir-int {
@ -187,76 +187,10 @@ index f4b6799a8..a1041ec3e 100644
+&spdif_sound {
status = "okay";
};
&tsadc {
+ rockchip,hw-tshut-mode = <0>;
+ rockchip,hw-tshut-polarity = <0>;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index eedc25132..5c62f0116 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -210,6 +210,26 @@
method = "smc";
};
+ spdif_out: spdif-out {
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ spdif_sound: spdif-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "SPDIF";
+ status = "disabled";
+
+ simple-audio-card,cpu {
+ sound-dai = <&spdif>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&spdif_out>;
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@@ -319,6 +339,10 @@
#address-cells = <1>;
#size-cells = <0>;
+ power-domain@RK3328_PD_GPU {
+ reg = <RK3328_PD_GPU>;
+ clocks = <&cru ACLK_GPU>;
+ };
power-domain@RK3328_PD_HEVC {
reg = <RK3328_PD_HEVC>;
};
@@ -621,6 +645,7 @@
"ppmmu1";
clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
clock-names = "bus", "core";
+ power-domains = <&power RK3328_PD_GPU>;
resets = <&cru SRST_GPU_A>;
};
@@ -793,6 +818,7 @@
<&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
<&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
<&cru HCLK_PERI>, <&cru PCLK_PERI>,
+ <&cru ACLK_GPU>,
<&cru SCLK_RTC32K>;
assigned-clock-parents =
<&cru HDMIPHY>, <&cru PLL_APLL>,
@@ -814,6 +840,7 @@
<150000000>, <75000000>,
<75000000>, <150000000>,
<75000000>, <75000000>,
+ <500000000>,
<32768>;
};

0
patch/kernel/archive/rockchip64-5.14/rk3328-fix-mali-node.patch → patch/kernel/archive/rockchip64-5.14/rk3328-dtsi-fix-mali-node.patch
View File

48
patch/kernel/archive/rockchip64-5.14/rk3328-dtsi-mali-opp-table.patch Normal file
View File

@ -0,0 +1,48 @@
From 6ad5abe4a75d50cb6abfd1aff35ebba4998336df Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sat, 25 Sep 2021 15:26:41 +0000
Subject: [PATCH] gpu operating points
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 25 ++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index c52c2a363..a69e40ee4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -646,6 +646,31 @@ gpu: gpu@ff300000 {
clock-names = "bus", "core";
power-domains = <&power RK3328_PD_GPU>;
resets = <&cru SRST_GPU_A>;
+ operating-points-v2 = <&gpu_opp_table>;
+ };
+
+ gpu_opp_table: gpu-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <950000>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <975000>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1050000>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1150000>;
+ };
};
h265e_mmu: iommu@ff330200 {
--
2.30.2

43
patch/kernel/archive/rockchip64-5.14/rk3328-dtsi-mmc-reset-properties.patch Normal file
View File

@ -0,0 +1,43 @@
From 169dff618823d0764624895413ac7cf0f0306e79 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sat, 25 Sep 2021 13:35:13 +0000
Subject: [PATCH 2/4] mmc reset properties
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index a261c8f54..2a9fecc7d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -902,6 +902,8 @@ sdmmc: mmc@ff500000 {
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ resets = <&cru SRST_MMC0>;
+ reset-names = "reset";
fifo-depth = <0x100>;
max-frequency = <150000000>;
status = "disabled";
@@ -914,6 +916,8 @@ sdio: mmc@ff510000 {
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ resets = <&cru SRST_SDIO>;
+ reset-names = "reset";
fifo-depth = <0x100>;
max-frequency = <150000000>;
status = "disabled";
@@ -926,6 +930,8 @@ emmc: mmc@ff520000 {
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ resets = <&cru SRST_EMMC>;
+ reset-names = "reset";
fifo-depth = <0x100>;
max-frequency = <150000000>;
status = "disabled";
--
2.30.2

35
patch/kernel/archive/rockchip64-5.14/rk3328-dtsi-rkvdec-power-domains.patch Normal file
View File

@ -0,0 +1,35 @@
From ea0e3b2d83bcc7a3a3b901d0cd9c55fa8a8a6c93 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sat, 25 Sep 2021 13:34:04 +0000
Subject: [PATCH 1/4] add rkvdec power domains
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 957daa4f4..a261c8f54 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -307,6 +307,10 @@ power-domain@RK3328_PD_HEVC {
power-domain@RK3328_PD_VIDEO {
reg = <RK3328_PD_VIDEO>;
#power-domain-cells = <0>;
+ clocks = <&cru ACLK_RKVDEC>,
+ <&cru HCLK_RKVDEC>,
+ <&cru SCLK_VDEC_CABAC>,
+ <&cru SCLK_VDEC_CORE>;
};
power-domain@RK3328_PD_VPU {
reg = <RK3328_PD_VPU>;
@@ -671,6 +675,7 @@ rkvdec_mmu: iommu@ff360480 {
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
+ power-domains = <&power RK3328_PD_VIDEO>;
status = "disabled";
};
--
2.30.2

37
patch/kernel/archive/rockchip64-5.14/rk3328-dtsi-sdmmc-ext-node.patch Normal file
View File

@ -0,0 +1,37 @@
From b3a4ba23d01ad2825a1efd013090f6c6bb352679 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sat, 25 Sep 2021 13:36:20 +0000
Subject: [PATCH 3/4] sdmmc-ext node
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 2a9fecc7d..48b170c63 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -937,6 +937,20 @@ emmc: mmc@ff520000 {
status = "disabled";
};
+ sdmmc_ext: dwmmc@ff5f0000 {
+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff5f0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>,
+ <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <150000000>;
+ resets = <&cru SRST_SDMMCEXT>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
gmac2io: ethernet@ff540000 {
compatible = "rockchip,rk3328-gmac";
reg = <0x0 0xff540000 0x0 0x10000>;
--
2.30.2

66
patch/kernel/archive/rockchip64-5.14/rk3328-dtsi-spdif.patch Normal file
View File

@ -0,0 +1,66 @@
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index eedc25132..5c62f0116 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -210,6 +210,26 @@
method = "smc";
};
+ spdif_out: spdif-out {
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ spdif_sound: spdif-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "SPDIF";
+ status = "disabled";
+
+ simple-audio-card,cpu {
+ sound-dai = <&spdif>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&spdif_out>;
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@@ -319,6 +339,10 @@
#address-cells = <1>;
#size-cells = <0>;
+ power-domain@RK3328_PD_GPU {
+ reg = <RK3328_PD_GPU>;
+ clocks = <&cru ACLK_GPU>;
+ };
power-domain@RK3328_PD_HEVC {
reg = <RK3328_PD_HEVC>;
};
@@ -621,6 +645,7 @@
"ppmmu1";
clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
clock-names = "bus", "core";
+ power-domains = <&power RK3328_PD_GPU>;
resets = <&cru SRST_GPU_A>;
};
@@ -793,6 +818,7 @@
<&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
<&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
<&cru HCLK_PERI>, <&cru PCLK_PERI>,
+ <&cru ACLK_GPU>,
<&cru SCLK_RTC32K>;
assigned-clock-parents =
<&cru HDMIPHY>, <&cru PLL_APLL>,
@@ -814,6 +840,7 @@
<150000000>, <75000000>,
<75000000>, <150000000>,
<75000000>, <75000000>,
+ <500000000>,
<32768>;
};

25
patch/kernel/archive/rockchip64-5.14/rk3328-dtsi-usb3-reset-properties.patch Normal file
View File

@ -0,0 +1,25 @@
From 2cc5008e97eacc69e4f4d42b733e84caa048ef9f Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sat, 25 Sep 2021 13:39:40 +0000
Subject: [PATCH 4/4] usb3 reset properties
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 48b170c63..b79c67df5 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -1054,6 +1054,8 @@ usbdrd3: usb@ff600000 {
<&cru ACLK_USB3OTG>;
clock-names = "ref_clk", "suspend_clk",
"bus_clk";
+ resets = <&cru SRST_USB3OTG>;
+ reset-names = "usb3-otg";
dr_mode = "otg";
phy_type = "utmi_wide";
snps,dis-del-phy-power-chg-quirk;
--
2.30.2