enoch/armbian-build
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

patch: sm8250: current: some reasonable modifications were made

Browse Source 
Based on the AI review

Co-authored-by: retro98boy <retro98boy@qq.com>
Signed-off-by: CodeChenL <2540735020@qq.com>
This commit is contained in:
Jiali Chen 2026-01-25 07:59:17 +00:00 committed by Igor
parent 446fdd8bfa
commit 9aa6e1e29e
6 changed files with 72 additions and 58 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
patch/kernel/archive/sm8250-6.18/0005-ASoC-qcom-sm8250-Add-tdm-support.patch
View File

@ -5,8 +5,8 @@ Subject: [PATCH 05/62] ASoC: qcom: sm8250: Add tdm support
Signed-off-by: Jiali Chen <chenjiali@radxa.com>
---
sound/soc/qcom/sm8250.c | 75 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 75 insertions(+)
sound/soc/qcom/sm8250.c | 83 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 83 insertions(+)
diff --git a/sound/soc/qcom/sm8250.c b/sound/soc/qcom/sm8250.c
index f5b75a06e5bd..a383f74c5187 100644
@ -88,29 +88,37 @@ index f5b75a06e5bd..a383f74c5187 100644
switch (cpu_dai->id) {
case PRIMARY_MI2S_RX:
@@ -105,6 +160,21 @@ static int sm8250_snd_startup(struct snd_pcm_substream *substream)
@@ -105,6 +160,29 @@ static int sm8250_snd_startup(struct snd_pcm_substream *substream)
snd_soc_dai_set_fmt(cpu_dai, fmt);
snd_soc_dai_set_fmt(codec_dai, codec_dai_fmt);
break;
+ case TERTIARY_TDM_RX_0:
+ codec_dai_fmt |= SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_DSP_A;
+ snd_soc_dai_set_sysclk(cpu_dai,
+ ret = snd_soc_dai_set_sysclk(cpu_dai,
+ Q6AFE_LPASS_CLK_ID_TER_TDM_IBIT,
+ TDM_BCLK_RATE, SNDRV_PCM_STREAM_PLAYBACK);
+ if (ret < 0) {
+ dev_err(rtd->dev, "TDM cpu sysclk err:%d\n", ret);
+ return ret;
+ }
+
+ for_each_rtd_codec_dais(rtd, j, codec_dai) {
+ ret = snd_soc_dai_set_fmt(codec_dai, codec_dai_fmt);
+ snd_soc_dai_set_sysclk(codec_dai, 0, TDM_BCLK_RATE, SNDRV_PCM_STREAM_PLAYBACK);
+ if (ret < 0) {
+ dev_err(rtd->dev, "TDM fmt err:%d\n", ret);
+ return ret;
+ }
+ ret = snd_soc_dai_set_sysclk(codec_dai, 0, TDM_BCLK_RATE, SNDRV_PCM_STREAM_PLAYBACK);
+ if (ret < 0) {
+ dev_err(rtd->dev, "TDM sysclk err:%d\n", ret);
+ return ret;
+ }
+ }
+ break;
default:
break;
}
@@ -130,6 +200,11 @@ static int sm8250_snd_hw_params(struct snd_pcm_substream *substream,
@@ -130,6 +208,11 @@ static int sm8250_snd_hw_params(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
struct sm8250_snd_data *pdata = snd_soc_card_get_drvdata(rtd->card);

9
patch/kernel/archive/sm8250-6.18/0008-arm64-dts-qcom-sm8250-oneplus-instantnoodlep-Add-dev.patch
View File

@ -7,15 +7,15 @@ Subject: [PATCH 08/62] arm64: dts: qcom: sm8250-oneplus-instantnoodlep: Add
Signed-off-by: Jiali Chen <chenjiali@radxa.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../qcom/sm8250-oneplus-instantnoodlep.dts | 832 ++++++++++++++++++
2 files changed, 833 insertions(+)
.../qcom/sm8250-oneplus-instantnoodlep.dts | 831 ++++++++++++++++++
2 files changed, 832 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sm8250-oneplus-instantnoodlep.dts
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 4bfa926b6a08..4dc01668765d 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -275,6 +275,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-bahamut.dtb
@@ -281,6 +281,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-bahamut.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-griffin.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb
@ -28,7 +28,7 @@ new file mode 100644
index 000000000000..2ff46c2979e5
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8250-oneplus-instantnoodlep.dts
@@ -0,0 +1,832 @@
@@ -0,0 +1,831 @@
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
@ -596,7 +596,6 @@ index 000000000000..2ff46c2979e5
+
+ charger@66 {
+ compatible = "ti,bq25980";
+ status = "ok";
+ reg = <0x66>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <0x0f 0x00>;

14
patch/kernel/archive/sm8250-6.18/0013-input-nt36xxx-Enable-pen-support.patch
View File

@ -5,10 +5,10 @@ Subject: [PATCH 13/62] input: nt36xxx: Enable pen support
Signed-off-by: Jiali Chen <chenjiali@radxa.com>
---
drivers/input/touchscreen/nt36523/nt36xxx.c | 47 +++++++++++++++++--
drivers/input/touchscreen/nt36523/nt36xxx.c | 49 +++++++++++++++++--
drivers/input/touchscreen/nt36523/nt36xxx.h | 1 +
.../touchscreen/nt36523/nt36xxx_fw_update.c | 1 +
3 files changed, 45 insertions(+), 4 deletions(-)
3 files changed, 47 insertions(+), 4 deletions(-)
diff --git a/drivers/input/touchscreen/nt36523/nt36xxx.c b/drivers/input/touchscreen/nt36523/nt36xxx.c
index 63c584f681d7..3a87a38a7780 100644
@ -82,14 +82,16 @@ index 63c584f681d7..3a87a38a7780 100644
}
if (ts->db_wakeup) {
@@ -1798,6 +1836,7 @@ static int32_t nvt_ts_resume(struct device *dev)
@@ -1796,6 +1834,9 @@ static int32_t nvt_ts_resume(struct device *dev)
bTouchIsAwake = 1;
+ NVT_LOG("always enable pen when resume");
+ disable_pen_input_device(false);
+
mutex_unlock(&ts->lock);
+ disable_pen_input_device(false);
if (likely(ts->ic_state == NVT_IC_RESUME_IN)) {
ts->ic_state = NVT_IC_RESUME_OUT;
} else {
diff --git a/drivers/input/touchscreen/nt36523/nt36xxx.h b/drivers/input/touchscreen/nt36523/nt36xxx.h
index 6642ec2f26cf..33c7614436b0 100644
--- a/drivers/input/touchscreen/nt36523/nt36xxx.h

37
patch/kernel/archive/sm8250-6.18/0024-power-supply-Add-driver-for-Qualcomm-PMIC-fuel-gauge.patch
View File

@ -33,15 +33,15 @@ Signed-off-by: Jiali Chen <chenjiali@radxa.com>
---
drivers/power/supply/Kconfig | 8 +
drivers/power/supply/Makefile | 1 +
drivers/power/supply/qcom_fg.c | 1320 ++++++++++++++++++++++++++++++++
3 files changed, 1329 insertions(+)
drivers/power/supply/qcom_fg.c | 1325 ++++++++++++++++++++++++++++++++
3 files changed, 1334 insertions(+)
create mode 100644 drivers/power/supply/qcom_fg.c
diff --git a/drivers/power/supply/Kconfig b/drivers/power/supply/Kconfig
index 6e0559e6baed..e138bdc837a7 100644
--- a/drivers/power/supply/Kconfig
+++ b/drivers/power/supply/Kconfig
@@ -1083,4 +1083,12 @@ config FUEL_GAUGE_MM8013
@@ -1106,4 +1106,12 @@ config FUEL_GAUGE_MM8013
the state of charge, temperature, cycle count, actual and design
capacity, etc.
@ -58,7 +58,7 @@ diff --git a/drivers/power/supply/Makefile b/drivers/power/supply/Makefile
index 60aec804ca8f..921cf6aac741 100644
--- a/drivers/power/supply/Makefile
+++ b/drivers/power/supply/Makefile
@@ -123,3 +123,4 @@ obj-$(CONFIG_CHARGER_SURFACE) += surface_charger.o
@@ -126,3 +126,4 @@ obj-$(CONFIG_CHARGER_SURFACE) += surface_charger.o
obj-$(CONFIG_BATTERY_UG3105) += ug3105_battery.o
obj-$(CONFIG_CHARGER_QCOM_SMB2) += qcom_smbx.o
obj-$(CONFIG_FUEL_GAUGE_MM8013) += mm8013.o
@ -68,7 +68,7 @@ new file mode 100644
index 000000000000..f8dd93aa23c7
--- /dev/null
+++ b/drivers/power/supply/qcom_fg.c
@@ -0,0 +1,1320 @@
@@ -0,0 +1,1325 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2020, The Linux Foundation. All rights reserved. */
+
@ -451,6 +451,8 @@ index 000000000000..f8dd93aa23c7
+ }
+
+ while(len > 0) {
+ int read_len = min(len, 4 - offset);
+
+ /* Set SRAM address register */
+ ret = qcom_fg_write(chip, (u8 *) &addr,
+ MEM_INTF_ADDR_LSB, 2);
@ -460,15 +462,15 @@ index 000000000000..f8dd93aa23c7
+ }
+
+ ret = qcom_fg_read(chip, rd_data,
+ MEM_INTF_RD_DATA0 + offset, len);
+ MEM_INTF_RD_DATA0 + offset, read_len);
+
+ addr += 4;
+
+ if (ret)
+ goto out;
+
+ rd_data += 4 - offset;
+ len -= 4 - offset;
+ rd_data += read_len;
+ len -= read_len;
+ offset = 0;
+ }
+out:
@ -502,7 +504,7 @@ index 000000000000..f8dd93aa23c7
+ spin_lock(&chip->sram_rw_lock);
+
+ dev_vdbg(chip->dev,
+ "Wrtiting address 0x%x with offset %d of length %d to SRAM",
+ "Writing address 0x%x with offset %d of length %d to SRAM",
+ addr, len, offset);
+
+ ret = qcom_fg_sram_config_access(chip, 1, (len > 4));
@ -512,6 +514,8 @@ index 000000000000..f8dd93aa23c7
+ }
+
+ while(len > 0) {
+ int write_len = min(len, 4 - offset);
+
+ /* Set SRAM address register */
+ ret = qcom_fg_write(chip, (u8 *) &addr,
+ MEM_INTF_ADDR_LSB, 2);
@ -521,15 +525,15 @@ index 000000000000..f8dd93aa23c7
+ }
+
+ ret = qcom_fg_write(chip, wr_data,
+ MEM_INTF_WR_DATA0 + offset, len);
+ MEM_INTF_WR_DATA0 + offset, write_len);
+
+ addr += 4;
+
+ if (ret)
+ goto out;
+
+ wr_data += 4 - offset;
+ len -= 4 - offset;
+ wr_data += write_len;
+ len -= write_len;
+ offset = 0;
+ }
+out:
@ -1134,10 +1138,11 @@ index 000000000000..f8dd93aa23c7
+ if (psy == chip->chg_psy) {
+ ret = power_supply_get_property(psy,
+ POWER_SUPPLY_PROP_STATUS, &propval);
+ if (ret)
+ if (ret) {
+ chip->status = POWER_SUPPLY_STATUS_UNKNOWN;
+
+ chip->status = propval.intval;
+ } else {
+ chip->status = propval.intval;
+ }
+
+ power_supply_changed(chip->batt_psy);
+
@ -1201,7 +1206,7 @@ index 000000000000..f8dd93aa23c7
+ MEM_INTF_IMA_CFG, BIT(3), BIT(3));
+ if (ret) {
+ dev_err(chip->dev,
+ "Failed to configure interrupt sourete: %d\n", ret);
+ "Failed to configure interrupt source: %d\n", ret);
+ return ret;
+ }
+

40
patch/kernel/archive/sm8250-6.18/0025-power-qcom_fg-Add-initial-pm8150b-support.patch
View File

@ -106,8 +106,8 @@ index f8dd93aa23c7..dd5b2738d553 100644
if (ret) {
dev_err(chip->dev, "Failed to configure SRAM access: %d\n", ret);
return ret;
@@ -382,14 +387,14 @@ static int qcom_fg_sram_read(struct qcom_fg_chip *chip,
while(len > 0) {
@@ -384,14 +389,14 @@ static int qcom_fg_sram_read(struct qcom_fg_chip *chip,
/* Set SRAM address register */
ret = qcom_fg_write(chip, (u8 *) &addr,
- MEM_INTF_ADDR_LSB, 2);
@ -118,13 +118,13 @@ index f8dd93aa23c7..dd5b2738d553 100644
}
ret = qcom_fg_read(chip, rd_data,
- MEM_INTF_RD_DATA0 + offset, len);
+ MEM_INTF_RD_DATA0(chip) + offset, len);
- MEM_INTF_RD_DATA0 + offset, read_len);
+ MEM_INTF_RD_DATA0(chip) + offset, read_len);
addr += 4;
@@ -443,14 +448,14 @@ static int qcom_fg_sram_write(struct qcom_fg_chip *chip,
while(len > 0) {
@@ -447,14 +452,14 @@ static int qcom_fg_sram_write(struct qcom_fg_chip *chip,
/* Set SRAM address register */
ret = qcom_fg_write(chip, (u8 *) &addr,
- MEM_INTF_ADDR_LSB, 2);
@ -135,12 +135,12 @@ index f8dd93aa23c7..dd5b2738d553 100644
}
ret = qcom_fg_write(chip, wr_data,
- MEM_INTF_WR_DATA0 + offset, len);
+ MEM_INTF_WR_DATA0(chip) + offset, len);
- MEM_INTF_WR_DATA0 + offset, write_len);
+ MEM_INTF_WR_DATA0(chip) + offset, write_len);
addr += 4;
@@ -784,6 +789,34 @@ static int qcom_fg_gen3_get_temp_threshold(struct qcom_fg_chip *chip,
@@ -788,6 +793,34 @@ static int qcom_fg_gen3_get_temp_threshold(struct qcom_fg_chip *chip,
return 0;
}
@ -175,7 +175,7 @@ index f8dd93aa23c7..dd5b2738d553 100644
/************************
* BATTERY POWER SUPPLY
* **********************/
@@ -796,6 +829,7 @@ static const struct qcom_fg_ops ops_fg = {
@@ -800,6 +833,7 @@ static const struct qcom_fg_ops ops_fg = {
.get_voltage = qcom_fg_get_voltage,
.get_temp_threshold = qcom_fg_get_temp_threshold,
.set_temp_threshold = qcom_fg_set_temp_threshold,
@ -183,7 +183,7 @@ index f8dd93aa23c7..dd5b2738d553 100644
};
/* Gen3 fuel gauge. PMI8998 and newer */
@@ -805,6 +839,17 @@ static const struct qcom_fg_ops ops_fg_gen3 = {
@@ -809,6 +843,17 @@ static const struct qcom_fg_ops ops_fg_gen3 = {
.get_current = qcom_fg_gen3_get_current,
.get_voltage = qcom_fg_gen3_get_voltage,
.get_temp_threshold = qcom_fg_gen3_get_temp_threshold,
@ -201,7 +201,7 @@ index f8dd93aa23c7..dd5b2738d553 100644
};
static enum power_supply_property qcom_fg_props[] = {
@@ -837,7 +882,7 @@ static int qcom_fg_get_property(struct power_supply *psy,
@@ -841,7 +886,7 @@ static int qcom_fg_get_property(struct power_supply *psy,
case POWER_SUPPLY_PROP_STATUS:
/* Get status from charger if available */
if (chip->chg_psy &&
@ -210,7 +210,7 @@ index f8dd93aa23c7..dd5b2738d553 100644
val->intval = chip->status;
break;
} else {
@@ -928,33 +973,33 @@ static int qcom_fg_iacs_clear_sequence(struct qcom_fg_chip *chip)
@@ -932,33 +977,33 @@ static int qcom_fg_iacs_clear_sequence(struct qcom_fg_chip *chip)
int ret;
/* clear the error */
@ -249,7 +249,7 @@ index f8dd93aa23c7..dd5b2738d553 100644
if (ret) {
dev_err(chip->dev, "Failed to write IMA_CFG: %d\n", ret);
return ret;
@@ -971,14 +1016,14 @@ static int qcom_fg_clear_ima(struct qcom_fg_chip *chip,
@@ -975,14 +1020,14 @@ static int qcom_fg_clear_ima(struct qcom_fg_chip *chip,
int ret;
ret = qcom_fg_read(chip, &err_sts,
@ -266,7 +266,7 @@ index f8dd93aa23c7..dd5b2738d553 100644
if (ret) {
dev_err(chip->dev, "Failed to read IMA_EXP_STS: %d\n", ret);
return ret;
@@ -986,7 +1031,7 @@ static int qcom_fg_clear_ima(struct qcom_fg_chip *chip,
@@ -990,7 +1035,7 @@ static int qcom_fg_clear_ima(struct qcom_fg_chip *chip,
if (check_hw_sts) {
ret = qcom_fg_read(chip, &hw_sts,
@ -275,7 +275,7 @@ index f8dd93aa23c7..dd5b2738d553 100644
if (ret) {
dev_err(chip->dev, "Failed to read IMA_HW_STS: %d\n", ret);
return ret;
@@ -1127,7 +1172,7 @@ static int qcom_fg_probe(struct platform_device *pdev)
@@ -1132,7 +1177,7 @@ static int qcom_fg_probe(struct platform_device *pdev)
* IACS_INTR_SRC_SLCT is BIT(3)
*/
ret = qcom_fg_masked_write(chip,
@ -283,8 +283,8 @@ index f8dd93aa23c7..dd5b2738d553 100644
+ MEM_INTF_IMA_CFG(chip), BIT(3), BIT(3));
if (ret) {
dev_err(chip->dev,
"Failed to configure interrupt sourete: %d\n", ret);
@@ -1141,14 +1186,14 @@ static int qcom_fg_probe(struct platform_device *pdev)
"Failed to configure interrupt source: %d\n", ret);
@@ -1146,14 +1191,14 @@ static int qcom_fg_probe(struct platform_device *pdev)
}
/* Check and clear DMA errors */
@ -301,7 +301,7 @@ index f8dd93aa23c7..dd5b2738d553 100644
error_present ? BIT(0) : 0);
if (ret < 0) {
dev_err(chip->dev, "Failed to write dma_ctl: %d\n", ret);
@@ -1287,7 +1332,7 @@ static int qcom_fg_remove(struct platform_device *pdev)
@@ -1292,7 +1337,7 @@ static int qcom_fg_remove(struct platform_device *pdev)
{
struct qcom_fg_chip *chip = platform_get_drvdata(pdev);
@ -310,7 +310,7 @@ index f8dd93aa23c7..dd5b2738d553 100644
if(chip->sram_wq)
destroy_workqueue(chip->sram_wq);
@@ -1298,6 +1343,7 @@ static int qcom_fg_remove(struct platform_device *pdev)
@@ -1303,6 +1348,7 @@ static int qcom_fg_remove(struct platform_device *pdev)
static const struct of_device_id fg_match_id_table[] = {
{ .compatible = "qcom,pmi8994-fg", .data = &ops_fg },
{ .compatible = "qcom,pmi8998-fg", .data = &ops_fg_gen3 },

10
patch/kernel/archive/sm8250-6.18/0028-From-Teguh-Sobirin-teguh-sobir.in-Date-Sun-24-Nov-20.patch
View File

@ -17,12 +17,12 @@ diff --git a/drivers/power/supply/Kconfig b/drivers/power/supply/Kconfig
index e138bdc837a7..c25987d343dd 100644
--- a/drivers/power/supply/Kconfig
+++ b/drivers/power/supply/Kconfig
@@ -1073,6 +1073,15 @@ config CHARGER_QCOM_SMB2
@@ -1096,6 +1096,15 @@ config CHARGER_QCOM_SMB2
adds support for the SMB2 switch mode battery charger found
in PMI8998 and related PMICs.
+config CHARGER_QCOM_SMB5
+ tristate "Qualcomm PMI8998 PMIC charger driver"
+ tristate "Qualcomm PM8150B PMIC charger driver"
+ depends on MFD_SPMI_PMIC
+ depends on IIO
+ help
@ -37,7 +37,7 @@ diff --git a/drivers/power/supply/Makefile b/drivers/power/supply/Makefile
index 921cf6aac741..0802f703aab8 100644
--- a/drivers/power/supply/Makefile
+++ b/drivers/power/supply/Makefile
@@ -122,5 +122,6 @@ obj-$(CONFIG_BATTERY_SURFACE) += surface_battery.o
@@ -125,5 +125,6 @@ obj-$(CONFIG_BATTERY_SURFACE) += surface_battery.o
obj-$(CONFIG_CHARGER_SURFACE) += surface_charger.o
obj-$(CONFIG_BATTERY_UG3105) += ug3105_battery.o
obj-$(CONFIG_CHARGER_QCOM_SMB2) += qcom_smbx.o
@ -599,7 +599,7 @@ index 000000000000..d3590b4d7d5b
+ }
+
+ if (stat & CHARGER_ERROR_STATUS_BAT_OV_BIT) {
+ dev_err(chip->dev, "battery over-voltage");
+ dev_err(chip->dev, "battery over-voltage\n");
+ }
+
+ rc = regmap_read(chip->regmap, chip->base + BATTERY_CHARGER_STATUS_7_REG,
@ -729,7 +729,7 @@ index 000000000000..d3590b4d7d5b
+
+ power_supply_changed(chip->chg_psy);
+
+ rc = regmap_write(chip->regmap, BARK_BITE_WDOG_PET,
+ rc = regmap_write(chip->regmap, chip->base + BARK_BITE_WDOG_PET,
+ BARK_BITE_WDOG_PET_BIT);
+ if (rc < 0)
+ dev_err(chip->dev, "Couldn't pet the dog rc=%d\n", rc);