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rockchip: bump tinkerboard and xt-q8l-v10 u-boot to v2025.01 (#7967)

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Paolo 2025-03-19 10:20:22 +01:00 committed by GitHub
parent 49e7d58ecf
commit 96defadfd0
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GPG Key ID: B5690EEEBB952194
6 changed files with 1541 additions and 2 deletions
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4
config/sources/families/rockchip.conf
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@ -23,8 +23,8 @@ if [[ "$BOOT_SOC" == "rk3288" ]]; then
OVERLAY_PREFIX='rockchip'
UBOOT_TARGET_MAP=";;u-boot-rockchip-with-spl.bin"
BOOTBRANCH='tag:v2024.07'
BOOTPATCHDIR='v2024.07'
BOOTBRANCH='tag:v2025.01'
BOOTPATCHDIR='v2025.01'
if [[ $BOARD == miqi ]]; then
BOOTBRANCH='tag:v2017.11'

42
patch/u-boot/v2025.01/board_tinkerboard/0001-tinkerboard-defconfig-fix.patch Normal file
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@ -0,0 +1,42 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Thu, 4 Jul 2024 21:28:24 +0200
Subject: accomodations for asus tinkerboard/s
---
configs/tinker-s-rk3288_defconfig | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig
index 111111111111..222222222222 100644
--- a/configs/tinker-s-rk3288_defconfig
+++ b/configs/tinker-s-rk3288_defconfig
@@ -11,6 +11,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_DEFAULT_DEVICE_TREE="rk3288-tinker-s"
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_SYS_MONITOR_LEN=614400
CONFIG_ROCKCHIP_RK3288=y
@@ -33,6 +34,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_PAD_TO=0x7f8000
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_CMD_GPIO=y
@@ -94,6 +96,9 @@ CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="ASUS"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0b05
+CONFIG_USB_GADGET_PRODUCT_NUM=0x7820
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
--
Armbian

403
patch/u-boot/v2025.01/board_tinkerboard/0003-UMS-mode-on-otg-port.patch Normal file
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@ -0,0 +1,403 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Thu, 4 Jul 2024 21:49:20 +0200
Subject: UMS mode for Asus Tinkerboard
---
arch/arm/include/asm/arch-rockchip/gpio.h | 22 ++
arch/arm/mach-rockchip/board.c | 114 ++++++++++
arch/arm/mach-rockchip/spl.c | 22 ++
cmd/usb_mass_storage.c | 9 +-
common/autoboot.c | 22 ++
common/board_r.c | 1 +
drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c | 1 +
drivers/usb/gadget/f_mass_storage.c | 10 +-
include/init.h | 1 +
include/linux/usb/gadget.h | 3 +
10 files changed, 202 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/gpio.h b/arch/arm/include/asm/arch-rockchip/gpio.h
index 111111111111..222222222222 100644
--- a/arch/arm/include/asm/arch-rockchip/gpio.h
+++ b/arch/arm/include/asm/arch-rockchip/gpio.h
@@ -24,6 +24,28 @@ struct rockchip_gpio_regs {
};
check_member(rockchip_gpio_regs, ls_sync, 0x60);
+/*
+ * RK3288 IO memory map:
+ *
+ */
+#define RKIO_GPIO0_PHYS 0xFF750000
+#define RKIO_GRF_PHYS 0xFF770000
+#define RKIO_GPIO1_PHYS 0xFF780000
+#define RKIO_GPIO2_PHYS 0xFF790000
+#define RKIO_GPIO3_PHYS 0xFF7A0000
+#define RKIO_GPIO4_PHYS 0xFF7B0000
+#define RKIO_GPIO5_PHYS 0xFF7C0000
+#define RKIO_GPIO6_PHYS 0xFF7D0000
+
+/* gpio power down/up control */
+#define GRF_GPIO2A_P 0x150
+#define GRF_GPIO6A_P 0x190
+
+/* gpio input/output control */
+#define GPIO_SWPORT_DR 0x00
+#define GPIO_SWPORT_DDR 0x04
+#define GPIO_EXT_PORT 0x50
+
enum gpio_pu_pd {
GPIO_PULL_NORMAL = 0,
GPIO_PULL_UP,
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index 111111111111..222222222222 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -19,6 +19,7 @@
#include <hash.h>
#include <init.h>
#include <log.h>
+#include <linux/delay.h>
#include <mmc.h>
#include <dm/uclass-internal.h>
#include <misc.h>
@@ -30,6 +31,7 @@
#include <u-boot/sha256.h>
#include <asm/cache.h>
#include <asm/io.h>
+#include <asm/arch-rockchip/gpio.h>
#include <asm/arch-rockchip/boot_mode.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/periph.h>
@@ -184,6 +186,19 @@ static void gpt_capsule_update_setup(void)
}
#endif /* CONFIG_EFI_HAVE_CAPSULE_SUPPORT && CONFIG_EFI_PARTITION */
+enum project_id {
+ TinkerBoardS = 0,
+ TinkerBoard = 7,
+};
+
+enum pcb_id {
+ SR,
+ ER,
+ PR,
+};
+
+extern bool force_ums;
+
__weak int rk_board_late_init(void)
{
return 0;
@@ -200,6 +215,105 @@ int board_late_init(void)
return rk_board_late_init();
}
+/*
+*
+* usb current limit : GPIO6_A6 (H:unlock, L:lock)
+*
+*/
+void usb_current_limit_ctrl(bool unlock_current)
+{
+ int tmp;
+
+ printf("%s: unlock_current = %d\n", __func__, unlock_current);
+ tmp = readl(RKIO_GPIO6_PHYS + GPIO_SWPORT_DR);
+ if(unlock_current == true)
+ writel(tmp | 0x40, RKIO_GPIO6_PHYS + GPIO_SWPORT_DR);
+ else
+ writel(tmp & ~0x40, RKIO_GPIO6_PHYS + GPIO_SWPORT_DR);
+
+ tmp = readl(RKIO_GPIO6_PHYS + GPIO_SWPORT_DDR);
+ writel(tmp | 0x40, RKIO_GPIO6_PHYS + GPIO_SWPORT_DDR);
+}
+
+/*
+*
+* eMMC maskrom mode : GPIO6_A7 (H:disable maskrom, L:enable maskrom)
+*
+*/
+void rk3288_maskrom_ctrl(bool enable_emmc)
+{
+ int tmp;
+
+ printf("%s: enable_emmc = %d\n", __func__, enable_emmc);
+ tmp = readl(RKIO_GPIO6_PHYS + GPIO_SWPORT_DR);
+ if(enable_emmc == true)
+ writel(tmp | 0x80, RKIO_GPIO6_PHYS + GPIO_SWPORT_DR);
+ else
+ writel(tmp & ~0x80, RKIO_GPIO6_PHYS + GPIO_SWPORT_DR);
+
+ tmp = readl(RKIO_GPIO6_PHYS + GPIO_SWPORT_DDR);
+ writel(tmp | 0x80, RKIO_GPIO6_PHYS + GPIO_SWPORT_DDR);
+ mdelay(10);
+}
+
+/*
+*
+* project id : GPIO2_A3 GPIO2_A2 GPIO2_A1
+* pcb id : GPIO2_B2 GPIO2_B1 GPIO2_B0
+* SDP/CDP : GPIO6_A5 (H:SDP, L:CDP)
+* usb current limit : GPIO6_A6 (H:unlock, L:lock)
+* eMMC maskrom mode : GPIO6_A7 (H:disable maskrom, L:enable maskrom)
+*
+* Please check TRM V1.2 part1 page 152 for the following register settings
+*
+*/
+int check_force_enter_ums_mode(void)
+{
+ int tmp;
+ enum pcb_id pcbid;
+ enum project_id projectid;
+
+ // GPIO2_A3/GPIO2_A2/GPIO2_A1 pull up enable
+ tmp = readl(RKIO_GRF_PHYS + GRF_GPIO2A_P);
+ writel((tmp&~(0x03F<<2)) | 0x3F<<(16 + 2) | 0x15<<2, RKIO_GRF_PHYS + GRF_GPIO2A_P);
+
+ // GPIO2_A3/GPIO2_A2/GPIO2_A1/GPIO2_B2/GPIO2_B1/GPIO2_B0 set to input
+ tmp = readl(RKIO_GPIO2_PHYS + GPIO_SWPORT_DDR);
+ writel(tmp & ~(0x70E), RKIO_GPIO2_PHYS + GPIO_SWPORT_DDR);
+
+ // GPIO6_A5 pull up/down disable
+ tmp = readl(RKIO_GRF_PHYS + GRF_GPIO6A_P);
+ writel((tmp&~(0x03<<10)) | 0x03<<(16 + 10), RKIO_GRF_PHYS + GRF_GPIO6A_P);
+
+ // GPIO6_A5 set to input
+ tmp = readl(RKIO_GPIO6_PHYS + GPIO_SWPORT_DDR);
+ writel(tmp & ~(0x20), RKIO_GPIO6_PHYS + GPIO_SWPORT_DDR);
+
+ mdelay(10);
+
+ // read GPIO2_A3/GPIO2_A2/GPIO2_A1 value
+ projectid = (readl(RKIO_GPIO2_PHYS + GPIO_EXT_PORT) & 0x0E) >>1;
+
+ // read GPIO2_B2/GPIO2_B1/GPIO2_B0 value
+ pcbid = (readl(RKIO_GPIO2_PHYS + GPIO_EXT_PORT) & 0x700) >> 8;
+
+ // only Tinker Board S and the PR stage PCB has this function
+ if(projectid!=TinkerBoard && pcbid >= ER){
+ printf("PC event = 0x%x\n", readl(RKIO_GPIO6_PHYS + GPIO_EXT_PORT)&0x20);
+ if((readl(RKIO_GPIO6_PHYS + GPIO_EXT_PORT)&0x20)==0x20) {
+ // SDP detected, enable EMMC and unlock usb current limit
+ printf("usb connected to SDP, force enter ums mode\n");
+ force_ums = true;
+ rk3288_maskrom_ctrl(true);
+ usb_current_limit_ctrl(true);
+ } else {
+ usb_current_limit_ctrl(false);
+ }
+ }
+ return 0;
+}
+
+
int board_init(void)
{
int ret;
diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c
index 111111111111..222222222222 100644
--- a/arch/arm/mach-rockchip/spl.c
+++ b/arch/arm/mach-rockchip/spl.c
@@ -116,10 +116,32 @@ __weak int arch_cpu_init(void)
return 0;
}
+/*
+*
+* usb current limit : GPIO6_A6 (H:unlock, L:lock)
+*
+*/
+void usb_current_limit_ctrl(bool unlock_current)
+{
+ int tmp;
+
+#include <asm/arch/gpio.h>
+
+ tmp = readl(RKIO_GPIO6_PHYS + GPIO_SWPORT_DR);
+ if(unlock_current == true)
+ writel(tmp | 0x40, RKIO_GPIO6_PHYS + GPIO_SWPORT_DR);
+ else
+ writel(tmp & ~0x40, RKIO_GPIO6_PHYS + GPIO_SWPORT_DR);
+
+ tmp = readl(RKIO_GPIO6_PHYS + GPIO_SWPORT_DDR);
+ writel(tmp | 0x40, RKIO_GPIO6_PHYS + GPIO_SWPORT_DDR);
+}
+
void board_init_f(ulong dummy)
{
int ret;
+ usb_current_limit_ctrl(true);
board_early_init_f();
ret = spl_early_init();
diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c
index 111111111111..222222222222 100644
--- a/cmd/usb_mass_storage.c
+++ b/cmd/usb_mass_storage.c
@@ -108,7 +108,7 @@ static int ums_init(const char *devtype, const char *devnums_part_str)
name = malloc(UMS_NAME_LEN);
if (!name)
goto cleanup;
- snprintf(name, UMS_NAME_LEN, "UMS disk %d", ums_count);
+ snprintf(name, UMS_NAME_LEN, "Armbian UMS disk %d", ums_count);
ums[ums_count].name = name;
ums[ums_count].block_dev = *block_dev;
@@ -133,7 +133,7 @@ cleanup:
return ret;
}
-static int do_usb_mass_storage(struct cmd_tbl *cmdtp, int flag,
+int do_usb_mass_storage(struct cmd_tbl *cmdtp, int flag,
int argc, char *const argv[])
{
const char *usb_controller;
@@ -217,6 +217,11 @@ static int do_usb_mass_storage(struct cmd_tbl *cmdtp, int flag,
dm_usb_gadget_handle_interrupts(udc);
rc = fsg_main_thread(NULL);
+
+ if (rc == -ETIMEDOUT) {
+ goto cleanup_register;
+ }
+
if (rc) {
/* Check I/O error */
if (rc == -EIO)
diff --git a/common/autoboot.c b/common/autoboot.c
index 111111111111..222222222222 100644
--- a/common/autoboot.c
+++ b/common/autoboot.c
@@ -40,6 +40,9 @@ DECLARE_GLOBAL_DATA_PTR;
static int stored_bootdelay;
static int menukey;
+bool force_ums = false;
+bool getdescriptor = false;
+
#if defined(CONFIG_AUTOBOOT_STOP_STR_CRYPT)
#define AUTOBOOT_STOP_STR_CRYPT CONFIG_AUTOBOOT_STOP_STR_CRYPT
#else
@@ -125,6 +128,10 @@ static int passwd_abort_crypt(uint64_t etime)
return abort;
}
+extern int do_usb_mass_storage(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]);
+void usb_current_limit_ctrl(bool unlock_current);
+void rk3288_maskrom_ctrl(bool enable_emmc);
+
/*
* Use a "constant-length" time compare function for this
* hash compare:
@@ -491,6 +498,21 @@ void autoboot_command(const char *s)
{
debug("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>");
+ if (force_ums) {
+ // force to enter ums mode
+ char *local_args[4];
+ char str1[]="ums", str2[]="1", str3[]="mmc", str4[]="0";
+
+ local_args[0]=str1;
+ local_args[1]=str2;
+ local_args[2]=str3;
+ local_args[3]=str4;
+ if (do_usb_mass_storage(NULL, 0, 4, local_args) == -ETIMEDOUT) {
+ rk3288_maskrom_ctrl(false);
+ usb_current_limit_ctrl(false);
+ }
+ }
+
if (s && (stored_bootdelay == -2 ||
(stored_bootdelay != -1 && !abortboot(stored_bootdelay)))) {
bool lock;
diff --git a/common/board_r.c b/common/board_r.c
index 111111111111..222222222222 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -667,6 +667,7 @@ static init_fnc_t init_sequence_r[] = {
#ifdef CONFIG_MMC
initr_mmc,
#endif
+ check_force_enter_ums_mode,
#ifdef CONFIG_XEN
xen_init,
#endif
diff --git a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
index 111111111111..222222222222 100644
--- a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
+++ b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c
@@ -1393,6 +1393,7 @@ static void dwc2_ep0_setup(struct dwc2_udc *dev)
debug_cond(DEBUG_SETUP != 0,
"%s: *** USB_REQ_GET_DESCRIPTOR\n",
__func__);
+ getdescriptor = true;
break;
case USB_REQ_SET_INTERFACE:
diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c
index 111111111111..222222222222 100644
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -657,7 +657,7 @@ static void busy_indicator(void)
static int sleep_thread(struct fsg_common *common)
{
int rc = 0;
- int i = 0, k = 0;
+ int i = 0, k = 0, j = 0;
/* Wait until a signal arrives or we are woken up */
for (;;) {
@@ -668,6 +668,7 @@ static int sleep_thread(struct fsg_common *common)
busy_indicator();
i = 0;
k++;
+ j++;
}
if (k == 10) {
@@ -686,6 +687,13 @@ static int sleep_thread(struct fsg_common *common)
k = 0;
}
+ if (j == 300) { //about 3 seconds
+ if(force_ums && !getdescriptor) {
+ printf("wait for usb get descriptor cmd timeout\n");
+ return -ETIMEDOUT;
+ }
+ }
+
dm_usb_gadget_handle_interrupts(udcdev);
}
common->thread_wakeup_needed = 0;
diff --git a/include/init.h b/include/init.h
index 111111111111..222222222222 100644
--- a/include/init.h
+++ b/include/init.h
@@ -337,6 +337,7 @@ int board_early_init_f(void);
/* manipulate the U-Boot fdt before its relocation */
int board_fix_fdt(void *rw_fdt_blob);
int board_late_init(void);
+int check_force_enter_ums_mode (void);
int board_postclk_init(void); /* after clocks/timebase, before env/serial */
int board_early_init_r(void);
diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h
index 111111111111..222222222222 100644
--- a/include/linux/usb/gadget.h
+++ b/include/linux/usb/gadget.h
@@ -25,6 +25,9 @@
struct usb_ep;
+extern bool force_ums;
+extern bool getdescriptor;
+
/**
* struct usb_request - describes one i/o request
* @buf: Buffer used for data. Always provide this; some controllers
--
Armbian

139
patch/u-boot/v2025.01/board_xt-q8l-v10/xt-q8l-v10-defconfig.patch Normal file
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@ -0,0 +1,139 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sat, 6 Jul 2024 20:21:59 +0200
Subject: add xt-q8l-v10 defconfig
---
configs/xt-q8l-v10-rk3288_defconfig | 121 ++++++++++
1 file changed, 121 insertions(+)
diff --git a/configs/xt-q8l-v10-rk3288_defconfig b/configs/xt-q8l-v10-rk3288_defconfig
new file mode 100644
index 000000000000..111111111111
--- /dev/null
+++ b/configs/xt-q8l-v10-rk3288_defconfig
@@ -0,0 +1,121 @@
+CONFIG_ARM=y
+CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_TPL_SKIP_LOWLEVEL_INIT_ONLY=y
+CONFIG_SYS_ARCH_TIMER=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_DEFAULT_DEVICE_TREE="rk3288-xt-q8l-v10"
+CONFIG_DM_RESET=y
+CONFIG_SYS_MONITOR_LEN=614400
+CONFIG_ROCKCHIP_RK3288=y
+CONFIG_ROCKCHIP_EXTERNAL_TPL=y
+CONFIG_TARGET_XT_Q8L_V10_RK3288=y
+CONFIG_SPL_STACK_R_ADDR=0x800000
+CONFIG_SPL_STACK=0xff718000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x300000
+CONFIG_SPL_SIZE_LIMIT=0x4b000
+CONFIG_DEBUG_UART_BASE=0xff690000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_CMD_HDMIDETECT=y
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART=y
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_USE_PREBOOT=y
+CONFIG_DEFAULT_FDT_FILE="rk3288-xt-q8l-v10.dtb"
+CONFIG_SILENT_CONSOLE=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_R=y
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_NO_BSS_LIMIT=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+# CONFIG_TPL_DRIVERS_MISC is not set
+# CONFIG_CMD_BOOTEFI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EROFS=y
+CONFIG_CMD_SQUASHFS=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+# CONFIG_SPL_SIMPLE_BUS is not set
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_MISC=y
+CONFIG_GATEWORKS_SC=y
+CONFIG_ROCKCHIP_EFUSE=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_ACT8846=y
+CONFIG_DM_PMIC_FAN53555=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_REGULATOR_ACT8846=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+# CONFIG_RAM_ROCKCHIP_DEBUG is not set
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_BPP8 is not set
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_VIDEO_ROCKCHIP_MAX_XRES=1920
+CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1080
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+CONFIG_CONSOLE_SCROLL_LINES=10
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_SHA256=y
+# CONFIG_SPL_SHA256 is not set
+CONFIG_ERRNO_STR=y
--
Armbian

157
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@ -0,0 +1,157 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sat, 6 Jul 2024 20:22:22 +0200
Subject: add xt-q8l-v10 ancillary makefile and sources
---
arch/arm/dts/Makefile | 1 +
arch/arm/mach-rockchip/rk3288/Kconfig | 12 ++++++
board/rockchip/xt-q8l-v10_rk3288/Kconfig | 15 +++++++
board/rockchip/xt-q8l-v10_rk3288/MAINTAINERS | 6 +++
board/rockchip/xt-q8l-v10_rk3288/Makefile | 7 ++++
board/rockchip/xt-q8l-v10_rk3288/xt-q8l-v10-rk3288.c | 21 ++++++++++
include/configs/xt-q8l-v10_rk3288.h | 21 ++++++++++
7 files changed, 83 insertions(+)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 111111111111..222222222222 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -84,6 +84,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \
rk3288-rock-pi-n8.dtb \
rk3288-tinker.dtb \
rk3288-tinker-s.dtb \
+ rk3288-xt-q8l-v10.dtb \
rk3288-veyron-jerry.dtb \
rk3288-veyron-mickey.dtb \
rk3288-veyron-minnie.dtb \
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig
index 111111111111..222222222222 100644
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -139,6 +139,16 @@ config TARGET_TINKER_RK3288
8GB eMMC and 2GB of SDRAM. Expansion connectors provide access to
I2C, SPI, UART, GPIOs.
+config TARGET_XT_Q8L_V10_RK3288
+ bool "xt-q8l-v10 tvbox board"
+ select BOARD_LATE_INIT
+ select TPL
+ help
+ xt-q8l-v10 is a RK3288 common tv box with 3 USB ports (1 OTG), HDMI,
+ micro-SD card, Gigabit Ethernet and SPDIF output. It also includes on-board
+ 8GB eMMC and 2GB of SDRAM, 802.11n Wifi and Bluetooth based upon AP6330
+ WiSoC.
+
endchoice
config ROCKCHIP_FAST_SPL
@@ -198,4 +208,6 @@ source "board/rockchip/evb_rk3288/Kconfig"
source "board/rockchip/tinker_rk3288/Kconfig"
+source "board/rockchip/xt-q8l-v10_rk3288/Kconfig"
+
endif
diff --git a/board/rockchip/xt-q8l-v10_rk3288/Kconfig b/board/rockchip/xt-q8l-v10_rk3288/Kconfig
new file mode 100644
index 000000000000..111111111111
--- /dev/null
+++ b/board/rockchip/xt-q8l-v10_rk3288/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_XT_Q8L_V10_RK3288
+
+config SYS_BOARD
+ default "xt-q8l-v10_rk3288"
+
+config SYS_VENDOR
+ default "rockchip"
+
+config SYS_CONFIG_NAME
+ default "xt-q8l-v10_rk3288"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
diff --git a/board/rockchip/xt-q8l-v10_rk3288/MAINTAINERS b/board/rockchip/xt-q8l-v10_rk3288/MAINTAINERS
new file mode 100644
index 000000000000..111111111111
--- /dev/null
+++ b/board/rockchip/xt-q8l-v10_rk3288/MAINTAINERS
@@ -0,0 +1,6 @@
+XT-Q8L-V10-RK3288
+M: Paolo Sabatino <a@b.c>
+S: Not mainlined
+F: board/rockchip/xt-q8l-v10_rk3288
+F: include/configs/xt-q8l-v10_rk3288.h
+F: configs/xt-q8l-v10-rk3288_defconfig
diff --git a/board/rockchip/xt-q8l-v10_rk3288/Makefile b/board/rockchip/xt-q8l-v10_rk3288/Makefile
new file mode 100644
index 000000000000..111111111111
--- /dev/null
+++ b/board/rockchip/xt-q8l-v10_rk3288/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += xt-q8l-v10-rk3288.o
diff --git a/board/rockchip/xt-q8l-v10_rk3288/xt-q8l-v10-rk3288.c b/board/rockchip/xt-q8l-v10_rk3288/xt-q8l-v10-rk3288.c
new file mode 100644
index 000000000000..111111111111
--- /dev/null
+++ b/board/rockchip/xt-q8l-v10_rk3288/xt-q8l-v10-rk3288.c
@@ -0,0 +1,20 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <spl.h>
+#include <asm/gpio.h>
+
+void spl_board_init(void)
+{
+
+ /*
+ * xt-q8l-v10 requires the power-hold gpio set (A11, or bank 0 pin 11
+ * if you prefer) as soon as possible.
+ * We hack it here :P
+ */
+ gpio_request(11, "power-hold");
+ gpio_direction_output(11, 1);
+
+}
+
diff --git a/include/configs/xt-q8l-v10_rk3288.h b/include/configs/xt-q8l-v10_rk3288.h
new file mode 100644
index 000000000000..111111111111
--- /dev/null
+++ b/include/configs/xt-q8l-v10_rk3288.h
@@ -0,0 +1,21 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdin=serial,usbkbd\0" \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#include <configs/rk3288_common.h>
+
+#undef BOOT_TARGETS
+
+#define BOOT_TARGETS "mmc1 usb mmc0 pxe dhcp"
+
+#endif
--
Armbian

798
patch/u-boot/v2025.01/board_xt-q8l-v10/xt-q8l-v10-device-tree.patch Normal file
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@ -0,0 +1,798 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sat, 6 Jul 2024 20:21:32 +0200
Subject: add xt-q8lv-10 device tree
---
arch/arm/dts/rk3288-xt-q8l-v10-u-boot.dtsi | 70 +
arch/arm/dts/rk3288-xt-q8l-v10.dts | 703 ++++++++++
2 files changed, 773 insertions(+)
diff --git a/arch/arm/dts/rk3288-xt-q8l-v10-u-boot.dtsi b/arch/arm/dts/rk3288-xt-q8l-v10-u-boot.dtsi
new file mode 100644
index 000000000000..111111111111
--- /dev/null
+++ b/arch/arm/dts/rk3288-xt-q8l-v10-u-boot.dtsi
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3288-u-boot.dtsi"
+
+&dmc {
+ bootph-all;
+ rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
+ 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
+ 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
+ 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
+ 0x8 0x1f4>;
+ rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
+ 0x0 0xc3 0x6 0x2>;
+ rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
+};
+
+&pinctrl {
+ bootph-all;
+};
+
+&uart2 {
+ bootph-all;
+};
+
+&uart2_xfer {
+ bootph-all;
+};
+
+&sdmmc {
+ bootph-pre-ram;
+};
+
+&gpio7 {
+ bootph-pre-ram;
+};
+
+&vcc_sd {
+ bootph-pre-ram;
+};
+
+&pcfg_pull_none {
+ bootph-pre-ram;
+};
+
+&pcfg_pull_up {
+ bootph-pre-ram;
+};
+
+&sdmmc_bus4 {
+ bootph-pre-ram;
+};
+
+&sdmmc_cd {
+ bootph-pre-ram;
+};
+
+&sdmmc_clk {
+ bootph-pre-ram;
+};
+
+&sdmmc_cmd {
+ bootph-pre-ram;
+};
+
+&sdmmc_pwr {
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/rk3288-xt-q8l-v10.dts b/arch/arm/dts/rk3288-xt-q8l-v10.dts
new file mode 100755
index 000000000000..111111111111
--- /dev/null
+++ b/arch/arm/dts/rk3288-xt-q8l-v10.dts
@@ -0,0 +1,703 @@
+/*
+ * Copyright (c) 2014, 2015 FUKAUMI Naoki <naobsd@gmail.com>
+ * 2018 Paolo Sabatino <paolo.sabatino@gm**l.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "rk3288.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "XT-Q8L-V10-RK3288";
+ compatible = "generic,xt-q8l-v10-rk3288", "rockchip,rk3288";
+
+ chosen {
+ stdout-path = &uart2;
+ /*
+ * We leave this here for future reference, but at the moment
+ * rk3288 does not support "same-as-spl", instead as a workaround
+ * we define the boot order statically in:
+ * board/rockchip/xt-q8l-v10_rk3288/xt-q8l-v10-rk3288.c
+ *
+ */
+ u-boot,spl-boot-order = &sdmmc, &emmc;
+ };
+
+ memory {
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ cpu0_opp_table: opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <900000>;
+ };
+ opp@816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp@1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1050000>;
+ };
+ opp@1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1100000>;
+ };
+ opp@1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <1200000>;
+ };
+ opp@1512000000 {
+ opp-hz = /bits/ 64 <1512000000>;
+ opp-microvolt = <1250000>;
+ };
+ opp@1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <1300000>;
+ };
+
+ };
+
+ ext_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ clock-output-names = "ext_gmac";
+ };
+
+ keys: gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_key>;
+
+ button@0 {
+ gpio-key,wakeup;
+ gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+ label = "GPIO Power";
+ linux,code = <116>;
+ wakeup-source;
+ };
+
+ };
+
+ leds {
+ bootph-all;
+ compatible = "gpio-leds";
+
+ power {
+ gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
+ bootph-all;
+ label = "power";
+ pinctrl-names = "default";
+ pinctrl-0 = <&power_led>;
+ };
+
+ };
+
+ vcc_sys: vsys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio7 11 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_pwr>;
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vcc_flash: flash-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_flash";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ vcc_host_5v: usb-host-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc_host_5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ enable-active-high;
+ vin-supply = <&vcc_sys>;
+ };
+
+
+ vcc_otg_5v: usb-otg-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+ regulator-name = "vcc_otg_5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ enable-active-high;
+ vin-supply = <&vcc_sys>;
+ };
+
+ io_domains {
+ compatible = "rockchip,rk3288-io-voltage-domain";
+ audio-supply = <&vcca_33>;
+ bb-supply = <&vcc_io>;
+ dvp-supply = <&vcc_18>;
+ flash0-supply = <&vcc_flash>;
+ flash1-supply = <&vcc_lan>;
+ gpio30-supply = <&vcc_io>;
+ gpio1830-supply = <&vcc_io>;
+ lcdc-supply = <&vcc_io>;
+ sdcard-supply = <&vccio_sd>;
+ wifi-supply = <&vcc_18>;
+ };
+
+};
+
+&cpu0 {
+ cpu0-supply = <&vdd_cpu>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ /delete-node/operating-points;
+ /*
+ // Rewrite the operating points table
+ operating-points = <
+ 1608000 1350000
+ 1512000 1300000
+ 1416000 1200000
+ 1200000 1100000
+ 1008000 1050000
+ 816000 1000000
+ 696000 950000
+ 600000 900000
+ >;
+ */
+
+};
+
+&gmac {
+ assigned-clocks = <&cru SCLK_MAC>;
+ assigned-clock-parents = <&ext_gmac>;
+ clock_in_out = "input";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
+ phy-supply = <&vcc_lan>;
+ phy-mode = "rgmii";
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c5>;
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ vdd_cpu: syr827@40 {
+ compatible = "silergy,syr827";
+ fcs,suspend-voltage-selector = <1>;
+ reg = <0x40>;
+ regulator-name = "vdd_cpu";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <8000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vdd_gpu: syr828@41 {
+ compatible = "silergy,syr828";
+ fcs,suspend-voltage-selector = <1>;
+ reg = <0x41>;
+ regulator-name = "vdd_gpu";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <8000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc_sys>;
+ };
+
+ hym8563: hym8563@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ interrupt-parent = <&gpio0>;
+ interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtc_int>;
+ };
+
+ act8846: act8846@5a {
+ compatible = "active-semi,act8846";
+ reg = <0x5a>;
+ system-power-controller;
+
+ vp1-supply = <&vcc_sys>;
+ vp2-supply = <&vcc_sys>;
+ vp3-supply = <&vcc_sys>;
+ vp4-supply = <&vcc_sys>;
+ inl1-supply = <&vcc_sys>;
+ inl2-supply = <&vcc_sys>;
+ inl3-supply = <&vcc_20>;
+
+ status = "okay";
+
+ regulators {
+ vcc_ddr: REG1 {
+ regulator-name = "vcc_ddr";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_io: vcc33_lcd: REG2 {
+ regulator-name = "vcc_io";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_log: REG3 {
+ regulator-name = "vdd_log";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_20: REG4 {
+ regulator-name = "vcc_20";
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vccio_sd: REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd10_lcd: REG6 {
+ regulator-name = "vdd10_lcd";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcca_18: REG7 {
+ regulator-name = "vcca_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcca_33: REG8 {
+ regulator-name = "vcca_33";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vcc_lan: REG9 {
+ regulator-name = "vcc_lan";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vdd_10: REG10 {
+ regulator-name = "vdd_10";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vccio_wl: vcc_18: REG11 {
+ regulator-name = "vcc_18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc18_lcd: REG12 {
+ regulator-name = "vcc18_lcd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+};
+
+&pinctrl {
+
+ bootph-pre-ram;
+
+ /*
+ This pin configuration enables the power led and, most important,
+ the power hold pin of the act8846 pmic. Without the power hold
+ bit set, the pmic will shut itself down after a few milliseconds,
+ turning off the whole device. Be aware that in u-boot configuration
+ "pinctrl-names" and "pinctrl-0" properties MUST NOT be stripped
+ away from SPL.
+ Note also that we set the pwr_hold GPIO in board_init_f()
+ function directly in SPL u-boot code which gets executed very soon.
+ The definition here is just a way to be sure that the bit is set
+ again later.
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <&power_led>, <&pwr_hold>;
+
+ pcfg_output_high: pcfg-output-high {
+ bootph-all;
+ output-high;
+ };
+
+ pcfg_output_low: pcfg-output-low {
+ output-low;
+ };
+
+ pcfg_wl: pcfg-wl {
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ pcfg_wl_clk: pcfg-wl-clk {
+ bias-disable;
+ drive-strength = <12>;
+ };
+
+ pcfg_wl_int: pcfg-wl-int {
+ bias-pull-up;
+ };
+
+
+ act8846 {
+
+ /*
+ * Original q8 device tree says:
+ * - gpio0 11 HIGH -> power hold
+ * - gpio7 1 LOW -> possibly pmic-vsel, we omit it here
+ */
+ /*pmic_vsel: pmic-vsel {
+ rockchip,pins = <7 1 RK_FUNC_GPIO &pcfg_output_low>;
+ };*/
+
+ pwr_hold: pwr-hold {
+ rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ };
+
+ gmac {
+ phy_int: phy-int {
+ rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ phy_pmeb: phy-pmeb {
+ rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ phy_rst: phy-rst {
+ rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
+ };
+ };
+
+ hym8563 {
+ rtc_int: rtc-int {
+ rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ keys {
+ pwr_key: pwr-key {
+ rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ leds {
+
+ power_led: power-led {
+ rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ };
+
+ ir {
+ ir_int: ir-int {
+ rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdmmc {
+ sdmmc_pwr: sdmmc-pwr {
+ rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb_host1 {
+
+ host_vbus_drv: host-vbus-drv {
+ rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ };
+
+ usb_otg {
+
+ otg_vbus_drv: otg-vbus-drv {
+ rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ };
+
+};
+
+&saradc {
+ vref-supply = <&vcc_18>;
+ status = "okay";
+};
+
+&emmc {
+ /*
+ * eMMC seems to be 52Mhz device on q8 devices, so set it here
+ * vmmc-supply and vqmmc-supply are removed because they hang
+ * u-boot >= v2018.03
+ * From the original q8l firmware and eMMC datasheet it also should
+ * support DDR highspeed mode, but using mmc-ddr-3_3v or mmc-ddr-1_8v
+ * properties are not working
+ */
+ clock-frequency = <50000000>;
+
+ broken-cd;
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ disable-wp;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>;
+
+ status = "okay";
+ bootph-all;
+
+};
+
+&sdmmc {
+ bus-width = <4>;
+ supports-sd;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
+ //vmmc-supply = <&vcc_sd>;
+ //vqmmc-supply = <&vccio_sd>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ sd-uhs-ddr50;
+ status = "okay";
+ bootph-all;
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <0>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+/*
+ * Accessible serial port for logging
+ */
+&uart2 {
+ dmas = <&dmac_bus_s 4 &dmac_bus_s 5>;
+ dma-names = "tx", "rx";
+ status = "okay";
+};
+
+/*
+ * Describing resets for usb phy is important because otherwise the USB
+ * port gets stuck in case it goes into autosuspend: plugging any device
+ * when the port is autosuspended will actually kill the port itself and
+ * require a power cycle.
+ * This is required for the usbphy1 phy, nonetheless it is a good idea to
+ * specify the proper resources for all the phys though.
+ * The reference patch which works in conjuction with the reset lines:
+ * https://patchwork.kernel.org/patch/9469811/
+ */
+&usbphy {
+ status = "okay";
+};
+
+&usbphy0 {
+ resets = <&cru SRST_USBOTG_PHY>;
+ reset-names = "phy-reset";
+ vbus-supply = <&vcc_otg_5v>;
+};
+
+&usbphy1 {
+ resets = <&cru SRST_USBHOST0_PHY>;
+ reset-names = "phy-reset";
+};
+
+&usbphy2 {
+ resets = <&cru SRST_USBHOST1_PHY>;
+ reset-names = "phy-reset";
+ vbus-supply = <&vcc_host_5v>;
+};
+
+&usb_host0_ehci {
+ dr_mode = "host";
+ reg = <0x0 0xff500000 0x0 0x20000>;
+ status = "disabled";
+};
+
+/*
+ * Enable the host only USB controller. vbus-supply property allows u-boot
+ * to turn power on for the vbus and allow booting from USB devices
+ */
+&usb_host1 {
+ dr_mode = "host";
+ vbus-supply = <&vcc_host_5v>;
+ status = "okay";
+};
+
+/*
+ * Enable the OTG USB controller. hnp-srp-disable is necessary to allow
+ * it work while in u-boot. Also we attach it to the proper regulator
+ * to enable power during boot phase and allow booting from USB devices
+ */
+&usb_otg {
+ hnp-srp-disable;
+ vbus-supply = <&vcc_otg_5v>;
+ status = "okay";
+};
+
+/*
+ * Disabling vop big because somewhere in some documentation it is stated
+ * that only one vop should be enabled to get video console
+ */
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
+ status = "okay";
+};
+
+&wdt {
+ status = "okay";
+};
+
+&uart2 {
+ bootph-all;
+};
+
+&gpio0 {
+ bootph-all;
+};
+
+&gpio7 {
+ bootph-all;
+};
+
+&i2c5 {
+ status="okay";
+ bootph-all;
+};
+
+&efuse {
+ status="okay";
+ bootph-all;
+};
+
+&pcfg_pull_up {
+ bootph-all;
+};
+
--
Armbian