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[dev][h6] update opp, fix stability issue

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new values are based on stabilityTester results
when using 930mV for 1.6GHz and 980mV for 1.8GHz, xhpl failed randomly.
So 930/980mV are the critical operation voltage.Then increase 10mV and
run 100 times test, result shows that xhpl (not always) failed 1~2 times.
It seems +10mV is still not enough to ensure dc-dc output voltage always
above operation voltage, that means the design of dc-dc converter is not
good enough that results in large ripple.
The testing script is "github.com/mzhboy/StabilityTester"
The following configuration have been tested.

1.08-1.32-1.48-1.64-1.8 GHz
900-910-920-930-990   *ok, 930 failed 2/100
900-900-910-940-990   *ok, 990 failed 1/100
890-900-910-940-990   *ok, 990 failed 1/100
880-880-910-940-1000  *ok, 940 failed 2/100
880-880-910-950-1000  *ok, 1000 failed 1/100
880-880-910-950-1010  *ok
This commit is contained in:
may 2019-06-05 03:27:12 +08:00
parent 3084b25c5e
commit 77f7231226
1 changed files with 7 additions and 7 deletions
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14
patch/kernel/sunxi-dev/0012-general-h6-new-opp-table.patch
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@ -1,12 +1,12 @@
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 141fd186b..4ab42048d 100644
index 141fd186b..4d4dcf8eb 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -67,61 +67,62 @@
};
};
+ /* 0.6~1.1V, 10mV/Step, 51 steps */
+ /* axp80,DCDC-A: 0.6~1.1V, 10mV/Step, 51 steps; 1.12~1.52V, 20mV/Step, 21 Steps */
cpu_opp_table: opp_table {
compatible = "operating-points-v2";
opp-shared;
@ -42,35 +42,35 @@ index 141fd186b..4ab42048d 100644
opp@1080000000 {
opp-hz = /bits/ 64 <1080000000>;
- opp-microvolt = <940000 940000 940000>;
+ opp-microvolt = <880000 880000 900000>;
+ opp-microvolt = <880000 880000 940000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
opp@1320000000 {
opp-hz = /bits/ 64 <1320000000>;
- opp-microvolt = <1000000 1000000 1000000>;
+ opp-microvolt = <880000 880000 900000>;
+ opp-microvolt = <880000 880000 960000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
opp@1488000000 {
opp-hz = /bits/ 64 <1488000000>;
- opp-microvolt = <1060000 1060000 1060000>;
+ opp-microvolt = <900000 900000 920000>;
+ opp-microvolt = <910000 900000 980000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
opp@1640000000 {
opp-hz = /bits/ 64 <1640000000>;
- opp-microvolt = <1160000 1160000 1160000>;
+ opp-microvolt = <910000 910000 930000>;
+ opp-microvolt = <950000 910000 1100000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
opp@1800000000 {
opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <1160000 1160000 1160000>;
+ opp-microvolt = <950000 930000 960000>;
+ opp-microvolt = <1010000 930000 1160000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
};