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u-boot usb m1 (#3221)

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Oleg 2021-10-27 19:56:02 +03:00 committed by GitHub
parent be5f2b8c75
commit 7789fef83f
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7 changed files with 282 additions and 3 deletions
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4
config/boards/station-m1.wip
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@ -1,11 +1,11 @@
# Rockchip RK3328 quad core 1GB-4GB GBE eMMC USB3 WiFi
BOARD_NAME="Station M1"
BOARDFAMILY="rockchip64"
BOOTCONFIG="rock64-rk3328_defconfig"
BOOTCONFIG="roc-pc-rk3328_defconfig"
KERNEL_TARGET="legacy,current,edge"
FULL_DESKTOP="yes"
BOOT_LOGO="desktop"
BOOT_FDT_FILE="rockchip/rk3328-roc-pc.dtb"
SRC_EXTLINUX="yes"
SRC_CMDLINE="console=uart8250,mmio32,0xff130000 console=tty0"
SRC_CMDLINE="console=ttyS2,1500000 console=tty0"
ASOUND_STATE="asound.state.station-m1"

2
config/boards/station-p1.wip
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@ -8,5 +8,5 @@ BOOT_LOGO="desktop"
BOOT_FDT_FILE="rockchip/rk3399-roc-pc-plus.dtb"
BOOT_SUPPORT_SPI=yes
SRC_EXTLINUX="yes"
SRC_CMDLINE="console=uart8250,mmio32,0xff1a0000 console=tty0"
SRC_CMDLINE="console=ttyS2,1500000 console=tty0"
ASOUND_STATE="asound.state.station-p1"

13
patch/u-boot/u-boot-rockchip64-mainline/board_station-m1/u-boot-0010-rk-usb-start.patch Normal file
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@ -0,0 +1,13 @@
--- a/include/configs/rockchip-common.h
+++ b/include/configs/rockchip-common.h
@@ -39,8 +39,8 @@
#endif
#define BOOT_TARGET_DEVICES(func) \
+ BOOT_TARGET_USB(func) \
BOOT_TARGET_MMC(func) \
- BOOT_TARGET_USB(func) \
BOOT_TARGET_PXE(func) \
BOOT_TARGET_DHCP(func)

107
patch/u-boot/u-boot-rockchip64-mainline/board_station-m1/u-boot-rk-rk3328-roc-pc-config.patch Normal file
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@ -0,0 +1,107 @@
--- /dev/null
+++ b/configs/roc-pc-rk3328_defconfig
@@ -0,0 +1,103 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_GPIO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-roc-pc"
+CONFIG_ROCKCHIP_RK3328=y
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_DEBUG_UART_BASE=0xFF130000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-roc-pc.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_R=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_TPL_OF_PLATDATA=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSINFO=y
+CONFIG_SYSINFO_SMBIOS=y
+CONFIG_SYSRESET=y
+# CONFIG_TPL_SYSRESET is not set
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y

127
patch/u-boot/u-boot-rockchip64-mainline/board_station-m1/u-boot-rk-rk3328-roc-pc-dts.patch Normal file
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@ -0,0 +1,127 @@
--- /dev/null
+++ b/arch/arm/dts/rk3328-roc-pc.dts
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2021 T-Chip Intelligent Technology Co., Ltd
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+
+#include "rk3328-roc-cc.dts"
+
+/ {
+ model = "Firefly ROC-RK3328-PC";
+ compatible = "firefly,roc-rk3328-pc", "rockchip,rk3328";
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1750000>;
+
+ /* This button is unpopulated out of the factory. */
+ button-recovery {
+ label = "Recovery";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <10000>;
+ };
+ };
+
+ ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
+ linux,rc-map-name = "rc-station";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_int>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_en>, <&wifi_host_wake>;
+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&codec {
+ mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>;
+};
+
+&gpu {
+ mali-supply = <&vdd_logic>;
+};
+
+&pinctrl {
+ ir {
+ ir_int: ir-int {
+ rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdmmcio {
+ sdio_per_pin: sdio-per-pin {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ wifi {
+ wifi_en: wifi-en {
+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wifi_host_wake: wifi-host-wake {
+ rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_4ma>;
+ };
+
+ bt_rst: bt-rst {
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_en: bt-en {
+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+//&sdmmc_ext {
+// bus-width = <4>;
+// cap-sd-highspeed;
+// cap-sdio-irq;
+// keep-power-in-suspend;
+// mmc-pwrseq = <&sdio_pwrseq>;
+// non-removable;
+// num-slots = <1>;
+// pinctrl-names = "default";
+// pinctrl-0 = <&sdmmc0ext_bus4 &sdmmc0ext_cmd &sdmmc0ext_clk>;
+// sd-uhs-sdr104;
+// status = "okay";
+//};
+
+&pmic_int_l {
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+};
+
+&rk805 {
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+};
+
+&saradc {
+ vref-supply = <&vcc_18>;
+ status = "okay";
+};
+
+&usb20_host_drv {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+};
+
+&vcc_host1_5v {
+ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+};
+
+&vcc_sdio {
+ gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio_per_pin>;
+};

21
patch/u-boot/u-boot-rockchip64-mainline/board_station-m1/u-boot-rk-rk3328-roc-pc-include.patch Normal file
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@ -0,0 +1,21 @@
--- /dev/null
+++ b/include/configs/roc_rk3328_pc.h
@@ -0,0 +1,18 @@
+/*
+ * (C) Copyright 2018 FIREFLY
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ROC_RK3328_PC_H
+#define __ROC_RK3328_PC_H
+
+#include <configs/rk3328_common.h>
+
+#define CONFIG_SYS_MMC_ENV_DEV 1
+
+#define SDRAM_BANK_SIZE (2UL << 30)
+
+#define CONFIG_CONSOLE_SCROLL_LINES 10
+
+#endif

11
patch/u-boot/u-boot-rockchip64-mainline/board_station-m1/u-boot-rk-rk3328-roc-pc-make-dts.patch Normal file
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@ -0,0 +1,11 @@
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -111,6 +111,7 @@
rk3328-evb.dtb \
rk3328-nanopi-r2s.dtb \
rk3328-roc-cc.dtb \
+ rk3328-roc-pc.dtb \
rk3328-rock64.dtb \
rk3328-rock-pi-e.dtb