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Merge pull request #270 from ThomasKaiser/master

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Define safe voltage/cpufreq defaults for sun8i/dev
This commit is contained in:
Igor Pečovnik 2016-04-09 16:40:21 +02:00
commit 763040bfa3
5 changed files with 1586 additions and 4 deletions
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2
config/linux-sunxi-dev.config
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@ -2857,6 +2857,7 @@ CONFIG_CLOCK_THERMAL=y
# CONFIG_THERMAL_EMULATION is not set
# CONFIG_IMX_THERMAL is not set
# CONFIG_RCAR_THERMAL is not set
CONFIG_SUN8I_THS=m
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
@ -3040,6 +3041,7 @@ CONFIG_REGULATOR_SKY81452=m
# CONFIG_REGULATOR_TPS65023 is not set
# CONFIG_REGULATOR_TPS6507X is not set
# CONFIG_REGULATOR_TPS6524X is not set
CONFIG_REGULATOR_SY8106A=y
CONFIG_MEDIA_SUPPORT=y
#

254
patch/kernel/sunxi-dev/0001-add-bananapim2-plus.patch Normal file
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@ -0,0 +1,254 @@
diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2plus.dts
new file mode 100644
index 0000000..ca7c0ec
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2plus.dts
@@ -0,0 +1,234 @@
+/*
+ * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Sinovoip Banana Pi M2 Plus";
+ compatible = "sinovoip,bananapi-m2-plus", "allwinner,sun8i-h3";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_r_opc>;
+
+ status_led {
+ label = "bananapi:red:status";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ r_gpio_keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sw_r_opc>;
+
+ sw2 {
+ label = "sw2";
+ linux,code = <BTN_1>;
+ gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>;
+ };
+
+ sw4 {
+ label = "sw4";
+ linux,code = <BTN_0>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_pwrseq_pin_orangepi>;
+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 WIFI_EN */
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_power_pin_orangepi>;
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_a>;
+ vmmc-supply = <&reg_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
+&r_pio {
+ leds_r_opc: led_pins@0 {
+ allwinner,pins = "PL10";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ sw_r_opc: key_pins@0 {
+ allwinner,pins = "PL3", "PL4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ wifi_pwrseq_pin_orangepi: wifi_pwrseq_pin@0 {
+ allwinner,pins = "PL7";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&reg_usb1_vbus {
+ gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usb1_vbus_pin_a {
+ allwinner,pins = "PG13";
+};
+
+&usbphy {
+ usb1_vbus-supply = <&reg_usb1_vbus>;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&mmc2_8bit_pins {
+ /* Increase drive strength for DDR modes */
+ allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+ /* eMMC is missing pull-ups */
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
+&pio {
+ gmac_power_pin_orangepi: gmac_power_pin@0 {
+ allwinner,pins = "PD6";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy = <&phy1>;
+ phy-mode = "rgmii";
+ phy-supply = <&reg_gmac_3v3>;
+ status = "okay";
+ phy1: ethernet-phy@1 {
+ reg = <0>;
+ };
+};
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4666e08..94e7470 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -722,7 +722,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a83t-cubietruck-plus.dtb \
sun8i-h3-orangepi-2.dtb \
sun8i-h3-orangepi-pc.dtb \
- sun8i-h3-orangepi-plus.dtb
+ sun8i-h3-orangepi-plus.dtb \
+ sun8i-h3-bananapi-m2plus.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb

1238
patch/kernel/sunxi-dev/0002-sun8i-sy8106a-dvfs-cpufreq.patch.disabled Normal file
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54
patch/u-boot/u-boot-dev/u-boot-99-opi-change-build-settings.patch
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@ -2,16 +2,18 @@ diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index 4e9051d..6fba0b0 100644
--- a/configs/orangepi_pc_defconfig
+++ b/configs/orangepi_pc_defconfig
@@ -17,3 +17,5 @@ CONFIG_USB_EHCI_HCD=y
@@ -17,3 +17,7 @@ CONFIG_USB_EHCI_HCD=y
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
CONFIG_USB3_VBUS_PIN=""
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_SY8106A_VOUT1_VOLT=1200
+CONFIG_SYS_CLK_FREQ=1008000000
diff -Nur a/configs/orangepi_h3_defconfig b/configs/orangepi_h3_defconfig
--- a/configs/orangepi_h3_defconfig 1970-01-01 01:00:00.000000000 +0100
+++ b/configs/orangepi_h3_defconfig 2016-02-19 00:58:31.007705977 +0100
@@ -0,0 +1,18 @@
@@ -0,0 +1,20 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
@ -33,22 +35,26 @@ diff -Nur a/configs/orangepi_h3_defconfig b/configs/orangepi_h3_defconfig
+CONFIG_USB3_VBUS_PIN=""
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_SY8106A_VOUT1_VOLT=1200
+CONFIG_SYS_CLK_FREQ=1008000000
diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index ff124bd..d78f8c7 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -18,3 +18,5 @@ CONFIG_SY8106A_POWER=y
@@ -18,3 +18,7 @@ CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB1_VBUS_PIN="PG13"
CONFIG_SYS_EXTRA_OPTIONS="SATAPWR=SUNXI_GPG(11)"
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_SY8106A_VOUT1_VOLT=1200
+CONFIG_SYS_CLK_FREQ=1008000000
diff --git a/configs/Sinovoip_BPI_M2_plus_defconfig b/configs/Sinovoip_BPI_M2_plus_defconfig
new file mode 100644
index 0000000..2e7c095
--- /dev/null
+++ b/configs/Sinovoip_BPI_M2_plus_defconfig
@@ -0,0 +1,17 @@
@@ -0,0 +1,18 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
@ -66,6 +72,7 @@ index 0000000..2e7c095
+CONFIG_USB_EHCI_HCD=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_SYS_CLK_FREQ=816000000
diff --git a/arch/arm/dts/sun8i-h3-bananapi-m2plus.dts b/arch/arm/dts/sun8i-h3-bananapi-m2plus.dts
new file mode 100644
index 0000000..da6481f
@ -381,3 +388,42 @@ index c2f63c5..e7b6334 100644
gic: interrupt-controller@01c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig
index ff9ac09..992cfa1 100644
--- a/configs/orangepi_2_defconfig
+++ b/configs/orangepi_2_defconfig
@@ -16,3 +16,7 @@ CONFIG_CMD_GPIO=y
CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB1_VBUS_PIN="PG13"
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_SY8106A_VOUT1_VOLT=1200
+CONFIG_SYS_CLK_FREQ=1008000000
diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig
new file mode 100644
index 0000000..a69961c
--- /dev/null
+++ b/configs/orangepi_one_defconfig
@@ -0,0 +1,21 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=624
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+# CONFIG_VIDEO is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB1_VBUS_PIN=""
+CONFIG_USB2_VBUS_PIN=""
+CONFIG_USB3_VBUS_PIN=""
+CONFIG_SYS_CLK_FREQ=1008000000
+CONFIG_DM=y
+CONFIG_DM_GPIO=y

42
patch/u-boot/u-boot-dev/u-boot-set-safe-axi_apb-clock-dividers.patch Normal file
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@ -0,0 +1,42 @@
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
index 15272c9..cedddc2 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -117,8 +117,8 @@ void clock_set_pll1(unsigned int clk)
sdelay(200);
/* Switch CPU to PLL1 */
- writel(AXI_DIV_3 << AXI_DIV_SHIFT |
- ATB_DIV_2 << ATB_DIV_SHIFT |
+ writel(AXI_DIV_4 << AXI_DIV_SHIFT |
+ ATB_DIV_4 << ATB_DIV_SHIFT |
CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
&ccm->cpu_axi_cfg);
}
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index f2990db..b3a8575 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -180,6 +180,7 @@ struct sunxi_ccm_reg {
#define CCM_PLL1_CTRL_N(n) ((((n) - 1) & 0x1f) << 8)
#define CCM_PLL1_CTRL_P(n) (((n) & 0x3) << 16)
#define CCM_PLL1_CTRL_EN (0x1 << 31)
+#define CCM_PLL1_CTRL_LOCK (0x1 << 28)
#define CCM_PLL3_CTRL_M_SHIFT 0
#define CCM_PLL3_CTRL_M_MASK (0xf << CCM_PLL3_CTRL_M_SHIFT)
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
index cedddc2..3fe9305 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -114,7 +114,9 @@ void clock_set_pll1(unsigned int clk)
writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
- sdelay(200);
+
+ while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_CTRL_LOCK))
+ ;
/* Switch CPU to PLL1 */
writel(AXI_DIV_4 << AXI_DIV_SHIFT |