rockchip64: remove patches upstreamed with 6.18.16
This commit is contained in:
EvilOlaf
Werner
parent
9ba4563ad9
commit
70ec868367
@ -1,49 +0,0 @@
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Date: Mon, 22 Sep 2025 13:15:02 +0200
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Subject: media: verisilicon: AV1: Fix enable cdef computation
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Testing V4L2_AV1_SEQUENCE_FLAG_ENABLE_CDEF flag isn't enough
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to know if cdef bit has to be set.
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If any of the used cdef fields isn't zero then we must enable
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cdef feature on the hardware.
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Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Fixes: 727a400686a2c ("media: verisilicon: Add Rockchip AV1 decoder")
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---
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drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c | 10 ++++++++--
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1 file changed, 8 insertions(+), 2 deletions(-)
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diff --git a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
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index 111111111111..222222222222 100644
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--- a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
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+++ b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
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@@ -1396,8 +1396,16 @@ static void rockchip_vpu981_av1_dec_set_cdef(struct hantro_ctx *ctx)
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u16 luma_sec_strength = 0;
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u32 chroma_pri_strength = 0;
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u16 chroma_sec_strength = 0;
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+ bool enable_cdef;
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int i;
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+ enable_cdef = !(cdef->bits == 0 &&
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+ cdef->damping_minus_3 == 0 &&
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+ cdef->y_pri_strength[0] == 0 &&
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+ cdef->y_sec_strength[0] == 0 &&
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+ cdef->uv_pri_strength[0] == 0 &&
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+ cdef->uv_sec_strength[0] == 0);
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+ hantro_reg_write(vpu, &av1_enable_cdef, enable_cdef);
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hantro_reg_write(vpu, &av1_cdef_bits, cdef->bits);
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hantro_reg_write(vpu, &av1_cdef_damping, cdef->damping_minus_3);
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@@ -1953,8 +1961,6 @@ static void rockchip_vpu981_av1_dec_set_parameters(struct hantro_ctx *ctx)
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!!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_SHOW_FRAME));
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hantro_reg_write(vpu, &av1_switchable_motion_mode,
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!!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_IS_MOTION_MODE_SWITCHABLE));
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- hantro_reg_write(vpu, &av1_enable_cdef,
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- !!(ctrls->sequence->flags & V4L2_AV1_SEQUENCE_FLAG_ENABLE_CDEF));
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hantro_reg_write(vpu, &av1_allow_masked_compound,
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!!(ctrls->sequence->flags
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& V4L2_AV1_SEQUENCE_FLAG_ENABLE_MASKED_COMPOUND));
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--
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Armbian
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@ -1,31 +0,0 @@
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Date: Thu, 8 Jan 2026 10:56:28 +0100
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Subject: media: verisilicon: AV1: Set IDR flag for intra_only frame type
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Intra_only frame could be considered as a key frame so
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Instantaneous Decoding Refresh (IDR) flag must be set of the both
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case and not only for key frames.
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Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Fixes: 727a400686a2c ("media: verisilicon: Add Rockchip AV1 decoder")
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---
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drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
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index 111111111111..222222222222 100644
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--- a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
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+++ b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
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@@ -1995,7 +1995,7 @@ static void rockchip_vpu981_av1_dec_set_parameters(struct hantro_ctx *ctx)
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!!(ctrls->frame->quantization.flags
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& V4L2_AV1_QUANTIZATION_FLAG_DELTA_Q_PRESENT));
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- hantro_reg_write(vpu, &av1_idr_pic_e, !ctrls->frame->frame_type);
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+ hantro_reg_write(vpu, &av1_idr_pic_e, IS_INTRA(ctrls->frame->frame_type));
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hantro_reg_write(vpu, &av1_quant_base_qindex, ctrls->frame->quantization.base_q_idx);
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hantro_reg_write(vpu, &av1_bit_depth_y_minus8, ctx->bit_depth - 8);
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hantro_reg_write(vpu, &av1_bit_depth_c_minus8, ctx->bit_depth - 8);
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--
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Armbian
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@ -1,78 +0,0 @@
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Date: Tue, 9 Dec 2025 11:34:17 +0100
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Subject: media: verisilicon: AV1: Fix tx mode bit setting
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AV1 specification describes 3 possibles tx modes: 4x4 only,
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largest and select.
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Hardware allows 5 possibles tx modes: 4x4 only, 8x8, 16x16,
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32x32 and select.
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Since the both aren't exactly matching we need to add a mapping
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function to set the correct mode on hardware.
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Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
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Fixes: 727a400686a2c ("media: verisilicon: Add Rockchip AV1 decoder")
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---
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drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c | 27 +++++++++-
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1 file changed, 26 insertions(+), 1 deletion(-)
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diff --git a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
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index 111111111111..222222222222 100644
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--- a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
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+++ b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
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@@ -72,6 +72,14 @@
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: AV1_DIV_ROUND_UP_POW2((_value_), (_n_))); \
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})
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+enum rockchip_av1_tx_mode {
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+ ROCKCHIP_AV1_TX_MODE_ONLY_4X4 = 0,
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+ ROCKCHIP_AV1_TX_MODE_8X8 = 1,
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+ ROCKCHIP_AV1_TX_MODE_16x16 = 2,
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+ ROCKCHIP_AV1_TX_MODE_32x32 = 3,
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+ ROCKCHIP_AV1_TX_MODE_SELECT = 4,
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+};
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+
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struct rockchip_av1_film_grain {
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u8 scaling_lut_y[256];
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u8 scaling_lut_cb[256];
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@@ -1935,11 +1943,26 @@ static void rockchip_vpu981_av1_dec_set_reference_frames(struct hantro_ctx *ctx)
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rockchip_vpu981_av1_dec_set_other_frames(ctx);
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}
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+static int rockchip_vpu981_av1_get_hardware_tx_mode(enum v4l2_av1_tx_mode tx_mode)
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+{
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+ switch (tx_mode) {
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+ case V4L2_AV1_TX_MODE_ONLY_4X4:
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+ return ROCKCHIP_AV1_TX_MODE_ONLY_4X4;
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+ case V4L2_AV1_TX_MODE_LARGEST:
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+ return ROCKCHIP_AV1_TX_MODE_32x32;
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+ case V4L2_AV1_TX_MODE_SELECT:
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+ return ROCKCHIP_AV1_TX_MODE_SELECT;
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+ }
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+
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+ return ROCKCHIP_AV1_TX_MODE_32x32;
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+}
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+
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static void rockchip_vpu981_av1_dec_set_parameters(struct hantro_ctx *ctx)
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{
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struct hantro_dev *vpu = ctx->dev;
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struct hantro_av1_dec_hw_ctx *av1_dec = &ctx->av1_dec;
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struct hantro_av1_dec_ctrls *ctrls = &av1_dec->ctrls;
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+ int tx_mode;
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hantro_reg_write(vpu, &av1_skip_mode,
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!!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_SKIP_MODE_PRESENT));
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@@ -2005,7 +2028,9 @@ static void rockchip_vpu981_av1_dec_set_parameters(struct hantro_ctx *ctx)
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!!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_ALLOW_HIGH_PRECISION_MV));
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hantro_reg_write(vpu, &av1_comp_pred_mode,
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(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_REFERENCE_SELECT) ? 2 : 0);
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- hantro_reg_write(vpu, &av1_transform_mode, (ctrls->frame->tx_mode == 1) ? 3 : 4);
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+
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+ tx_mode = rockchip_vpu981_av1_get_hardware_tx_mode(ctrls->frame->tx_mode);
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+ hantro_reg_write(vpu, &av1_transform_mode, tx_mode);
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hantro_reg_write(vpu, &av1_max_cb_size,
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(ctrls->sequence->flags
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& V4L2_AV1_SEQUENCE_FLAG_USE_128X128_SUPERBLOCK) ? 7 : 6);
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--
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Armbian
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