Update LPDDR3/SoPine support patch
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@ -69,7 +69,7 @@ index 6f0ed5d..6261322 100644
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+ writel(MCTL_LPDDR3_MR2, &mctl_ctl->mr[2]);
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+ writel(MCTL_LPDDR3_MR3, &mctl_ctl->mr[3]);
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+
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+ /* timing parameters for LPDDR3 */
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+ /* timing parameters for LPDDR3, copied from dram_sun8i_a83t.c */
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+ tfaw = max(ns_to_t(50), 4);
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+ trrd = max(ns_to_t(10), 2);
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+ trcd = max(ns_to_t(24), 2);
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@ -106,10 +106,15 @@ index 6f0ed5d..6261322 100644
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MCTL_CR_EIGHT_BANKS | MCTL_CR_BUS_WIDTH(para->bus_width) |
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(para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) |
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MCTL_CR_PAGE_SIZE(para->page_size) |
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@@ -628,6 +662,17 @@ static void mctl_auto_detect_dram_size(struct dram_para *para)
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@@ -628,6 +661,22 @@ static void mctl_auto_detect_dram_size(struct dram_para *para)
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3, 4, 0, 3, 4, 1, 4, 0, \
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1, 1, 0, 1, 13, 5, 4 }
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+/* FIXME: Last byte of each row of write delays
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+ * doesn't match memory dump values from boot0 on Pine64+
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+ * so copying the second to last byte instead?
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+ */
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+
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+#define SUN50I_A64_LPDDR3_DX_READ_DELAYS \
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+ {{ 16, 16, 16, 16, 17, 16, 16, 17, 16, 6, 5 }, \
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+ { 17, 17, 17, 17, 17, 17, 17, 17, 17, 6, 5 }, \
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@ -119,7 +124,7 @@ index 6f0ed5d..6261322 100644
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+ {{ 6, 6, 6, 6, 6, 6, 6, 6, 6, 16, 16 }, \
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+ { 6, 6, 6, 6, 7, 7, 7, 7, 6, 18, 18 }, \
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+ { 1, 0, 1, 1, 1, 1, 1, 1, 0, 11, 11 }, \
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+ { 1, 0, 0, 1, 1, 1, 1, 1, 0, 12, 12 }}
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+ { 1, 0, 0, 1, 1, 1, 1, 1, 0, 14, 14 }}
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+
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#define SUN8I_H5_DX_READ_DELAYS \
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{{ 14, 15, 17, 17, 17, 17, 17, 18, 17, 3, 3 }, \
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