Update LPDDR3/SoPine support patch

This commit is contained in:
zador-blood-stained 2017-02-08 23:56:03 +03:00
parent 475fd3c98d
commit 4a2986b715

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@ -69,7 +69,7 @@ index 6f0ed5d..6261322 100644
+ writel(MCTL_LPDDR3_MR2, &mctl_ctl->mr[2]);
+ writel(MCTL_LPDDR3_MR3, &mctl_ctl->mr[3]);
+
+ /* timing parameters for LPDDR3 */
+ /* timing parameters for LPDDR3, copied from dram_sun8i_a83t.c */
+ tfaw = max(ns_to_t(50), 4);
+ trrd = max(ns_to_t(10), 2);
+ trcd = max(ns_to_t(24), 2);
@ -106,10 +106,15 @@ index 6f0ed5d..6261322 100644
MCTL_CR_EIGHT_BANKS | MCTL_CR_BUS_WIDTH(para->bus_width) |
(para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) |
MCTL_CR_PAGE_SIZE(para->page_size) |
@@ -628,6 +662,17 @@ static void mctl_auto_detect_dram_size(struct dram_para *para)
@@ -628,6 +661,22 @@ static void mctl_auto_detect_dram_size(struct dram_para *para)
3, 4, 0, 3, 4, 1, 4, 0, \
1, 1, 0, 1, 13, 5, 4 }
+/* FIXME: Last byte of each row of write delays
+ * doesn't match memory dump values from boot0 on Pine64+
+ * so copying the second to last byte instead?
+ */
+
+#define SUN50I_A64_LPDDR3_DX_READ_DELAYS \
+ {{ 16, 16, 16, 16, 17, 16, 16, 17, 16, 6, 5 }, \
+ { 17, 17, 17, 17, 17, 17, 17, 17, 17, 6, 5 }, \
@ -119,7 +124,7 @@ index 6f0ed5d..6261322 100644
+ {{ 6, 6, 6, 6, 6, 6, 6, 6, 6, 16, 16 }, \
+ { 6, 6, 6, 6, 7, 7, 7, 7, 6, 18, 18 }, \
+ { 1, 0, 1, 1, 1, 1, 1, 1, 0, 11, 11 }, \
+ { 1, 0, 0, 1, 1, 1, 1, 1, 0, 12, 12 }}
+ { 1, 0, 0, 1, 1, 1, 1, 1, 0, 14, 14 }}
+
#define SUN8I_H5_DX_READ_DELAYS \
{{ 14, 15, 17, 17, 17, 17, 17, 18, 17, 3, 3 }, \