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Merge branch 'master' of https://github.com/armbian/build

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This commit is contained in:
Igor Pecovnik 2020-01-03 11:43:16 +01:00
commit 441bd84149
5 changed files with 103 additions and 5 deletions
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2
config/kernel/linux-rk3399-legacy.config
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@ -5905,7 +5905,7 @@ CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
CONFIG_EXT4_ENCRYPTION=y
CONFIG_EXT4_FS_ENCRYPTION=y
CONFIG_EXT4_DEBUG=y
# CONFIG_EXT4_DEBUG is not set
CONFIG_JBD2=y
# CONFIG_JBD2_DEBUG is not set
CONFIG_FS_MBCACHE=y

2
config/kernel/linux-rockchip64-legacy.config
View File

@ -5638,7 +5638,7 @@ CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
CONFIG_EXT4_ENCRYPTION=y
CONFIG_EXT4_FS_ENCRYPTION=y
CONFIG_EXT4_DEBUG=y
# CONFIG_EXT4_DEBUG is not set
CONFIG_JBD2=y
# CONFIG_JBD2_DEBUG is not set
CONFIG_FS_MBCACHE=y

6
packages/bsp/common/usr/lib/armbian/armbian-truncate-logs
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@ -22,9 +22,9 @@ if [ $logusage -ge $treshold ]; then
# rotate logs on "disk"
/usr/sbin/logrotate --force /etc/logrotate.conf
# truncate
/usr/bin/find /var/log -name '*.log' -or -name '*.xz' -or -name 'lastlog' -or -name 'messages' -or -name 'debug' -or -name 'syslog' | xargs truncate --size 0
/usr/bin/find /var/log -name 'btmp' -or -name 'wtmp' -or -name 'faillog' -or -name 'firewalld' | xargs truncate --size 0
/usr/bin/find /var/log -name 'mail.err' -or -name 'mail.info' -or -name 'mail.warning' | xargs truncate --size 0
/usr/bin/find /var/log -name '*.log' -or -name '*.xz' -or -name 'lastlog' -or -name 'messages' -or -name 'debug' -or -name 'syslog' | xargs truncate --size 0 >/dev/null 2>&1
/usr/bin/find /var/log -name 'btmp' -or -name 'wtmp' -or -name 'faillog' -or -name 'firewalld' | xargs truncate --size 0 >/dev/null 2>&1
/usr/bin/find /var/log -name 'mail.err' -or -name 'mail.info' -or -name 'mail.warning' | xargs truncate --size 0 >/dev/null 2>&1
# remove
/usr/bin/find /var/log -name '*.[0-9]' -or -name '*.gz' | xargs rm >/dev/null 2>&1
fi

49
patch/u-boot/u-boot-mvebu-dev/board_clearfogbase/do_pcie_reset_during_init.patch Normal file
View File

@ -0,0 +1,49 @@
diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c
index f644547..f6e8ad5 100644
--- a/board/solidrun/clearfog/clearfog.c
+++ b/board/solidrun/clearfog/clearfog.c
@@ -10,6 +10,7 @@
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
+#include <asm-generic/gpio.h>
#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
#include <../serdes/a38x/high_speed_env_spec.h>
@@ -120,6 +121,36 @@ int board_init(void)
setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
mdelay(10);
+#ifdef CONFIG_DM_GPIO
+ struct gpio_desc pcie0_reset,
+ pcie1_reset;
+ int res;
+
+ /* Toogle PERST# on miniPCIe1 (CON2) and miniPCIe0 (CON3) */
+ res = dm_gpio_lookup_name("gpio@20_1", &pcie0_reset);
+ if (!res) {
+ res = dm_gpio_request(&pcie0_reset, "pcie0-reset");
+ if (!res)
+ dm_gpio_set_dir_flags(&pcie0_reset,GPIOD_IS_OUT |
+ GPIOD_ACTIVE_LOW);
+ }
+
+ res = dm_gpio_lookup_name("gpio@20_2", &pcie1_reset);
+ if (!res) {
+ res = dm_gpio_request(&pcie1_reset, "pcie1-reset");
+ if (!res)
+ dm_gpio_set_dir_flags(&pcie1_reset,GPIOD_IS_OUT |
+ GPIOD_ACTIVE_LOW);
+ }
+
+ dm_gpio_set_value(&pcie0_reset, 1);
+ dm_gpio_set_value(&pcie1_reset, 1);
+ mdelay(100);
+ dm_gpio_set_value(&pcie0_reset, 0);
+ dm_gpio_set_value(&pcie1_reset, 0);
+ mdelay(100);
+#endif
+
return 0;
}

49
patch/u-boot/u-boot-mvebu-dev/board_clearfogpro/do_pcie_reset_during_init.patch Normal file
View File

@ -0,0 +1,49 @@
diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c
index f644547..f6e8ad5 100644
--- a/board/solidrun/clearfog/clearfog.c
+++ b/board/solidrun/clearfog/clearfog.c
@@ -10,6 +10,7 @@
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
+#include <asm-generic/gpio.h>
#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
#include <../serdes/a38x/high_speed_env_spec.h>
@@ -120,6 +121,36 @@ int board_init(void)
setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
mdelay(10);
+#ifdef CONFIG_DM_GPIO
+ struct gpio_desc pcie0_reset,
+ pcie1_reset;
+ int res;
+
+ /* Toogle PERST# on miniPCIe1 (CON2) and miniPCIe0 (CON3) */
+ res = dm_gpio_lookup_name("gpio@20_1", &pcie0_reset);
+ if (!res) {
+ res = dm_gpio_request(&pcie0_reset, "pcie0-reset");
+ if (!res)
+ dm_gpio_set_dir_flags(&pcie0_reset,GPIOD_IS_OUT |
+ GPIOD_ACTIVE_LOW);
+ }
+
+ res = dm_gpio_lookup_name("gpio@20_2", &pcie1_reset);
+ if (!res) {
+ res = dm_gpio_request(&pcie1_reset, "pcie1-reset");
+ if (!res)
+ dm_gpio_set_dir_flags(&pcie1_reset,GPIOD_IS_OUT |
+ GPIOD_ACTIVE_LOW);
+ }
+
+ dm_gpio_set_value(&pcie0_reset, 1);
+ dm_gpio_set_value(&pcie1_reset, 1);
+ mdelay(100);
+ dm_gpio_set_value(&pcie0_reset, 0);
+ dm_gpio_set_value(&pcie1_reset, 0);
+ mdelay(100);
+#endif
+
return 0;
}