[ sunxi ] lower DDR clock rate to 504MHz for H5 boards

This change brings the u-boot into line with the FriendlyARM BSP default (e.g., see
https://github.com/friendlyarm/u-boot/blob/sunxi-v2017.x/configs/nanopi_h5_defconfig),
and addresses serious device instabilities under various load conditions
This commit is contained in:
5kft 2020-03-01 16:54:20 -08:00
parent 5bf41736b9
commit 42201fd3fc
2 changed files with 6 additions and 6 deletions

View File

@ -143,7 +143,7 @@ index 0000000..4624ec3
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN50I_H5=y
+CONFIG_DRAM_CLK=624
+CONFIG_DRAM_CLK=504
+CONFIG_DRAM_ZQ=3881977
+CONFIG_MACPWR="PD6"
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo-core2"

View File

@ -111,7 +111,7 @@ index c7db07a..38b6646 100644
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN50I_H5=y
-CONFIG_DRAM_CLK=672
+CONFIG_DRAM_CLK=624
+CONFIG_DRAM_CLK=504
CONFIG_DRAM_ZQ=3881977
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@ -124,7 +124,7 @@ index f6b4ca7..34437fc 100644
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN50I_H5=y
-CONFIG_DRAM_CLK=408
+CONFIG_DRAM_CLK=624
+CONFIG_DRAM_CLK=504
CONFIG_DRAM_ZQ=3881977
CONFIG_MACPWR="PD6"
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo-plus2"
@ -193,7 +193,7 @@ index ba0f2d5..93641c3 100644
CONFIG_SPL=y
CONFIG_MACH_SUN50I_H5=y
-CONFIG_DRAM_CLK=672
+CONFIG_DRAM_CLK=624
+CONFIG_DRAM_CLK=504
CONFIG_DRAM_ZQ=3881977
+CONFIG_DRAM_ODT_EN=y
# CONFIG_DRAM_ODT_EN is not set
@ -238,7 +238,7 @@ index d7b8004..2ee5937 100644
CONFIG_SPL=y
CONFIG_MACH_SUN50I_H5=y
-CONFIG_DRAM_CLK=672
+CONFIG_DRAM_CLK=624
+CONFIG_DRAM_CLK=504
CONFIG_DRAM_ZQ=3881977
+CONFIG_DRAM_ODT_EN=y
# CONFIG_DRAM_ODT_EN is not set
@ -268,7 +268,7 @@ index 57c63b962a..ec9e5c73b1 100644
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN50I_H5=y
-CONFIG_DRAM_CLK=672
+CONFIG_DRAM_CLK=624
+CONFIG_DRAM_CLK=504
CONFIG_DRAM_ZQ=3881977
CONFIG_MMC0_CD_PIN="PH13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2