rk3568: add 51.2MHz PLL rate for HDMI (#9477)

* rk3568: add 51.2MHz PLL rate for HDMI
* Fix From/Signed-off values
* Moved patch into 6.18 and 6.19 fodlers
---------
Co-authored-by: Serhii Korobkov <skorobkov78@gmail.com>

patch/kernel/archive/rockchip64-6.18/rk356x-add-51.2MHz-PLL-rate-for-HDMI.patch

@@ -0,0 +1,42 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Serhii Korobkov <skorobkov78@gmail.com>
+Date: Tue, 3 Mar 2026 22:39:55 +0000
+Subject: Patching kernel rockchip64 files drivers/clk/rockchip/clk-rk3568.c:
+ add 51.2MHz PLL rate for HDMI
+
+The rk3568_pll_rates table lacks a 51.2 MHz entry, which is the pixel
+clock required by 1024x600@60Hz displays (e.g. BigTreeTech HDMI7).
+
+Without this rate, dw_hdmi_rockchip_mode_valid() rejects all modes from
+such displays because clk_round_rate() on the HDMI ref clock (HPLL)
+cannot find a matching frequency within 0.1% tolerance. The nearest
+existing entries are 74.25 MHz and 33.3 MHz, both far outside the
+acceptable range.
+
+PLL parameters: 24 MHz * 64 / (6 * 5) = 51.2 MHz exactly.
+VCO = 24 MHz / 1 * 64 = 1536 MHz (within 800-3200 MHz range).
+
+Signed-off-by: Serhii Korobkov <skorobkov78@gmail.com>
+---
+ drivers/clk/rockchip/clk-rk3568.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
+index 97d279399..de350538a 100644
+--- a/drivers/clk/rockchip/clk-rk3568.c
++++ b/drivers/clk/rockchip/clk-rk3568.c
+@@ -88,10 +88,11 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
+ 	RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0),
+ 	RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
+ 	RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
+ 	RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0),
+ 	RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
++	RK3036_PLL_RATE(51200000, 1, 64, 6, 5, 1, 0),
+ 	RK3036_PLL_RATE(33300000, 4, 111, 5, 4, 1, 0),
+ 	{ /* sentinel */ },
+ };
+ 
+ #define RK3568_DIV_ATCLK_CORE_MASK	0x1f
+-- 
+Created with Armbian build tools https://github.com/armbian/build
+

patch/kernel/archive/rockchip64-6.19/rk356x-add-51.2MHz-PLL-rate-for-HDMI.patch

@@ -0,0 +1,42 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Serhii Korobkov <skorobkov78@gmail.com>
+Date: Tue, 3 Mar 2026 22:39:55 +0000
+Subject: Patching kernel rockchip64 files drivers/clk/rockchip/clk-rk3568.c:
+ add 51.2MHz PLL rate for HDMI
+
+The rk3568_pll_rates table lacks a 51.2 MHz entry, which is the pixel
+clock required by 1024x600@60Hz displays (e.g. BigTreeTech HDMI7).
+
+Without this rate, dw_hdmi_rockchip_mode_valid() rejects all modes from
+such displays because clk_round_rate() on the HDMI ref clock (HPLL)
+cannot find a matching frequency within 0.1% tolerance. The nearest
+existing entries are 74.25 MHz and 33.3 MHz, both far outside the
+acceptable range.
+
+PLL parameters: 24 MHz * 64 / (6 * 5) = 51.2 MHz exactly.
+VCO = 24 MHz / 1 * 64 = 1536 MHz (within 800-3200 MHz range).
+
+Signed-off-by: Serhii Korobkov <skorobkov78@gmail.com>
+---
+ drivers/clk/rockchip/clk-rk3568.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
+index 97d279399..de350538a 100644
+--- a/drivers/clk/rockchip/clk-rk3568.c
++++ b/drivers/clk/rockchip/clk-rk3568.c
+@@ -88,10 +88,11 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
+ 	RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0),
+ 	RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
+ 	RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
+ 	RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0),
+ 	RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
++	RK3036_PLL_RATE(51200000, 1, 64, 6, 5, 1, 0),
+ 	RK3036_PLL_RATE(33300000, 4, 111, 5, 4, 1, 0),
+ 	{ /* sentinel */ },
+ };
+ 
+ #define RK3568_DIV_ATCLK_CORE_MASK	0x1f
+-- 
+Created with Armbian build tools https://github.com/armbian/build
+