enoch/armbian-build
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

filogic kernel edge - change from frank-w's tree to just a git-format-patches from his tree

Browse Source
This commit is contained in:
tabris 2025-10-31 06:45:08 -04:00 committed by Igor
parent af13870a7d
commit 3fcb8ef7b2
88 changed files with 22985 additions and 185480 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
config/sources/families/filogic.conf
View File

@ -59,11 +59,8 @@ case $BRANCH in
;;
edge)
KERNELSOURCE='https://github.com/frank-w/BPI-Router-Linux.git'
KERNELBRANCH="branch:6.16-rsslro"
#KERNELSOURCE='https://github.com/tabrisnet/BPI-Router-Linux.git'
# this is just frank-w's 6.16-rsslro with the kernel.org 6.16.12 patch applied.
#KERNELBRANCH="branch:6.16.12-rsslro"
#KERNELSOURCE='https://github.com/frank-w/BPI-Router-Linux.git'
#KERNELBRANCH="branch:6.16-rsslro"
declare -g KERNEL_MAJOR_MINOR="6.16"
KERNELPATCHDIR="archive/${LINUXFAMILY}-${KERNEL_MAJOR_MINOR}"
LINUXCONFIG="linux-${LINUXFAMILY}-${BRANCH}"

185462
patch/kernel/archive/filogic-6.16/patches.armbian/0001-6.16.12.diff
View File

File diff suppressed because it is too large Load Diff

0
patch/kernel/archive/filogic-6.16/patches.armbian/0001-v6-coverletter-net-next-rework-IRQ-handling-in-mtk_e.patch Normal file
View File

99
patch/kernel/archive/filogic-6.16/patches.armbian/0002-net-ethernet-mtk_eth_soc-support-named-IRQs.patch Normal file
View File

@ -0,0 +1,99 @@
From ad319b24f3eae33c753c406611d49032333b25da Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Fri, 13 Jun 2025 16:06:37 +0200
Subject: [PATCH 02/84] net: ethernet: mtk_eth_soc: support named IRQs
Add named interrupts and keep index based fallback for existing
devicetrees.
Currently only rx and tx IRQs are defined to be used with mt7988, but
later extended with RSS/LRO support.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Simon Horman <horms@kernel.org>
---
v6:
- change irq names from tx/rx to fe1/fe2 because reserved irqs
are usable and not bound to specific function
- dropped Simons RB because of this
v5:
- fix typo in description
- add comments from previous patch #3 with changes suggested by simon
v2:
- move irqs loading part into own helper function
- reduce indentation
- place mtk_get_irqs helper before the irq_handler (note for simon)
net: mtk_eth_soc: change irq name back to fe1 + fe2
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 46 ++++++++++++++++-----
1 file changed, 35 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 880f27ca84d4..1de594a93146 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -3344,6 +3344,37 @@ static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue)
schedule_work(&eth->pending_work);
}
+static int mtk_get_irqs(struct platform_device *pdev, struct mtk_eth *eth)
+{
+ int i;
+
+ /* future SoCs beginning with MT7988 should use named IRQs in dts */
+ eth->irq[1] = platform_get_irq_byname(pdev, "fe1");
+ eth->irq[2] = platform_get_irq_byname(pdev, "fe2");
+ if (eth->irq[1] >= 0 && eth->irq[2] >= 0)
+ return 0;
+
+ /* legacy way:
+ * On MTK_SHARED_INT SoCs (MT7621 + MT7628) the first IRQ is taken
+ * from devicetree and used for both RX and TX - it is shared.
+ * On SoCs with non-shared IRQs the first entry is not used,
+ * the second is for TX, and the third is for RX.
+ */
+ for (i = 0; i < 3; i++) {
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0)
+ eth->irq[i] = eth->irq[0];
+ else
+ eth->irq[i] = platform_get_irq(pdev, i);
+
+ if (eth->irq[i] < 0) {
+ dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
+ return -ENXIO;
+ }
+ }
+
+ return 0;
+}
+
static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
{
struct mtk_eth *eth = _eth;
@@ -5113,17 +5144,10 @@ static int mtk_probe(struct platform_device *pdev)
}
}
- for (i = 0; i < 3; i++) {
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0)
- eth->irq[i] = eth->irq[0];
- else
- eth->irq[i] = platform_get_irq(pdev, i);
- if (eth->irq[i] < 0) {
- dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
- err = -ENXIO;
- goto err_wed_exit;
- }
- }
+ err = mtk_get_irqs(pdev, eth);
+ if (err)
+ goto err_wed_exit;
+
for (i = 0; i < ARRAY_SIZE(eth->clks); i++) {
eth->clks[i] = devm_clk_get(eth->dev,
mtk_clks_source_name[i]);
--
2.30.2

129
patch/kernel/archive/filogic-6.16/patches.armbian/0003-net-ethernet-mtk_eth_soc-add-consts-for-irq-index.patch Normal file
View File

@ -0,0 +1,129 @@
From d32c956e9f42925aa91839d127ee2f2c04bf6f7f Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Sun, 15 Jun 2025 12:10:44 +0200
Subject: [PATCH 03/84] net: ethernet: mtk_eth_soc: add consts for irq index
Use consts instead of fixed integers for accessing IRQ array.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Simon Horman <horms@kernel.org>
Reviewed-by: Daniel Golle <daniel@makrotopia.org>
---
v5:
- rename consts to be compatible with upcoming RSS/LRO changes
MTK_ETH_IRQ_SHARED => MTK_FE_IRQ_SHARED
MTK_ETH_IRQ_TX => MTK_FE_IRQ_TX
MTK_ETH_IRQ_RX => MTK_FE_IRQ_RX
MTK_ETH_IRQ_MAX => MTK_FE_IRQ_NUM
v4:
- calculate max from last (rx) irq index and use it for array size too
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 22 ++++++++++-----------
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 7 ++++++-
2 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 1de594a93146..2b9c24bbe7c3 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -3349,9 +3349,9 @@ static int mtk_get_irqs(struct platform_device *pdev, struct mtk_eth *eth)
int i;
/* future SoCs beginning with MT7988 should use named IRQs in dts */
- eth->irq[1] = platform_get_irq_byname(pdev, "fe1");
- eth->irq[2] = platform_get_irq_byname(pdev, "fe2");
- if (eth->irq[1] >= 0 && eth->irq[2] >= 0)
+ eth->irq[MTK_FE_IRQ_TX] = platform_get_irq_byname(pdev, "fe1");
+ eth->irq[MTK_FE_IRQ_RX] = platform_get_irq_byname(pdev, "fe2");
+ if (eth->irq[MTK_FE_IRQ_TX] >= 0 && eth->irq[MTK_FE_IRQ_RX] >= 0)
return 0;
/* legacy way:
@@ -3360,9 +3360,9 @@ static int mtk_get_irqs(struct platform_device *pdev, struct mtk_eth *eth)
* On SoCs with non-shared IRQs the first entry is not used,
* the second is for TX, and the third is for RX.
*/
- for (i = 0; i < 3; i++) {
+ for (i = 0; i < MTK_FE_IRQ_NUM; i++) {
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0)
- eth->irq[i] = eth->irq[0];
+ eth->irq[i] = eth->irq[MTK_FE_IRQ_SHARED];
else
eth->irq[i] = platform_get_irq(pdev, i);
@@ -3428,7 +3428,7 @@ static void mtk_poll_controller(struct net_device *dev)
mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
- mtk_handle_irq_rx(eth->irq[2], dev);
+ mtk_handle_irq_rx(eth->irq[MTK_FE_IRQ_RX], dev);
mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask);
}
@@ -4914,7 +4914,7 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
eth->netdev[id]->features |= eth->soc->hw_features;
eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
- eth->netdev[id]->irq = eth->irq[0];
+ eth->netdev[id]->irq = eth->irq[MTK_FE_IRQ_SHARED];
eth->netdev[id]->dev.of_node = np;
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
@@ -5191,17 +5191,17 @@ static int mtk_probe(struct platform_device *pdev)
}
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
- err = devm_request_irq(eth->dev, eth->irq[0],
+ err = devm_request_irq(eth->dev, eth->irq[MTK_FE_IRQ_SHARED],
mtk_handle_irq, 0,
dev_name(eth->dev), eth);
} else {
- err = devm_request_irq(eth->dev, eth->irq[1],
+ err = devm_request_irq(eth->dev, eth->irq[MTK_FE_IRQ_TX],
mtk_handle_irq_tx, 0,
dev_name(eth->dev), eth);
if (err)
goto err_free_dev;
- err = devm_request_irq(eth->dev, eth->irq[2],
+ err = devm_request_irq(eth->dev, eth->irq[MTK_FE_IRQ_RX],
mtk_handle_irq_rx, 0,
dev_name(eth->dev), eth);
}
@@ -5247,7 +5247,7 @@ static int mtk_probe(struct platform_device *pdev)
} else
netif_info(eth, probe, eth->netdev[i],
"mediatek frame engine at 0x%08lx, irq %d\n",
- eth->netdev[i]->base_addr, eth->irq[0]);
+ eth->netdev[i]->base_addr, eth->irq[MTK_FE_IRQ_SHARED]);
}
/* we run 2 devices on the same DMA ring so we need a dummy device
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 6f72a8c8ae1e..8cdf1317dff5 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -642,6 +642,11 @@
#define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100))
+#define MTK_FE_IRQ_SHARED 0
+#define MTK_FE_IRQ_TX 1
+#define MTK_FE_IRQ_RX 2
+#define MTK_FE_IRQ_NUM (MTK_FE_IRQ_RX + 1)
+
struct mtk_rx_dma {
unsigned int rxd1;
unsigned int rxd2;
@@ -1292,7 +1297,7 @@ struct mtk_eth {
struct net_device *dummy_dev;
struct net_device *netdev[MTK_MAX_DEVS];
struct mtk_mac *mac[MTK_MAX_DEVS];
- int irq[3];
+ int irq[MTK_FE_IRQ_NUM];
u32 msg_enable;
unsigned long sysclk;
struct regmap *ethsys;
--
2.30.2

68
patch/kernel/archive/filogic-6.16/patches.armbian/0004-net-ethernet-mtk_eth_soc-skip-first-IRQ-if-not-used.patch Normal file
View File

@ -0,0 +1,68 @@
From 6345b3efe38255c3c0b500c0fbf6b7dcf9055663 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Sun, 15 Jun 2025 12:39:14 +0200
Subject: [PATCH 04/84] net: ethernet: mtk_eth_soc: skip first IRQ if not used
On SoCs with dedicated RX and TX interrupts (all except MT7621 and
MT7628) platform_get_irq() is called for the first IRQ (eth->irq[0])
but it is never used.
Skip the first IRQ and reduce the IRQ-count to 2.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Simon Horman <horms@kernel.org>
---
v6:
- changed commit description a bit
- use MTK_FE_IRQ_SHARED instead of 0
v5:
- change commit title and description
v4:
- drop >2 condition as max is already 2 and drop the else continue
- update comment to explain which IRQs are taken in legacy way
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 12 ++++++++----
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++--
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 2b9c24bbe7c3..0068a983fcd0 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -3361,10 +3361,14 @@ static int mtk_get_irqs(struct platform_device *pdev, struct mtk_eth *eth)
* the second is for TX, and the third is for RX.
*/
for (i = 0; i < MTK_FE_IRQ_NUM; i++) {
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0)
- eth->irq[i] = eth->irq[MTK_FE_IRQ_SHARED];
- else
- eth->irq[i] = platform_get_irq(pdev, i);
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
+ if (i == MTK_FE_IRQ_SHARED)
+ eth->irq[MTK_FE_IRQ_SHARED] = platform_get_irq(pdev, i);
+ else
+ eth->irq[i] = eth->irq[MTK_FE_IRQ_SHARED];
+ } else {
+ eth->irq[i] = platform_get_irq(pdev, i + 1);
+ }
if (eth->irq[i] < 0) {
dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 8cdf1317dff5..9261c0e13b59 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -643,8 +643,8 @@
#define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100))
#define MTK_FE_IRQ_SHARED 0
-#define MTK_FE_IRQ_TX 1
-#define MTK_FE_IRQ_RX 2
+#define MTK_FE_IRQ_TX 0
+#define MTK_FE_IRQ_RX 1
#define MTK_FE_IRQ_NUM (MTK_FE_IRQ_RX + 1)
struct mtk_rx_dma {
--
2.30.2

37
patch/kernel/archive/filogic-6.16/patches.armbian/0005-net-ethernet-mtk_eth_soc-only-use-legacy-mode-on-mis.patch Normal file
View File

@ -0,0 +1,37 @@
From d9c6fd5ac513e0268cffd88d651d14181724c367 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Wed, 18 Jun 2025 19:03:10 +0200
Subject: [PATCH 05/84] net: ethernet: mtk_eth_soc: only use legacy mode on
missing IRQ name
If platform_get_irq_byname returns -ENXIO fall back to legacy (index
based) mode, but on other errors function should return this error.
Suggested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Simon Horman <horms@kernel.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 0068a983fcd0..9333f2b8e1d6 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -3354,6 +3354,13 @@ static int mtk_get_irqs(struct platform_device *pdev, struct mtk_eth *eth)
if (eth->irq[MTK_FE_IRQ_TX] >= 0 && eth->irq[MTK_FE_IRQ_RX] >= 0)
return 0;
+ /* only use legacy mode if platform_get_irq_byname returned -ENXIO */
+ if (eth->irq[MTK_FE_IRQ_TX] != -ENXIO)
+ return eth->irq[MTK_FE_IRQ_TX];
+
+ if (eth->irq[MTK_FE_IRQ_RX] != -ENXIO)
+ return eth->irq[MTK_FE_IRQ_RX];
+
/* legacy way:
* On MTK_SHARED_INT SoCs (MT7621 + MT7628) the first IRQ is taken
* from devicetree and used for both RX and TX - it is shared.
--
2.30.2

2766
patch/kernel/archive/filogic-6.16/patches.armbian/0006-build.sh-add-build-script-config-defconfig-and-fit-s.patch Normal file
View File

File diff suppressed because it is too large Load Diff

3796
patch/kernel/archive/filogic-6.16/patches.armbian/0007-build.sh-add-additional-build-script-config-defconfi.patch Normal file
View File

File diff suppressed because it is too large Load Diff

25
patch/kernel/archive/filogic-6.16/patches.armbian/0008-defconfig-r3-fix-warning-about-BASE_SMALL.patch Normal file
View File

@ -0,0 +1,25 @@
From 4b3f2fdb02d16d5346b4b6c14f51a7000a3c5325 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Mon, 16 Jun 2025 09:03:11 +0200
Subject: [PATCH 08/84] defconfig: r3: fix warning about BASE_SMALL
---
arch/arm64/configs/mt7986a_bpi-r3_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/configs/mt7986a_bpi-r3_defconfig b/arch/arm64/configs/mt7986a_bpi-r3_defconfig
index fccecc3b2375..32710280133d 100644
--- a/arch/arm64/configs/mt7986a_bpi-r3_defconfig
+++ b/arch/arm64/configs/mt7986a_bpi-r3_defconfig
@@ -21,7 +21,7 @@ CONFIG_ATA_SFF=y
CONFIG_ATM_BR2684_IPFILTER=y
CONFIG_ATM_CLIP_NO_ICMP=y
CONFIG_BASE_FULL=y
-CONFIG_BASE_SMALL=0
+CONFIG_BASE_SMALL=n
CONFIG_BCMA_POSSIBLE=y
CONFIG_BINARY_PRINTF=y
CONFIG_BINFMT_ELF=y
--
2.30.2

23
patch/kernel/archive/filogic-6.16/patches.armbian/0009-build.conf-change-upload-target.patch Normal file
View File

@ -0,0 +1,23 @@
From b72f0fe031ab48a161637592b03012372dc6bcc7 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Mon, 16 Jun 2025 09:03:51 +0200
Subject: [PATCH 09/84] build.conf: change upload target
---
build.conf | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/build.conf b/build.conf
index 7681a4e75ce5..c6521172e2da 100644
--- a/build.conf
+++ b/build.conf
@@ -1,5 +1,5 @@
uploaduser=$USER
-uploadserver=r2
+uploadserver=r3
uploaddir=/var/lib/tftp
#uploaduser=root
#uploadserver=192.168.0.11
--
2.30.2

87
patch/kernel/archive/filogic-6.16/patches.armbian/0010-arm-dts-mt7623-swap-mmc-and-put-uart2-first.patch Normal file
View File

@ -0,0 +1,87 @@
From 1d780489e2f3b5de6d922d30a1a258113a031cef Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Mon, 12 Jul 2021 09:00:02 +0200
Subject: [PATCH 10/84] arm: dts: mt7623: swap mmc and put uart2 first
---
arch/arm/boot/dts/mediatek/mt7623.dtsi | 42 +++++++++++++-------------
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/arch/arm/boot/dts/mediatek/mt7623.dtsi b/arch/arm/boot/dts/mediatek/mt7623.dtsi
index fd7a89cc337d..0ad545ec0734 100644
--- a/arch/arm/boot/dts/mediatek/mt7623.dtsi
+++ b/arch/arm/boot/dts/mediatek/mt7623.dtsi
@@ -372,6 +372,17 @@ auxadc: adc@11001000 {
#io-channel-cells = <1>;
};
+ uart2: serial@11004000 {
+ compatible = "mediatek,mt7623-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11004000 0 0x400>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_UART2_SEL>,
+ <&pericfg CLK_PERI_UART2>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt7623-uart",
"mediatek,mt6577-uart";
@@ -394,17 +405,6 @@ uart1: serial@11003000 {
status = "disabled";
};
- uart2: serial@11004000 {
- compatible = "mediatek,mt7623-uart",
- "mediatek,mt6577-uart";
- reg = <0 0x11004000 0 0x400>;
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_UART2_SEL>,
- <&pericfg CLK_PERI_UART2>;
- clock-names = "baud", "bus";
- status = "disabled";
- };
-
uart3: serial@11005000 {
compatible = "mediatek,mt7623-uart",
"mediatek,mt6577-uart";
@@ -712,24 +712,24 @@ afe: audio-controller {
};
};
- mmc0: mmc@11230000 {
+ mmc1: mmc@11240000 {
compatible = "mediatek,mt7623-mmc",
"mediatek,mt2701-mmc";
- reg = <0 0x11230000 0 0x1000>;
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_MSDC30_0>,
- <&topckgen CLK_TOP_MSDC30_0_SEL>;
+ reg = <0 0x11240000 0 0x1000>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_MSDC30_1>,
+ <&topckgen CLK_TOP_MSDC30_1_SEL>;
clock-names = "source", "hclk";
status = "disabled";
};
- mmc1: mmc@11240000 {
+ mmc0: mmc@11230000 {
compatible = "mediatek,mt7623-mmc",
"mediatek,mt2701-mmc";
- reg = <0 0x11240000 0 0x1000>;
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_MSDC30_1>,
- <&topckgen CLK_TOP_MSDC30_1_SEL>;
+ reg = <0 0x11230000 0 0x1000>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_MSDC30_0>,
+ <&topckgen CLK_TOP_MSDC30_0_SEL>;
clock-names = "source", "hclk";
status = "disabled";
};
--
2.30.2

307
patch/kernel/archive/filogic-6.16/patches.armbian/0011-arm64-dts-disable-dtbs-for-dtbs_check.patch Normal file
View File

@ -0,0 +1,307 @@
From 475a62480df18eb13c58fcfd75f0337cb2749104 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Fri, 11 Apr 2025 08:45:54 +0200
Subject: [PATCH 11/84] arm64: dts: disable dtbs for dtbs_check
---
arch/arm64/boot/dts/Makefile | 70 ++++-----
arch/arm64/boot/dts/mediatek/Makefile | 204 +++++++++++++-------------
2 files changed, 137 insertions(+), 137 deletions(-)
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 79b73a21ddc2..42ebeaeedf3b 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,37 +1,37 @@
# SPDX-License-Identifier: GPL-2.0
-subdir-y += actions
-subdir-y += airoha
-subdir-y += allwinner
-subdir-y += altera
-subdir-y += amazon
-subdir-y += amd
-subdir-y += amlogic
-subdir-y += apm
-subdir-y += apple
-subdir-y += arm
-subdir-y += bitmain
-subdir-y += blaize
-subdir-y += broadcom
-subdir-y += cavium
-subdir-y += exynos
-subdir-y += freescale
-subdir-y += hisilicon
-subdir-y += intel
-subdir-y += lg
-subdir-y += marvell
+#subdir-y += actions
+#subdir-y += airoha
+#subdir-y += allwinner
+#subdir-y += altera
+#subdir-y += amazon
+#subdir-y += amd
+#subdir-y += amlogic
+#subdir-y += apm
+#subdir-y += apple
+#subdir-y += arm
+#subdir-y += bitmain
+#subdir-y += blaize
+#subdir-y += broadcom
+#subdir-y += cavium
+#subdir-y += exynos
+#subdir-y += freescale
+#subdir-y += hisilicon
+#subdir-y += intel
+#subdir-y += lg
+#subdir-y += marvell
subdir-y += mediatek
-subdir-y += microchip
-subdir-y += nuvoton
-subdir-y += nvidia
-subdir-y += qcom
-subdir-y += realtek
-subdir-y += renesas
-subdir-y += rockchip
-subdir-y += socionext
-subdir-y += sprd
-subdir-y += st
-subdir-y += synaptics
-subdir-y += tesla
-subdir-y += ti
-subdir-y += toshiba
-subdir-y += xilinx
+#subdir-y += microchip
+#subdir-y += nuvoton
+#subdir-y += nvidia
+#subdir-y += qcom
+#subdir-y += realtek
+#subdir-y += renesas
+#subdir-y += rockchip
+#subdir-y += socionext
+#subdir-y += sprd
+#subdir-y += st
+#subdir-y += synaptics
+#subdir-y += tesla
+#subdir-y += ti
+#subdir-y += toshiba
+#subdir-y += xilinx
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index f68865d06edd..e60462fa2b6f 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,110 +1,110 @@
# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-sony-xperia-m5.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-cudy-wr3000-v1.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-openwrt-one.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-xiaomi-ax3000t.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-acelink-ew-7886cax.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-mini.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sata.dtbo
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-sony-xperia-m5.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-cudy-wr3000-v1.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-openwrt-one.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-xiaomi-ax3000t.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-acelink-ew-7886cax.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-mini.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sata.dtbo
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-2g5.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-emmc.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-sd.dtbo
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-burnet.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-cozmo.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku1.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku6.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku7.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14-sku2.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-juniper-sku16.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kappa.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kenzo.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-makomo-sku0.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-makomo-sku1.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-pico.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-pico6.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku0.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku1.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu-sku22.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-katsu-sku32.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-katsu-sku38.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku16.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku272.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku288.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku0.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku1.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku16.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393216.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393217.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393218.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-ponyta-sku0.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-ponyta-sku1.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-rusty-sku196608.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-starmie-sku0.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-starmie-sku1.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-steelix-sku131072.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-steelix-sku131073.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacool-sku327681.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacool-sku327683.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacruel-sku262144.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacruel-sku262148.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-voltorb-sku589824.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-voltorb-sku589825.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-evb.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku0.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku1.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku2.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku3.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku4.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku5.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku6.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku7.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-dojo-r1.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r1.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-genio-510-evk.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-kontron-3-5-sbc-i1200.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l-8-hd-panel.dtbo
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-burnet.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-cozmo.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku1.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku6.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku7.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14-sku2.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-juniper-sku16.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kappa.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kenzo.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-makomo-sku0.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-makomo-sku1.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-pico.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-pico6.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku0.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku1.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu-sku22.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-katsu-sku32.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-katsu-sku38.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku16.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku272.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku288.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku0.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku1.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku16.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393216.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393217.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393218.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-ponyta-sku0.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-ponyta-sku1.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-rusty-sku196608.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-starmie-sku0.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-starmie-sku1.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-steelix-sku131072.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-steelix-sku131073.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacool-sku327681.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacool-sku327683.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacruel-sku262144.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacruel-sku262148.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-voltorb-sku589824.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-voltorb-sku589825.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-evb.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku0.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku1.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku2.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku3.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku4.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku5.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku6.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku7.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-dojo-r1.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r1.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-genio-510-evk.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-kontron-3-5-sbc-i1200.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l-8-hd-panel.dtbo
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
# Device tree overlays support
DTC_FLAGS_mt7986a-bananapi-bpi-r3 := -@
--
2.30.2

45
patch/kernel/archive/filogic-6.16/patches.armbian/0012-dt-bindings-interconnect-add-mt7988-cci-compatible.patch Normal file
View File

@ -0,0 +1,45 @@
From 8aa7779a777a3b78193affeca2676039052f7a08 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 20 May 2025 19:04:22 +0200
Subject: [PATCH 12/84] dt-bindings: interconnect: add mt7988-cci compatible
Add compatible for Mediatek MT7988 SoC with mediatek,mt8183-cci fallback
which is taken by driver.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Georgi Djakov <djakov@kernel.org>
---
v2:
- no RFC
- drop "items" as sugested by conor
---
.../bindings/interconnect/mediatek,cci.yaml | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
index 58611ba2a0f4..4d72525f407e 100644
--- a/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
+++ b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
@@ -17,9 +17,14 @@ description: |
properties:
compatible:
- enum:
- - mediatek,mt8183-cci
- - mediatek,mt8186-cci
+ oneOf:
+ - enum:
+ - mediatek,mt8183-cci
+ - mediatek,mt8186-cci
+ - items:
+ - enum:
+ - mediatek,mt7988-cci
+ - const: mediatek,mt8183-cci
clocks:
items:
--
2.30.2

92
patch/kernel/archive/filogic-6.16/patches.armbian/0013-arm64-dts-mediatek-mt7988-add-cci-node.patch Normal file
View File

@ -0,0 +1,92 @@
From a6bb99087048bd61a6f71a76f6d5bda171da5fd7 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Sat, 1 Feb 2025 15:22:59 +0100
Subject: [PATCH 13/84] arm64: dts: mediatek: mt7988: add cci node
Add cci devicetree node for cpu frequency scaling.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
v3:
- add mt7988-cci compatible as suggested by angelo
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 33 +++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index c46b31f8d653..560ec86dbec0 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -12,6 +12,35 @@ / {
#address-cells = <2>;
#size-cells = <2>;
+ cci: cci {
+ compatible = "mediatek,mt7988-cci", "mediatek,mt8183-cci";
+ clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
+ <&topckgen CLK_TOP_XTAL>;
+ clock-names = "cci", "intermediate";
+ operating-points-v2 = <&cci_opp>;
+ };
+
+ cci_opp: opp-table-cci {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <850000>;
+ };
+ opp-660000000 {
+ opp-hz = /bits/ 64 <660000000>;
+ opp-microvolt = <850000>;
+ };
+ opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <850000>;
+ };
+ opp-1080000000 {
+ opp-hz = /bits/ 64 <1080000000>;
+ opp-microvolt = <900000>;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -25,6 +54,7 @@ cpu0: cpu@0 {
<&topckgen CLK_TOP_XTAL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
+ mediatek,cci = <&cci>;
};
cpu1: cpu@1 {
@@ -36,6 +66,7 @@ cpu1: cpu@1 {
<&topckgen CLK_TOP_XTAL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
+ mediatek,cci = <&cci>;
};
cpu2: cpu@2 {
@@ -47,6 +78,7 @@ cpu2: cpu@2 {
<&topckgen CLK_TOP_XTAL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
+ mediatek,cci = <&cci>;
};
cpu3: cpu@3 {
@@ -58,6 +90,7 @@ cpu3: cpu@3 {
<&topckgen CLK_TOP_XTAL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
+ mediatek,cci = <&cci>;
};
cluster0_opp: opp-table-0 {
--
2.30.2

32
patch/kernel/archive/filogic-6.16/patches.armbian/0014-arm64-dts-mediatek-mt7988a-bpi-r4-add-proc-supply-fo.patch Normal file
View File

@ -0,0 +1,32 @@
From 6d1ea6d069461b0a97af8295fc5c46542b5b1cb4 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Sun, 4 May 2025 15:17:13 +0200
Subject: [PATCH 14/84] arm64: dts: mediatek: mt7988a-bpi-r4: add proc-supply
for cci
CCI requires proc-supply. Add it on board level.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
index 81ba045e0e0e..afa9e3b2b16a 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -40,6 +40,10 @@ reg_3p3v: regulator-3p3v {
};
};
+&cci {
+ proc-supply = <&rt5190_buck3>;
+};
+
&cpu0 {
proc-supply = <&rt5190_buck3>;
};
--
2.30.2

151
patch/kernel/archive/filogic-6.16/patches.armbian/0015-arm64-dts-mediatek-mt7988a-bpi-r4-drop-unused-pins.patch Normal file
View File

@ -0,0 +1,151 @@
From 84dc2ca96d2acd136085ab98fcc92176c1be1aa9 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Sat, 17 May 2025 09:04:19 +0200
Subject: [PATCH 15/84] arm64: dts: mediatek: mt7988a-bpi-r4: drop unused pins
Pins were moved from SoC dtsi to Board level dtsi without cleaning up
to needed ones. Drop the unused pins now.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 89 -------------------
1 file changed, 89 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
index afa9e3b2b16a..30affedf84d4 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -223,18 +223,6 @@ &pcie3 {
};
&pio {
- mdio0_pins: mdio0-pins {
- mux {
- function = "eth";
- groups = "mdc_mdio0";
- };
-
- conf {
- pins = "SMI_0_MDC", "SMI_0_MDIO";
- drive-strength = <8>;
- };
- };
-
i2c0_pins: i2c0-g0-pins {
mux {
function = "i2c";
@@ -249,20 +237,6 @@ mux {
};
};
- i2c1_sfp_pins: i2c1-sfp-g0-pins {
- mux {
- function = "i2c";
- groups = "i2c1_sfp";
- };
- };
-
- i2c2_0_pins: i2c2-g0-pins {
- mux {
- function = "i2c";
- groups = "i2c2_0";
- };
- };
-
i2c2_1_pins: i2c2-g1-pins {
mux {
function = "i2c";
@@ -298,34 +272,6 @@ mux {
};
};
- gbe0_led1_pins: gbe0-led1-pins {
- mux {
- function = "led";
- groups = "gbe0_led1";
- };
- };
-
- gbe1_led1_pins: gbe1-led1-pins {
- mux {
- function = "led";
- groups = "gbe1_led1";
- };
- };
-
- gbe2_led1_pins: gbe2-led1-pins {
- mux {
- function = "led";
- groups = "gbe2_led1";
- };
- };
-
- gbe3_led1_pins: gbe3-led1-pins {
- mux {
- function = "led";
- groups = "gbe3_led1";
- };
- };
-
i2p5gbe_led0_pins: 2p5gbe-led0-pins {
mux {
function = "led";
@@ -333,13 +279,6 @@ mux {
};
};
- i2p5gbe_led1_pins: 2p5gbe-led1-pins {
- mux {
- function = "led";
- groups = "2p5gbe_led1";
- };
- };
-
mmc0_pins_emmc_45: mmc0-emmc-45-pins {
mux {
function = "flash";
@@ -361,40 +300,12 @@ mux {
};
};
- snfi_pins: snfi-pins {
- mux {
- function = "flash";
- groups = "snfi";
- };
- };
-
- spi0_pins: spi0-pins {
- mux {
- function = "spi";
- groups = "spi0";
- };
- };
-
spi0_flash_pins: spi0-flash-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
};
-
- spi2_pins: spi2-pins {
- mux {
- function = "spi";
- groups = "spi2";
- };
- };
-
- spi2_flash_pins: spi2-flash-pins {
- mux {
- function = "spi";
- groups = "spi2", "spi2_wp_hold";
- };
- };
};
&pwm {
--
2.30.2

50
patch/kernel/archive/filogic-6.16/patches.armbian/0016-arm64-dts-mediatek-mt7988a-bpi-r4-add-gpio-leds.patch Normal file
View File

@ -0,0 +1,50 @@
From c5a6b9feed48fc85b9dcae3b0a171df317e159f7 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Wed, 4 Jun 2025 17:50:22 +0200
Subject: [PATCH 16/84] arm64: dts: mediatek: mt7988a-bpi-r4: add gpio leds
Bananapi R4 has a green and a blue led which can be switched by gpio.
Green led is for running state so default on.
Green led also shares pin with eeprom writeprotect where led off allows
writing to eeprom.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
index 30affedf84d4..21eb91c8609f 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -21,6 +21,25 @@ fan: pwm-fan {
status = "okay";
};
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ led_green: led-green {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 79 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ led_blue: led-blue {
+ function = LED_FUNCTION_WPS;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&pio 63 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
--
2.30.2

0
patch/kernel/archive/filogic-6.16/patches.armbian/0017-v9-coverletter-further-mt7988-devicetree-work.patch Normal file
View File

32
patch/kernel/archive/filogic-6.16/patches.armbian/0018-dt-bindings-net-mediatek-net-update-mac-subnode-patt.patch Normal file
View File

@ -0,0 +1,32 @@
From a156ad0546aec9ecca31c219f9658be8475d752b Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Thu, 3 Jul 2025 20:19:35 +0200
Subject: [PATCH 18/84] dt-bindings: net: mediatek,net: update mac subnode
pattern for mt7988
MT7888 have 3 Macs and so its nodes have names from mac0 - mac2. Update
pattern to fix this.
Fixes: c94a9aabec36 ("dt-bindings: net: mediatek,net: add mt7988-eth binding")
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Documentation/devicetree/bindings/net/mediatek,net.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml
index 9e02fd80af83..175d1d011dc6 100644
--- a/Documentation/devicetree/bindings/net/mediatek,net.yaml
+++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml
@@ -382,7 +382,7 @@ allOf:
- const: xgp3
patternProperties:
- "^mac@[0-1]$":
+ "^mac@[0-2]$":
type: object
unevaluatedProperties: false
allOf:
--
2.30.2

90
patch/kernel/archive/filogic-6.16/patches.armbian/0019-dt-bindings-net-mediatek-net-allow-up-to-8-IRQs.patch Normal file
View File

@ -0,0 +1,90 @@
From 35f241527f0146b5608a2239684005469bca4d4d Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Thu, 3 Jul 2025 20:22:18 +0200
Subject: [PATCH 19/84] dt-bindings: net: mediatek,net: allow up to 8 IRQs
Increase the maximum IRQ count to 8 (4 FE + 4 RSS/LRO).
Frame-engine-IRQs (max 4):
MT7621, MT7628: 1 FE-IRQ
MT7622, MT7623: 3 FE-IRQs (only two used by the driver for now)
MT7981, MT7986, MT7988: 4 FE-IRQs (only two used by the driver for now)
Mediatek Filogic SoCs (mt798x) have 4 additional IRQs for RSS and/or
LRO. So MT798x have 8 IRQs in total.
MT7981 does not have a ethernet-node yet.
MT7986 Ethernet node is updated with RSS/LRO IRQs in this series.
MT7988 Ethernet node is added in this series.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
v9:
- set interrupt minitems to 8 for filogic
- mt7981 does not have a ethernet node yet, so no ABI break
- devicetree for mt7986 is updated later in this series, ABI-Break,
but RSS/LRO should use interrupt names and is simply disabled when
using older DT
- extend mt7986 example with PDMA-IRQs because minItems now 8
v8: separate irq-count change from interrupt-names patch
---
.../devicetree/bindings/net/mediatek,net.yaml | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml
index 175d1d011dc6..99dc0401eb9a 100644
--- a/Documentation/devicetree/bindings/net/mediatek,net.yaml
+++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml
@@ -40,7 +40,7 @@ properties:
interrupts:
minItems: 1
- maxItems: 4
+ maxItems: 8
power-domains:
maxItems: 1
@@ -272,7 +272,7 @@ allOf:
then:
properties:
interrupts:
- minItems: 4
+ minItems: 8
clocks:
minItems: 15
@@ -310,7 +310,7 @@ allOf:
then:
properties:
interrupts:
- minItems: 4
+ minItems: 8
clocks:
minItems: 15
@@ -348,7 +348,7 @@ allOf:
then:
properties:
interrupts:
- minItems: 4
+ minItems: 8
clocks:
minItems: 24
@@ -507,7 +507,11 @@ examples:
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ethsys CLK_ETH_FE_EN>,
<&ethsys CLK_ETH_GP2_EN>,
<&ethsys CLK_ETH_GP1_EN>,
--
2.30.2

141
patch/kernel/archive/filogic-6.16/patches.armbian/0020-dt-bindings-net-mediatek-net-allow-irq-names.patch Normal file
View File

@ -0,0 +1,141 @@
From 2c7be45741bd444a44e0bf18a010ce378396d8ac Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Thu, 3 Jul 2025 20:31:42 +0200
Subject: [PATCH 20/84] dt-bindings: net: mediatek,net: allow irq names
In preparation for MT7988 and RSS/LRO allow the interrupt-names
property.
In this way driver can request the interrupts by name which is much
more readable in the driver code and SoC's dtsi than relying on a
specific order.
Frame-engine-IRQs (fe0..3):
MT7621, MT7628: 1 FE-IRQ
MT7622, MT7623: 3 FE-IRQs (only two used by the driver for now)
MT7981, MT7986: 4 FE-IRQs (only two used by the driver for now)
RSS/LRO IRQs (pdma0..3) additional only on Filogic (MT798x) with
count of 4. So all IRQ-names (8) for Filogic.
Set boundaries for all compatibles same as irq count.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
v9:
- add interrupt-names minitems to 8 for filogic
- mt7981 does not have a ethernet node yet
- devicetree for mt7986 is updated later in this series
- small rephrase IRQ => FE-IRQ and mention total count of IRQs on Filogic.
- kept angelos RB because of small change, i hope it is ok :)
v8:
- fixed typo in mt7621 section "interrupt-namess"
- separated interrupt count from interrupt-names
- rephrased description a bit to explain the "why"
v7: fixed wrong rebase
v6: new patch splitted from the mt7988 changes
---
.../devicetree/bindings/net/mediatek,net.yaml | 36 +++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml
index 99dc0401eb9a..d2b5461e73bc 100644
--- a/Documentation/devicetree/bindings/net/mediatek,net.yaml
+++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml
@@ -42,6 +42,18 @@ properties:
minItems: 1
maxItems: 8
+ interrupt-names:
+ minItems: 1
+ items:
+ - const: fe0
+ - const: fe1
+ - const: fe2
+ - const: fe3
+ - const: pdma0
+ - const: pdma1
+ - const: pdma2
+ - const: pdma3
+
power-domains:
maxItems: 1
@@ -135,6 +147,10 @@ allOf:
minItems: 3
maxItems: 3
+ interrupt-names:
+ minItems: 3
+ maxItems: 3
+
clocks:
minItems: 4
maxItems: 4
@@ -166,6 +182,9 @@ allOf:
interrupts:
maxItems: 1
+ interrupt-names:
+ maxItems: 1
+
clocks:
minItems: 2
maxItems: 2
@@ -192,6 +211,10 @@ allOf:
minItems: 3
maxItems: 3
+ interrupt-names:
+ minItems: 3
+ maxItems: 3
+
clocks:
minItems: 11
maxItems: 11
@@ -232,6 +255,10 @@ allOf:
minItems: 3
maxItems: 3
+ interrupt-names:
+ minItems: 3
+ maxItems: 3
+
clocks:
minItems: 17
maxItems: 17
@@ -274,6 +301,9 @@ allOf:
interrupts:
minItems: 8
+ interrupt-names:
+ minItems: 8
+
clocks:
minItems: 15
maxItems: 15
@@ -312,6 +342,9 @@ allOf:
interrupts:
minItems: 8
+ interrupt-names:
+ minItems: 8
+
clocks:
minItems: 15
maxItems: 15
@@ -350,6 +383,9 @@ allOf:
interrupts:
minItems: 8
+ interrupt-names:
+ minItems: 8
+
clocks:
minItems: 24
maxItems: 24
--
2.30.2

107
patch/kernel/archive/filogic-6.16/patches.armbian/0021-dt-bindings-net-mediatek-net-add-sram-property.patch Normal file
View File

@ -0,0 +1,107 @@
From ceafe6027cde06a1216ceb52a1f2da05d4c564fd Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Sat, 28 Jun 2025 10:42:49 +0200
Subject: [PATCH 21/84] dt-bindings: net: mediatek,net: add sram property
Meditak Filogic SoCs (MT798x) have dedicated MMIO-SRAM for dma operations.
MT7981 and MT7986 currently use static offset to ethernet MAC register
which will be changed in separate patch once this way is accepted.
Add "sram" property to map ethernet controller to dedicated mmio-sram node.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
v9:
- add "sram: false" for non-filogic
v8:
- splitted out mac subnode pattern
- dropped reg naming change
- rephrased description
- drop change of reg-name
v6:
- split out the interrupt-names into separate patch
- update irq(name) min count to 4
- add sram-property
- drop second reg entry and minitems as there is only 1 item left again
v5:
- fix v4 logmessage and change description a bit describing how i get
the irq count.
- update binding for 8 irqs with different names (rx,tx => fe0..fe3)
including the 2 reserved irqs which can be used later
- change rx-ringX to pdmaX to be closer to hardware documentation
v4:
- increase max interrupts to 6 because of adding RSS/LRO interrupts (4)
and dropping 2 reserved irqs (0+3) around rx+tx
- dropped Robs RB due to this change
- allow interrupt names
- add interrupt-names without reserved IRQs on mt7988
this requires mtk driver patch:
https://patchwork.kernel.org/project/netdevbpf/patch/20250616080738.117993-2-linux@fw-web.de/
v2:
- change reg to list of items
---
.../devicetree/bindings/net/mediatek,net.yaml | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml
index d2b5461e73bc..b45f67f92e80 100644
--- a/Documentation/devicetree/bindings/net/mediatek,net.yaml
+++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml
@@ -66,6 +66,10 @@ properties:
- const: gmac
- const: ppe
+ sram:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to mmio SRAM
+
mediatek,ethsys:
$ref: /schemas/types.yaml#/definitions/phandle
description:
@@ -162,6 +166,8 @@ allOf:
- const: gp1
- const: gp2
+ sram: false
+
mediatek,infracfg: false
mediatek,wed: false
@@ -194,6 +200,8 @@ allOf:
- const: ethif
- const: fe
+ sram: false
+
mediatek,infracfg: false
mediatek,wed: false
@@ -233,6 +241,8 @@ allOf:
- const: sgmii_ck
- const: eth2pll
+ sram: false
+
mediatek,infracfg: false
mediatek,sgmiisys:
@@ -283,6 +293,8 @@ allOf:
- const: sgmii_ck
- const: eth2pll
+ sram: false
+
mediatek,sgmiisys:
minItems: 2
maxItems: 2
--
2.30.2

51
patch/kernel/archive/filogic-6.16/patches.armbian/0022-dt-bindings-net-dsa-mediatek-mt7530-add-dsa-port-def.patch Normal file
View File

@ -0,0 +1,51 @@
From 7334c38f35771ab025253b803990d07864ca1ffb Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 6 May 2025 17:29:16 +0200
Subject: [PATCH 22/84] dt-bindings: net: dsa: mediatek,mt7530: add dsa-port
definition for mt7988
Add own dsa-port binding for SoC with internal switch where only phy-mode
'internal' is valid.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../bindings/net/dsa/mediatek,mt7530.yaml | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
index 51205f9f2985..9b983fdbf3c7 100644
--- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
+++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
@@ -190,6 +190,18 @@ required:
- reg
$defs:
+ builtin-dsa-port:
+ patternProperties:
+ "^(ethernet-)?ports$":
+ patternProperties:
+ "^(ethernet-)?port@[0-6]$":
+ if:
+ required: [ ethernet ]
+ then:
+ properties:
+ phy-mode:
+ const: internal
+
mt7530-dsa-port:
patternProperties:
"^(ethernet-)?ports$":
@@ -297,7 +309,7 @@ allOf:
- airoha,en7581-switch
- airoha,an7583-switch
then:
- $ref: "#/$defs/mt7530-dsa-port"
+ $ref: "#/$defs/builtin-dsa-port"
properties:
gpio-controller: false
mediatek,mcm: false
--
2.30.2

44
patch/kernel/archive/filogic-6.16/patches.armbian/0023-dt-bindings-net-dsa-mediatek-mt7530-add-internal-mdi.patch Normal file
View File

@ -0,0 +1,44 @@
From 71bb13e3a85a6efd666cb698acb3f8227a7f2fa5 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 6 May 2025 18:56:25 +0200
Subject: [PATCH 23/84] dt-bindings: net: dsa: mediatek,mt7530: add internal
mdio bus
Mt7988 buildin switch has own mdio bus where ge-phys are connected.
Add related property for this.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
v2:
- change from patternproperty to property
- add unevaluatedProperties and mediatek,pio subproperty
---
.../devicetree/bindings/net/dsa/mediatek,mt7530.yaml | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
index 9b983fdbf3c7..815a90808901 100644
--- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
+++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
@@ -136,6 +136,16 @@ properties:
See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt for
details for the regulator setup on these boards.
+ mdio:
+ $ref: /schemas/net/mdio.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ mediatek,pio:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle pointing to the mediatek pinctrl node.
+
mediatek,mcm:
type: boolean
description:
--
2.30.2

53
patch/kernel/archive/filogic-6.16/patches.armbian/0024-arm64-dts-mediatek-mt7986-add-sram-node.patch Normal file
View File

@ -0,0 +1,53 @@
From 088c4b18aeb6c7be84f381549a331a26735db576 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Fri, 27 Jun 2025 22:58:16 +0200
Subject: [PATCH 24/84] arm64: dts: mediatek: mt7986: add sram node
Currently sram is allocated in driver via offset from reg of ethernet
node. Change it to use a dedicated sram node like mt7988.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
index 559990dcd1d1..550f569451fb 100644
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -523,7 +523,7 @@ wed1: wed@15011000 {
eth: ethernet@15100000 {
compatible = "mediatek,mt7986-eth";
- reg = <0 0x15100000 0 0x80000>;
+ reg = <0 0x15100000 0 0x40000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
@@ -553,6 +553,7 @@ eth: ethernet@15100000 {
<&topckgen CLK_TOP_SGM_325M_SEL>;
assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
<&apmixedsys CLK_APMIXED_SGMPLL>;
+ sram = <&eth_sram>;
#address-cells = <1>;
#size-cells = <0>;
mediatek,ethsys = <&ethsys>;
@@ -562,6 +563,15 @@ eth: ethernet@15100000 {
status = "disabled";
};
+ /*15100000+0x40000*/
+ eth_sram: sram@15140000 {
+ compatible = "mmio-sram";
+ reg = <0 0x15140000 0 0x40000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x15140000 0 0x40000>;
+ };
+
wo_ccif0: syscon@151a5000 {
compatible = "mediatek,mt7986-wo-ccif", "syscon";
reg = <0 0x151a5000 0 0x1000>;
--
2.30.2

36
patch/kernel/archive/filogic-6.16/patches.armbian/0025-arm64-dts-mediatek-mt7986-add-interrupts-for-RSS-and.patch Normal file
View File

@ -0,0 +1,36 @@
From 676b92ba3ccac93969807ec86cfde2acbe80f99a Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Wed, 12 Mar 2025 18:11:21 +0100
Subject: [PATCH 25/84] arm64: dts: mediatek: mt7986: add interrupts for RSS
and interrupt names
Add interrupts for RSS/LRO and names to access them via name instead of
index.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
index 550f569451fb..a9e079fd42c6 100644
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -527,7 +527,13 @@ eth: ethernet@15100000 {
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "fe0", "fe1", "fe2", "fe3", "pdma0",
+ "pdma1", "pdma2", "pdma3";
clocks = <&ethsys CLK_ETH_FE_EN>,
<&ethsys CLK_ETH_GP2_EN>,
<&ethsys CLK_ETH_GP1_EN>,
--
2.30.2

208
patch/kernel/archive/filogic-6.16/patches.armbian/0026-arm64-dts-mediatek-mt7988-add-basic-ethernet-nodes.patch Normal file
View File

@ -0,0 +1,208 @@
From db0b8ad2dbed7ab767af5684c83aea353d11e327 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Thu, 28 Nov 2024 18:48:07 +0100
Subject: [PATCH 26/84] arm64: dts: mediatek: mt7988: add basic ethernet-nodes
Add basic ethernet related nodes.
Mac1+2 needs pcs (sgmii+usxgmii) to work correctly which will be linked
later when driver is merged.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
v8:
- change ethernet register size to 0x40000
range from 0x15140000 ~ 0x1517ffff is not usable on mt7988 => 0xDEADBEEF
v6:
- fix whitespace-errors for pdma irqs (spaces vs. tabs)
- move sram from eth reg to own sram node (needs CONFIG_SRAM)
v5:
- add reserved irqs and change names to fe0..fe3
- change rx-ringX to pdmaX to be closer to documentation
v4:
- comment for fixed-link on gmac0
- update 2g5 phy node
- unit-name dec instead of hex to match reg property
- move compatible before reg
- drop phy-mode
- add interrupts for RSS
- add interrupt-names and drop reserved irqs for ethernet
- some reordering
- eth-reg and clock whitespace-fix based on angelos review
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 137 +++++++++++++++++++++-
1 file changed, 134 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index 560ec86dbec0..897b5a82b53e 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -680,7 +680,28 @@ xphyu3port0: usb-phy@11e13000 {
};
};
- clock-controller@11f40000 {
+ xfi_tphy0: phy@11f20000 {
+ compatible = "mediatek,mt7988-xfi-tphy";
+ reg = <0 0x11f20000 0 0x10000>;
+ clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>,
+ <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
+ clock-names = "xfipll", "topxtal";
+ resets = <&watchdog 14>;
+ mediatek,usxgmii-performance-errata;
+ #phy-cells = <0>;
+ };
+
+ xfi_tphy1: phy@11f30000 {
+ compatible = "mediatek,mt7988-xfi-tphy";
+ reg = <0 0x11f30000 0 0x10000>;
+ clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>,
+ <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>;
+ clock-names = "xfipll", "topxtal";
+ resets = <&watchdog 15>;
+ #phy-cells = <0>;
+ };
+
+ xfi_pll: clock-controller@11f40000 {
compatible = "mediatek,mt7988-xfi-pll";
reg = <0 0x11f40000 0 0x1000>;
resets = <&watchdog 16>;
@@ -714,19 +735,129 @@ phy_calibration_p3: calib@97c {
};
};
- clock-controller@15000000 {
+ ethsys: clock-controller@15000000 {
compatible = "mediatek,mt7988-ethsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
- clock-controller@15031000 {
+ ethwarp: clock-controller@15031000 {
compatible = "mediatek,mt7988-ethwarp";
reg = <0 0x15031000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
+
+ eth: ethernet@15100000 {
+ compatible = "mediatek,mt7988-eth";
+ reg = <0 0x15100000 0 0x40000>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "fe0", "fe1", "fe2", "fe3", "pdma0",
+ "pdma1", "pdma2", "pdma3";
+ clocks = <&ethsys CLK_ETHDMA_CRYPT0_EN>,
+ <&ethsys CLK_ETHDMA_FE_EN>,
+ <&ethsys CLK_ETHDMA_GP2_EN>,
+ <&ethsys CLK_ETHDMA_GP1_EN>,
+ <&ethsys CLK_ETHDMA_GP3_EN>,
+ <&ethwarp CLK_ETHWARP_WOCPU2_EN>,
+ <&ethwarp CLK_ETHWARP_WOCPU1_EN>,
+ <&ethwarp CLK_ETHWARP_WOCPU0_EN>,
+ <&ethsys CLK_ETHDMA_ESW_EN>,
+ <&topckgen CLK_TOP_ETH_GMII_SEL>,
+ <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
+ <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
+ <&topckgen CLK_TOP_ETH_SYS_SEL>,
+ <&topckgen CLK_TOP_ETH_XGMII_SEL>,
+ <&topckgen CLK_TOP_ETH_MII_SEL>,
+ <&topckgen CLK_TOP_NETSYS_SEL>,
+ <&topckgen CLK_TOP_NETSYS_500M_SEL>,
+ <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
+ <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
+ <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
+ <&topckgen CLK_TOP_NETSYS_WARP_SEL>,
+ <&ethsys CLK_ETHDMA_XGP1_EN>,
+ <&ethsys CLK_ETHDMA_XGP2_EN>,
+ <&ethsys CLK_ETHDMA_XGP3_EN>;
+ clock-names = "crypto", "fe", "gp2", "gp1", "gp3",
+ "ethwarp_wocpu2", "ethwarp_wocpu1",
+ "ethwarp_wocpu0", "esw", "top_eth_gmii_sel",
+ "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
+ "top_eth_sys_sel", "top_eth_xgmii_sel",
+ "top_eth_mii_sel", "top_netsys_sel",
+ "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
+ "top_netsys_sync_250m_sel",
+ "top_netsys_ppefb_250m_sel",
+ "top_netsys_warp_sel","xgp1", "xgp2", "xgp3";
+ assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
+ <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
+ <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
+ <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
+ <&topckgen CLK_TOP_SGM_0_SEL>,
+ <&topckgen CLK_TOP_SGM_1_SEL>;
+ assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
+ <&topckgen CLK_TOP_NET1PLL_D4>,
+ <&topckgen CLK_TOP_NET1PLL_D8_D4>,
+ <&topckgen CLK_TOP_NET1PLL_D8_D4>,
+ <&apmixedsys CLK_APMIXED_SGMPLL>,
+ <&apmixedsys CLK_APMIXED_SGMPLL>;
+ sram = <&eth_sram>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mediatek,ethsys = <&ethsys>;
+ mediatek,infracfg = <&topmisc>;
+
+ gmac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-mode = "internal";
+
+ /* Connected to internal switch */
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ pause;
+ };
+ };
+
+ gmac1: mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+ status = "disabled";
+ };
+
+ gmac2: mac@2 {
+ compatible = "mediatek,eth-mac";
+ reg = <2>;
+ status = "disabled";
+ };
+
+ mdio_bus: mdio-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* internal 2.5G PHY */
+ int_2p5g_phy: ethernet-phy@15 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <15>;
+ };
+ };
+ };
+
+ eth_sram: sram@15400000 {
+ compatible = "mmio-sram";
+ reg = <0 0x15400000 0 0x200000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x15400000 0 0x200000>;
+ };
};
thermal-zones {
--
2.30.2

184
patch/kernel/archive/filogic-6.16/patches.armbian/0027-arm64-dts-mediatek-mt7988-add-switch-node.patch Normal file
View File

@ -0,0 +1,184 @@
From 2292b669f7c265c39f2836b894270305b1d32a39 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Sat, 1 Feb 2025 15:18:12 +0100
Subject: [PATCH 27/84] arm64: dts: mediatek: mt7988: add switch node
Add mt7988 builtin mt753x switch nodes.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
v4:
- drop phy-mode for gsw-phy
- reorder phy-mode after phy-handle
- drop interrupt parent from switch
v2:
- drop labels and led-function too (have to be in board)
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 148 ++++++++++++++++++++++
1 file changed, 148 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index 897b5a82b53e..366203a72d6d 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -742,6 +742,154 @@ ethsys: clock-controller@15000000 {
#reset-cells = <1>;
};
+ switch: switch@15020000 {
+ compatible = "mediatek,mt7988-switch";
+ reg = <0 0x15020000 0 0x8000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&ethwarp MT7988_ETHWARP_RST_SWITCH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gsw_port0: port@0 {
+ reg = <0>;
+ phy-handle = <&gsw_phy0>;
+ phy-mode = "internal";
+ };
+
+ gsw_port1: port@1 {
+ reg = <1>;
+ phy-handle = <&gsw_phy1>;
+ phy-mode = "internal";
+ };
+
+ gsw_port2: port@2 {
+ reg = <2>;
+ phy-handle = <&gsw_phy2>;
+ phy-mode = "internal";
+ };
+
+ gsw_port3: port@3 {
+ reg = <3>;
+ phy-handle = <&gsw_phy3>;
+ phy-mode = "internal";
+ };
+
+ port@6 {
+ reg = <6>;
+ ethernet = <&gmac0>;
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mediatek,pio = <&pio>;
+
+ gsw_phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ interrupts = <0>;
+ nvmem-cells = <&phy_calibration_p0>;
+ nvmem-cell-names = "phy-cal-data";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gsw_phy0_led0: led@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ gsw_phy0_led1: led@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+ };
+ };
+
+ gsw_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ interrupts = <1>;
+ nvmem-cells = <&phy_calibration_p1>;
+ nvmem-cell-names = "phy-cal-data";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gsw_phy1_led0: led@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ gsw_phy1_led1: led@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+ };
+ };
+
+ gsw_phy2: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ interrupts = <2>;
+ nvmem-cells = <&phy_calibration_p2>;
+ nvmem-cell-names = "phy-cal-data";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gsw_phy2_led0: led@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ gsw_phy2_led1: led@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+ };
+ };
+
+ gsw_phy3: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ interrupts = <3>;
+ nvmem-cells = <&phy_calibration_p3>;
+ nvmem-cell-names = "phy-cal-data";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gsw_phy3_led0: led@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ gsw_phy3_led1: led@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+ };
+
ethwarp: clock-controller@15031000 {
compatible = "mediatek,mt7988-ethwarp";
reg = <0 0x15031000 0 0x1000>;
--
2.30.2

34
patch/kernel/archive/filogic-6.16/patches.armbian/0028-arm64-dts-mediatek-mt7988a-bpi-r4-add-aliases-for-et.patch Normal file
View File

@ -0,0 +1,34 @@
From 27b63d1a7ead4d934e1557bed3ee44f2a8295f61 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Thu, 5 Jun 2025 18:38:51 +0200
Subject: [PATCH 28/84] arm64: dts: mediatek: mt7988a-bpi-r4: add aliases for
ethernet
Add aliases for gmacs to allow bootloader setting mac-adresses.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
index 21eb91c8609f..20073eb4d1bd 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -8,6 +8,12 @@
#include "mt7988a.dtsi"
/ {
+ aliases {
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ ethernet2 = &gmac2;
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
--
2.30.2

114
patch/kernel/archive/filogic-6.16/patches.armbian/0029-arm64-dts-mediatek-mt7988a-bpi-r4-add-sfp-cages-and-.patch Normal file
View File

@ -0,0 +1,114 @@
From f4e52f16c979828597c900959d7a955f699903be Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Sat, 3 May 2025 11:02:27 +0200
Subject: [PATCH 29/84] arm64: dts: mediatek: mt7988a-bpi-r4: add sfp cages and
link to gmac
Add SFP cages to Bananapi-R4 board. The 2.5g phy variant only contains the
wan-SFP, so add this to common dtsi and the lan-sfp only to the dual-SFP
variant.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
v4:
- update 2g5-board (reorder and drop phy-connection-type)
- order sfp properties
v3:
- enable mac with 2.5g phy on r4 phy variant because driver is now mainline
---
.../mediatek/mt7988a-bananapi-bpi-r4-2g5.dts | 11 +++++++++++
.../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 19 +++++++++++++++++++
.../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 19 +++++++++++++++++++
3 files changed, 49 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts
index 53de9c113f60..6f0c81e3fd94 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts
@@ -9,3 +9,14 @@ / {
model = "Banana Pi BPI-R4 (1x SFP+, 1x 2.5GbE)";
chassis-type = "embedded";
};
+
+&gmac1 {
+ phy = <&int_2p5g_phy>;
+ phy-mode = "internal";
+ status = "okay";
+};
+
+&int_2p5g_phy {
+ pinctrl-0 = <&i2p5gbe_led0_pins>;
+ pinctrl-names = "i2p5gbe-led";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
index 36bd1ef2efab..4b3796ba82e3 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
@@ -8,6 +8,25 @@ / {
compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
model = "Banana Pi BPI-R4 (2x SFP+)";
chassis-type = "embedded";
+
+ /* SFP2 cage (LAN) */
+ sfp2: sfp2 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp2>;
+ maximum-power-milliwatt = <3000>;
+
+ los-gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&pio 83 GPIO_ACTIVE_LOW>;
+ rate-select0-gpios = <&pio 3 GPIO_ACTIVE_LOW>;
+ tx-disable-gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&gmac1 {
+ managed = "in-band-status";
+ phy-mode = "usxgmii";
+ sfp = <&sfp2>;
};
&pca9545 {
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
index 20073eb4d1bd..4d709ee527df 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -63,6 +63,19 @@ reg_3p3v: regulator-3p3v {
regulator-boot-on;
regulator-always-on;
};
+
+ /* SFP1 cage (WAN) */
+ sfp1: sfp1 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp1>;
+ maximum-power-milliwatt = <3000>;
+
+ los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
+ rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>;
+ tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
+ };
};
&cci {
@@ -133,6 +146,12 @@ map-cpu-active-low {
};
};
+&gmac2 {
+ managed = "in-band-status";
+ phy-mode = "usxgmii";
+ sfp = <&sfp1>;
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
--
2.30.2

102
patch/kernel/archive/filogic-6.16/patches.armbian/0030-arm64-dts-mediatek-mt7988a-bpi-r4-configure-switch-p.patch Normal file
View File

@ -0,0 +1,102 @@
From 50fb825ca91959e8c00e3d792df1e09c0ef011c1 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Sat, 3 May 2025 13:06:40 +0200
Subject: [PATCH 30/84] arm64: dts: mediatek: mt7988a-bpi-r4: configure switch
phys and leds
Assign pinctrl to switch phys and leds.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
v4:
- reorder switch phy(-led) properties
v2:
- add labels and led-function and include after dropping from soc dtsi
---
.../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 61 +++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
index 4d709ee527df..7c9df606f60d 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -4,6 +4,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
+#include <dt-bindings/leds/common.h>
#include "mt7988a.dtsi"
@@ -152,6 +153,66 @@ &gmac2 {
sfp = <&sfp1>;
};
+&gsw_phy0 {
+ pinctrl-0 = <&gbe0_led0_pins>;
+ pinctrl-names = "gbe-led";
+};
+
+&gsw_phy0_led0 {
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_GREEN>;
+ status = "okay";
+};
+
+&gsw_port0 {
+ label = "wan";
+};
+
+&gsw_phy1 {
+ pinctrl-0 = <&gbe1_led0_pins>;
+ pinctrl-names = "gbe-led";
+};
+
+&gsw_phy1_led0 {
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_GREEN>;
+ status = "okay";
+};
+
+&gsw_port1 {
+ label = "lan1";
+};
+
+&gsw_phy2 {
+ pinctrl-0 = <&gbe2_led0_pins>;
+ pinctrl-names = "gbe-led";
+};
+
+&gsw_phy2_led0 {
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_GREEN>;
+ status = "okay";
+};
+
+&gsw_port2 {
+ label = "lan2";
+};
+
+&gsw_phy3 {
+ pinctrl-0 = <&gbe3_led0_pins>;
+ pinctrl-names = "gbe-led";
+};
+
+&gsw_phy3_led0 {
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_GREEN>;
+ status = "okay";
+};
+
+&gsw_port3 {
+ label = "lan3";
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
--
2.30.2

31
patch/kernel/archive/filogic-6.16/patches.armbian/0031-arm64-dts-mediatek-mt7988a-bpi-r4-drop-readonly-from.patch Normal file
View File

@ -0,0 +1,31 @@
From 060ce20b9896abbb7bd44f9637d78fbfd0ff1f23 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Sat, 5 Jul 2025 22:58:15 +0200
Subject: [PATCH 31/84] arm64: dts: mediatek: mt7988a-bpi-r4: drop readonly
from bl2 partition
This flag must be removed to allow nand install scripts writing the bl2.
Fixes: 6b7642e9d095 ("arm64: dts: mediatek: mt7988a-bpi-r4: configure spi-nodes")
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
v8: new patch
---
arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
index 7c9df606f60d..6436263d2328 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -448,7 +448,6 @@ partitions {
partition@0 {
label = "bl2";
reg = <0x0 0x200000>;
- read-only;
};
};
};
--
2.30.2

52
patch/kernel/archive/filogic-6.16/patches.armbian/0032-dt-bindings-net-pcs-mediatek-sgmiisys-add-phys-and-r.patch Normal file
View File

@ -0,0 +1,52 @@
From 1d055f70cc1e201be29bbaf05947b2ef1644b259 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Thu, 1 May 2025 21:18:27 +0200
Subject: [PATCH 32/84] dt-bindings: net: pcs: mediatek,sgmiisys: add phys and
resets
For mt7988 we need 2 additional properties:
- phys
- resets
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
.../bindings/net/pcs/mediatek,sgmiisys.yaml | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
index 1bacc0eeff75..ca0f4f4ec765 100644
--- a/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
+++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
@@ -58,6 +58,11 @@ properties:
- const: sgmii_tx
- const: sgmii_rx
+ phys:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the (xfi) phy.
+
required:
- compatible
- clocks
@@ -65,6 +70,16 @@ properties:
additionalProperties: false
+ resets:
+ description:
+ A phandle to reset the sgmiisys controller.
+ items:
+ - items:
+ - description:
+ Phandle to the reset controller
+ - description:
+ value for reset
+
required:
- compatible
- reg
--
2.30.2

26
patch/kernel/archive/filogic-6.16/patches.armbian/0033-dt-binding-sgmiisys-re-add-pcs-cells.patch Normal file
View File

@ -0,0 +1,26 @@
From dfcf69513fa1161889f0ae09bd20d00cce92b7af Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Mon, 5 May 2025 19:58:25 +0200
Subject: [PATCH 33/84] dt-binding: sgmiisys: re-add pcs-cells"
---
.../devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
index ca0f4f4ec765..375c166727c5 100644
--- a/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
+++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
@@ -58,6 +58,9 @@ properties:
- const: sgmii_tx
- const: sgmii_rx
+ "#pcs-cells":
+ const: 0
+
phys:
$ref: /schemas/types.yaml#/definitions/phandle
description:
--
2.30.2

61
patch/kernel/archive/filogic-6.16/patches.armbian/0034-dts-re-add-sgmiisys.patch Normal file
View File

@ -0,0 +1,61 @@
From c656470a7109031ebafa95174a0ecd11d251b788 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Mon, 5 May 2025 20:01:00 +0200
Subject: [PATCH 34/84] dts: re-add sgmiisys
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 38 +++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index 366203a72d6d..e4833dbdd7af 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -277,6 +277,44 @@ pwm: pwm@10048000 {
status = "disabled";
};
+ sgmiisys0: syscon@10060000 {
+ compatible = "mediatek,mt7988-sgmiisys0",
+ "simple-mfd",
+ "syscon";
+ reg = <0 0x10060000 0 0x1000>;
+ resets = <&watchdog 1>;
+ #clock-cells = <1>;
+
+ sgmiipcs0: pcs {
+ compatible = "mediatek,mt7988-sgmii";
+ clocks = <&topckgen CLK_TOP_SGM_0_SEL>,
+ <&sgmiisys0 CLK_SGM0_TX_EN>,
+ <&sgmiisys0 CLK_SGM0_RX_EN>;
+ clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
+ phys = <&xfi_tphy0>;
+ #pcs-cells = <0>;
+ };
+ };
+
+ sgmiisys1: syscon@10070000 {
+ compatible = "mediatek,mt7988-sgmiisys1",
+ "simple-mfd",
+ "syscon";
+ reg = <0 0x10070000 0 0x1000>;
+ resets = <&watchdog 2>;
+ #clock-cells = <1>;
+
+ sgmiipcs1: pcs {
+ compatible = "mediatek,mt7988-sgmii";
+ clocks = <&topckgen CLK_TOP_SGM_1_SEL>,
+ <&sgmiisys1 CLK_SGM1_TX_EN>,
+ <&sgmiisys1 CLK_SGM1_RX_EN>;
+ clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
+ phys = <&xfi_tphy1>;
+ #pcs-cells = <0>;
+ };
+ };
+
mcusys: mcusys@100e0000 {
compatible = "mediatek,mt7988-mcusys", "syscon";
reg = <0 0x100e0000 0 0x1000>;
--
2.30.2

27
patch/kernel/archive/filogic-6.16/patches.armbian/0035-arm64-dts-mt7988-add-cpufreq-calibration-efuse-subno.patch Normal file
View File

@ -0,0 +1,27 @@
From eeeadc20f05134123868769f8def2ce1ab0933ec Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Fri, 2 May 2025 12:29:54 +0200
Subject: [PATCH 35/84] arm64: dts: mt7988: add cpufreq calibration efuse
subnode
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index e4833dbdd7af..88f201ad78cf 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -752,6 +752,9 @@ efuse@11f50000 {
#address-cells = <1>;
#size-cells = <1>;
+ cpufreq_calibration: calib@278 {
+ reg = <0x278 0x1>;
+ };
lvts_calibration: calib@918 {
reg = <0x918 0x28>;
};
--
2.30.2

39
patch/kernel/archive/filogic-6.16/patches.armbian/0036-net-ethernet-mtk_eth_soc-move-desc-assignment-below-.patch Normal file
View File

@ -0,0 +1,39 @@
From 682eb678991b3dde629df9178e7e088bbe4b7039 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Wed, 26 Mar 2025 19:44:18 +0100
Subject: [PATCH 36/84] net: ethernet: mtk_eth_soc: move desc assignment below
check for its txd3
The field desc->txd3 should be checked for TX_DMA_OWNER_CPU flag before
assign a new desc.
old MTK-SDK uses same order:
https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/refs/heads/master/21.02/files/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c#2895
new SDK seems not changing it.
Fixes: 656e705243fd ("net-next: mediatek: add support for MT7623 ethernet")
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 9333f2b8e1d6..5b201c0214a0 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -2439,10 +2439,11 @@ static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget,
while ((cpu != dma) && budget) {
u32 next_cpu = desc->txd2;
- desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
break;
+ desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
+
tx_buf = mtk_desc_to_tx_buf(ring, desc,
eth->soc->tx.desc_size);
if (!tx_buf->data)
--
2.30.2

121
patch/kernel/archive/filogic-6.16/patches.armbian/0037-dts-enable-mt818-36-for-cci-testing.patch Normal file
View File

@ -0,0 +1,121 @@
From b5d5dcd4cbbed8369b58ee562cc7717c39496c48 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Sat, 31 May 2025 13:09:24 +0200
Subject: [PATCH 37/84] dts: enable mt818[36] for cci testing
---
arch/arm64/boot/dts/mediatek/Makefile | 98 +++++++++++++--------------
1 file changed, 49 insertions(+), 49 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index e60462fa2b6f..87608df68fab 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -30,55 +30,55 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-sd.dtbo
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-burnet.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-cozmo.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku1.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku6.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku7.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14-sku2.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-juniper-sku16.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kappa.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kenzo.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-makomo-sku0.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-makomo-sku1.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-pico.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-pico6.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku0.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku1.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu-sku22.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-katsu-sku32.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-katsu-sku38.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku16.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku272.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku288.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku0.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku1.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku16.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393216.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393217.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393218.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-ponyta-sku0.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-ponyta-sku1.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-rusty-sku196608.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-starmie-sku0.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-starmie-sku1.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-steelix-sku131072.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-steelix-sku131073.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacool-sku327681.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacool-sku327683.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacruel-sku262144.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacruel-sku262148.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-voltorb-sku589824.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-voltorb-sku589825.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-burnet.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-cozmo.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku1.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku6.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku7.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14-sku2.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-juniper-sku16.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kappa.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kenzo.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-makomo-sku0.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-makomo-sku1.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-pico.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-pico6.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku0.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku1.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu-sku22.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-katsu-sku32.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-katsu-sku38.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku16.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku272.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku288.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku0.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku1.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku16.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393216.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393217.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393218.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-ponyta-sku0.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-ponyta-sku1.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-rusty-sku196608.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-starmie-sku0.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-starmie-sku1.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-steelix-sku131072.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-steelix-sku131073.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacool-sku327681.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacool-sku327683.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacruel-sku262144.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacruel-sku262148.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-voltorb-sku589824.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-voltorb-sku589825.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-evb.dtb
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku0.dtb
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku1.dtb
--
2.30.2

122
patch/kernel/archive/filogic-6.16/patches.armbian/0038-Revert-dts-enable-mt818-36-for-cci-testing.patch Normal file
View File

@ -0,0 +1,122 @@
From bac17b5f648913aef5ff8b2559631dffbed56ab8 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Wed, 4 Jun 2025 22:33:49 +0200
Subject: [PATCH 38/84] Revert "dts: enable mt818[36] for cci testing"
This reverts commit 1e0327fc048d602fbc85ce160202bbe998a62cb0.
---
arch/arm64/boot/dts/mediatek/Makefile | 98 +++++++++++++--------------
1 file changed, 49 insertions(+), 49 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 87608df68fab..e60462fa2b6f 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -30,55 +30,55 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-sd.dtbo
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-burnet.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-cozmo.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku1.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku6.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku7.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14-sku2.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-juniper-sku16.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kappa.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kenzo.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-makomo-sku0.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-makomo-sku1.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-pico.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-pico6.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku0.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku1.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu-sku22.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-katsu-sku32.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-katsu-sku38.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku16.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku272.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku288.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku0.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku1.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku16.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393216.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393217.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393218.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-ponyta-sku0.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-ponyta-sku1.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-rusty-sku196608.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-starmie-sku0.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-starmie-sku1.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-steelix-sku131072.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-steelix-sku131073.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacool-sku327681.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacool-sku327683.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacruel-sku262144.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacruel-sku262148.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-voltorb-sku589824.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-voltorb-sku589825.dtb
-dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-burnet.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-cozmo.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku1.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku6.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku7.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14-sku2.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-juniper-sku16.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kappa.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kenzo.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-makomo-sku0.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-makomo-sku1.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-pico.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-pico6.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku0.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku1.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu-sku22.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-katsu-sku32.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-katsu-sku38.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku16.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku272.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku288.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku0.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku1.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku16.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393216.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393217.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393218.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-ponyta-sku0.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-ponyta-sku1.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-rusty-sku196608.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-starmie-sku0.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-starmie-sku1.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-steelix-sku131072.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-steelix-sku131073.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacool-sku327681.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacool-sku327683.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacruel-sku262144.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacruel-sku262148.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-voltorb-sku589824.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-voltorb-sku589825.dtb
+#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-evb.dtb
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku0.dtb
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku1.dtb
--
2.30.2

37
patch/kernel/archive/filogic-6.16/patches.armbian/0039-enable-bpi-r3-DTBs-for-testing.patch Normal file
View File

@ -0,0 +1,37 @@
From b012720e24c54270538cdb6808f895791084da49 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Sun, 15 Jun 2025 16:49:01 +0200
Subject: [PATCH 39/84] enable bpi-r3 DTBs for testing
---
arch/arm64/boot/dts/mediatek/Makefile | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index e60462fa2b6f..d4f56f8e8463 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -12,13 +12,13 @@
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-openwrt-one.dtb
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-xiaomi-ax3000t.dtb
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-acelink-ew-7886cax.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-mini.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sata.dtbo
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-mini.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sata.dtbo
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4.dtb
--
2.30.2

97
patch/kernel/archive/filogic-6.16/patches.armbian/0040-only-enable-mediatek-for-arm-to-increase-dtbs_check.patch Normal file
View File

@ -0,0 +1,97 @@
From 606aeff7dcc0f97ace6cb54e8098b9ca72a30c32 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Mon, 23 Jun 2025 22:17:54 +0200
Subject: [PATCH 40/84] only enable mediatek for arm to increase dtbs_check
---
arch/arm/boot/dts/Makefile | 78 +++++++++++++++++++-------------------
1 file changed, 39 insertions(+), 39 deletions(-)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index efe38eb25301..8afa52394d6d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1,41 +1,41 @@
# SPDX-License-Identifier: GPL-2.0
-subdir-y += actions
-subdir-y += airoha
-subdir-y += allwinner
-subdir-y += alphascale
-subdir-y += amazon
-subdir-y += amlogic
-subdir-y += arm
-subdir-y += aspeed
-subdir-y += axis
-subdir-y += broadcom
-subdir-y += calxeda
-subdir-y += cirrus
-subdir-y += cnxt
-subdir-y += gemini
-subdir-y += hisilicon
-subdir-y += hpe
-subdir-y += intel
-subdir-y += marvell
+#subdir-y += actions
+#subdir-y += airoha
+#subdir-y += allwinner
+#subdir-y += alphascale
+#subdir-y += amazon
+#subdir-y += amlogic
+#subdir-y += arm
+#subdir-y += aspeed
+#subdir-y += axis
+#subdir-y += broadcom
+#subdir-y += calxeda
+#subdir-y += cirrus
+#subdir-y += cnxt
+#subdir-y += gemini
+#subdir-y += hisilicon
+#subdir-y += hpe
+#subdir-y += intel
+#subdir-y += marvell
subdir-y += mediatek
-subdir-y += microchip
-subdir-y += moxa
-subdir-y += nspire
-subdir-y += nuvoton
-subdir-y += nvidia
-subdir-y += nxp
-subdir-y += qcom
-subdir-y += realtek
-subdir-y += renesas
-subdir-y += rockchip
-subdir-y += samsung
-subdir-y += sigmastar
-subdir-y += socionext
-subdir-y += st
-subdir-y += sunplus
-subdir-y += synaptics
-subdir-y += ti
-subdir-y += unisoc
-subdir-y += vt8500
-subdir-y += xen
-subdir-y += xilinx
+#subdir-y += microchip
+#subdir-y += moxa
+#subdir-y += nspire
+#subdir-y += nuvoton
+#subdir-y += nvidia
+#subdir-y += nxp
+#subdir-y += qcom
+#subdir-y += realtek
+#subdir-y += renesas
+#subdir-y += rockchip
+#subdir-y += samsung
+#subdir-y += sigmastar
+#subdir-y += socionext
+#subdir-y += st
+#subdir-y += sunplus
+#subdir-y += synaptics
+#subdir-y += ti
+#subdir-y += unisoc
+#subdir-y += vt8500
+#subdir-y += xen
+#subdir-y += xilinx
--
2.30.2

41
patch/kernel/archive/filogic-6.16/patches.armbian/0041-enable-some-arm64-dts-to-check-binding.patch Normal file
View File

@ -0,0 +1,41 @@
From f66d885af3510cd9fbe765354bea75955b791b95 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Mon, 23 Jun 2025 22:18:41 +0200
Subject: [PATCH 41/84] enable some arm64 dts to check binding
---
arch/arm64/boot/dts/mediatek/Makefile | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index d4f56f8e8463..d728953c10ad 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -7,7 +7,7 @@
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-cudy-wr3000-v1.dtb
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-openwrt-one.dtb
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-xiaomi-ax3000t.dtb
@@ -25,12 +25,12 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-2g5.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-emmc.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-sd.dtbo
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
-#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-burnet.dtb
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-cozmo.dtb
#dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb
--
2.30.2

25
patch/kernel/archive/filogic-6.16/patches.armbian/0042-defconfig-r4-add-sram-driver.patch Normal file
View File

@ -0,0 +1,25 @@
From ba3dd9a702c9ba546f569fdd0da5e3dc0e533b8d Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Wed, 25 Jun 2025 21:08:16 +0200
Subject: [PATCH 42/84] defconfig: r4: add sram driver
---
arch/arm64/configs/mt7988a_bpi-r4_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/configs/mt7988a_bpi-r4_defconfig b/arch/arm64/configs/mt7988a_bpi-r4_defconfig
index 69de56a20462..29bc60ce564f 100644
--- a/arch/arm64/configs/mt7988a_bpi-r4_defconfig
+++ b/arch/arm64/configs/mt7988a_bpi-r4_defconfig
@@ -1274,7 +1274,7 @@ CONFIG_SECCOMP=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
-
+CONFIG_SRAM=y
CONFIG_PCS_MTK_USXGMII=y
CONFIG_MT7915E=m
--
2.30.2

52
patch/kernel/archive/filogic-6.16/patches.armbian/0043-net-ethernet-mtk_eth_soc-improve-support-for-named-i.patch Normal file
View File

@ -0,0 +1,52 @@
From 67cbba9936c2fabc97392f3ac67ffd289a205c2f Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Wed, 2 Jul 2025 14:14:29 +0100
Subject: [PATCH 43/84] net: ethernet: mtk_eth_soc: improve support for named
interrupts
Use platform_get_irq_byname_optional() to avoid outputting error
messages when using legacy device trees which rely identifying
interrupts only by index. Instead, output a warning notifying the user
to update their device tree.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 5b201c0214a0..a119094645e4 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -3350,17 +3350,22 @@ static int mtk_get_irqs(struct platform_device *pdev, struct mtk_eth *eth)
int i;
/* future SoCs beginning with MT7988 should use named IRQs in dts */
- eth->irq[MTK_FE_IRQ_TX] = platform_get_irq_byname(pdev, "fe1");
- eth->irq[MTK_FE_IRQ_RX] = platform_get_irq_byname(pdev, "fe2");
+ eth->irq[MTK_FE_IRQ_TX] = platform_get_irq_byname_optional(pdev, "fe1");
+ eth->irq[MTK_FE_IRQ_RX] = platform_get_irq_byname_optional(pdev, "fe2");
if (eth->irq[MTK_FE_IRQ_TX] >= 0 && eth->irq[MTK_FE_IRQ_RX] >= 0)
return 0;
- /* only use legacy mode if platform_get_irq_byname returned -ENXIO */
+ /* only use legacy mode if platform_get_irq_byname_optional returned -ENXIO */
if (eth->irq[MTK_FE_IRQ_TX] != -ENXIO)
- return eth->irq[MTK_FE_IRQ_TX];
+ return dev_err_probe(&pdev->dev, eth->irq[MTK_FE_IRQ_TX],
+ "Error requesting FE TX IRQ\n");
if (eth->irq[MTK_FE_IRQ_RX] != -ENXIO)
- return eth->irq[MTK_FE_IRQ_RX];
+ return dev_err_probe(&pdev->dev, eth->irq[MTK_FE_IRQ_RX],
+ "Error requesting FE RX IRQ\n");
+
+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT))
+ dev_warn(&pdev->dev, "legacy DT: missing interrupt-names.");
/* legacy way:
* On MTK_SHARED_INT SoCs (MT7621 + MT7628) the first IRQ is taken
--
2.30.2

32
patch/kernel/archive/filogic-6.16/patches.armbian/0044-net-ethernet-mtk_eth_soc-fix-kernel-doc-comment.patch Normal file
View File

@ -0,0 +1,32 @@
From 5a3c93c4023f57befd6cf590088e6095b70a001f Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Wed, 2 Jul 2025 14:14:39 +0100
Subject: [PATCH 44/84] net: ethernet: mtk_eth_soc: fix kernel-doc comment
Fix and add some missing field descriptions to kernel-doc comment of
struct mtk_eth.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 9261c0e13b59..1ad9075a9b69 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -1243,8 +1243,9 @@ struct mtk_soc_data {
/* struct mtk_eth - This is the main datasructure for holding the state
* of the driver
* @dev: The device pointer
- * @dev: The device pointer used for dma mapping/alloc
+ * @dma_dev: The device pointer used for dma mapping/alloc
* @base: The mapped register i/o base
+ * @sram_base: The mapped SRAM base
* @page_lock: Make sure that register operations are atomic
* @tx_irq__lock: Make sure that IRQ register operations are atomic
* @rx_irq__lock: Make sure that IRQ register operations are atomic
--
2.30.2

324
patch/kernel/archive/filogic-6.16/patches.armbian/0045-net-ethernet-mtk_eth_soc-use-generic-allocator-for-S.patch Normal file
View File

@ -0,0 +1,324 @@
From 4ba463a09585baacc97b544c939f379a4d784e5b Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Wed, 2 Jul 2025 14:14:56 +0100
Subject: [PATCH 45/84] net: ethernet: mtk_eth_soc: use generic allocator for
SRAM
Use a dedicated "mmio-sram" node and the generic allocator
instead of open-coding SRAM allocation for DMA rings.
Keep support for legacy device trees but notify the user via a
warning to update, and let the ethernet driver create the
gen_pool in this case.
Co-developed-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
drivers/net/ethernet/mediatek/Kconfig | 1 +
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 152 +++++++++++---------
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 10 +-
3 files changed, 90 insertions(+), 73 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/Kconfig b/drivers/net/ethernet/mediatek/Kconfig
index 7bfd3f230ff5..2ba361f8ce7d 100644
--- a/drivers/net/ethernet/mediatek/Kconfig
+++ b/drivers/net/ethernet/mediatek/Kconfig
@@ -17,6 +17,7 @@ config NET_MEDIATEK_SOC
select PINCTRL
select PHYLINK
select DIMLIB
+ select GENERIC_ALLOCATOR
select PAGE_POOL
select PAGE_POOL_STATS
select PCS_MTK_LYNXI
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index a119094645e4..7916c99d5ebb 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -27,6 +27,7 @@
#include <net/dsa.h>
#include <net/dst_metadata.h>
#include <net/page_pool/helpers.h>
+#include <linux/genalloc.h>
#include "mtk_eth_soc.h"
#include "mtk_wed.h"
@@ -1267,6 +1268,34 @@ static void *mtk_max_lro_buf_alloc(gfp_t gfp_mask)
return (void *)data;
}
+static void *mtk_dma_ring_alloc(struct mtk_eth *eth, size_t size,
+ dma_addr_t *dma_handle, bool use_sram)
+{
+ void *dma_ring;
+
+ if (use_sram && eth->sram_pool) {
+ dma_ring = (void *)gen_pool_alloc(eth->sram_pool, size);
+ if (!dma_ring)
+ return dma_ring;
+ *dma_handle = gen_pool_virt_to_phys(eth->sram_pool,
+ (unsigned long)dma_ring);
+ } else {
+ dma_ring = dma_alloc_coherent(eth->dma_dev, size, dma_handle,
+ GFP_KERNEL);
+ }
+
+ return dma_ring;
+}
+
+static void mtk_dma_ring_free(struct mtk_eth *eth, size_t size, void *dma_ring,
+ dma_addr_t dma_handle, bool in_sram)
+{
+ if (in_sram && eth->sram_pool)
+ gen_pool_free(eth->sram_pool, (unsigned long)dma_ring, size);
+ else
+ dma_free_coherent(eth->dma_dev, size, dma_ring, dma_handle);
+}
+
/* the qdma core needs scratch memory to be setup */
static int mtk_init_fq_dma(struct mtk_eth *eth)
{
@@ -1276,13 +1305,8 @@ static int mtk_init_fq_dma(struct mtk_eth *eth)
dma_addr_t dma_addr;
int i, j, len;
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM))
- eth->scratch_ring = eth->sram_base;
- else
- eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
- cnt * soc->tx.desc_size,
- &eth->phy_scratch_ring,
- GFP_KERNEL);
+ eth->scratch_ring = mtk_dma_ring_alloc(eth, cnt * soc->tx.desc_size,
+ &eth->phy_scratch_ring, true);
if (unlikely(!eth->scratch_ring))
return -ENOMEM;
@@ -2629,14 +2653,7 @@ static int mtk_tx_alloc(struct mtk_eth *eth)
if (!ring->buf)
goto no_tx_mem;
- if (MTK_HAS_CAPS(soc->caps, MTK_SRAM)) {
- ring->dma = eth->sram_base + soc->tx.fq_dma_size * sz;
- ring->phys = eth->phy_scratch_ring + soc->tx.fq_dma_size * (dma_addr_t)sz;
- } else {
- ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz,
- &ring->phys, GFP_KERNEL);
- }
-
+ ring->dma = mtk_dma_ring_alloc(eth, ring_size * sz, &ring->phys, true);
if (!ring->dma)
goto no_tx_mem;
@@ -2735,10 +2752,10 @@ static void mtk_tx_clean(struct mtk_eth *eth)
kfree(ring->buf);
ring->buf = NULL;
}
- if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) {
- dma_free_coherent(eth->dma_dev,
- ring->dma_size * soc->tx.desc_size,
- ring->dma, ring->phys);
+
+ if (ring->dma) {
+ mtk_dma_ring_free(eth, ring->dma_size * soc->tx.desc_size,
+ ring->dma, ring->phys, true);
ring->dma = NULL;
}
@@ -2755,14 +2772,9 @@ static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
const struct mtk_reg_map *reg_map = eth->soc->reg_map;
const struct mtk_soc_data *soc = eth->soc;
struct mtk_rx_ring *ring;
- int rx_data_len, rx_dma_size, tx_ring_size;
+ int rx_data_len, rx_dma_size;
int i;
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
- tx_ring_size = MTK_QDMA_RING_SIZE;
- else
- tx_ring_size = soc->tx.dma_size;
-
if (rx_flag == MTK_RX_FLAGS_QDMA) {
if (ring_no)
return -EINVAL;
@@ -2797,20 +2809,10 @@ static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
ring->page_pool = pp;
}
- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) ||
- rx_flag != MTK_RX_FLAGS_NORMAL) {
- ring->dma = dma_alloc_coherent(eth->dma_dev,
- rx_dma_size * eth->soc->rx.desc_size,
- &ring->phys, GFP_KERNEL);
- } else {
- struct mtk_tx_ring *tx_ring = &eth->tx_ring;
-
- ring->dma = tx_ring->dma + tx_ring_size *
- eth->soc->tx.desc_size * (ring_no + 1);
- ring->phys = tx_ring->phys + tx_ring_size *
- eth->soc->tx.desc_size * (ring_no + 1);
- }
-
+ ring->dma = mtk_dma_ring_alloc(eth,
+ rx_dma_size * eth->soc->rx.desc_size,
+ &ring->phys,
+ rx_flag == MTK_RX_FLAGS_NORMAL);
if (!ring->dma)
return -ENOMEM;
@@ -2925,10 +2927,9 @@ static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, bool in_
ring->data = NULL;
}
- if (!in_sram && ring->dma) {
- dma_free_coherent(eth->dma_dev,
- ring->dma_size * eth->soc->rx.desc_size,
- ring->dma, ring->phys);
+ if (ring->dma) {
+ mtk_dma_ring_free(eth, ring->dma_size * eth->soc->rx.desc_size,
+ ring->dma, ring->phys, in_sram);
ring->dma = NULL;
}
@@ -3296,15 +3297,16 @@ static void mtk_dma_free(struct mtk_eth *eth)
netdev_tx_reset_subqueue(eth->netdev[i], j);
}
- if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) {
- dma_free_coherent(eth->dma_dev,
- MTK_QDMA_RING_SIZE * soc->tx.desc_size,
- eth->scratch_ring, eth->phy_scratch_ring);
+ if (eth->scratch_ring) {
+ mtk_dma_ring_free(eth, soc->tx.fq_dma_size * soc->tx.desc_size,
+ eth->scratch_ring, eth->phy_scratch_ring,
+ true);
eth->scratch_ring = NULL;
eth->phy_scratch_ring = 0;
}
+
mtk_tx_clean(eth);
- mtk_rx_clean(eth, &eth->rx_ring[0], MTK_HAS_CAPS(soc->caps, MTK_SRAM));
+ mtk_rx_clean(eth, &eth->rx_ring[0], true);
mtk_rx_clean(eth, &eth->rx_ring_qdma, false);
if (eth->hwlro) {
@@ -5016,9 +5018,30 @@ static int mtk_sgmii_init(struct mtk_eth *eth)
return 0;
}
+static int mtk_setup_legacy_sram(struct mtk_eth *eth, struct resource *res)
+{
+ dev_warn(eth->dev, "legacy DT: using hard-coded SRAM offset.\n");
+
+ if (res->start + MTK_ETH_SRAM_OFFSET + MTK_ETH_NETSYS_V2_SRAM_SIZE - 1 >
+ res->end)
+ return -EINVAL;
+
+ eth->sram_pool = devm_gen_pool_create(eth->dev,
+ const_ilog2(MTK_ETH_SRAM_GRANULARITY),
+ NUMA_NO_NODE, dev_name(eth->dev));
+
+ if (IS_ERR(eth->sram_pool))
+ return PTR_ERR(eth->sram_pool);
+
+ return gen_pool_add_virt(eth->sram_pool,
+ (unsigned long)eth->base + MTK_ETH_SRAM_OFFSET,
+ res->start + MTK_ETH_SRAM_OFFSET,
+ MTK_ETH_NETSYS_V2_SRAM_SIZE, NUMA_NO_NODE);
+}
+
static int mtk_probe(struct platform_device *pdev)
{
- struct resource *res = NULL, *res_sram;
+ struct resource *res = NULL;
struct device_node *mac_np;
struct mtk_eth *eth;
int err, i;
@@ -5038,20 +5061,6 @@ static int mtk_probe(struct platform_device *pdev)
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
eth->ip_align = NET_IP_ALIGN;
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) {
- /* SRAM is actual memory and supports transparent access just like DRAM.
- * Hence we don't require __iomem being set and don't need to use accessor
- * functions to read from or write to SRAM.
- */
- if (mtk_is_netsys_v3_or_greater(eth)) {
- eth->sram_base = (void __force *)devm_platform_ioremap_resource(pdev, 1);
- if (IS_ERR(eth->sram_base))
- return PTR_ERR(eth->sram_base);
- } else {
- eth->sram_base = (void __force *)eth->base + MTK_ETH_SRAM_OFFSET;
- }
- }
-
if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) {
err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(36));
if (!err)
@@ -5126,16 +5135,21 @@ static int mtk_probe(struct platform_device *pdev)
err = -EINVAL;
goto err_destroy_sgmii;
}
+
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) {
- if (mtk_is_netsys_v3_or_greater(eth)) {
- res_sram = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- if (!res_sram) {
+ eth->sram_pool = of_gen_pool_get(pdev->dev.of_node,
+ "sram", 0);
+ if (!eth->sram_pool) {
+ if (!mtk_is_netsys_v3_or_greater(eth)) {
+ err = mtk_setup_legacy_sram(eth, res);
+ if (err)
+ goto err_destroy_sgmii;
+ } else {
+ dev_err(&pdev->dev,
+ "Could not get SRAM pool\n");
err = -EINVAL;
goto err_destroy_sgmii;
}
- eth->phy_scratch_ring = res_sram->start;
- } else {
- eth->phy_scratch_ring = res->start + MTK_ETH_SRAM_OFFSET;
}
}
}
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 1ad9075a9b69..0168e2fbc619 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -141,8 +141,10 @@
#define MTK_GDMA_MAC_ADRH(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \
0x54C : 0x50C + (_x * 0x1000); })
-/* Internal SRAM offset */
-#define MTK_ETH_SRAM_OFFSET 0x40000
+/* legacy DT support for internal SRAM */
+#define MTK_ETH_SRAM_OFFSET 0x40000
+#define MTK_ETH_SRAM_GRANULARITY 32
+#define MTK_ETH_NETSYS_V2_SRAM_SIZE 0x40000
/* FE global misc reg*/
#define MTK_FE_GLO_MISC 0x124
@@ -1245,7 +1247,7 @@ struct mtk_soc_data {
* @dev: The device pointer
* @dma_dev: The device pointer used for dma mapping/alloc
* @base: The mapped register i/o base
- * @sram_base: The mapped SRAM base
+ * @sram_pool: Pointer to SRAM pool used for DMA descriptor rings
* @page_lock: Make sure that register operations are atomic
* @tx_irq__lock: Make sure that IRQ register operations are atomic
* @rx_irq__lock: Make sure that IRQ register operations are atomic
@@ -1291,7 +1293,7 @@ struct mtk_eth {
struct device *dev;
struct device *dma_dev;
void __iomem *base;
- void *sram_base;
+ struct gen_pool *sram_pool;
spinlock_t page_lock;
spinlock_t tx_irq_lock;
spinlock_t rx_irq_lock;
--
2.30.2

21
patch/kernel/archive/filogic-6.16/patches.armbian/0046-defconfig-r3-add-sram.patch Normal file
View File

@ -0,0 +1,21 @@
From 00ef5d4e0a6d6e118b03706c3e2bae2bf9a906a6 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Fri, 27 Jun 2025 22:58:49 +0200
Subject: [PATCH 46/84] defconfig: r3: add sram
---
arch/arm64/configs/mt7986a_bpi-r3_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/mt7986a_bpi-r3_defconfig b/arch/arm64/configs/mt7986a_bpi-r3_defconfig
index 32710280133d..29421f5f3e1f 100644
--- a/arch/arm64/configs/mt7986a_bpi-r3_defconfig
+++ b/arch/arm64/configs/mt7986a_bpi-r3_defconfig
@@ -1263,3 +1263,4 @@ CONFIG_EXTRA_FIRMWARE="airoha/EthMD32.dm.bin airoha/EthMD32.DSP.bin"
CONFIG_EXTRA_FIRMWARE_DIR="utils/firmware/"
CONFIG_PANIC_TIMEOUT=30
+CONFIG_SRAM=y
--
2.30.2

53
patch/kernel/archive/filogic-6.16/patches.armbian/0047-WIP-dts64-r4-add-ubi-partition-to-spin-nand.patch Normal file
View File

@ -0,0 +1,53 @@
From b452c304864e95f043e8ea2cd5696fbd98bf0041 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Fri, 4 Jul 2025 19:51:42 +0200
Subject: [PATCH 47/84] WIP: dts64: r4: add ubi partition to spin nand
---
.../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
index 6436263d2328..38e27ef6bc0c 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -449,6 +449,36 @@ partition@0 {
label = "bl2";
reg = <0x0 0x200000>;
};
+
+ partition@200000 {
+ label = "ubi";
+ reg = <0x200000 0x7e00000>;
+ compatible = "linux,ubi";
+
+ /*volumes {
+ ubi-volume-fip {
+ volname = "fip";
+ };
+
+ ubi-volume-ubootenv {
+ volname = "ubootenv";
+ nvmem-layout {
+ compatible = "u-boot,env-redundant-bool-layout";
+ };
+ };
+
+ ubi-volume-ubootenv2 {
+ volname = "ubootenv2";
+ nvmem-layout {
+ compatible = "u-boot,env-redundant-bool-layout";
+ };
+ };
+
+ ubi_rootfs: ubi-volume-rootfs {
+ volname = "rootfs";
+ };
+ };*/
+ };
};
};
--
2.30.2

594
patch/kernel/archive/filogic-6.16/patches.armbian/0048-add-mtd-rw-driver.patch Normal file
View File

@ -0,0 +1,594 @@
From 33e651e124d1f4fc3dabcc9b83da1fb7c52ce88c Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Sun, 6 Jul 2025 17:00:18 +0200
Subject: [PATCH 48/84] add mtd-rw driver
from https://github.com/jclehner/mtd-rw
---
drivers/mtd/Kconfig | 2 +
drivers/mtd/Makefile | 2 +
drivers/mtd/mtdrw/Kconfig | 8 +
drivers/mtd/mtdrw/LICENSE | 339 ++++++++++++++++++++++++++++++++++++
drivers/mtd/mtdrw/Makefile | 15 ++
drivers/mtd/mtdrw/README.md | 25 +++
drivers/mtd/mtdrw/mtd-rw.c | 132 ++++++++++++++
7 files changed, 523 insertions(+)
create mode 100644 drivers/mtd/mtdrw/Kconfig
create mode 100644 drivers/mtd/mtdrw/LICENSE
create mode 100644 drivers/mtd/mtdrw/Makefile
create mode 100644 drivers/mtd/mtdrw/README.md
create mode 100644 drivers/mtd/mtdrw/mtd-rw.c
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index 796a2eccbef0..7bd7ea0d5ddc 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -222,4 +222,6 @@ source "drivers/mtd/ubi/Kconfig"
source "drivers/mtd/hyperbus/Kconfig"
+source "drivers/mtd/mtdrw/Kconfig"
+
endif # MTD
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 593d0593a038..4c2437657a9c 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -31,3 +31,5 @@ obj-y += chips/ lpddr/ maps/ devices/ nand/ tests/
obj-$(CONFIG_MTD_SPI_NOR) += spi-nor/
obj-$(CONFIG_MTD_UBI) += ubi/
obj-$(CONFIG_MTD_HYPERBUS) += hyperbus/
+
+obj-y += mtdrw/
diff --git a/drivers/mtd/mtdrw/Kconfig b/drivers/mtd/mtdrw/Kconfig
new file mode 100644
index 000000000000..a81af6f11b91
--- /dev/null
+++ b/drivers/mtd/mtdrw/Kconfig
@@ -0,0 +1,8 @@
+config MTD_RW
+ tristate "Module to make all MTD partitions writeable"
+ default n
+ help
+ Say M here to build a module which, upon loading, will make
+ all read-only MTD partitions writeable. Do not say Y here.
+
+ If unsure, say N.
diff --git a/drivers/mtd/mtdrw/LICENSE b/drivers/mtd/mtdrw/LICENSE
new file mode 100644
index 000000000000..23cb790338e1
--- /dev/null
+++ b/drivers/mtd/mtdrw/LICENSE
@@ -0,0 +1,339 @@
+ GNU GENERAL PUBLIC LICENSE
+ Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc., <http://fsf.org/>
+ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+ Preamble
+
+ The licenses for most software are designed to take away your
+freedom to share and change it. By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users. This
+General Public License applies to most of the Free Software
+Foundation's software and to any other program whose authors commit to
+using it. (Some other Free Software Foundation software is covered by
+the GNU Lesser General Public License instead.) You can apply it to
+your programs, too.
+
+ When we speak of free software, we are referring to freedom, not
+price. Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+this service if you wish), that you receive source code or can get it
+if you want it, that you can change the software or use pieces of it
+in new free programs; and that you know you can do these things.
+
+ To protect your rights, we need to make restrictions that forbid
+anyone to deny you these rights or to ask you to surrender the rights.
+These restrictions translate to certain responsibilities for you if you
+distribute copies of the software, or if you modify it.
+
+ For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must give the recipients all the rights that
+you have. You must make sure that they, too, receive or can get the
+source code. And you must show them these terms so they know their
+rights.
+
+ We protect your rights with two steps: (1) copyright the software, and
+(2) offer you this license which gives you legal permission to copy,
+distribute and/or modify the software.
+
+ Also, for each author's protection and ours, we want to make certain
+that everyone understands that there is no warranty for this free
+software. If the software is modified by someone else and passed on, we
+want its recipients to know that what they have is not the original, so
+that any problems introduced by others will not reflect on the original
+authors' reputations.
+
+ Finally, any free program is threatened constantly by software
+patents. We wish to avoid the danger that redistributors of a free
+program will individually obtain patent licenses, in effect making the
+program proprietary. To prevent this, we have made it clear that any
+patent must be licensed for everyone's free use or not licensed at all.
+
+ The precise terms and conditions for copying, distribution and
+modification follow.
+
+ GNU GENERAL PUBLIC LICENSE
+ TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
+ 0. This License applies to any program or other work which contains
+a notice placed by the copyright holder saying it may be distributed
+under the terms of this General Public License. The "Program", below,
+refers to any such program or work, and a "work based on the Program"
+means either the Program or any derivative work under copyright law:
+that is to say, a work containing the Program or a portion of it,
+either verbatim or with modifications and/or translated into another
+language. (Hereinafter, translation is included without limitation in
+the term "modification".) Each licensee is addressed as "you".
+
+Activities other than copying, distribution and modification are not
+covered by this License; they are outside its scope. The act of
+running the Program is not restricted, and the output from the Program
+is covered only if its contents constitute a work based on the
+Program (independent of having been made by running the Program).
+Whether that is true depends on what the Program does.
+
+ 1. You may copy and distribute verbatim copies of the Program's
+source code as you receive it, in any medium, provided that you
+conspicuously and appropriately publish on each copy an appropriate
+copyright notice and disclaimer of warranty; keep intact all the
+notices that refer to this License and to the absence of any warranty;
+and give any other recipients of the Program a copy of this License
+along with the Program.
+
+You may charge a fee for the physical act of transferring a copy, and
+you may at your option offer warranty protection in exchange for a fee.
+
+ 2. You may modify your copy or copies of the Program or any portion
+of it, thus forming a work based on the Program, and copy and
+distribute such modifications or work under the terms of Section 1
+above, provided that you also meet all of these conditions:
+
+ a) You must cause the modified files to carry prominent notices
+ stating that you changed the files and the date of any change.
+
+ b) You must cause any work that you distribute or publish, that in
+ whole or in part contains or is derived from the Program or any
+ part thereof, to be licensed as a whole at no charge to all third
+ parties under the terms of this License.
+
+ c) If the modified program normally reads commands interactively
+ when run, you must cause it, when started running for such
+ interactive use in the most ordinary way, to print or display an
+ announcement including an appropriate copyright notice and a
+ notice that there is no warranty (or else, saying that you provide
+ a warranty) and that users may redistribute the program under
+ these conditions, and telling the user how to view a copy of this
+ License. (Exception: if the Program itself is interactive but
+ does not normally print such an announcement, your work based on
+ the Program is not required to print an announcement.)
+
+These requirements apply to the modified work as a whole. If
+identifiable sections of that work are not derived from the Program,
+and can be reasonably considered independent and separate works in
+themselves, then this License, and its terms, do not apply to those
+sections when you distribute them as separate works. But when you
+distribute the same sections as part of a whole which is a work based
+on the Program, the distribution of the whole must be on the terms of
+this License, whose permissions for other licensees extend to the
+entire whole, and thus to each and every part regardless of who wrote it.
+
+Thus, it is not the intent of this section to claim rights or contest
+your rights to work written entirely by you; rather, the intent is to
+exercise the right to control the distribution of derivative or
+collective works based on the Program.
+
+In addition, mere aggregation of another work not based on the Program
+with the Program (or with a work based on the Program) on a volume of
+a storage or distribution medium does not bring the other work under
+the scope of this License.
+
+ 3. You may copy and distribute the Program (or a work based on it,
+under Section 2) in object code or executable form under the terms of
+Sections 1 and 2 above provided that you also do one of the following:
+
+ a) Accompany it with the complete corresponding machine-readable
+ source code, which must be distributed under the terms of Sections
+ 1 and 2 above on a medium customarily used for software interchange; or,
+
+ b) Accompany it with a written offer, valid for at least three
+ years, to give any third party, for a charge no more than your
+ cost of physically performing source distribution, a complete
+ machine-readable copy of the corresponding source code, to be
+ distributed under the terms of Sections 1 and 2 above on a medium
+ customarily used for software interchange; or,
+
+ c) Accompany it with the information you received as to the offer
+ to distribute corresponding source code. (This alternative is
+ allowed only for noncommercial distribution and only if you
+ received the program in object code or executable form with such
+ an offer, in accord with Subsection b above.)
+
+The source code for a work means the preferred form of the work for
+making modifications to it. For an executable work, complete source
+code means all the source code for all modules it contains, plus any
+associated interface definition files, plus the scripts used to
+control compilation and installation of the executable. However, as a
+special exception, the source code distributed need not include
+anything that is normally distributed (in either source or binary
+form) with the major components (compiler, kernel, and so on) of the
+operating system on which the executable runs, unless that component
+itself accompanies the executable.
+
+If distribution of executable or object code is made by offering
+access to copy from a designated place, then offering equivalent
+access to copy the source code from the same place counts as
+distribution of the source code, even though third parties are not
+compelled to copy the source along with the object code.
+
+ 4. You may not copy, modify, sublicense, or distribute the Program
+except as expressly provided under this License. Any attempt
+otherwise to copy, modify, sublicense or distribute the Program is
+void, and will automatically terminate your rights under this License.
+However, parties who have received copies, or rights, from you under
+this License will not have their licenses terminated so long as such
+parties remain in full compliance.
+
+ 5. You are not required to accept this License, since you have not
+signed it. However, nothing else grants you permission to modify or
+distribute the Program or its derivative works. These actions are
+prohibited by law if you do not accept this License. Therefore, by
+modifying or distributing the Program (or any work based on the
+Program), you indicate your acceptance of this License to do so, and
+all its terms and conditions for copying, distributing or modifying
+the Program or works based on it.
+
+ 6. Each time you redistribute the Program (or any work based on the
+Program), the recipient automatically receives a license from the
+original licensor to copy, distribute or modify the Program subject to
+these terms and conditions. You may not impose any further
+restrictions on the recipients' exercise of the rights granted herein.
+You are not responsible for enforcing compliance by third parties to
+this License.
+
+ 7. If, as a consequence of a court judgment or allegation of patent
+infringement or for any other reason (not limited to patent issues),
+conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License. If you cannot
+distribute so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you
+may not distribute the Program at all. For example, if a patent
+license would not permit royalty-free redistribution of the Program by
+all those who receive copies directly or indirectly through you, then
+the only way you could satisfy both it and this License would be to
+refrain entirely from distribution of the Program.
+
+If any portion of this section is held invalid or unenforceable under
+any particular circumstance, the balance of the section is intended to
+apply and the section as a whole is intended to apply in other
+circumstances.
+
+It is not the purpose of this section to induce you to infringe any
+patents or other property right claims or to contest validity of any
+such claims; this section has the sole purpose of protecting the
+integrity of the free software distribution system, which is
+implemented by public license practices. Many people have made
+generous contributions to the wide range of software distributed
+through that system in reliance on consistent application of that
+system; it is up to the author/donor to decide if he or she is willing
+to distribute software through any other system and a licensee cannot
+impose that choice.
+
+This section is intended to make thoroughly clear what is believed to
+be a consequence of the rest of this License.
+
+ 8. If the distribution and/or use of the Program is restricted in
+certain countries either by patents or by copyrighted interfaces, the
+original copyright holder who places the Program under this License
+may add an explicit geographical distribution limitation excluding
+those countries, so that distribution is permitted only in or among
+countries not thus excluded. In such case, this License incorporates
+the limitation as if written in the body of this License.
+
+ 9. The Free Software Foundation may publish revised and/or new versions
+of the General Public License from time to time. Such new versions will
+be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+Each version is given a distinguishing version number. If the Program
+specifies a version number of this License which applies to it and "any
+later version", you have the option of following the terms and conditions
+either of that version or of any later version published by the Free
+Software Foundation. If the Program does not specify a version number of
+this License, you may choose any version ever published by the Free Software
+Foundation.
+
+ 10. If you wish to incorporate parts of the Program into other free
+programs whose distribution conditions are different, write to the author
+to ask for permission. For software which is copyrighted by the Free
+Software Foundation, write to the Free Software Foundation; we sometimes
+make exceptions for this. Our decision will be guided by the two goals
+of preserving the free status of all derivatives of our free software and
+of promoting the sharing and reuse of software generally.
+
+ NO WARRANTY
+
+ 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
+FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
+OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
+PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
+OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
+TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
+PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
+REPAIR OR CORRECTION.
+
+ 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
+REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
+INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
+OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
+TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
+YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGES.
+
+ END OF TERMS AND CONDITIONS
+
+ How to Apply These Terms to Your New Programs
+
+ If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+ To do so, attach the following notices to the program. It is safest
+to attach them to the start of each source file to most effectively
+convey the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+ {description}
+ Copyright (C) {year} {fullname}
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+
+Also add information on how to contact you by electronic and paper mail.
+
+If the program is interactive, make it output a short notice like this
+when it starts in an interactive mode:
+
+ Gnomovision version 69, Copyright (C) year name of author
+ Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+ This is free software, and you are welcome to redistribute it
+ under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License. Of course, the commands you use may
+be called something other than `show w' and `show c'; they could even be
+mouse-clicks or menu items--whatever suits your program.
+
+You should also get your employer (if you work as a programmer) or your
+school, if any, to sign a "copyright disclaimer" for the program, if
+necessary. Here is a sample; alter the names:
+
+ Yoyodyne, Inc., hereby disclaims all copyright interest in the program
+ `Gnomovision' (which makes passes at compilers) written by James Hacker.
+
+ {signature of Ty Coon}, 1 April 1989
+ Ty Coon, President of Vice
+
+This General Public License does not permit incorporating your program into
+proprietary programs. If your program is a subroutine library, you may
+consider it more useful to permit linking proprietary applications with the
+library. If this is what you want to do, use the GNU Lesser General
+Public License instead of this License.
diff --git a/drivers/mtd/mtdrw/Makefile b/drivers/mtd/mtdrw/Makefile
new file mode 100644
index 000000000000..d1061ccf3a67
--- /dev/null
+++ b/drivers/mtd/mtdrw/Makefile
@@ -0,0 +1,15 @@
+# Build module only if kernel supports MTD
+ifdef CONFIG_MTD
+obj-m += mtd-rw.o
+endif
+
+KDIR ?= /lib/modules/$(shell uname -r)/build
+
+modules:
+ $(MAKE) -C $(KDIR) M=$$PWD modules
+
+modules_install:
+ $(MAKE) -C $(KDIR) M=$$PWD modules_install
+
+clean:
+ $(MAKE) -C $(KDIR) M=$$PWD clean
diff --git a/drivers/mtd/mtdrw/README.md b/drivers/mtd/mtdrw/README.md
new file mode 100644
index 000000000000..dc3b08894ae5
--- /dev/null
+++ b/drivers/mtd/mtdrw/README.md
@@ -0,0 +1,25 @@
+mtd-rw - Write-enabler for MTD partitions
+=========================================
+
+Sets the `MTD_WRITEABLE` flag on all MTD partitions that are marked readonly.
+When unloading, read-only partitions will be restored. This module is intended
+for embedded devices where the mtd partition layout may be hard-coded in the
+firmware. If, for some reason, you DO have to write to a read-only partition
+(which is often a bad idea), this module is the way to go.
+
+The module is currently limited to the first 64 partitions, but this
+should suffice for most purposes.
+
+Inspired by dougg3@electronics.stackexchange.com:
+https://electronics.stackexchange.com/a/116133/97342
+
+Usage:
+```
+# insmod mtd-rw.ko i_want_a_brick=1
+# dmesg | grep mtd-rw
+[52997.620000] mtd-rw: mtd0: setting writeable flag
+[52997.630000] mtd-rw: mtd1: setting writeable flag
+[52997.640000] mtd-rw: mtd3: setting writeable flag
+[52997.650000] mtd-rw: mtd4: setting writeable flag
+[52997.660000] mtd-rw: mtd6: setting writeable flag
+```
diff --git a/drivers/mtd/mtdrw/mtd-rw.c b/drivers/mtd/mtdrw/mtd-rw.c
new file mode 100644
index 000000000000..706714d3db77
--- /dev/null
+++ b/drivers/mtd/mtdrw/mtd-rw.c
@@ -0,0 +1,132 @@
+/*
+ * mtd-rw - Make all MTD partitions writeable.
+ *
+ * Copyright (C) 2016 Joseph C. Lehner <joseph.c.lehner@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.
+ * If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mtd/mtd.h>
+#include <linux/err.h>
+
+/*
+ * This module is intended for embedded devices where the mtd partition
+ * layout may be hard-coded in the firmware. If, for some reason, you
+ * DO have to write to a read-only partition (which is often a bad idea),
+ * this module is the way to go.
+ *
+ * The module is currently limited to the first 64 partitions, but this
+ * should suffice for most purposes.
+ *
+ * Inspired by dougg3@electronics.stackexchange.com:
+ * https://electronics.stackexchange.com/a/116133/97342
+ */
+
+#ifndef MODULE
+#error "Must be compiled as a module."
+#endif
+
+#define MOD_WARNING KERN_WARNING "mtd-rw: "
+#define MOD_INFO KERN_INFO "mtd-rw: "
+#define MOD_ERR KERN_ERR "mtd-rw: "
+
+#define MTD_MAX (8 * sizeof(unlocked))
+
+static uint64_t unlocked = 0;
+static unsigned mtd_last = 0;
+
+static bool i_want_a_brick = false;
+module_param(i_want_a_brick, bool, S_IRUGO);
+MODULE_PARM_DESC(i_want_a_brick, "Make all partitions writeable");
+
+static int set_writeable(unsigned n, bool w)
+{
+ struct mtd_info *mtd = get_mtd_device(NULL, n);
+ int err;
+
+ if (IS_ERR(mtd)) {
+ if (PTR_ERR(mtd) != -ENODEV || !w) {
+ printk(MOD_ERR "mtd%d: error %ld\n", n, PTR_ERR(mtd));
+ }
+ return PTR_ERR(mtd);
+ }
+
+ err = -EEXIST;
+
+ if (w && !(mtd->flags & MTD_WRITEABLE)) {
+ printk(MOD_INFO "mtd%d: setting writeable flag\n", n);
+ mtd->flags |= MTD_WRITEABLE;
+ err = 0;
+ } else if (!w && (mtd->flags & MTD_WRITEABLE)) {
+ printk(MOD_INFO "mtd%d: clearing writeable flag\n", n);
+ mtd->flags &= ~MTD_WRITEABLE;
+ err = 0;
+ }
+
+ put_mtd_device(mtd);
+ return err;
+}
+
+static int __init mtd_rw_init(void)
+{
+ int i, err;
+
+ if (!i_want_a_brick) {
+ printk(MOD_ERR "must specify i_want_a_brick=1 to continue\n");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < MTD_MAX; ++i) {
+ err = set_writeable(i, true);
+ if (!err) {
+ unlocked |= (1 << i);
+ } else if (err == -ENODEV) {
+ break;
+ }
+ }
+
+ if (i == MTD_MAX) {
+ printk(MOD_WARNING "partitions beyond mtd%d are ignored\n", i - 1);
+ }
+
+ if (!unlocked) {
+ printk(MOD_INFO "no partitions to unlock\n");
+ return -ENODEV;
+ }
+
+ mtd_last = i;
+
+ return 0;
+}
+
+static void __exit mtd_rw_exit(void)
+{
+ unsigned i;
+
+ for (i = 0; i < mtd_last; ++i) {
+ if (unlocked & (1 << i)) {
+ set_writeable(i, false);
+ }
+ }
+}
+
+module_init(mtd_rw_init);
+module_exit(mtd_rw_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Joseph C. Lehner <joseph.c.lehner@gmail.com>");
+MODULE_DESCRIPTION("Write-enabler for MTD partitions");
+MODULE_VERSION("1");
--
2.30.2

56
patch/kernel/archive/filogic-6.16/patches.armbian/0049-arm64-dts-add-usxgmii-pcs-and-link-both-pcs.patch Normal file
View File

@ -0,0 +1,56 @@
From 2141bb55b2e6e0ce036206ada409d588588ed8ef Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Thu, 1 May 2025 19:46:37 +0200
Subject: [PATCH 49/84] arm64: dts: add usxgmii pcs and link both pcs
---
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
index 88f201ad78cf..bbe088ea620f 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
@@ -315,6 +315,24 @@ sgmiipcs1: pcs {
};
};
+ usxgmiisys0: pcs@10080000 {
+ compatible = "mediatek,mt7988-usxgmiisys";
+ reg = <0 0x10080000 0 0x1000>;
+ resets = <&watchdog 12>;
+ clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>;
+ phys = <&xfi_tphy0>;
+ #pcs-cells = <0>;
+ };
+
+ usxgmiisys1: pcs@10081000 {
+ compatible = "mediatek,mt7988-usxgmiisys";
+ reg = <0 0x10081000 0 0x1000>;
+ resets = <&watchdog 13>;
+ clocks = <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>;
+ phys = <&xfi_tphy1>;
+ #pcs-cells = <0>;
+ };
+
mcusys: mcusys@100e0000 {
compatible = "mediatek,mt7988-mcusys", "syscon";
reg = <0 0x100e0000 0 0x1000>;
@@ -1020,12 +1038,14 @@ gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
status = "disabled";
+ pcs-handle = <&sgmiipcs1>, <&usxgmiisys1>;
};
gmac2: mac@2 {
compatible = "mediatek,eth-mac";
reg = <2>;
status = "disabled";
+ pcs-handle = <&sgmiipcs0>, <&usxgmiisys0>;
};
mdio_bus: mdio-bus {
--
2.30.2

142
patch/kernel/archive/filogic-6.16/patches.armbian/0050-arm64-dts-update-bpi-r4.dtsi-to-actual-state.patch Normal file
View File

@ -0,0 +1,142 @@
From 6c08db21a2f0d37c9ffeba6c327aff67e3be28da Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Sun, 3 Nov 2024 11:18:31 +0100
Subject: [PATCH 50/84] arm64: dts: update bpi-r4.dtsi to actual state
---
.../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 1 +
.../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 40 +++++++++++++++++--
2 files changed, 38 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
index 4b3796ba82e3..499f0c91c213 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts
@@ -27,6 +27,7 @@ &gmac1 {
managed = "in-band-status";
phy-mode = "usxgmii";
sfp = <&sfp2>;
+ status = "okay";
};
&pca9545 {
diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
index 38e27ef6bc0c..a614729e9e47 100644
--- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi
@@ -3,6 +3,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
#include <dt-bindings/leds/common.h>
@@ -13,10 +14,20 @@ aliases {
ethernet0 = &gmac0;
ethernet1 = &gmac1;
ethernet2 = &gmac2;
+ led-boot = &led_green;
+ led-failsafe = &led_green;
+ led-running = &led_green;
+ led-upgrade = &led_green;
};
chosen {
stdout-path = "serial0:115200n8";
+ bootargs = "loglevel=8 pci=pcie_bus_perf ubi.block=0,fit root=/dev/fit0";
+ rootdisk-spim-nand = <&ubi_rootfs>;
+ };
+
+ memory {
+ reg = <0x00 0x40000000 0x00 0x10000000>;
};
fan: pwm-fan {
@@ -28,6 +39,16 @@ fan: pwm-fan {
status = "okay";
};
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ wps {
+ label = "WPS";
+ linux,code = <KEY_RESTART>;
+ gpios = <&pio 14 GPIO_ACTIVE_LOW>;
+ };
+ };
+
gpio-leds {
compatible = "gpio-leds";
@@ -151,6 +172,7 @@ &gmac2 {
managed = "in-band-status";
phy-mode = "usxgmii";
sfp = <&sfp1>;
+ status = "okay";
};
&gsw_phy0 {
@@ -280,7 +302,7 @@ pca9545: i2c-mux@70 {
#address-cells = <1>;
#size-cells = <0>;
- i2c@0 {
+ i2c@0 { //eeprom,rtc,ngff
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
@@ -288,12 +310,16 @@ i2c@0 {
pcf8563: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
+ //interrupts = <&pio 6 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <0>;
+ //status = "disabled";
};
eeprom@57 {
compatible = "atmel,24c02";
reg = <0x57>;
+ address-bits = <8>;
+ page-size = <8>;
size = <256>;
};
@@ -304,6 +330,14 @@ i2c_sfp1: i2c@1 {
#size-cells = <0>;
reg = <1>;
};
+
+ i2c_wifi: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ status = "disabled";
+ };
};
};
@@ -455,7 +489,7 @@ partition@200000 {
reg = <0x200000 0x7e00000>;
compatible = "linux,ubi";
- /*volumes {
+ volumes {
ubi-volume-fip {
volname = "fip";
};
@@ -477,7 +511,7 @@ nvmem-layout {
ubi_rootfs: ubi-volume-rootfs {
volname = "rootfs";
};
- };*/
+ };
};
};
};
--
2.30.2

578
patch/kernel/archive/filogic-6.16/patches.armbian/0051-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch Normal file
View File

@ -0,0 +1,578 @@
From 2130ea2c451f40a26214c6702ea8230dd6da2044 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Tue, 12 Dec 2023 03:51:14 +0000
Subject: [PATCH 51/84] net: ethernet: mtk_eth_soc: add paths and SerDes modes
for MT7988
MT7988 comes with two SerDes interfaces to connect external PHYs or
transceivers in USXGMII, 10GBase-R, 5GBase-R, 2500Base-X, 1000Base-X and
Cisco SGMII interface modes.
Implement support for configuring for the new paths to SerDes interfaces.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/net/ethernet/mediatek/mtk_eth_path.c | 81 +++++++++-
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 149 +++++++++++++++----
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 48 +++++-
3 files changed, 238 insertions(+), 40 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_path.c b/drivers/net/ethernet/mediatek/mtk_eth_path.c
index b4c01e2878f6..249b2fe7c10d 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
@@ -35,8 +35,16 @@ static const char *mtk_eth_path_name(u64 path)
return "gmac2_2p5gphy";
case MTK_ETH_PATH_GMAC2_GEPHY:
return "gmac2_gephy";
+ case MTK_ETH_PATH_GMAC3_SGMII:
+ return "gmac3_sgmii";
case MTK_ETH_PATH_GDM1_ESW:
return "gdm1_esw";
+ case MTK_ETH_PATH_GMAC1_USXGMII:
+ return "gmac1_usxgmii";
+ case MTK_ETH_PATH_GMAC2_USXGMII:
+ return "gmac2_usxgmii";
+ case MTK_ETH_PATH_GMAC3_USXGMII:
+ return "gmac3_usxgmii";
default:
return "unknown path";
}
@@ -190,7 +198,48 @@ static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, u64 path)
return 0;
}
-static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, u64 path)
+static int set_mux_gmac123_to_usxgmii(struct mtk_eth *eth, u64 path)
+{
+ unsigned int val = 0;
+ bool updated = true;
+ int mac_id = 0;
+
+ /* Disable SYSCFG1 SGMII */
+ regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
+
+ switch (path) {
+ case MTK_ETH_PATH_GMAC1_USXGMII:
+ val &= ~(u32)SYSCFG0_SGMII_GMAC1_V2;
+ mac_id = MTK_GMAC1_ID;
+ break;
+ case MTK_ETH_PATH_GMAC2_USXGMII:
+ val &= ~(u32)SYSCFG0_SGMII_GMAC2_V2;
+ mac_id = MTK_GMAC2_ID;
+ break;
+ case MTK_ETH_PATH_GMAC3_USXGMII:
+ val &= ~(u32)SYSCFG0_SGMII_GMAC3_V2;
+ mac_id = MTK_GMAC3_ID;
+ break;
+ default:
+ updated = false;
+ };
+
+ if (updated) {
+ regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
+ SYSCFG0_SGMII_MASK, val);
+
+ if (mac_id == MTK_GMAC2_ID)
+ regmap_set_bits(eth->infra, TOP_MISC_NETSYS_PCS_MUX,
+ MUX_G2_USXGMII_SEL);
+ }
+
+ dev_dbg(eth->dev, "path %s in %s updated = %d\n",
+ mtk_eth_path_name(path), __func__, updated);
+
+ return 0;
+}
+
+static int set_mux_gmac123_to_gephy_sgmii(struct mtk_eth *eth, u64 path)
{
unsigned int val = 0;
bool updated = true;
@@ -207,6 +256,9 @@ static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, u64 path)
case MTK_ETH_PATH_GMAC2_SGMII:
val |= SYSCFG0_SGMII_GMAC2_V2;
break;
+ case MTK_ETH_PATH_GMAC3_SGMII:
+ val |= SYSCFG0_SGMII_GMAC3_V2;
+ break;
default:
updated = false;
}
@@ -245,7 +297,15 @@ static const struct mtk_eth_muxc mtk_eth_muxc[] = {
}, {
.name = "mux_gmac12_to_gephy_sgmii",
.cap_bit = MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII,
- .set_path = set_mux_gmac12_to_gephy_sgmii,
+ .set_path = set_mux_gmac123_to_gephy_sgmii,
+ }, {
+ .name = "mux_gmac123_to_gephy_sgmii",
+ .cap_bit = MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII,
+ .set_path = set_mux_gmac123_to_gephy_sgmii,
+ }, {
+ .name = "mux_gmac123_to_usxgmii",
+ .cap_bit = MTK_ETH_MUX_GMAC123_TO_USXGMII,
+ .set_path = set_mux_gmac123_to_usxgmii,
},
};
@@ -278,12 +338,25 @@ static int mtk_eth_mux_setup(struct mtk_eth *eth, u64 path)
return err;
}
+int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id)
+{
+ u64 path;
+
+ path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_USXGMII :
+ (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_USXGMII :
+ MTK_ETH_PATH_GMAC3_USXGMII;
+
+ /* Setup proper MUXes along the path */
+ return mtk_eth_mux_setup(eth, path);
+}
+
int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id)
{
u64 path;
- path = (mac_id == 0) ? MTK_ETH_PATH_GMAC1_SGMII :
- MTK_ETH_PATH_GMAC2_SGMII;
+ path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_SGMII :
+ (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_SGMII :
+ MTK_ETH_PATH_GMAC3_SGMII;
/* Setup proper MUXes along the path */
return mtk_eth_mux_setup(eth, path);
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 7916c99d5ebb..ac7250003b1d 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -22,6 +22,8 @@
#include <linux/pinctrl/devinfo.h>
#include <linux/phylink.h>
#include <linux/pcs/pcs-mtk-lynxi.h>
+#include <linux/pcs/pcs.h>
+#include <linux/phy/phy.h>
#include <linux/jhash.h>
#include <linux/bitfield.h>
#include <net/dsa.h>
@@ -514,23 +516,28 @@ static void mtk_setup_bridge_switch(struct mtk_eth *eth)
MTK_GSW_CFG);
}
-static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
- phy_interface_t interface)
+static bool mtk_check_gmac23_idle(struct mtk_mac *mac)
{
- struct mtk_mac *mac = container_of(config, struct mtk_mac,
- phylink_config);
- struct mtk_eth *eth = mac->hw;
- unsigned int sid;
+ u32 mac_fsm, gdm_fsm;
- if (interface == PHY_INTERFACE_MODE_SGMII ||
- phy_interface_mode_is_8023z(interface)) {
- sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
- 0 : mac->id;
+ mac_fsm = mtk_r32(mac->hw, MTK_MAC_FSM(mac->id));
- return eth->sgmii_pcs[sid];
- }
+ switch (mac->id) {
+ case MTK_GMAC2_ID:
+ gdm_fsm = mtk_r32(mac->hw, MTK_FE_GDM2_FSM);
+ break;
+ case MTK_GMAC3_ID:
+ gdm_fsm = mtk_r32(mac->hw, MTK_FE_GDM3_FSM);
+ break;
+ default:
+ return true;
+ };
- return NULL;
+ if ((mac_fsm & 0xFFFF0000) == 0x01010000 &&
+ (gdm_fsm & 0xFFFF0000) == 0x00000000)
+ return true;
+
+ return false;
}
static int mtk_mac_prepare(struct phylink_config *config, unsigned int mode,
@@ -593,6 +600,15 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
goto init_err;
}
break;
+ case PHY_INTERFACE_MODE_USXGMII:
+ case PHY_INTERFACE_MODE_10GBASER:
+ case PHY_INTERFACE_MODE_5GBASER:
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) {
+ err = mtk_gmac_usxgmii_path_setup(eth, mac->id);
+ if (err)
+ goto init_err;
+ }
+ break;
case PHY_INTERFACE_MODE_INTERNAL:
if (mac->id == MTK_GMAC2_ID &&
MTK_HAS_CAPS(eth->soc->caps, MTK_2P5GPHY)) {
@@ -646,8 +662,6 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
-
- mac->interface = state->interface;
}
/* SGMII */
@@ -664,9 +678,12 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
/* Save the syscfg0 value for mac_finish */
mac->syscfg0 = val;
- } else if (phylink_autoneg_inband(mode)) {
+ } else if (state->interface != PHY_INTERFACE_MODE_USXGMII &&
+ state->interface != PHY_INTERFACE_MODE_10GBASER &&
+ state->interface != PHY_INTERFACE_MODE_5GBASER &&
+ phylink_autoneg_inband(mode)) {
dev_err(eth->dev,
- "In-band mode not supported in non SGMII mode!\n");
+ "In-band mode not supported in non-SerDes modes!\n");
return;
}
@@ -677,8 +694,22 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
if (mac->id == MTK_GMAC1_ID)
mtk_setup_bridge_switch(eth);
+ } else if (mtk_is_netsys_v3_or_greater(eth)) {
+ mtk_w32(eth, 0, MTK_GDMA_EG_CTRL(mac->id));
+
+ /* FIXME: In current hardware design, we have to reset FE
+ * when swtiching XGDM to GDM. Therefore, here trigger an SER
+ * to let GDM go back to the initial state.
+ */
+ if ((mtk_interface_mode_is_xgmii(eth, mac->interface) ||
+ mac->interface == PHY_INTERFACE_MODE_NA) &&
+ !mtk_check_gmac23_idle(mac) &&
+ !test_bit(MTK_RESETTING, &eth->state))
+ schedule_work(&eth->pending_work);
}
+ mac->interface = state->interface;
+
return;
err_phy:
@@ -729,6 +760,9 @@ static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
mtk_m32(mac->hw,
MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK, 0,
MTK_MAC_MCR(mac->id));
+ if (mtk_is_netsys_v3_or_greater(mac->hw))
+ mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), 0,
+ MTK_XGMAC_STS(mac->id));
} else if (mac->id != MTK_GMAC1_ID) {
/* XGMAC except for built-in switch */
mtk_m32(mac->hw, XMAC_MCR_TRX_DISABLE, XMAC_MCR_TRX_DISABLE,
@@ -947,7 +981,6 @@ static int mtk_mac_enable_tx_lpi(struct phylink_config *config, u32 timer,
static const struct phylink_mac_ops mtk_phylink_ops = {
.mac_prepare = mtk_mac_prepare,
- .mac_select_pcs = mtk_mac_select_pcs,
.mac_config = mtk_mac_config,
.mac_finish = mtk_mac_finish,
.mac_link_down = mtk_mac_link_down,
@@ -4774,7 +4807,8 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
phy_interface_t phy_mode;
struct phylink *phylink;
struct mtk_mac *mac;
- int id, err;
+ int id, err, count;
+ unsigned int sid;
int txqs = 1;
u32 val;
@@ -4856,6 +4890,7 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
mac->phylink_config.lpi_capabilities = MAC_100FD | MAC_1000FD |
MAC_2500FD;
mac->phylink_config.lpi_timer_default = 1000;
+ mac->phylink_config.num_available_pcs = 0;
/* MT7623 gmac0 is now missing its speed-specific PLL configuration
* in its .mac_config method (since state->speed is not valid there.
@@ -4886,13 +4921,52 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) {
__set_bit(PHY_INTERFACE_MODE_SGMII,
- mac->phylink_config.supported_interfaces);
+ mac->phylink_config.pcs_interfaces);
__set_bit(PHY_INTERFACE_MODE_1000BASEX,
- mac->phylink_config.supported_interfaces);
+ mac->phylink_config.pcs_interfaces);
__set_bit(PHY_INTERFACE_MODE_2500BASEX,
- mac->phylink_config.supported_interfaces);
+ mac->phylink_config.pcs_interfaces);
+
+ if (mtk_is_netsys_v3_or_greater(mac->hw)) {
+ __set_bit(PHY_INTERFACE_MODE_5GBASER,
+ mac->phylink_config.pcs_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_10GBASER,
+ mac->phylink_config.pcs_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_USXGMII,
+ mac->phylink_config.pcs_interfaces);
+
+ err = fwnode_phylink_pcs_parse(of_fwnode_handle(np), NULL, &count);
+ if (err == -ENODEV) {
+ err = 0;
+ goto no_pcs;
+ }
+
+ if (count > 2)
+ err = -ENOMEM;
+
+ if (err)
+ goto free_netdev;
+
+ err = fwnode_phylink_pcs_parse(of_fwnode_handle(np), mac->available_pcs, &count);
+ if (err)
+ goto free_netdev;
+
+ mac->phylink_config.available_pcs = mac->available_pcs;
+ mac->phylink_config.num_available_pcs = count;
+ } else {
+ sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
+ 0 : id;
+
+ mac->phylink_config.available_pcs = &eth->sgmii_pcs[sid];
+ mac->phylink_config.num_available_pcs = 1;
+ }
+
+ phy_interface_or(mac->phylink_config.supported_interfaces,
+ mac->phylink_config.supported_interfaces,
+ mac->phylink_config.pcs_interfaces);
}
+no_pcs:
if (mtk_is_netsys_v3_or_greater(mac->hw) &&
MTK_HAS_CAPS(mac->hw->soc->caps, MTK_ESW) &&
id == MTK_GMAC1_ID) {
@@ -4902,18 +4976,16 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
phy_interface_zero(mac->phylink_config.supported_interfaces);
__set_bit(PHY_INTERFACE_MODE_INTERNAL,
mac->phylink_config.supported_interfaces);
+ } else if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_USXGMII)) {
+ mac->phylink_config.mac_capabilities |= MAC_5000FD | MAC_10000FD;
+ __set_bit(PHY_INTERFACE_MODE_5GBASER,
+ mac->phylink_config.supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_10GBASER,
+ mac->phylink_config.supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_USXGMII,
+ mac->phylink_config.supported_interfaces);
}
- phylink = phylink_create(&mac->phylink_config,
- of_fwnode_handle(mac->of_node),
- phy_mode, &mtk_phylink_ops);
- if (IS_ERR(phylink)) {
- err = PTR_ERR(phylink);
- goto free_netdev;
- }
-
- mac->phylink = phylink;
-
if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_2P5GPHY) &&
id == MTK_GMAC2_ID)
__set_bit(PHY_INTERFACE_MODE_INTERNAL,
@@ -4936,6 +5008,16 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
eth->netdev[id]->irq = eth->irq[MTK_FE_IRQ_SHARED];
eth->netdev[id]->dev.of_node = np;
+ phylink = phylink_create(&mac->phylink_config,
+ of_fwnode_handle(mac->of_node),
+ phy_mode, &mtk_phylink_ops);
+ if (IS_ERR(phylink)) {
+ err = PTR_ERR(phylink);
+ goto free_netdev;
+ }
+
+ mac->phylink = phylink;
+
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
else
@@ -5112,7 +5194,8 @@ static int mtk_probe(struct platform_device *pdev)
regmap_write(cci, 0, 3);
}
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII) &&
+ !mtk_is_netsys_v3_or_greater(eth)) {
err = mtk_sgmii_init(eth);
if (err)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 0168e2fbc619..88406e80dfec 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -15,6 +15,7 @@
#include <linux/u64_stats_sync.h>
#include <linux/refcount.h>
#include <linux/phylink.h>
+#include <linux/reset.h>
#include <linux/rhashtable.h>
#include <linux/dim.h>
#include <linux/bitfield.h>
@@ -567,6 +568,7 @@
#define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK)
#define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
#define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
+#define SYSCFG0_SGMII_GMAC3_V2 BIT(7)
/* ethernet subsystem clock register */
@@ -608,6 +610,7 @@
#define TOP_MISC_NETSYS_PCS_MUX 0x0
#define NETSYS_PCS_MUX_MASK GENMASK(1, 0)
#define MUX_G2_USXGMII_SEL BIT(1)
+#define MUX_HSGMII1_G1_SEL BIT(0)
#define USB_PHY_SWITCH_REG 0x218
#define QPHY_SEL_MASK GENMASK(1, 0)
@@ -633,6 +636,8 @@
#define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c)
#define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110)
+/* Debug Purpose Register */
+#define MTK_PSE_FQFC_CFG 0x100
#define MTK_FE_CDM1_FSM 0x220
#define MTK_FE_CDM2_FSM 0x224
#define MTK_FE_CDM3_FSM 0x238
@@ -641,6 +646,11 @@
#define MTK_FE_CDM6_FSM 0x328
#define MTK_FE_GDM1_FSM 0x228
#define MTK_FE_GDM2_FSM 0x22C
+#define MTK_FE_GDM3_FSM 0x23C
+#define MTK_FE_PSE_FREE 0x240
+#define MTK_FE_DROP_FQ 0x244
+#define MTK_FE_DROP_FC 0x248
+#define MTK_FE_DROP_PPE 0x24C
#define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100))
@@ -978,6 +988,7 @@ enum mkt_eth_capabilities {
MTK_RGMII_BIT = 0,
MTK_TRGMII_BIT,
MTK_SGMII_BIT,
+ MTK_USXGMII_BIT,
MTK_2P5GPHY_BIT,
MTK_ESW_BIT,
MTK_GEPHY_BIT,
@@ -1002,6 +1013,8 @@ enum mkt_eth_capabilities {
MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT,
MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
+ MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT,
+ MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT,
/* PATH BITS */
MTK_ETH_PATH_GMAC1_RGMII_BIT,
@@ -1011,13 +1024,18 @@ enum mkt_eth_capabilities {
MTK_ETH_PATH_GMAC2_SGMII_BIT,
MTK_ETH_PATH_GMAC2_2P5GPHY_BIT,
MTK_ETH_PATH_GMAC2_GEPHY_BIT,
+ MTK_ETH_PATH_GMAC3_SGMII_BIT,
MTK_ETH_PATH_GDM1_ESW_BIT,
+ MTK_ETH_PATH_GMAC1_USXGMII_BIT,
+ MTK_ETH_PATH_GMAC2_USXGMII_BIT,
+ MTK_ETH_PATH_GMAC3_USXGMII_BIT,
};
/* Supported hardware group on SoCs */
#define MTK_RGMII BIT_ULL(MTK_RGMII_BIT)
#define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT)
#define MTK_SGMII BIT_ULL(MTK_SGMII_BIT)
+#define MTK_USXGMII BIT_ULL(MTK_USXGMII_BIT)
#define MTK_2P5GPHY BIT_ULL(MTK_2P5GPHY_BIT)
#define MTK_ESW BIT_ULL(MTK_ESW_BIT)
#define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT)
@@ -1047,6 +1065,10 @@ enum mkt_eth_capabilities {
BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
#define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \
BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
+#define MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII \
+ BIT_ULL(MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT)
+#define MTK_ETH_MUX_GMAC123_TO_USXGMII \
+ BIT_ULL(MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT)
/* Supported path present on SoCs */
#define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT)
@@ -1056,7 +1078,11 @@ enum mkt_eth_capabilities {
#define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)
#define MTK_ETH_PATH_GMAC2_2P5GPHY BIT_ULL(MTK_ETH_PATH_GMAC2_2P5GPHY_BIT)
#define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
+#define MTK_ETH_PATH_GMAC3_SGMII BIT_ULL(MTK_ETH_PATH_GMAC3_SGMII_BIT)
#define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT)
+#define MTK_ETH_PATH_GMAC1_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC1_USXGMII_BIT)
+#define MTK_ETH_PATH_GMAC2_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC2_USXGMII_BIT)
+#define MTK_ETH_PATH_GMAC3_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC3_USXGMII_BIT)
#define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
@@ -1065,7 +1091,11 @@ enum mkt_eth_capabilities {
#define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
#define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
#define MTK_GMAC2_2P5GPHY (MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY)
+#define MTK_GMAC3_SGMII (MTK_ETH_PATH_GMAC3_SGMII | MTK_SGMII)
#define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW)
+#define MTK_GMAC1_USXGMII (MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII)
+#define MTK_GMAC2_USXGMII (MTK_ETH_PATH_GMAC2_USXGMII | MTK_USXGMII)
+#define MTK_GMAC3_USXGMII (MTK_ETH_PATH_GMAC3_USXGMII | MTK_USXGMII)
/* MUXes present on SoCs */
/* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
@@ -1092,6 +1122,12 @@ enum mkt_eth_capabilities {
#define MTK_MUX_GMAC12_TO_GEPHY_SGMII \
(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX)
+#define MTK_MUX_GMAC123_TO_GEPHY_SGMII \
+ (MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII | MTK_MUX)
+
+#define MTK_MUX_GMAC123_TO_USXGMII \
+ (MTK_ETH_MUX_GMAC123_TO_USXGMII | MTK_MUX | MTK_INFRA)
+
#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
@@ -1123,9 +1159,12 @@ enum mkt_eth_capabilities {
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
MTK_RSTCTRL_PPE1 | MTK_SRAM)
-#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_GMAC2_2P5GPHY | \
- MTK_MUX_GMAC2_TO_2P5GPHY | MTK_QDMA | MTK_RSTCTRL_PPE1 | \
- MTK_RSTCTRL_PPE2 | MTK_SRAM)
+#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_GMAC1_SGMII | \
+ MTK_GMAC2_2P5GPHY | MTK_GMAC2_SGMII | MTK_GMAC2_USXGMII | \
+ MTK_GMAC3_SGMII | MTK_GMAC3_USXGMII | \
+ MTK_MUX_GMAC123_TO_GEPHY_SGMII | \
+ MTK_MUX_GMAC123_TO_USXGMII | MTK_MUX_GMAC2_TO_2P5GPHY | \
+ MTK_QDMA | MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | MTK_SRAM)
struct mtk_tx_dma_desc_info {
dma_addr_t addr;
@@ -1372,6 +1411,8 @@ struct mtk_mac {
struct device_node *of_node;
struct phylink *phylink;
struct phylink_config phylink_config;
+ struct phylink_pcs *current_pcs;
+ struct phylink_pcs *available_pcs[2];
struct mtk_eth *hw;
struct mtk_hw_stats *hw_stats;
__be32 hwlro_ip[MTK_MAX_LRO_IP_CNT];
@@ -1506,6 +1547,7 @@ int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id);
int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
+int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id);
int mtk_eth_offload_init(struct mtk_eth *eth, u8 id);
int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,
--
2.30.2

108
patch/kernel/archive/filogic-6.16/patches.armbian/0052-net-phylink-keep-and-use-MAC-supported_interfaces-in.patch Normal file
View File

@ -0,0 +1,108 @@
From 7d9a25bf143c3edee1ad46a57ac64acc0c49316d Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Mon, 7 Apr 2025 00:13:55 +0200
Subject: [PATCH 52/84] net: phylink: keep and use MAC supported_interfaces in
phylink struct
Add in phylink struct a copy of supported_interfaces from phylink_config
and make use of that instead of relying on phylink_config value.
This in preparation for support of PCS handling internally to phylink
where a PCS can be removed or added after the phylink is created and we
need both a reference of the supported_interfaces value from
phylink_config and an internal value that can be updated with the new
PCS info.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/net/phy/phylink.c | 22 +++++++++++++++-------
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 229a503d601e..a0cfa49fe84c 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -59,6 +59,11 @@ struct phylink {
/* The link configuration settings */
struct phylink_link_state link_config;
+ /* What interface are supported by the current link.
+ * Can change on removal or addition of new PCS.
+ */
+ DECLARE_PHY_INTERFACE_MASK(supported_interfaces);
+
/* The current settings */
phy_interface_t cur_interface;
@@ -612,7 +617,7 @@ static int phylink_validate_mask(struct phylink *pl, struct phy_device *phy,
static int phylink_validate(struct phylink *pl, unsigned long *supported,
struct phylink_link_state *state)
{
- const unsigned long *interfaces = pl->config->supported_interfaces;
+ const unsigned long *interfaces = pl->supported_interfaces;
if (state->interface == PHY_INTERFACE_MODE_NA)
return phylink_validate_mask(pl, NULL, supported, state,
@@ -1825,6 +1830,9 @@ struct phylink *phylink_create(struct phylink_config *config,
mutex_init(&pl->state_mutex);
INIT_WORK(&pl->resolve, phylink_resolve);
+ phy_interface_copy(pl->supported_interfaces,
+ config->supported_interfaces);
+
pl->config = config;
if (config->type == PHYLINK_NETDEV) {
pl->netdev = to_net_dev(config->dev);
@@ -1983,7 +1991,7 @@ static int phylink_validate_phy(struct phylink *pl, struct phy_device *phy,
* those which the host supports.
*/
phy_interface_and(interfaces, phy->possible_interfaces,
- pl->config->supported_interfaces);
+ pl->supported_interfaces);
if (phy_interface_empty(interfaces)) {
phylink_err(pl, "PHY has no common interfaces\n");
@@ -2706,12 +2714,12 @@ static phy_interface_t phylink_sfp_select_interface(struct phylink *pl,
return interface;
}
- if (!test_bit(interface, pl->config->supported_interfaces)) {
+ if (!test_bit(interface, pl->supported_interfaces)) {
phylink_err(pl,
"selection of interface failed, SFP selected %s (%u) but MAC supports %*pbl\n",
phy_modes(interface), interface,
(int)PHY_INTERFACE_MODE_MAX,
- pl->config->supported_interfaces);
+ pl->supported_interfaces);
return PHY_INTERFACE_MODE_NA;
}
@@ -3598,14 +3606,14 @@ static int phylink_sfp_config_optical(struct phylink *pl)
phylink_dbg(pl, "optical SFP: interfaces=[mac=%*pbl, sfp=%*pbl]\n",
(int)PHY_INTERFACE_MODE_MAX,
- pl->config->supported_interfaces,
+ pl->supported_interfaces,
(int)PHY_INTERFACE_MODE_MAX,
pl->sfp_interfaces);
/* Find the union of the supported interfaces by the PCS/MAC and
* the SFP module.
*/
- phy_interface_and(interfaces, pl->config->supported_interfaces,
+ phy_interface_and(interfaces, pl->supported_interfaces,
pl->sfp_interfaces);
if (phy_interface_empty(interfaces)) {
phylink_err(pl, "unsupported SFP module: no common interface modes\n");
@@ -3751,7 +3759,7 @@ static int phylink_sfp_connect_phy(void *upstream, struct phy_device *phy)
/* Set the PHY's host supported interfaces */
phy_interface_and(phy->host_interfaces, phylink_sfp_interfaces,
- pl->config->supported_interfaces);
+ pl->supported_interfaces);
/* Do the initial configuration */
return phylink_sfp_config_phy(pl, phy);
--
2.30.2

36
patch/kernel/archive/filogic-6.16/patches.armbian/0053-net-phy-introduce-phy_interface_copy-helper.patch Normal file
View File

@ -0,0 +1,36 @@
From 8ba5b5a70e5c337ecbb42de895dc06c50f129de3 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Mon, 7 Apr 2025 00:13:56 +0200
Subject: [PATCH 53/84] net: phy: introduce phy_interface_copy helper
Introduce phy_interface_copy helper as a shorthand to copy the PHY
interface bitmap to a different location.
This is useful if a PHY interface bitmap needs to be stored in a
different variable and needs to be reset to an original value saved in a
different bitmap.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
include/linux/phy.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/linux/phy.h b/include/linux/phy.h
index e194dad1623d..6e09b2290726 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -173,6 +173,11 @@ static inline void phy_interface_or(unsigned long *dst, const unsigned long *a,
bitmap_or(dst, a, b, PHY_INTERFACE_MODE_MAX);
}
+static inline void phy_interface_copy(unsigned long *dst, const unsigned long *src)
+{
+ bitmap_copy(dst, src, PHY_INTERFACE_MODE_MAX);
+}
+
static inline void phy_interface_set_rgmii(unsigned long *intf)
{
__set_bit(PHY_INTERFACE_MODE_RGMII, intf);
--
2.30.2

388
patch/kernel/archive/filogic-6.16/patches.armbian/0054-net-phylink-introduce-internal-phylink-PCS-handling.patch Normal file
View File

@ -0,0 +1,388 @@
From 5515ca927f396489c7bc2224289777e60295e0f0 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Mon, 7 Apr 2025 00:13:57 +0200
Subject: [PATCH 54/84] net: phylink: introduce internal phylink PCS handling
Introduce internal handling of PCS for phylink. This is an alternative
to .mac_select_pcs that moves the selection logic of the PCS entirely to
phylink with the usage of supported_interface value in the PCS struct.
MAC should now provide an array of available PCS in phylink_config in
.available_pcs and fill the .num_available_pcs with the number of
elements in the array. MAC should also define a new bitmap,
pcs_interfaces, in phylink_config to define for what interface mode a
dedicated PCS is required.
On phylink_create() this array is parsed and a linked list of PCS is
created based on the PCS passed in phylink_config.
Also the supported_interface value in phylink struct is updated with the
new supported_interface from the provided PCS.
On phylink_start() every PCS in phylink PCS list gets attached to the
phylink instance. This is done by setting the phylink value in
phylink_pcs struct to the phylink instance.
On phylink_stop(), every PCS in phylink PCS list is detached from the
phylink instance. This is done by setting the phylink value in
phylink_pcs struct to NULL.
On phylink_stop(), every PCS in phylink PCS list is removed from the
list.
phylink_validate_mac_and_pcs(), phylink_major_config() and
phylink_inband_caps() are updated to support this new implementation
with the PCS list stored in phylink.
They will make use of phylink_validate_pcs_interface() that will loop
for every PCS in the phylink PCS available list and find one that supports
the passed interface.
phylink_validate_pcs_interface() apply the same logic of .mac_select_pcs
where if a supported_interface value is not set for the PCS struct, then
it's assumed every interface is supported.
It's required for a MAC that implement either a .mac_select_pcs or make
use of the PCS list implementation. Implementing both will result in a fail
on MAC/PCS validation.
phylink value in phylink_pcs struct with this implementation is used to
track from PCS side when it's attached to a phylink instance. PCS driver
will make use of this information to correctly detach from a phylink
instance if needed.
The .mac_select_pcs implementation is not changed but it's expected that
every MAC driver migrates to the new implementation to later deprecate
and remove .mac_select_pcs.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/net/phy/phylink.c | 147 +++++++++++++++++++++++++++++++++-----
include/linux/phylink.h | 10 +++
2 files changed, 139 insertions(+), 18 deletions(-)
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index a0cfa49fe84c..8539519536b2 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -59,6 +59,9 @@ struct phylink {
/* The link configuration settings */
struct phylink_link_state link_config;
+ /* List of available PCS */
+ struct list_head pcs_list;
+
/* What interface are supported by the current link.
* Can change on removal or addition of new PCS.
*/
@@ -146,6 +149,8 @@ static const phy_interface_t phylink_sfp_interface_preference[] = {
static DECLARE_PHY_INTERFACE_MASK(phylink_sfp_interfaces);
+static void phylink_run_resolve(struct phylink *pl);
+
/**
* phylink_set_port_modes() - set the port type modes in the ethtool mask
* @mask: ethtool link mode mask
@@ -501,22 +506,59 @@ static void phylink_validate_mask_caps(unsigned long *supported,
linkmode_and(state->advertising, state->advertising, mask);
}
+static int phylink_validate_pcs_interface(struct phylink_pcs *pcs,
+ phy_interface_t interface)
+{
+ /* If PCS define an empty supported_interfaces value, assume
+ * all interface are supported.
+ */
+ if (phy_interface_empty(pcs->supported_interfaces))
+ return 0;
+
+ /* Ensure that this PCS supports the interface mode */
+ if (!test_bit(interface, pcs->supported_interfaces))
+ return -EINVAL;
+
+ return 0;
+}
+
static int phylink_validate_mac_and_pcs(struct phylink *pl,
unsigned long *supported,
struct phylink_link_state *state)
{
- struct phylink_pcs *pcs = NULL;
unsigned long capabilities;
+ struct phylink_pcs *pcs;
+ bool pcs_found = false;
int ret;
/* Get the PCS for this interface mode */
if (pl->mac_ops->mac_select_pcs) {
+ /* Make sure either PCS internal validation or .mac_select_pcs
+ * is used. Return error if both are defined.
+ */
+ if (!list_empty(&pl->pcs_list)) {
+ phylink_err(pl, "either phylink_pcs_add() or .mac_select_pcs must be used\n");
+ return -EINVAL;
+ }
+
pcs = pl->mac_ops->mac_select_pcs(pl->config, state->interface);
if (IS_ERR(pcs))
return PTR_ERR(pcs);
+
+ pcs_found = !!pcs;
+ } else {
+ /* Check every assigned PCS and search for one that supports
+ * the interface.
+ */
+ list_for_each_entry(pcs, &pl->pcs_list, list) {
+ if (!phylink_validate_pcs_interface(pcs, state->interface)) {
+ pcs_found = true;
+ break;
+ }
+ }
}
- if (pcs) {
+ if (pcs_found) {
/* The PCS, if present, must be setup before phylink_create()
* has been called. If the ops is not initialised, print an
* error and backtrace rather than oopsing the kernel.
@@ -528,13 +570,10 @@ static int phylink_validate_mac_and_pcs(struct phylink *pl,
return -EINVAL;
}
- /* Ensure that this PCS supports the interface which the MAC
- * returned it for. It is an error for the MAC to return a PCS
- * that does not support the interface mode.
- */
- if (!phy_interface_empty(pcs->supported_interfaces) &&
- !test_bit(state->interface, pcs->supported_interfaces)) {
- phylink_err(pl, "MAC returned PCS which does not support %s\n",
+ /* Recheck PCS to handle legacy way for .mac_select_pcs */
+ ret = phylink_validate_pcs_interface(pcs, state->interface);
+ if (ret) {
+ phylink_err(pl, "selected PCS does not support %s\n",
phy_modes(state->interface));
return -EINVAL;
}
@@ -939,12 +978,22 @@ static unsigned int phylink_inband_caps(struct phylink *pl,
phy_interface_t interface)
{
struct phylink_pcs *pcs;
+ bool pcs_found = false;
- if (!pl->mac_ops->mac_select_pcs)
- return 0;
+ if (pl->mac_ops->mac_select_pcs) {
+ pcs = pl->mac_ops->mac_select_pcs(pl->config,
+ interface);
+ pcs_found = !!pcs;
+ } else {
+ list_for_each_entry(pcs, &pl->pcs_list, list) {
+ if (!phylink_validate_pcs_interface(pcs, interface)) {
+ pcs_found = true;
+ break;
+ }
+ }
+ }
- pcs = pl->mac_ops->mac_select_pcs(pl->config, interface);
- if (!pcs)
+ if (!pcs_found)
return 0;
return phylink_pcs_inband_caps(pcs, interface);
@@ -1230,10 +1279,36 @@ static void phylink_major_config(struct phylink *pl, bool restart,
pl->major_config_failed = true;
return;
}
+ /* Find a PCS in available PCS list for the requested interface.
+ * This doesn't overwrite the previous .mac_select_pcs as either
+ * .mac_select_pcs or PCS list implementation are permitted.
+ *
+ * Skip searching if the MAC doesn't require a dedicaed PCS for
+ * the requested interface.
+ */
+ } else if (test_bit(state->interface, pl->config->pcs_interfaces)) {
+ bool pcs_found = false;
+
+ list_for_each_entry(pcs, &pl->pcs_list, list) {
+ if (!phylink_validate_pcs_interface(pcs,
+ state->interface)) {
+ pcs_found = true;
+ break;
+ }
+ }
+
+ if (!pcs_found) {
+ phylink_err(pl,
+ "couldn't find a PCS for %s\n",
+ phy_modes(state->interface));
- pcs_changed = pl->pcs != pcs;
+ pl->major_config_failed = true;
+ return;
+ }
}
+ pcs_changed = pl->pcs != pcs;
+
phylink_pcs_neg_mode(pl, pcs, state->interface, state->advertising);
phylink_dbg(pl, "major config, active %s/%s/%s\n",
@@ -1260,10 +1335,12 @@ static void phylink_major_config(struct phylink *pl, bool restart,
if (pcs_changed) {
phylink_pcs_disable(pl->pcs);
- if (pl->pcs)
- pl->pcs->phylink = NULL;
+ if (pl->mac_ops->mac_select_pcs) {
+ if (pl->pcs)
+ pl->pcs->phylink = NULL;
- pcs->phylink = pl;
+ pcs->phylink = pl;
+ }
pl->pcs = pcs;
}
@@ -1812,8 +1889,9 @@ struct phylink *phylink_create(struct phylink_config *config,
phy_interface_t iface,
const struct phylink_mac_ops *mac_ops)
{
+ struct phylink_pcs *pcs;
struct phylink *pl;
- int ret;
+ int i, ret;
/* Validate the supplied configuration */
if (phy_interface_empty(config->supported_interfaces)) {
@@ -1829,9 +1907,21 @@ struct phylink *phylink_create(struct phylink_config *config,
mutex_init(&pl->phydev_mutex);
mutex_init(&pl->state_mutex);
INIT_WORK(&pl->resolve, phylink_resolve);
+ INIT_LIST_HEAD(&pl->pcs_list);
+
+ /* Fill the PCS list with available PCS from phylink config */
+ for (i = 0; i < config->num_available_pcs; i++) {
+ pcs = config->available_pcs[i];
+
+ list_add(&pcs->list, &pl->pcs_list);
+ }
phy_interface_copy(pl->supported_interfaces,
config->supported_interfaces);
+ list_for_each_entry(pcs, &pl->pcs_list, list)
+ phy_interface_or(pl->supported_interfaces,
+ pl->supported_interfaces,
+ pcs->supported_interfaces);
pl->config = config;
if (config->type == PHYLINK_NETDEV) {
@@ -1910,10 +2000,16 @@ EXPORT_SYMBOL_GPL(phylink_create);
*/
void phylink_destroy(struct phylink *pl)
{
+ struct phylink_pcs *pcs, *tmp;
+
sfp_bus_del_upstream(pl->sfp_bus);
if (pl->link_gpio)
gpiod_put(pl->link_gpio);
+ /* Remove every PCS from phylink PCS list */
+ list_for_each_entry_safe(pcs, tmp, &pl->pcs_list, list)
+ list_del(&pcs->list);
+
cancel_work_sync(&pl->resolve);
kfree(pl);
}
@@ -2396,6 +2492,7 @@ static irqreturn_t phylink_link_handler(int irq, void *data)
*/
void phylink_start(struct phylink *pl)
{
+ struct phylink_pcs *pcs;
bool poll = false;
ASSERT_RTNL();
@@ -2422,6 +2519,10 @@ void phylink_start(struct phylink *pl)
pl->pcs_state = PCS_STATE_STARTED;
+ /* link available PCS to phylink struct */
+ list_for_each_entry(pcs, &pl->pcs_list, list)
+ pcs->phylink = pl;
+
phylink_enable_and_run_resolve(pl, PHYLINK_DISABLE_STOPPED);
if (pl->cfg_link_an_mode == MLO_AN_FIXED && pl->link_gpio) {
@@ -2466,6 +2567,8 @@ EXPORT_SYMBOL_GPL(phylink_start);
*/
void phylink_stop(struct phylink *pl)
{
+ struct phylink_pcs *pcs;
+
ASSERT_RTNL();
if (pl->sfp_bus)
@@ -2483,6 +2586,14 @@ void phylink_stop(struct phylink *pl)
pl->pcs_state = PCS_STATE_DOWN;
phylink_pcs_disable(pl->pcs);
+
+ /* Drop link between phylink and PCS */
+ list_for_each_entry(pcs, &pl->pcs_list, list)
+ pcs->phylink = NULL;
+
+ /* Restore original supported interfaces */
+ phy_interface_copy(pl->supported_interfaces,
+ pl->config->supported_interfaces);
}
EXPORT_SYMBOL_GPL(phylink_stop);
diff --git a/include/linux/phylink.h b/include/linux/phylink.h
index 30659b615fca..ef0b5a0729c8 100644
--- a/include/linux/phylink.h
+++ b/include/linux/phylink.h
@@ -150,12 +150,16 @@ enum phylink_op_type {
* if MAC link is at %MLO_AN_FIXED mode.
* @supported_interfaces: bitmap describing which PHY_INTERFACE_MODE_xxx
* are supported by the MAC/PCS.
+ * @pcs_interfaces: bitmap describing for which PHY_INTERFACE_MODE_xxx a
+ * dedicated PCS is required.
* @lpi_interfaces: bitmap describing which PHY interface modes can support
* LPI signalling.
* @mac_capabilities: MAC pause/speed/duplex capabilities.
* @lpi_capabilities: MAC speeds which can support LPI signalling
* @lpi_timer_default: Default EEE LPI timer setting.
* @eee_enabled_default: If set, EEE will be enabled by phylink at creation time
+ * @available_pcs: array of available phylink_pcs PCS
+ * @num_available_pcs: num of available phylink_pcs PCS
*/
struct phylink_config {
struct device *dev;
@@ -168,11 +172,14 @@ struct phylink_config {
void (*get_fixed_state)(struct phylink_config *config,
struct phylink_link_state *state);
DECLARE_PHY_INTERFACE_MASK(supported_interfaces);
+ DECLARE_PHY_INTERFACE_MASK(pcs_interfaces);
DECLARE_PHY_INTERFACE_MASK(lpi_interfaces);
unsigned long mac_capabilities;
unsigned long lpi_capabilities;
u32 lpi_timer_default;
bool eee_enabled_default;
+ struct phylink_pcs **available_pcs;
+ unsigned int num_available_pcs;
};
void phylink_limit_mac_speed(struct phylink_config *config, u32 max_speed);
@@ -469,6 +476,9 @@ struct phylink_pcs {
struct phylink *phylink;
bool poll;
bool rxc_always_on;
+
+ /* private: */
+ struct list_head list;
};
/**
--
2.30.2

142
patch/kernel/archive/filogic-6.16/patches.armbian/0055-net-phylink-add-phylink_release_pcs-to-externally-re.patch Normal file
View File

@ -0,0 +1,142 @@
From b9b90aa82fedf47b035bc1f7196037e0cb481e41 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Mon, 7 Apr 2025 00:13:58 +0200
Subject: [PATCH 55/84] net: phylink: add phylink_release_pcs() to externally
release a PCS
Add phylink_release_pcs() to externally release a PCS from a phylink
instance. This can be used to handle case when a single PCS needs to be
removed and the phylink instance needs to be refreshed.
On calling phylink_release_pcs(), the PCS will be removed from the
phylink internal PCS list and the phylink supported_interfaces value is
reparsed with the remaining PCS interfaces.
Also a phylink resolve is triggered to handle the PCS removal.
It's also added to phylink a flag to make phylink resolve reconfigure
the interface mode (even if it didn't change). This is needed to handle
the special case when the current PCS used by phylink is removed and a
major_config is needed to propagae the configuration change. With this
option enabled we also force mac_config even if the PHY link is not up
for the in-band case.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/net/phy/phylink.c | 58 ++++++++++++++++++++++++++++++++++++++-
include/linux/phylink.h | 2 ++
2 files changed, 59 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 8539519536b2..ef393e49a314 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -86,6 +86,7 @@ struct phylink {
bool link_failed;
bool suspend_link_up;
bool major_config_failed;
+ bool reconfig_interface;
bool mac_supports_eee_ops;
bool mac_supports_eee;
bool phy_enable_tx_lpi;
@@ -897,6 +898,55 @@ static void phylink_resolve_an_pause(struct phylink_link_state *state)
}
}
+/**
+ * phylink_release_pcs - Removes a PCS from the phylink PCS available list
+ * @pcs: a pointer to the phylink_pcs struct to be released
+ *
+ * This function release a PCS from the phylink PCS available list if
+ * actually in use. It also refreshes the supported interfaces of the
+ * phylink instance by copying the supported interfaces from the phylink
+ * conf and merging the supported interfaces of the remaining available PCS
+ * in the list and trigger a resolve.
+ */
+void phylink_release_pcs(struct phylink_pcs *pcs)
+{
+ struct phylink *pl;
+
+ ASSERT_RTNL();
+
+ pl = pcs->phylink;
+ if (!pl)
+ return;
+
+ list_del(&pcs->list);
+ pcs->phylink = NULL;
+
+ /* Check if we are removing the PCS currently
+ * in use by phylink. If this is the case,
+ * force phylink resolve to reconfigure the interface
+ * mode and set the phylink PCS to NULL.
+ */
+ if (pl->pcs == pcs) {
+ mutex_lock(&pl->state_mutex);
+
+ pl->reconfig_interface = true;
+ pl->pcs = NULL;
+
+ mutex_unlock(&pl->state_mutex);
+ }
+
+ /* Refresh supported interfaces */
+ phy_interface_copy(pl->supported_interfaces,
+ pl->config->supported_interfaces);
+ list_for_each_entry(pcs, &pl->pcs_list, list)
+ phy_interface_or(pl->supported_interfaces,
+ pl->supported_interfaces,
+ pcs->supported_interfaces);
+
+ phylink_run_resolve(pl);
+}
+EXPORT_SYMBOL_GPL(phylink_release_pcs);
+
static unsigned int phylink_pcs_inband_caps(struct phylink_pcs *pcs,
phy_interface_t interface)
{
@@ -1700,6 +1750,10 @@ static void phylink_resolve(struct work_struct *w)
if (phy)
link_state.link &= pl->phy_state.link;
+ /* Force mac_config if we need to reconfig the interface */
+ if (pl->reconfig_interface)
+ mac_config = true;
+
/* Only update if the PHY link is up */
if (phy && pl->phy_state.link) {
/* If the interface has changed, force a link down
@@ -1734,7 +1788,8 @@ static void phylink_resolve(struct work_struct *w)
phylink_apply_manual_flow(pl, &link_state);
if (mac_config) {
- if (link_state.interface != pl->link_config.interface) {
+ if (link_state.interface != pl->link_config.interface ||
+ pl->reconfig_interface) {
/* The interface has changed, force the link down and
* then reconfigure.
*/
@@ -1744,6 +1799,7 @@ static void phylink_resolve(struct work_struct *w)
}
phylink_major_config(pl, false, &link_state);
pl->link_config.interface = link_state.interface;
+ pl->reconfig_interface = false;
}
}
diff --git a/include/linux/phylink.h b/include/linux/phylink.h
index ef0b5a0729c8..c5496c063b6a 100644
--- a/include/linux/phylink.h
+++ b/include/linux/phylink.h
@@ -717,6 +717,8 @@ void phylink_disconnect_phy(struct phylink *);
int phylink_set_fixed_link(struct phylink *,
const struct phylink_link_state *);
+void phylink_release_pcs(struct phylink_pcs *pcs);
+
void phylink_mac_change(struct phylink *, bool up);
void phylink_pcs_change(struct phylink_pcs *, bool up);
--
2.30.2

401
patch/kernel/archive/filogic-6.16/patches.armbian/0056-net-pcs-implement-Firmware-node-support-for-PCS-driv.patch Normal file
View File

@ -0,0 +1,401 @@
From 05d36511b44291340cdb31205d39b3e53ab56e04 Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Mon, 7 Apr 2025 00:13:59 +0200
Subject: [PATCH 56/84] net: pcs: implement Firmware node support for PCS
driver
Implement the foundation of Firmware node support for PCS driver.
To support this, implement a simple Provider API where a PCS driver can
expose multiple PCS with an xlate .get function.
PCS driver will have to call fwnode_pcs_add_provider() and pass the
firmware node pointer and a xlate function to return the correct PCS for
the passed #pcs-cells.
This will register the PCS in a global list of providers so that
consumer can access it.
Consumer will then use fwnode_pcs_get() to get the actual PCS by passing
the firmware node pointer and the index for #pcs-cells.
For simple implementation where #pcs-cells is 0 and the PCS driver
expose a single PCS, the xlate function fwnode_pcs_simple_get() is
provided.
For advanced implementation a custom xlate function is required.
PCS driver on removal should first delete as a provider with
the usage of fwnode_pcs_del_provider() and then call
phylink_release_pcs() on every PCS the driver provides and
A generic function fwnode_phylink_pcs_parse() is provided for any MAC
driver that will declare PCS in DT (or ACPI).
This function will parse "pcs-handle" property and fill the passed array
with the parsed PCS in availabel_pcs up to the passed num_pcs value.
It's also possible to pass NULL as array to only parse the PCS and
update the num_pcs value with the count of scanned PCS.
Co-developed-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/net/pcs/Kconfig | 7 ++
drivers/net/pcs/Makefile | 1 +
drivers/net/pcs/pcs.c | 201 +++++++++++++++++++++++++++++++
include/linux/pcs/pcs-provider.h | 41 +++++++
include/linux/pcs/pcs.h | 56 +++++++++
5 files changed, 306 insertions(+)
create mode 100644 drivers/net/pcs/pcs.c
create mode 100644 include/linux/pcs/pcs-provider.h
create mode 100644 include/linux/pcs/pcs.h
diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig
index f6aa437473de..2951aa2f4cda 100644
--- a/drivers/net/pcs/Kconfig
+++ b/drivers/net/pcs/Kconfig
@@ -5,6 +5,13 @@
menu "PCS device drivers"
+config FWNODE_PCS
+ tristate
+ depends on (ACPI || OF)
+ depends on PHYLINK
+ help
+ Firmware node PCS accessors
+
config PCS_XPCS
tristate "Synopsys DesignWare Ethernet XPCS"
select PHYLINK
diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile
index 4f7920618b90..3005cdd89ab7 100644
--- a/drivers/net/pcs/Makefile
+++ b/drivers/net/pcs/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
# Makefile for Linux PCS drivers
+obj-$(CONFIG_FWNODE_PCS) += pcs.o
pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs.o pcs-xpcs-plat.o \
pcs-xpcs-nxp.o pcs-xpcs-wx.o
diff --git a/drivers/net/pcs/pcs.c b/drivers/net/pcs/pcs.c
new file mode 100644
index 000000000000..14a5cd3eeda1
--- /dev/null
+++ b/drivers/net/pcs/pcs.c
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include <linux/mutex.h>
+#include <linux/property.h>
+#include <linux/phylink.h>
+#include <linux/pcs/pcs.h>
+#include <linux/pcs/pcs-provider.h>
+
+MODULE_DESCRIPTION("PCS library");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_LICENSE("GPL");
+
+struct fwnode_pcs_provider {
+ struct list_head link;
+
+ struct fwnode_handle *fwnode;
+ struct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,
+ void *data);
+
+ void *data;
+};
+
+static LIST_HEAD(fwnode_pcs_providers);
+static DEFINE_MUTEX(fwnode_pcs_mutex);
+
+struct phylink_pcs *fwnode_pcs_simple_get(struct fwnode_reference_args *pcsspec,
+ void *data)
+{
+ return data;
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_simple_get);
+
+int fwnode_pcs_add_provider(struct fwnode_handle *fwnode,
+ struct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,
+ void *data),
+ void *data)
+{
+ struct fwnode_pcs_provider *pp;
+
+ if (!fwnode)
+ return 0;
+
+ pp = kzalloc(sizeof(*pp), GFP_KERNEL);
+ if (!pp)
+ return -ENOMEM;
+
+ pp->fwnode = fwnode_handle_get(fwnode);
+ pp->data = data;
+ pp->get = get;
+
+ mutex_lock(&fwnode_pcs_mutex);
+ list_add(&pp->link, &fwnode_pcs_providers);
+ mutex_unlock(&fwnode_pcs_mutex);
+ pr_debug("Added pcs provider from %pfwf\n", fwnode);
+
+ fwnode_dev_initialized(fwnode, true);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_add_provider);
+
+void fwnode_pcs_del_provider(struct fwnode_handle *fwnode)
+{
+ struct fwnode_pcs_provider *pp;
+
+ if (!fwnode)
+ return;
+
+ mutex_lock(&fwnode_pcs_mutex);
+ list_for_each_entry(pp, &fwnode_pcs_providers, link) {
+ if (pp->fwnode == fwnode) {
+ list_del(&pp->link);
+ fwnode_dev_initialized(pp->fwnode, false);
+ fwnode_handle_put(pp->fwnode);
+ kfree(pp);
+ break;
+ }
+ }
+ mutex_unlock(&fwnode_pcs_mutex);
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_del_provider);
+
+static int fwnode_parse_pcsspec(const struct fwnode_handle *fwnode, int index,
+ const char *name,
+ struct fwnode_reference_args *out_args)
+{
+ int ret = -ENOENT;
+
+ if (!fwnode)
+ return -ENOENT;
+
+ if (name)
+ index = fwnode_property_match_string(fwnode, "pcs-names",
+ name);
+
+ ret = fwnode_property_get_reference_args(fwnode, "pcs-handle",
+ "#pcs-cells",
+ -1, index, out_args);
+ if (ret || (name && index < 0))
+ return ret;
+
+ return 0;
+}
+
+static struct phylink_pcs *
+fwnode_pcs_get_from_pcsspec(struct fwnode_reference_args *pcsspec)
+{
+ struct fwnode_pcs_provider *provider;
+ struct phylink_pcs *pcs = ERR_PTR(-EPROBE_DEFER);
+
+ if (!pcsspec)
+ return ERR_PTR(-EINVAL);
+
+ mutex_lock(&fwnode_pcs_mutex);
+ list_for_each_entry(provider, &fwnode_pcs_providers, link) {
+ if (provider->fwnode == pcsspec->fwnode) {
+ pcs = provider->get(pcsspec, provider->data);
+ if (!IS_ERR(pcs))
+ break;
+ }
+ }
+ mutex_unlock(&fwnode_pcs_mutex);
+
+ return pcs;
+}
+
+static struct phylink_pcs *__fwnode_pcs_get(struct fwnode_handle *fwnode,
+ int index, const char *con_id)
+{
+ struct fwnode_reference_args pcsspec;
+ struct phylink_pcs *pcs;
+ int ret;
+
+ ret = fwnode_parse_pcsspec(fwnode, index, con_id, &pcsspec);
+ if (ret)
+ return ERR_PTR(ret);
+
+ pcs = fwnode_pcs_get_from_pcsspec(&pcsspec);
+ fwnode_handle_put(pcsspec.fwnode);
+
+ return pcs;
+}
+
+struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode, int index)
+{
+ return __fwnode_pcs_get(fwnode, index, NULL);
+}
+EXPORT_SYMBOL_GPL(fwnode_pcs_get);
+
+static int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode,
+ unsigned int *num_pcs)
+{
+ struct fwnode_reference_args out_args;
+ int index = 0;
+ int ret;
+
+ while (true) {
+ ret = fwnode_property_get_reference_args(fwnode, "pcs-handle",
+ "#pcs-cells",
+ -1, index, &out_args);
+ /* We expect to reach an -ENOENT error while counting */
+ if (ret)
+ break;
+
+ fwnode_handle_put(out_args.fwnode);
+ index++;
+ }
+
+ /* Update num_pcs with parsed PCS */
+ *num_pcs = index;
+
+ /* Return error if we didn't found any PCS */
+ return index > 0 ? 0 : -ENOENT;
+}
+
+int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
+ struct phylink_pcs **available_pcs,
+ unsigned int *num_pcs)
+{
+ int i;
+
+ if (!fwnode_property_present(fwnode, "pcs-handle"))
+ return -ENODEV;
+
+ /* With available_pcs NULL, only count the PCS */
+ if (!available_pcs)
+ return fwnode_phylink_pcs_count(fwnode, num_pcs);
+
+ for (i = 0; i < *num_pcs; i++) {
+ struct phylink_pcs *pcs;
+
+ pcs = fwnode_pcs_get(fwnode, i);
+ if (IS_ERR(pcs))
+ return PTR_ERR(pcs);
+
+ available_pcs[i] = pcs;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_parse);
diff --git a/include/linux/pcs/pcs-provider.h b/include/linux/pcs/pcs-provider.h
new file mode 100644
index 000000000000..2fcc1d696c97
--- /dev/null
+++ b/include/linux/pcs/pcs-provider.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef __LINUX_PCS_PROVIDER_H
+#define __LINUX_PCS_PROVIDER_H
+
+/**
+ * fwnode_pcs_simple_get - Simple xlate function to retrieve PCS
+ * @pcsspec: reference arguments
+ * @data: Context data (assumed assigned to the single PCS)
+ *
+ * Returns the PCS. (pointed by data)
+ */
+struct phylink_pcs *fwnode_pcs_simple_get(struct fwnode_reference_args *pcsspec,
+ void *data);
+
+/**
+ * fwnode_pcs_add_provider - Registers a new PCS provider
+ * @np: Firmware node
+ * @get: xlate function to retrieve the PCS
+ * @data: Context data
+ *
+ * Register and add a new PCS to the global providers list
+ * for the firmware node. A function to get the PCS from
+ * firmware node with the use fwnode reference arguments.
+ * To the get function is also passed the interface type
+ * requested for the PHY. PCS driver will use the passed
+ * interface to understand if the PCS can support it or not.
+ *
+ * Returns 0 on success or -ENOMEM on allocation failure.
+ */
+int fwnode_pcs_add_provider(struct fwnode_handle *fwnode,
+ struct phylink_pcs *(*get)(struct fwnode_reference_args *pcsspec,
+ void *data),
+ void *data);
+
+/**
+ * fwnode_pcs_del_provider - Removes a PCS provider
+ * @fwnode: Firmware node
+ */
+void fwnode_pcs_del_provider(struct fwnode_handle *fwnode);
+
+#endif /* __LINUX_PCS_PROVIDER_H */
diff --git a/include/linux/pcs/pcs.h b/include/linux/pcs/pcs.h
new file mode 100644
index 000000000000..c7a4d63bcd6d
--- /dev/null
+++ b/include/linux/pcs/pcs.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef __LINUX_PCS_H
+#define __LINUX_PCS_H
+
+#include <linux/phylink.h>
+
+#if IS_ENABLED(CONFIG_FWNODE_PCS)
+/**
+ * fwnode_pcs_get - Retrieves a PCS from a firmware node
+ * @fwnode: firmware node
+ * @index: index fwnode PCS handle in firmware node
+ *
+ * Get a PCS from the firmware node at index.
+ *
+ * Returns a pointer to the phylink_pcs or a negative
+ * error pointer. Can return -EPROBE_DEFER if the PCS is not
+ * present in global providers list (either due to driver
+ * still needs to be probed or it failed to probe/removed)
+ */
+struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
+ int index);
+
+/**
+ * fwnode_phylink_pcs_parse - generic PCS parse for fwnode PCS provider
+ * @fwnode: firmware node
+ * @available_pcs: pointer to preallocated array of PCS
+ * @num_pcs: where to store count of parsed PCS
+ *
+ * Generic helper function to fill available_pcs array with PCS parsed
+ * from a "pcs-handle" fwnode property defined in firmware node up to
+ * passed num_pcs.
+ *
+ * If available_pcs is NULL, num_pcs is updated with the count of the
+ * parsed PCS.
+ *
+ * Returns 0 or a negative error.
+ */
+int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
+ struct phylink_pcs **available_pcs,
+ unsigned int *num_pcs);
+#else
+static inline struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
+ int index)
+{
+ return ERR_PTR(-ENOENT);
+}
+
+static inline int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
+ struct phylink_pcs **available_pcs,
+ unsigned int *num_pcs)
+{
+ return -EOPNOTSUPP;
+}
+#endif
+
+#endif /* __LINUX_PCS_H */
--
2.30.2

263
patch/kernel/archive/filogic-6.16/patches.armbian/0057-net-phylink-support-late-PCS-provider-attach.patch Normal file
View File

@ -0,0 +1,263 @@
From eb72f36586bb4c7f52180d6c3158e5a33de99c7f Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Mon, 7 Apr 2025 00:14:00 +0200
Subject: [PATCH 57/84] net: phylink: support late PCS provider attach
Add support in phylink for late PCS provider attach to a phylink
instance. This works by creating a global notifier for the PCS provider
and making each phylink instance that makes use of fwnode subscribe to
this notifier.
The PCS notifier will emit the event FWNODE_PCS_PROVIDER_ADD every time
a new PCS provider is added.
phylink will then react to this event and will call the new function
fwnode_phylink_pcs_get_from_fwnode() that will check if the PCS fwnode
provided by the event is present in the phy-handle property of the
phylink instance.
If a related PCS is found, then such PCS is added to the phylink
instance PCS list.
Then we link the PCS to the phylink instance if it's not disable and we
refresh the supported interfaces of the phylink instance.
Finally we check if we are in a major_config_failed scenario and trigger
an interface reconfiguration in the next phylink resolve.
If link was previously torn down due to removal of PCS, the link will be
established again as the PCS came back and is not available to phylink.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/net/pcs/pcs.c | 34 +++++++++++++++++++++++++
drivers/net/phy/phylink.c | 52 +++++++++++++++++++++++++++++++++++++++
include/linux/pcs/pcs.h | 48 ++++++++++++++++++++++++++++++++++++
3 files changed, 134 insertions(+)
diff --git a/drivers/net/pcs/pcs.c b/drivers/net/pcs/pcs.c
index 14a5cd3eeda1..a7352effa92f 100644
--- a/drivers/net/pcs/pcs.c
+++ b/drivers/net/pcs/pcs.c
@@ -22,6 +22,13 @@ struct fwnode_pcs_provider {
static LIST_HEAD(fwnode_pcs_providers);
static DEFINE_MUTEX(fwnode_pcs_mutex);
+static BLOCKING_NOTIFIER_HEAD(fwnode_pcs_notify_list);
+
+int register_fwnode_pcs_notifier(struct notifier_block *nb)
+{
+ return blocking_notifier_chain_register(&fwnode_pcs_notify_list, nb);
+}
+EXPORT_SYMBOL_GPL(register_fwnode_pcs_notifier);
struct phylink_pcs *fwnode_pcs_simple_get(struct fwnode_reference_args *pcsspec,
void *data)
@@ -55,6 +62,10 @@ int fwnode_pcs_add_provider(struct fwnode_handle *fwnode,
fwnode_dev_initialized(fwnode, true);
+ blocking_notifier_call_chain(&fwnode_pcs_notify_list,
+ FWNODE_PCS_PROVIDER_ADD,
+ fwnode);
+
return 0;
}
EXPORT_SYMBOL_GPL(fwnode_pcs_add_provider);
@@ -147,6 +158,29 @@ struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode, int index)
}
EXPORT_SYMBOL_GPL(fwnode_pcs_get);
+struct phylink_pcs *
+fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,
+ struct fwnode_handle *pcs_fwnode)
+{
+ struct fwnode_reference_args pcsspec;
+ int i = 0;
+ int ret;
+
+ while (true) {
+ ret = fwnode_parse_pcsspec(fwnode, i, NULL, &pcsspec);
+ if (ret)
+ break;
+
+ if (pcsspec.fwnode == pcs_fwnode)
+ break;
+
+ i++;
+ }
+
+ return fwnode_pcs_get(fwnode, i);
+}
+EXPORT_SYMBOL_GPL(fwnode_phylink_pcs_get_from_fwnode);
+
static int fwnode_phylink_pcs_count(struct fwnode_handle *fwnode,
unsigned int *num_pcs)
{
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index ef393e49a314..409a5dbb1cfc 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -12,6 +12,7 @@
#include <linux/netdevice.h>
#include <linux/of.h>
#include <linux/of_mdio.h>
+#include <linux/pcs/pcs.h>
#include <linux/phy.h>
#include <linux/phy_fixed.h>
#include <linux/phylink.h>
@@ -61,6 +62,7 @@ struct phylink {
/* List of available PCS */
struct list_head pcs_list;
+ struct notifier_block fwnode_pcs_nb;
/* What interface are supported by the current link.
* Can change on removal or addition of new PCS.
@@ -1924,6 +1926,51 @@ int phylink_set_fixed_link(struct phylink *pl,
}
EXPORT_SYMBOL_GPL(phylink_set_fixed_link);
+static int pcs_provider_notify(struct notifier_block *self,
+ unsigned long val, void *data)
+{
+ struct phylink *pl = container_of(self, struct phylink, fwnode_pcs_nb);
+ struct fwnode_handle *pcs_fwnode = data;
+ struct phylink_pcs *pcs;
+
+ /* Check if the just added PCS provider is
+ * in the phylink instance phy-handle property
+ */
+ pcs = fwnode_phylink_pcs_get_from_fwnode(dev_fwnode(pl->config->dev),
+ pcs_fwnode);
+ if (IS_ERR(pcs))
+ return NOTIFY_DONE;
+
+ /* Add the PCS */
+ rtnl_lock();
+
+ list_add(&pcs->list, &pl->pcs_list);
+
+ /* Link phylink if we are started */
+ if (!pl->phylink_disable_state)
+ pcs->phylink = pl;
+
+ /* Refresh supported interfaces */
+ phy_interface_copy(pl->supported_interfaces,
+ pl->config->supported_interfaces);
+ list_for_each_entry(pcs, &pl->pcs_list, list)
+ phy_interface_or(pl->supported_interfaces,
+ pl->supported_interfaces,
+ pcs->supported_interfaces);
+
+ mutex_lock(&pl->state_mutex);
+ /* Force an interface reconfig if major config fail */
+ if (pl->major_config_failed)
+ pl->reconfig_interface = true;
+ mutex_unlock(&pl->state_mutex);
+
+ rtnl_unlock();
+
+ phylink_run_resolve(pl);
+
+ return NOTIFY_OK;
+}
+
/**
* phylink_create() - create a phylink instance
* @config: a pointer to the target &struct phylink_config
@@ -1979,6 +2026,11 @@ struct phylink *phylink_create(struct phylink_config *config,
pl->supported_interfaces,
pcs->supported_interfaces);
+ if (!phy_interface_empty(config->pcs_interfaces)) {
+ pl->fwnode_pcs_nb.notifier_call = pcs_provider_notify;
+ register_fwnode_pcs_notifier(&pl->fwnode_pcs_nb);
+ }
+
pl->config = config;
if (config->type == PHYLINK_NETDEV) {
pl->netdev = to_net_dev(config->dev);
diff --git a/include/linux/pcs/pcs.h b/include/linux/pcs/pcs.h
index c7a4d63bcd6d..480c155a3f03 100644
--- a/include/linux/pcs/pcs.h
+++ b/include/linux/pcs/pcs.h
@@ -4,7 +4,24 @@
#include <linux/phylink.h>
+enum fwnode_pcs_notify_event {
+ FWNODE_PCS_PROVIDER_ADD,
+};
+
#if IS_ENABLED(CONFIG_FWNODE_PCS)
+/**
+ * register_fwnode_pcs_notifier - Register a notifier block for fwnode
+ * PCS events
+ * @nb: pointer to the notifier block
+ *
+ * Registers a notifier block to the fwnode_pcs_notify_list blocking
+ * notifier chain. This allows phylink instance to subscribe for
+ * PCS provider events.
+ *
+ * Returns 0 or a negative error.
+ */
+int register_fwnode_pcs_notifier(struct notifier_block *nb);
+
/**
* fwnode_pcs_get - Retrieves a PCS from a firmware node
* @fwnode: firmware node
@@ -20,6 +37,25 @@
struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
int index);
+/**
+ * fwnode_phylink_pcs_get_from_fwnode - Retrieves the PCS provided
+ * by the firmware node from a
+ * firmware node
+ * @fwnode: firmware node
+ * @pcs_fwnode: PCS firmware node
+ *
+ * Parse 'pcs-handle' in 'fwnode' and get the PCS that match
+ * 'pcs_fwnode' firmware node.
+ *
+ * Returns a pointer to the phylink_pcs or a negative
+ * error pointer. Can return -EPROBE_DEFER if the PCS is not
+ * present in global providers list (either due to driver
+ * still needs to be probed or it failed to probe/removed)
+ */
+struct phylink_pcs *
+fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,
+ struct fwnode_handle *pcs_fwnode);
+
/**
* fwnode_phylink_pcs_parse - generic PCS parse for fwnode PCS provider
* @fwnode: firmware node
@@ -39,12 +75,24 @@ int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
struct phylink_pcs **available_pcs,
unsigned int *num_pcs);
#else
+static int register_fwnode_pcs_notifier(struct notifier_block *nb)
+{
+ return -EOPNOTSUPP;
+}
+
static inline struct phylink_pcs *fwnode_pcs_get(struct fwnode_handle *fwnode,
int index)
{
return ERR_PTR(-ENOENT);
}
+static struct phylink_pcs *
+fwnode_phylink_pcs_get_from_fwnode(struct fwnode_handle *fwnode,
+ struct fwnode_handle *pcs_fwnode)
+{
+ return ERR_PTR(-ENOENT);
+}
+
static inline int fwnode_phylink_pcs_parse(struct fwnode_handle *fwnode,
struct phylink_pcs **available_pcs,
unsigned int *num_pcs)
--
2.30.2

34
patch/kernel/archive/filogic-6.16/patches.armbian/0058-dt-bindings-net-ethernet-controller-permit-to-define.patch Normal file
View File

@ -0,0 +1,34 @@
From 2f5f92f20fe06d54b826a446be6504063207f82b Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Mon, 7 Apr 2025 00:14:01 +0200
Subject: [PATCH 58/84] dt-bindings: net: ethernet-controller: permit to define
multiple PCS
Drop the limitation of a single PCS in pcs-handle property. Multiple PCS
can be defined for an ethrnet-controller node to support various PHY
interface mode type.
It's very common for SoCs to have a dedicated PCS for SGMII mode and one
for USXGMII mode.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
Documentation/devicetree/bindings/net/ethernet-controller.yaml | 2 --
1 file changed, 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
index 7cbf11bbe99c..60605b34d242 100644
--- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml
+++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml
@@ -84,8 +84,6 @@ properties:
pcs-handle:
$ref: /schemas/types.yaml#/definitions/phandle-array
- items:
- maxItems: 1
description:
Specifies a reference to a node representing a PCS PHY device on a MDIO
bus to link with an external PHY (phy-handle) if exists.
--
2.30.2

2938
patch/kernel/archive/filogic-6.16/patches.armbian/0059-net-pcs-airoha-add-PCS-driver-for-Airoha-SoC.patch Normal file
View File

File diff suppressed because it is too large Load Diff

141
patch/kernel/archive/filogic-6.16/patches.armbian/0060-dt-bindings-net-pcs-Document-support-for-Airoha-Ethe.patch Normal file
View File

@ -0,0 +1,141 @@
From 867bdc4af013a1f530133b01c7d4494a99d88b2b Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Mon, 7 Apr 2025 00:14:03 +0200
Subject: [PATCH 60/84] dt-bindings: net: pcs: Document support for Airoha
Ethernet PCS
Document support for Airoha Ethernet PCS for AN7581 SoC.
Airoha AN7581 SoC expose multiple Physical Coding Sublayer (PCS) for
the various Serdes port supporting different Media Independent Interface
(10BASE-R, USXGMII, 2500BASE-X, 1000BASE-X, SGMII).
This follow the new PCS provider with the use of #pcs-cells property.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
.../bindings/net/pcs/airoha,pcs.yaml | 112 ++++++++++++++++++
1 file changed, 112 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
diff --git a/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
new file mode 100644
index 000000000000..8bcf7757c728
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/pcs/airoha,pcs.yaml
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/pcs/airoha,pcs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha Ethernet PCS and Serdes
+
+maintainers:
+ - Christian Marangi <ansuelsmth@gmail.com>
+
+description:
+ Airoha AN7581 SoC expose multiple Physical Coding Sublayer (PCS) for
+ the various Serdes port supporting different Media Independent Interface
+ (10BASE-R, USXGMII, 2500BASE-X, 1000BASE-X, SGMII).
+
+properties:
+ compatible:
+ enum:
+ - airoha,an7581-pcs-eth
+ - airoha,an7581-pcs-pon
+
+ reg:
+ items:
+ - description: XFI MAC reg
+ - description: HSGMII AN reg
+ - description: HSGMII PCS reg
+ - description: MULTI SGMII reg
+ - description: USXGMII reg
+ - description: HSGMII rate adaption reg
+ - description: XFI Analog register
+ - description: XFI PMA (Physical Medium Attachment) register
+
+ reg-names:
+ items:
+ - const: xfi_mac
+ - const: hsgmii_an
+ - const: hsgmii_pcs
+ - const: multi_sgmii
+ - const: usxgmii
+ - const: hsgmii_rate_adp
+ - const: xfi_ana
+ - const: xfi_pma
+
+ resets:
+ items:
+ - description: MAC reset
+ - description: PHY reset
+
+ reset-names:
+ items:
+ - const: mac
+ - const: phy
+
+ "#pcs-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - resets
+ - reset-names
+ - "#pcs-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/reset/airoha,en7581-reset.h>
+
+ pcs@1fa08000 {
+ compatible = "airoha,an7581-pcs-pon";
+ reg = <0x1fa08000 0x1000>,
+ <0x1fa80000 0x60>,
+ <0x1fa80a00 0x164>,
+ <0x1fa84000 0x450>,
+ <0x1fa85900 0x338>,
+ <0x1fa86000 0x300>,
+ <0x1fa8a000 0x1000>,
+ <0x1fa8b000 0x1000>;
+ reg-names = "xfi_mac", "hsgmii_an", "hsgmii_pcs",
+ "multi_sgmii", "usxgmii",
+ "hsgmii_rate_adp", "xfi_ana", "xfi_pma";
+
+ resets = <&scuclk EN7581_XPON_MAC_RST>,
+ <&scuclk EN7581_XPON_PHY_RST>;
+ reset-names = "mac", "phy";
+
+ #pcs-cells = <0>;
+ };
+
+ pcs@1fa09000 {
+ compatible = "airoha,an7581-pcs-eth";
+ reg = <0x1fa09000 0x1000>,
+ <0x1fa70000 0x60>,
+ <0x1fa70a00 0x164>,
+ <0x1fa74000 0x450>,
+ <0x1fa75900 0x338>,
+ <0x1fa76000 0x300>,
+ <0x1fa7a000 0x1000>,
+ <0x1fa7b000 0x1000>;
+ reg-names = "xfi_mac", "hsgmii_an", "hsgmii_pcs",
+ "multi_sgmii", "usxgmii",
+ "hsgmii_rate_adp", "xfi_ana", "xfi_pma";
+
+ resets = <&scuclk EN7581_XSI_MAC_RST>,
+ <&scuclk EN7581_XSI_PHY_RST>;
+ reset-names = "mac", "phy";
+
+ #pcs-cells = <0>;
+ };
--
2.30.2

367
patch/kernel/archive/filogic-6.16/patches.armbian/0061-net-pcs-pcs-mtk-lynxi-add-platform-driver-for-MT7988.patch Normal file
View File

@ -0,0 +1,367 @@
From df68e3182801a4c6c4a7e3b3f68cefb8f58f52d3 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Tue, 12 Dec 2023 03:47:18 +0000
Subject: [PATCH 61/84] net: pcs: pcs-mtk-lynxi: add platform driver for MT7988
Introduce a full platform MFD driver for the LynxI (H)SGMII PCS which
is going to initially be used for the MT7988 SoC.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/net/pcs/pcs-mtk-lynxi.c | 206 +++++++++++++++++++++++++++++---
1 file changed, 189 insertions(+), 17 deletions(-)
diff --git a/drivers/net/pcs/pcs-mtk-lynxi.c b/drivers/net/pcs/pcs-mtk-lynxi.c
index 149ddf51d785..19c1b29beeac 100644
--- a/drivers/net/pcs/pcs-mtk-lynxi.c
+++ b/drivers/net/pcs/pcs-mtk-lynxi.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018-2019 MediaTek Inc.
-/* A library for MediaTek SGMII circuit
+/* A library and platform driver for the MediaTek LynxI SGMII circuit
*
* Author: Sean Wang <sean.wang@mediatek.com>
* Author: Alexander Couzens <lynxis@fe80.eu>
@@ -8,11 +8,20 @@
*
*/
+#include <linux/clk.h>
#include <linux/mdio.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mutex.h>
#include <linux/of.h>
+#include <linux/of_platform.h>
#include <linux/pcs/pcs-mtk-lynxi.h>
+#include <linux/pcs/pcs-provider.h>
+#include <linux/phy/phy.h>
#include <linux/phylink.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/rtnetlink.h>
/* SGMII subsystem config registers */
/* BMCR (low 16) BMSR (high 16) */
@@ -65,6 +74,8 @@
#define SGMII_PN_SWAP_MASK GENMASK(1, 0)
#define SGMII_PN_SWAP_TX_RX (BIT(0) | BIT(1))
+#define MTK_NETSYS_V3_AMA_RGC3 0x128
+
/* struct mtk_pcs_lynxi - This structure holds each sgmii regmap andassociated
* data
* @regmap: The register map pointing at the range used to setup
@@ -74,13 +85,26 @@
* @interface: Currently configured interface mode
* @pcs: Phylink PCS structure
* @flags: Flags indicating hardware properties
+ * @rstc: Reset controller
+ * @sgmii_sel: SGMII Register Clock
+ * @sgmii_rx: SGMII RX Clock
+ * @sgmii_tx: SGMII TX Clock
+ * @node: List node
*/
struct mtk_pcs_lynxi {
struct regmap *regmap;
+ struct device *dev;
u32 ana_rgc3;
phy_interface_t interface;
struct phylink_pcs pcs;
u32 flags;
+ int advertise;
+ struct reset_control *rstc;
+ struct clk *sgmii_sel;
+ struct clk *sgmii_rx;
+ struct clk *sgmii_tx;
+ struct phy *xfi_tphy;
+ struct list_head node;
};
static struct mtk_pcs_lynxi *pcs_to_mtk_pcs_lynxi(struct phylink_pcs *pcs)
@@ -120,6 +144,17 @@ static void mtk_pcs_lynxi_get_state(struct phylink_pcs *pcs,
FIELD_GET(SGMII_LPA, adv));
}
+static void mtk_sgmii_reset(struct mtk_pcs_lynxi *mpcs)
+{
+ if (!mpcs->rstc)
+ return;
+
+ reset_control_assert(mpcs->rstc);
+ udelay(100);
+ reset_control_deassert(mpcs->rstc);
+ mdelay(1);
+}
+
static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode,
phy_interface_t interface,
const unsigned long *advertising,
@@ -128,12 +163,14 @@ static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode,
struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
bool mode_changed = false, changed;
unsigned int rgc3, sgm_mode, bmcr;
- int advertise, link_timer;
+ int link_timer;
- advertise = phylink_mii_c22_pcs_encode_advertisement(interface,
- advertising);
- if (advertise < 0)
- return advertise;
+ if (advertising) {
+ mpcs->advertise = phylink_mii_c22_pcs_encode_advertisement(interface,
+ advertising);
+ if (mpcs->advertise < 0)
+ return mpcs->advertise;
+ }
/* Clearing IF_MODE_BIT0 switches the PCS to BASE-X mode, and
* we assume that fixes it's speed at bitrate = line rate (in
@@ -165,6 +202,10 @@ static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode,
SGMII_PHYA_PWD);
/* Reset SGMII PCS state */
+ if (mpcs->xfi_tphy)
+ phy_reset(mpcs->xfi_tphy);
+
+ mtk_sgmii_reset(mpcs);
regmap_set_bits(mpcs->regmap, SGMSYS_RESERVED_0,
SGMII_SW_RESET);
@@ -192,7 +233,7 @@ static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode,
/* Update the advertisement, noting whether it has changed */
regmap_update_bits_check(mpcs->regmap, SGMSYS_PCS_ADVERTISE,
- SGMII_ADVERTISE, advertise, &changed);
+ SGMII_ADVERTISE, mpcs->advertise, &changed);
/* Update the sgmsys mode register */
regmap_update_bits(mpcs->regmap, SGMSYS_SGMII_MODE,
@@ -215,6 +256,10 @@ static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode,
usleep_range(50, 100);
regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
+ /* Setup PMA/PMD */
+ if (mpcs->xfi_tphy)
+ phy_set_mode_ext(mpcs->xfi_tphy, PHY_MODE_ETHERNET, interface);
+
return changed || mode_changed;
}
@@ -233,6 +278,11 @@ static void mtk_pcs_lynxi_link_up(struct phylink_pcs *pcs,
struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
unsigned int sgm_mode;
+ if (mpcs->xfi_tphy) {
+ phy_reset(mpcs->xfi_tphy);
+ phy_set_mode_ext(mpcs->xfi_tphy, PHY_MODE_ETHERNET, interface);
+ }
+
if (neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) {
/* Force the speed and duplex setting */
if (speed == SPEED_10)
@@ -249,13 +299,39 @@ static void mtk_pcs_lynxi_link_up(struct phylink_pcs *pcs,
SGMII_DUPLEX_HALF | SGMII_SPEED_MASK,
sgm_mode);
}
+
+ mtk_pcs_lynxi_config(pcs, neg_mode, interface, NULL, false);
+}
+
+static int mtk_pcs_lynxi_enable(struct phylink_pcs *pcs)
+{
+ struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
+
+ if (mpcs->sgmii_tx && mpcs->sgmii_rx) {
+ clk_prepare_enable(mpcs->sgmii_rx);
+ clk_prepare_enable(mpcs->sgmii_tx);
+ }
+
+ if (mpcs->xfi_tphy)
+ phy_power_on(mpcs->xfi_tphy);
+
+ return 0;
}
static void mtk_pcs_lynxi_disable(struct phylink_pcs *pcs)
{
struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
+ regmap_set_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
+
+ if (mpcs->sgmii_tx && mpcs->sgmii_rx) {
+ clk_disable_unprepare(mpcs->sgmii_tx);
+ clk_disable_unprepare(mpcs->sgmii_rx);
+ }
+
mpcs->interface = PHY_INTERFACE_MODE_NA;
+ if (mpcs->xfi_tphy)
+ phy_power_off(mpcs->xfi_tphy);
}
static const struct phylink_pcs_ops mtk_pcs_lynxi_ops = {
@@ -265,11 +341,12 @@ static const struct phylink_pcs_ops mtk_pcs_lynxi_ops = {
.pcs_an_restart = mtk_pcs_lynxi_restart_an,
.pcs_link_up = mtk_pcs_lynxi_link_up,
.pcs_disable = mtk_pcs_lynxi_disable,
+ .pcs_enable = mtk_pcs_lynxi_enable,
};
-struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev,
- struct regmap *regmap, u32 ana_rgc3,
- u32 flags)
+static struct phylink_pcs *mtk_pcs_lynxi_init(struct device *dev, struct regmap *regmap,
+ u32 ana_rgc3, u32 flags,
+ struct mtk_pcs_lynxi *prealloc)
{
struct mtk_pcs_lynxi *mpcs;
u32 id, ver;
@@ -277,29 +354,33 @@ struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev,
ret = regmap_read(regmap, SGMSYS_PCS_DEVICE_ID, &id);
if (ret < 0)
- return NULL;
+ return ERR_PTR(ret);
if (id != SGMII_LYNXI_DEV_ID) {
dev_err(dev, "unknown PCS device id %08x\n", id);
- return NULL;
+ return ERR_PTR(-ENODEV);
}
ret = regmap_read(regmap, SGMSYS_PCS_SCRATCH, &ver);
if (ret < 0)
- return NULL;
+ return ERR_PTR(ret);
ver = FIELD_GET(SGMII_DEV_VERSION, ver);
if (ver != 0x1) {
dev_err(dev, "unknown PCS device version %04x\n", ver);
- return NULL;
+ return ERR_PTR(-ENODEV);
}
dev_dbg(dev, "MediaTek LynxI SGMII PCS (id 0x%08x, ver 0x%04x)\n", id,
ver);
- mpcs = kzalloc(sizeof(*mpcs), GFP_KERNEL);
- if (!mpcs)
- return NULL;
+ if (prealloc) {
+ mpcs = prealloc;
+ } else {
+ mpcs = kzalloc(sizeof(*mpcs), GFP_KERNEL);
+ if (!mpcs)
+ return ERR_PTR(-ENOMEM);
+ };
mpcs->ana_rgc3 = ana_rgc3;
mpcs->regmap = regmap;
@@ -313,6 +394,13 @@ struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev,
__set_bit(PHY_INTERFACE_MODE_2500BASEX, mpcs->pcs.supported_interfaces);
return &mpcs->pcs;
+};
+
+struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev,
+ struct regmap *regmap, u32 ana_rgc3,
+ u32 flags)
+{
+ return mtk_pcs_lynxi_init(dev, regmap, ana_rgc3, flags, NULL);
}
EXPORT_SYMBOL(mtk_pcs_lynxi_create);
@@ -325,5 +413,89 @@ void mtk_pcs_lynxi_destroy(struct phylink_pcs *pcs)
}
EXPORT_SYMBOL(mtk_pcs_lynxi_destroy);
+#ifdef CONFIG_FWNODE_PCS
+static int mtk_pcs_lynxi_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct mtk_pcs_lynxi *mpcs;
+ struct phylink_pcs *pcs;
+ struct regmap *regmap;
+ u32 flags = 0;
+
+ mpcs = devm_kzalloc(dev, sizeof(*mpcs), GFP_KERNEL);
+ if (!mpcs)
+ return -ENOMEM;
+
+ mpcs->dev = dev;
+ regmap = syscon_node_to_regmap(np->parent);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ if (of_property_read_bool(np->parent, "mediatek,pnswap"))
+ flags |= MTK_SGMII_FLAG_PN_SWAP;
+
+ mpcs->rstc = of_reset_control_get_shared(np->parent, NULL);
+ if (IS_ERR(mpcs->rstc))
+ return PTR_ERR(mpcs->rstc);
+
+ reset_control_deassert(mpcs->rstc);
+ mpcs->sgmii_sel = devm_clk_get_enabled(dev, "sgmii_sel");
+ if (IS_ERR(mpcs->sgmii_sel))
+ return PTR_ERR(mpcs->sgmii_sel);
+
+ mpcs->sgmii_rx = devm_clk_get(dev, "sgmii_rx");
+ if (IS_ERR(mpcs->sgmii_rx))
+ return PTR_ERR(mpcs->sgmii_rx);
+
+ mpcs->sgmii_tx = devm_clk_get(dev, "sgmii_tx");
+ if (IS_ERR(mpcs->sgmii_tx))
+ return PTR_ERR(mpcs->sgmii_tx);
+
+ mpcs->xfi_tphy = devm_of_phy_get(mpcs->dev, np, NULL);
+ if (IS_ERR(mpcs->xfi_tphy))
+ return PTR_ERR(mpcs->xfi_tphy);
+
+ pcs = mtk_pcs_lynxi_init(dev, regmap, (uintptr_t)of_device_get_match_data(dev),
+ flags, mpcs);
+ if (IS_ERR(pcs))
+ return PTR_ERR(pcs);
+
+ regmap_set_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
+
+ platform_set_drvdata(pdev, mpcs);
+
+ return fwnode_pcs_add_provider(of_fwnode_handle(np), fwnode_pcs_simple_get, &mpcs->pcs);
+}
+
+static void mtk_pcs_lynxi_remove(struct platform_device *pdev)
+{
+ struct mtk_pcs_lynxi *mpcs = platform_get_drvdata(pdev);
+
+ fwnode_pcs_del_provider(dev_fwnode(&pdev->dev));
+
+ rtnl_lock();
+ phylink_release_pcs(&mpcs->pcs);
+ rtnl_unlock();
+};
+
+static const struct of_device_id mtk_pcs_lynxi_of_match[] = {
+ { .compatible = "mediatek,mt7988-sgmii", .data = (void *)MTK_NETSYS_V3_AMA_RGC3 },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, mtk_pcs_lynxi_of_match);
+
+static struct platform_driver mtk_pcs_lynxi_driver = {
+ .driver = {
+ .name = "mtk-pcs-lynxi",
+ .of_match_table = mtk_pcs_lynxi_of_match,
+ },
+ .probe = mtk_pcs_lynxi_probe,
+ .remove = mtk_pcs_lynxi_remove,
+};
+module_platform_driver(mtk_pcs_lynxi_driver);
+#endif
+
+MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
MODULE_DESCRIPTION("MediaTek SGMII library for LynxI");
MODULE_LICENSE("GPL");
--
2.30.2

87
patch/kernel/archive/filogic-6.16/patches.armbian/0062-dt-bindings-net-pcs-add-bindings-for-MediaTek-USXGMI.patch Normal file
View File

@ -0,0 +1,87 @@
From 7a515019768258fa8183fd1784745197a5bc45d3 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Tue, 12 Dec 2023 03:47:31 +0000
Subject: [PATCH 62/84] dt-bindings: net: pcs: add bindings for MediaTek
USXGMII PCS
MediaTek's USXGMII can be found in the MT7988 SoC. We need to access
it in order to configure and monitor the Ethernet SerDes link in
USXGMII, 10GBase-R and 5GBase-R mode. By including a wrapped
legacy 1000Base-X/2500Base-X/Cisco SGMII LynxI PCS as well, those
interface modes are also available.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
.../bindings/net/pcs/mediatek,usxgmii.yaml | 60 +++++++++++++++++++
1 file changed, 60 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml
diff --git a/Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml b/Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml
new file mode 100644
index 000000000000..0cdaa3545edb
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/pcs/mediatek,usxgmii.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek USXGMII PCS
+
+maintainers:
+ - Daniel Golle <daniel@makrotopia.org>
+
+description:
+ The MediaTek USXGMII PCS provides physical link control and status
+ for USXGMII, 10GBase-R and 5GBase-R links on the SerDes interfaces
+ provided by the PEXTP PHY.
+ In order to also support legacy 2500Base-X, 1000Base-X and Cisco
+ SGMII an existing mediatek,*-sgmiisys LynxI PCS is wrapped to
+ provide those interfaces modes on the same SerDes interfaces shared
+ with the USXGMII PCS.
+
+properties:
+ $nodename:
+ pattern: "^pcs@[0-9a-f]+$"
+
+ compatible:
+ const: mediatek,mt7988-usxgmiisys
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: USXGMII top-level clock
+
+ resets:
+ items:
+ - description: XFI reset
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mediatek,mt7988-clk.h>
+ #define MT7988_TOPRGU_XFI0_GRST 12
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ usxgmiisys0: pcs@10080000 {
+ compatible = "mediatek,mt7988-usxgmiisys";
+ reg = <0 0x10080000 0 0x1000>;
+ clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>;
+ resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>;
+ };
+ };
--
2.30.2

576
patch/kernel/archive/filogic-6.16/patches.armbian/0063-net-pcs-add-driver-for-MediaTek-USXGMII-PCS.patch Normal file
View File

@ -0,0 +1,576 @@
From 00c9b2059de66096114b0a566ffcb4481aa83f81 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Tue, 12 Dec 2023 03:47:47 +0000
Subject: [PATCH 63/84] net: pcs: add driver for MediaTek USXGMII PCS
Add driver for USXGMII PCS found in the MediaTek MT7988 SoC and supporting
USXGMII, 10GBase-R and 5GBase-R interface modes.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
MAINTAINERS | 2 +
drivers/net/pcs/Kconfig | 12 +
drivers/net/pcs/Kconfig.orig | 55 ++++
drivers/net/pcs/Makefile | 1 +
drivers/net/pcs/pcs-mtk-usxgmii.c | 440 ++++++++++++++++++++++++++++++
5 files changed, 510 insertions(+)
create mode 100644 drivers/net/pcs/Kconfig.orig
create mode 100644 drivers/net/pcs/pcs-mtk-usxgmii.c
diff --git a/MAINTAINERS b/MAINTAINERS
index c0b444e5fd5a..ad3b057e1c43 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -15275,7 +15275,9 @@ M: Daniel Golle <daniel@makrotopia.org>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/pcs/pcs-mtk-lynxi.c
+F: drivers/net/pcs/pcs-mtk-usxgmii.c
F: include/linux/pcs/pcs-mtk-lynxi.h
+F: include/linux/pcs/pcs-mtk-usxgmii.h
MEDIATEK ETHERNET PHY DRIVERS
M: Daniel Golle <daniel@makrotopia.org>
diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig
index 69d28cd1e624..a63c910da105 100644
--- a/drivers/net/pcs/Kconfig
+++ b/drivers/net/pcs/Kconfig
@@ -39,6 +39,18 @@ config PCS_MTK_LYNXI
This module provides helpers to phylink for managing the LynxI PCS
which is part of MediaTek's SoC and Ethernet switch ICs.
+config PCS_MTK_USXGMII
+ tristate "MediaTek USXGMII PCS"
+ select FWNODE_PCS
+ select PCS_MTK_LYNXI
+ select PHYLINK
+ imply PHY_MTK_PEXTP
+ help
+ This module provides a driver for MediaTek's USXGMII PCS supporting
+ 10GBase-R, 5GBase-R and USXGMII interface modes.
+ 1000Base-X, 2500Base-X and Cisco SGMII are supported on the same
+ differential pairs via an embedded LynxI PCS.
+
config PCS_RZN1_MIIC
tristate "Renesas RZ/N1 MII converter"
depends on OF && (ARCH_RZN1 || COMPILE_TEST)
diff --git a/drivers/net/pcs/Kconfig.orig b/drivers/net/pcs/Kconfig.orig
new file mode 100644
index 000000000000..4f26acc7d47a
--- /dev/null
+++ b/drivers/net/pcs/Kconfig.orig
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# PCS Layer Configuration
+#
+
+menu "PCS device drivers"
+
+config OF_PCS
+ tristate
+ depends on OF
+ depends on PHYLINK
+ help
+ OpenFirmware PCS accessors
+
+config PCS_XPCS
+ tristate "Synopsys DesignWare Ethernet XPCS"
+ select PHYLINK
+ help
+ This module provides a driver and helper functions for Synopsys
+ DesignWare XPCS controllers.
+
+config PCS_LYNX
+ tristate
+ help
+ This module provides helpers to phylink for managing the Lynx PCS
+ which is part of the Layerscape and QorIQ Ethernet SERDES.
+
+config PCS_MTK_LYNXI
+ tristate
+ select REGMAP
+ help
+ This module provides helpers to phylink for managing the LynxI PCS
+ which is part of MediaTek's SoC and Ethernet switch ICs.
+
+config PCS_MTK_USXGMII
+ tristate "MediaTek USXGMII PCS"
+ select OF_PCS
+ select PCS_MTK_LYNXI
+ select PHY_MTK_PEXTP
+ select PHYLINK
+ help
+ This module provides a driver for MediaTek's USXGMII PCS supporting
+ 10GBase-R, 5GBase-R and USXGMII interface modes.
+ 1000Base-X, 2500Base-X and Cisco SGMII are supported on the same
+ differential pairs via an embedded LynxI PHY.
+
+config PCS_RZN1_MIIC
+ tristate "Renesas RZ/N1 MII converter"
+ depends on OF && (ARCH_RZN1 || COMPILE_TEST)
+ help
+ This module provides a driver for the MII converter that is available
+ on RZ/N1 SoCs. This PCS converts MII to RMII/RGMII or can be set in
+ pass-through mode for MII.
+
+endmenu
diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile
index c48450f08fb7..8492324b84e5 100644
--- a/drivers/net/pcs/Makefile
+++ b/drivers/net/pcs/Makefile
@@ -9,4 +9,5 @@ pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs.o pcs-xpcs-plat.o \
obj-$(CONFIG_PCS_XPCS) += pcs_xpcs.o
obj-$(CONFIG_PCS_LYNX) += pcs-lynx.o
obj-$(CONFIG_PCS_MTK_LYNXI) += pcs-mtk-lynxi.o
+obj-$(CONFIG_PCS_MTK_USXGMII) += pcs-mtk-usxgmii.o
obj-$(CONFIG_PCS_RZN1_MIIC) += pcs-rzn1-miic.o
diff --git a/drivers/net/pcs/pcs-mtk-usxgmii.c b/drivers/net/pcs/pcs-mtk-usxgmii.c
new file mode 100644
index 000000000000..c2fa0ba8fcc7
--- /dev/null
+++ b/drivers/net/pcs/pcs-mtk-usxgmii.c
@@ -0,0 +1,440 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 MediaTek Inc.
+ * Author: Henry Yen <henry.yen@mediatek.com>
+ * Daniel Golle <daniel@makrotopia.org>
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mdio.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/reset.h>
+#include <linux/pcs/pcs-provider.h>
+#include <linux/phy/phy.h>
+#include <linux/phylink.h>
+#include <linux/platform_device.h>
+#include <linux/rtnetlink.h>
+
+/* USXGMII subsystem config registers */
+/* Register to control speed */
+#define RG_PHY_TOP_SPEED_CTRL1 0x80c
+#define USXGMII_RATE_UPDATE_MODE BIT(31)
+#define USXGMII_MAC_CK_GATED BIT(29)
+#define USXGMII_IF_FORCE_EN BIT(28)
+#define USXGMII_RATE_ADAPT_MODE GENMASK(10, 8)
+#define USXGMII_RATE_ADAPT_MODE_X1 0
+#define USXGMII_RATE_ADAPT_MODE_X2 1
+#define USXGMII_RATE_ADAPT_MODE_X4 2
+#define USXGMII_RATE_ADAPT_MODE_X10 3
+#define USXGMII_RATE_ADAPT_MODE_X100 4
+#define USXGMII_RATE_ADAPT_MODE_X5 5
+#define USXGMII_RATE_ADAPT_MODE_X50 6
+#define USXGMII_XFI_RX_MODE GENMASK(6, 4)
+#define USXGMII_XFI_TX_MODE GENMASK(2, 0)
+#define USXGMII_XFI_MODE_10G 0
+#define USXGMII_XFI_MODE_5G 1
+#define USXGMII_XFI_MODE_2P5G 3
+
+/* Register to control PCS AN */
+#define RG_PCS_AN_CTRL0 0x810
+#define USXGMII_AN_RESTART BIT(31)
+#define USXGMII_AN_SYNC_CNT GENMASK(30, 11)
+#define USXGMII_AN_ENABLE BIT(0)
+
+#define RG_PCS_AN_CTRL2 0x818
+#define USXGMII_LINK_TIMER_IDLE_DETECT GENMASK(29, 20)
+#define USXGMII_LINK_TIMER_COMP_ACK_DETECT GENMASK(19, 10)
+#define USXGMII_LINK_TIMER_AN_RESTART GENMASK(9, 0)
+
+/* Register to read PCS AN status */
+#define RG_PCS_AN_STS0 0x81c
+#define USXGMII_LPA GENMASK(15, 0)
+#define USXGMII_LPA_LATCH BIT(31)
+
+/* Register to read PCS link status */
+#define RG_PCS_RX_STATUS0 0x904
+#define RG_PCS_RX_STATUS_UPDATE BIT(16)
+#define RG_PCS_RX_LINK_STATUS BIT(2)
+
+/* struct mtk_usxgmii_pcs - This structure holds each usxgmii PCS
+ * @pcs: Phylink PCS structure
+ * @dev: Pointer to device structure
+ * @base: IO memory to access PCS hardware
+ * @clk: Pointer to USXGMII clk
+ * @reset: Pointer to USXGMII reset control
+ * @interface: Currently selected interface mode
+ * @neg_mode: Currently used phylink neg_mode
+ * @node: List node
+ */
+struct mtk_usxgmii_pcs {
+ struct phylink_pcs pcs;
+ struct device *dev;
+ void __iomem *base;
+ struct clk *clk;
+ struct reset_control *reset;
+ struct phy *xfi_tphy;
+ phy_interface_t interface;
+ unsigned int neg_mode;
+ struct list_head node;
+};
+
+static u32 mtk_r32(struct mtk_usxgmii_pcs *mpcs, unsigned int reg)
+{
+ return ioread32(mpcs->base + reg);
+}
+
+static void mtk_m32(struct mtk_usxgmii_pcs *mpcs, unsigned int reg, u32 mask, u32 set)
+{
+ u32 val;
+
+ val = ioread32(mpcs->base + reg);
+ val &= ~mask;
+ val |= set;
+ iowrite32(val, mpcs->base + reg);
+}
+
+static struct mtk_usxgmii_pcs *pcs_to_mtk_usxgmii_pcs(struct phylink_pcs *pcs)
+{
+ return container_of(pcs, struct mtk_usxgmii_pcs, pcs);
+}
+
+static void mtk_usxgmii_reset(struct mtk_usxgmii_pcs *mpcs)
+{
+ reset_control_assert(mpcs->reset);
+ udelay(100);
+ reset_control_deassert(mpcs->reset);
+
+ mdelay(10);
+}
+
+static int mtk_usxgmii_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ phy_interface_t interface,
+ const unsigned long *advertising,
+ bool permit_pause_to_mac)
+{
+ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
+ unsigned int an_ctrl = 0, link_timer = 0, xfi_mode = 0, adapt_mode = 0;
+ bool mode_changed = false;
+
+ if (interface == PHY_INTERFACE_MODE_USXGMII) {
+ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF) | USXGMII_AN_ENABLE;
+ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
+ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
+ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
+ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_MODE_10G) |
+ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_MODE_10G);
+ } else if (interface == PHY_INTERFACE_MODE_10GBASER) {
+ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF);
+ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
+ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
+ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
+ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_MODE_10G) |
+ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_MODE_10G);
+ adapt_mode = USXGMII_RATE_UPDATE_MODE;
+ } else if (interface == PHY_INTERFACE_MODE_5GBASER) {
+ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0xFF);
+ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x3D) |
+ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x3D) |
+ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x3D);
+ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_MODE_5G) |
+ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_MODE_5G);
+ adapt_mode = USXGMII_RATE_UPDATE_MODE;
+ } else {
+ return -EINVAL;
+ }
+
+ adapt_mode |= FIELD_PREP(USXGMII_RATE_ADAPT_MODE, USXGMII_RATE_ADAPT_MODE_X1);
+
+ if (mpcs->interface != interface) {
+ mpcs->interface = interface;
+ mode_changed = true;
+ }
+
+ phy_reset(mpcs->xfi_tphy);
+ mtk_usxgmii_reset(mpcs);
+
+ /* Setup USXGMII AN ctrl */
+ mtk_m32(mpcs, RG_PCS_AN_CTRL0,
+ USXGMII_AN_SYNC_CNT | USXGMII_AN_ENABLE,
+ an_ctrl);
+
+ mtk_m32(mpcs, RG_PCS_AN_CTRL2,
+ USXGMII_LINK_TIMER_IDLE_DETECT |
+ USXGMII_LINK_TIMER_COMP_ACK_DETECT |
+ USXGMII_LINK_TIMER_AN_RESTART,
+ link_timer);
+
+ mpcs->neg_mode = neg_mode;
+
+ /* Gated MAC CK */
+ mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
+ USXGMII_MAC_CK_GATED, USXGMII_MAC_CK_GATED);
+
+ /* Enable interface force mode */
+ mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
+ USXGMII_IF_FORCE_EN, USXGMII_IF_FORCE_EN);
+
+ /* Setup USXGMII adapt mode */
+ mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
+ USXGMII_RATE_UPDATE_MODE | USXGMII_RATE_ADAPT_MODE,
+ adapt_mode);
+
+ /* Setup USXGMII speed */
+ mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
+ USXGMII_XFI_RX_MODE | USXGMII_XFI_TX_MODE,
+ xfi_mode);
+
+ usleep_range(1, 10);
+
+ /* Un-gated MAC CK */
+ mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1, USXGMII_MAC_CK_GATED, 0);
+
+ usleep_range(1, 10);
+
+ /* Disable interface force mode for the AN mode */
+ if (an_ctrl & USXGMII_AN_ENABLE)
+ mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1, USXGMII_IF_FORCE_EN, 0);
+
+ /* Setup PMA/PMD */
+ phy_set_mode_ext(mpcs->xfi_tphy, PHY_MODE_ETHERNET, interface);
+
+ return mode_changed;
+}
+
+static void mtk_usxgmii_pcs_get_fixed_speed(struct mtk_usxgmii_pcs *mpcs,
+ struct phylink_link_state *state)
+{
+ u32 val = mtk_r32(mpcs, RG_PHY_TOP_SPEED_CTRL1);
+ int speed;
+
+ /* Calculate speed from interface speed and rate adapt mode */
+ switch (FIELD_GET(USXGMII_XFI_RX_MODE, val)) {
+ case USXGMII_XFI_MODE_10G:
+ speed = 10000;
+ break;
+ case USXGMII_XFI_MODE_5G:
+ speed = 5000;
+ break;
+ case USXGMII_XFI_MODE_2P5G:
+ speed = 2500;
+ break;
+ default:
+ state->speed = SPEED_UNKNOWN;
+ return;
+ }
+
+ switch (FIELD_GET(USXGMII_RATE_ADAPT_MODE, val)) {
+ case USXGMII_RATE_ADAPT_MODE_X100:
+ speed /= 100;
+ break;
+ case USXGMII_RATE_ADAPT_MODE_X50:
+ speed /= 50;
+ break;
+ case USXGMII_RATE_ADAPT_MODE_X10:
+ speed /= 10;
+ break;
+ case USXGMII_RATE_ADAPT_MODE_X5:
+ speed /= 5;
+ break;
+ case USXGMII_RATE_ADAPT_MODE_X4:
+ speed /= 4;
+ break;
+ case USXGMII_RATE_ADAPT_MODE_X2:
+ speed /= 2;
+ break;
+ case USXGMII_RATE_ADAPT_MODE_X1:
+ break;
+ default:
+ state->speed = SPEED_UNKNOWN;
+ return;
+ }
+
+ state->speed = speed;
+ state->duplex = DUPLEX_FULL;
+}
+
+static void mtk_usxgmii_pcs_get_an_state(struct mtk_usxgmii_pcs *mpcs,
+ struct phylink_link_state *state)
+{
+ u16 lpa;
+
+ /* Refresh LPA by toggling LPA_LATCH */
+ mtk_m32(mpcs, RG_PCS_AN_STS0, USXGMII_LPA_LATCH, USXGMII_LPA_LATCH);
+ ndelay(1020);
+ mtk_m32(mpcs, RG_PCS_AN_STS0, USXGMII_LPA_LATCH, 0);
+ ndelay(1020);
+ lpa = FIELD_GET(USXGMII_LPA, mtk_r32(mpcs, RG_PCS_AN_STS0));
+
+ phylink_decode_usxgmii_word(state, lpa);
+}
+
+static void mtk_usxgmii_pcs_get_state(struct phylink_pcs *pcs,
+ unsigned int neg_mode,
+ struct phylink_link_state *state)
+{
+ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
+
+ /* Refresh USXGMII link status by toggling RG_PCS_AN_STATUS_UPDATE */
+ mtk_m32(mpcs, RG_PCS_RX_STATUS0, RG_PCS_RX_STATUS_UPDATE,
+ RG_PCS_RX_STATUS_UPDATE);
+ ndelay(1020);
+ mtk_m32(mpcs, RG_PCS_RX_STATUS0, RG_PCS_RX_STATUS_UPDATE, 0);
+ ndelay(1020);
+
+ /* Read USXGMII link status */
+ state->link = FIELD_GET(RG_PCS_RX_LINK_STATUS,
+ mtk_r32(mpcs, RG_PCS_RX_STATUS0));
+
+ /* Continuously repeat re-configuration sequence until link comes up */
+ if (!state->link) {
+ mtk_usxgmii_pcs_config(pcs, mpcs->neg_mode,
+ state->interface, NULL, false);
+ return;
+ }
+
+ if (FIELD_GET(USXGMII_AN_ENABLE, mtk_r32(mpcs, RG_PCS_AN_CTRL0)))
+ mtk_usxgmii_pcs_get_an_state(mpcs, state);
+ else
+ mtk_usxgmii_pcs_get_fixed_speed(mpcs, state);
+}
+
+static void mtk_usxgmii_pcs_restart_an(struct phylink_pcs *pcs)
+{
+ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
+
+ mtk_m32(mpcs, RG_PCS_AN_CTRL0, USXGMII_AN_RESTART, USXGMII_AN_RESTART);
+}
+
+static void mtk_usxgmii_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
+ phy_interface_t interface,
+ int speed, int duplex)
+{
+ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
+
+ /* Reconfiguring USXGMII to ensure the quality of the RX signal
+ * after the line side link up.
+ */
+ mtk_usxgmii_pcs_config(pcs, neg_mode, interface, NULL, false);
+ phy_reset(mpcs->xfi_tphy);
+ phy_set_mode_ext(mpcs->xfi_tphy, PHY_MODE_ETHERNET, interface);
+}
+
+static int mtk_usxgmii_pcs_enable(struct phylink_pcs *pcs)
+{
+ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
+
+ phy_power_on(mpcs->xfi_tphy);
+
+ return 0;
+}
+
+static void mtk_usxgmii_pcs_disable(struct phylink_pcs *pcs)
+{
+ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
+
+ mpcs->interface = PHY_INTERFACE_MODE_NA;
+ mpcs->neg_mode = -1;
+
+ phy_power_off(mpcs->xfi_tphy);
+}
+
+static unsigned int mtk_usxgmii_pcs_inband_caps(struct phylink_pcs *pcs,
+ phy_interface_t interface)
+{
+ switch (interface) {
+ case PHY_INTERFACE_MODE_5GBASER:
+ case PHY_INTERFACE_MODE_10GBASER:
+ case PHY_INTERFACE_MODE_USXGMII:
+ return LINK_INBAND_ENABLE;
+
+ default:
+ return 0;
+ }
+}
+
+static const struct phylink_pcs_ops mtk_usxgmii_pcs_ops = {
+ .pcs_inband_caps = mtk_usxgmii_pcs_inband_caps,
+ .pcs_config = mtk_usxgmii_pcs_config,
+ .pcs_get_state = mtk_usxgmii_pcs_get_state,
+ .pcs_an_restart = mtk_usxgmii_pcs_restart_an,
+ .pcs_link_up = mtk_usxgmii_pcs_link_up,
+ .pcs_enable = mtk_usxgmii_pcs_enable,
+ .pcs_disable = mtk_usxgmii_pcs_disable,
+};
+
+static int mtk_usxgmii_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_usxgmii_pcs *mpcs;
+
+ mpcs = devm_kzalloc(dev, sizeof(*mpcs), GFP_KERNEL);
+ if (!mpcs)
+ return -ENOMEM;
+
+ mpcs->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(mpcs->base))
+ return PTR_ERR(mpcs->base);
+
+ mpcs->dev = dev;
+ mpcs->pcs.ops = &mtk_usxgmii_pcs_ops;
+ mpcs->pcs.poll = true;
+ mpcs->interface = PHY_INTERFACE_MODE_NA;
+ mpcs->neg_mode = -1;
+
+ __set_bit(PHY_INTERFACE_MODE_5GBASER, mpcs->pcs.supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_10GBASER, mpcs->pcs.supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_USXGMII, mpcs->pcs.supported_interfaces);
+
+ mpcs->clk = devm_clk_get_enabled(mpcs->dev, NULL);
+ if (IS_ERR(mpcs->clk))
+ return PTR_ERR(mpcs->clk);
+
+ mpcs->xfi_tphy = devm_of_phy_get(mpcs->dev, dev->of_node, NULL);
+ if (IS_ERR(mpcs->xfi_tphy))
+ return PTR_ERR(mpcs->xfi_tphy);
+
+ mpcs->reset = devm_reset_control_get_shared(dev, NULL);
+ if (IS_ERR(mpcs->reset))
+ return PTR_ERR(mpcs->reset);
+
+ reset_control_deassert(mpcs->reset);
+
+ platform_set_drvdata(pdev, mpcs);
+
+ return fwnode_pcs_add_provider(dev_fwnode(dev), fwnode_pcs_simple_get, &mpcs->pcs);
+}
+
+static void mtk_usxgmii_remove(struct platform_device *pdev)
+{
+ struct mtk_usxgmii_pcs *mpcs = platform_get_drvdata(pdev);
+
+ fwnode_pcs_del_provider(dev_fwnode(&pdev->dev));
+
+ rtnl_lock();
+ phylink_release_pcs(&mpcs->pcs);
+ rtnl_unlock();
+};
+
+static const struct of_device_id mtk_usxgmii_of_mtable[] = {
+ { .compatible = "mediatek,mt7988-usxgmiisys" },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, mtk_usxgmii_of_mtable);
+
+static struct platform_driver mtk_usxgmii_driver = {
+ .driver = {
+ .name = "mtk-pcs-usxgmii",
+ .of_match_table = mtk_usxgmii_of_mtable,
+ },
+ .probe = mtk_usxgmii_probe,
+ .remove = mtk_usxgmii_remove,
+};
+module_platform_driver(mtk_usxgmii_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("MediaTek USXGMII PCS driver");
+MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
--
2.30.2

141
patch/kernel/archive/filogic-6.16/patches.armbian/0064-net-ethernet-mtk_eth_soc-add-more-DMA-monitor-for-MT.patch Normal file
View File

@ -0,0 +1,141 @@
From 67b86aed2e5cad973b8616f685228c03f94ef9b9 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Fri, 1 Sep 2023 12:31:38 +0100
Subject: [PATCH 64/84] net: ethernet: mtk_eth_soc: add more DMA monitor for
MT7988
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 55 +++++++++++++++++++--
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 11 +++++
2 files changed, 61 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index ac7250003b1d..e5f0b9220aa1 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -4022,10 +4022,13 @@ static void mtk_hw_warm_reset(struct mtk_eth *eth)
static bool mtk_hw_check_dma_hang(struct mtk_eth *eth)
{
const struct mtk_reg_map *reg_map = eth->soc->reg_map;
- bool gmac1_tx, gmac2_tx, gdm1_tx, gdm2_tx;
+ bool gmac1_tx, gmac2_tx, gmac3_tx = false, gdm1_tx, gdm2_tx, gdm3_tx = false;
bool oq_hang, cdm1_busy, adma_busy;
bool wtx_busy, cdm_full, oq_free;
- u32 wdidx, val, gdm1_fc, gdm2_fc;
+ u32 wdidx, val, gdm1_fc, gdm2_fc, gdm3_fc;
+ u32 tdma_glo_cfg, cur_fsm, ipq10;
+ bool rx_busy, tx_busy, cur_fsm_tx, cur_fsm_rx;
+
bool qfsm_hang, qfwd_hang;
bool ret = false;
@@ -4061,12 +4064,19 @@ static bool mtk_hw_check_dma_hang(struct mtk_eth *eth)
gdm2_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM2_FSM)) > 0;
gmac1_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(0))) != 1;
gmac2_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(1))) != 1;
- gdm1_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x24);
- gdm2_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x64);
+ gdm1_fc = mtk_r32(eth, reg_map->gdm1_cnt + MTK_GDM_RX_FC_OFFSET(eth, 0));
+ gdm2_fc = mtk_r32(eth, reg_map->gdm1_cnt + MTK_GDM_RX_FC_OFFSET(eth, 1));
+
+ if (mtk_is_netsys_v3_or_greater(eth)) {
+ gdm3_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM3_FSM)) > 0;
+ gmac3_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(2))) != 1;
+ gdm3_fc = mtk_r32(eth, reg_map->gdm1_cnt + MTK_GDM_RX_FC_OFFSET(eth, 2));
+ }
if (qfsm_hang && qfwd_hang &&
((gdm1_tx && gmac1_tx && gdm1_fc < 1) ||
- (gdm2_tx && gmac2_tx && gdm2_fc < 1))) {
+ (gdm2_tx && gmac2_tx && gdm2_fc < 1) ||
+ (mtk_is_netsys_v3_or_greater(eth) && gdm3_tx && gmac3_tx && gdm3_fc < 1))) {
if (++eth->reset.qdma_hang_count > 2) {
eth->reset.qdma_hang_count = 0;
ret = true;
@@ -4088,12 +4098,47 @@ static bool mtk_hw_check_dma_hang(struct mtk_eth *eth)
goto out;
}
+ if (mtk_is_netsys_v3_or_greater(eth)) {
+ ipq10 = mtk_r32(eth, reg_map->pse_iq_sta + 24) & GENMASK(23, 0);
+ cur_fsm = mtk_r32(eth, MTK_FE_CDM6_FSM);
+ tdma_glo_cfg = mtk_r32(eth, MTK_TDMA_GLO_CFG);
+ cur_fsm_rx = !(cur_fsm & GENMASK(27, 16));
+ cur_fsm_tx = !(cur_fsm & GENMASK(24, 0));
+ tx_busy = !(tdma_glo_cfg & BIT(1));
+ rx_busy = !(tdma_glo_cfg & BIT(3));
+
+ if (ipq10 && cur_fsm_tx && tx_busy &&
+ cur_fsm_tx == !!(eth->reset.pre_fsm & GENMASK(24, 0)) &&
+ ipq10 == eth->reset.pre_ipq10) {
+ if (++eth->reset.tdma_tx_hang_count > 2) {
+ eth->reset.tdma_tx_hang_count = 0;
+ ret = true;
+ }
+ goto out;
+ }
+
+ if (cur_fsm_rx && rx_busy &&
+ cur_fsm_rx == (eth->reset.pre_fsm & GENMASK(27, 16))) {
+ if (++eth->reset.tdma_rx_hang_count > 2) {
+ eth->reset.tdma_rx_hang_count = 0;
+ ret = true;
+ }
+ goto out;
+ }
+ }
+
eth->reset.wdma_hang_count = 0;
eth->reset.qdma_hang_count = 0;
eth->reset.adma_hang_count = 0;
+ eth->reset.tdma_tx_hang_count = 0;
+ eth->reset.tdma_rx_hang_count = 0;
out:
eth->reset.wdidx = wdidx;
+ if (mtk_is_netsys_v3_or_greater(eth)) {
+ eth->reset.pre_fsm = cur_fsm;
+ eth->reset.pre_ipq10 = ipq10;
+ }
return ret;
}
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 88406e80dfec..91b2375f9405 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -401,6 +401,8 @@
#define RX_DMA_VTAG_V2 BIT(0)
#define RX_DMA_L4_VALID_V2 BIT(2)
+#define MTK_TDMA_GLO_CFG 0x6204
+
/* PHY Polling and SMI Master Control registers */
#define MTK_PPSC 0x10000
#define PPSC_MDC_CFG GENMASK(29, 24)
@@ -659,6 +661,11 @@
#define MTK_FE_IRQ_RX 1
#define MTK_FE_IRQ_NUM (MTK_FE_IRQ_RX + 1)
+#define MTK_STAT_OFFSET 0x40
+#define MTK_STAT_OFFSET_V3 0x80
+#define MTK_GDM_RX_FC 0x24
+#define MTK_GDM_RX_FC_OFFSET(eth, i) (i * (mtk_is_netsys_v3_or_greater(eth) ? MTK_STAT_OFFSET_V3 : MTK_STAT_OFFSET) + MTK_GDM_RX_FC)
+
struct mtk_rx_dma {
unsigned int rxd1;
unsigned int rxd2;
@@ -1392,6 +1399,10 @@ struct mtk_eth {
u8 wdma_hang_count;
u8 qdma_hang_count;
u8 adma_hang_count;
+ u8 tdma_rx_hang_count;
+ u8 tdma_tx_hang_count;
+ u32 pre_ipq10;
+ u32 pre_fsm;
} reset;
};
--
2.30.2

140
patch/kernel/archive/filogic-6.16/patches.armbian/0065-hwrng-add-driver-for-MediaTek-TRNG-SMC.patch Normal file
View File

@ -0,0 +1,140 @@
From 2d33fddfcc8e36b50910e92bb965a75c4685fb98 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Wed, 25 Jan 2023 00:27:49 +0000
Subject: [PATCH 65/84] hwrng: add driver for MediaTek TRNG SMC
Add driver providing kernel-side support for the Random Number
Generator hardware found on Mediatek SoCs which have a driver in ARM
TrustedFirmware-A allowing Linux to read random numbers using a
non-standard vendor-defined Secure Monitor Call.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/char/hw_random/Kconfig | 16 +++++++
drivers/char/hw_random/Makefile | 1 +
drivers/char/hw_random/mtk-rng-v2.c | 74 +++++++++++++++++++++++++++++
3 files changed, 91 insertions(+)
create mode 100644 drivers/char/hw_random/mtk-rng-v2.c
diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
index c85827843447..1a5fd4a966bd 100644
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -477,6 +477,22 @@ config HW_RANDOM_MTK
If unsure, say Y.
+config HW_RANDOM_MTK_V2
+ tristate "Mediatek Random Number Generator support (v2/SMC)"
+ depends on HW_RANDOM
+ depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
+ default y
+ help
+ This driver provides kernel-side support for the Random Number
+ Generator hardware found on Mediatek SoCs which have a driver
+ in ARM TrustedFirmware-A allowing Linux to read using a non-
+ standard vendor-defined Secure Monitor Call.
+
+ To compile this driver as a module, choose M here. the
+ module will be called mtk-rng-v2.
+
+ If unsure, say Y.
+
config HW_RANDOM_S390
tristate "S390 True Random Number Generator support"
depends on S390
diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
index b9132b3f5d21..1e7ad556e784 100644
--- a/drivers/char/hw_random/Makefile
+++ b/drivers/char/hw_random/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_HW_RANDOM_PIC32) += pic32-rng.o
obj-$(CONFIG_HW_RANDOM_MESON) += meson-rng.o
obj-$(CONFIG_HW_RANDOM_CAVIUM) += cavium-rng.o cavium-rng-vf.o
obj-$(CONFIG_HW_RANDOM_MTK) += mtk-rng.o
+obj-$(CONFIG_HW_RANDOM_MTK_V2) += mtk-rng-v2.o
obj-$(CONFIG_HW_RANDOM_S390) += s390-trng.o
obj-$(CONFIG_HW_RANDOM_KEYSTONE) += ks-sa-rng.o
obj-$(CONFIG_HW_RANDOM_OPTEE) += optee-rng.o
diff --git a/drivers/char/hw_random/mtk-rng-v2.c b/drivers/char/hw_random/mtk-rng-v2.c
new file mode 100644
index 000000000000..6e61f4361d9e
--- /dev/null
+++ b/drivers/char/hw_random/mtk-rng-v2.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Driver for Mediatek Hardware Random Number Generator (v2/SMCC)
+ *
+ * Copyright (C) 2023 Daniel Golle <daniel@makrotopia.org>
+ * based on patch from Mingming Su <Mingming.Su@mediatek.com>
+ */
+#define MTK_RNG_DEV KBUILD_MODNAME
+
+#include <linux/arm-smccc.h>
+#include <linux/err.h>
+#include <linux/hw_random.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk_sip_svc.h>
+
+#define MTK_SIP_KERNEL_GET_RND MTK_SIP_SMC_CMD(0x550)
+
+static int mtk_rng_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+{
+ struct arm_smccc_res res;
+ int retval = 0;
+
+ while (max >= sizeof(u32)) {
+ arm_smccc_smc(MTK_SIP_KERNEL_GET_RND, 0, 0, 0, 0, 0, 0, 0,
+ &res);
+ if (res.a0)
+ break;
+
+ *(u32 *)buf = res.a1;
+ retval += sizeof(u32);
+ buf += sizeof(u32);
+ max -= sizeof(u32);
+ }
+
+ return retval || !wait ? retval : -EIO;
+}
+
+static int mtk_rng_v2_probe(struct platform_device *pdev)
+{
+ struct hwrng *trng;
+
+ trng = devm_kzalloc(&pdev->dev, sizeof(*trng), GFP_KERNEL);
+ if (!trng)
+ return -ENOMEM;
+
+ trng->name = pdev->name;
+ trng->read = mtk_rng_v2_read;
+ trng->quality = 900;
+
+ return devm_hwrng_register(&pdev->dev, trng);
+}
+
+static const struct of_device_id mtk_rng_v2_match[] = {
+ { .compatible = "mediatek,mt7981-rng" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mtk_rng_v2_match);
+
+static struct platform_driver mtk_rng_v2_driver = {
+ .probe = mtk_rng_v2_probe,
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .of_match_table = mtk_rng_v2_match,
+ },
+};
+module_platform_driver(mtk_rng_v2_driver);
+
+MODULE_DESCRIPTION("Mediatek Random Number Generator Driver (v2/SMC)");
+MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
+MODULE_LICENSE("GPL");
--
2.30.2

39
patch/kernel/archive/filogic-6.16/patches.armbian/0066-dts64-enable-sata-and-disable-pcie-slot-CN8-shared.patch Normal file
View File

@ -0,0 +1,39 @@
From 2bb35754b2c9f707d1921952dbc6314ea285f360 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Wed, 27 Nov 2019 17:19:07 +0100
Subject: [PATCH 66/84] dts64: enable sata and disable pcie-slot CN8 (shared)
---
arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
index 9f100b18a676..7e6c5c25cfa1 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -323,7 +323,7 @@ &pio {
asm-sel-hog {
gpio-hog;
gpios = <90 GPIO_ACTIVE_HIGH>;
- output-high;
+ output-low;
};
/* eMMC is shared pin with parallel NAND */
@@ -597,11 +597,11 @@ &pwrap {
};
&sata {
- status = "disabled";
+ status = "okay";
};
&sata_phy {
- status = "disabled";
+ status = "okay";
};
&spi0 {
--
2.30.2

29
patch/kernel/archive/filogic-6.16/patches.armbian/0067-arm64-dts-mt7622-fix-sata.patch Normal file
View File

@ -0,0 +1,29 @@
From 951a242f5e95fc590e383ba9c9f0a91f3313b49d Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Thu, 27 Jun 2024 22:48:27 +0200
Subject: [PATCH 67/84] arm64: dts: mt7622: fix sata
[ 2.480551] ahci-mtk 1a200000.sata: missing phy-mode phandle
[ 2.486249] ahci-mtk 1a200000.sata: probe with driver ahci-mtk failed with error -22
Fixes: 3ba5a6159434 ("arm64: dts: mediatek: mt7622: fix clock controllers")
---
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index 917fa39a74f8..f22983c33365 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -790,7 +790,7 @@ u2port1: usb-phy@1a0c5000 {
};
pciesys: clock-controller@1a100800 {
- compatible = "mediatek,mt7622-pciesys";
+ compatible = "mediatek,mt7622-pciesys","syscon";
reg = <0 0x1a100800 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
--
2.30.2

65
patch/kernel/archive/filogic-6.16/patches.armbian/0068-kdeb-try-to-add-kernels-for-bpi-boards-to-deb-packag.patch Normal file
View File

@ -0,0 +1,65 @@
From b8a589bd3322f55d7642e2c32f5aceb33c792e6e Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Sun, 14 Jan 2024 14:47:21 +0100
Subject: [PATCH 68/84] kdeb: try to add kernels for bpi-boards to deb-packages
---
scripts/package/builddeb | 41 ++++++++++++++++++++++++++++++++++++++--
1 file changed, 39 insertions(+), 2 deletions(-)
diff --git a/scripts/package/builddeb b/scripts/package/builddeb
index 3627ca227e5a..4c2142959768 100755
--- a/scripts/package/builddeb
+++ b/scripts/package/builddeb
@@ -61,9 +61,46 @@ install_linux_image () {
parisc|mips|powerpc)
installed_image_path="boot/vmlinux-${KERNELRELEASE}";;
*)
- installed_image_path="boot/vmlinuz-${KERNELRELEASE}";;
+ source_image_path="./$board.itb"
+ installed_image_path=boot/$board-${KERNELRELEASE}.itb
+ case $board in
+ bpi-r2)
+ mkdir -p "${pdir}/boot/bananapi/$board/linux/dtb"
+ DTBFILE=arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dtb
+ cp ${srctree}/uImage_nodt "${pdir}/boot/bananapi/$board/linux/uImage-${KERNELRELEASE}_nodt"
+ source_image_path="${srctree}/uImage"
+ installed_image_path="boot/bananapi/$board/linux/uImage-${KERNELRELEASE}"
+ ;;
+ bpi-r64)
+ mkdir -p "${pdir}/boot/bananapi/$board/linux/dtb"
+ DTBFILE=arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dtb
+ cp ${srctree}/uImage_nodt "${pdir}/boot/bananapi/$board/linux/uImage-${KERNELRELEASE}_nodt"
+ ;;
+ bpi-r2pro)
+ DTBFILE=arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dtb
+ mkdir -p ${pdir}/boot/extlinux/
+ cp arch/arm64/boot/Image.gz "${pdir}/boot/extlinux/Image-${KERNELRELEASE}.gz"
+ ;;
+ bpi-r3|bpi-r4)
+ #R3/R4 only use FIT and no standalone kernel/dtbs
+ ;;
+ *)
+ installed_image_path="boot/vmlinuz-${KERNELRELEASE}"
+ source_image_path="$($MAKE -s -f ${srctree}/Makefile image_name)"
+ ;;
+ esac
+ ;;
esac
- cp "$(${MAKE} -s -f ${srctree}/Makefile image_name)" "${pdir}/${installed_image_path}"
+
+ if [ -n "$DTBFILE" ];then
+ if [ $board != "bpi-r2pro" ];then
+ cp $DTBFILE "${pdir}/boot/bananapi/$board/linux/dtb/$board-${KERNELRELEASE}.dtb"
+ else
+ cp $DTBFILE "${pdir}/boot/extlinux/$board-${KERNELRELEASE}.dtb"
+ fi
+ fi
+
+ cp "${source_image_path}" "${pdir}/${installed_image_path}"
if [ "${ARCH}" != um ]; then
install_maint_scripts "${pdir}"
--
2.30.2

26
patch/kernel/archive/filogic-6.16/patches.armbian/0069-kdeb-fix-deb-build-for-R3-R4.patch Normal file
View File

@ -0,0 +1,26 @@
From 7483e1ad82099905e2f462be333074c8f8942f13 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 22 Apr 2025 19:45:32 +0200
Subject: [PATCH 69/84] kdeb: fix deb build for R3+R4
due to the set +u unassigned variables will be handled as error
and so build fails.
---
scripts/package/builddeb | 1 +
1 file changed, 1 insertion(+)
diff --git a/scripts/package/builddeb b/scripts/package/builddeb
index 4c2142959768..11429129e044 100755
--- a/scripts/package/builddeb
+++ b/scripts/package/builddeb
@@ -63,6 +63,7 @@ install_linux_image () {
*)
source_image_path="./$board.itb"
installed_image_path=boot/$board-${KERNELRELEASE}.itb
+ DTBFILE=""
case $board in
bpi-r2)
mkdir -p "${pdir}/boot/bananapi/$board/linux/dtb"
--
2.30.2

25
patch/kernel/archive/filogic-6.16/patches.armbian/0070-build.conf-change-to-r4.patch Normal file
View File

@ -0,0 +1,25 @@
From 0df363d725b08ae1b2d848415ce2384da6556d20 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Sat, 21 Jun 2025 15:00:03 +0200
Subject: [PATCH 70/84] build.conf: change to r4
---
build.conf | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/build.conf b/build.conf
index c6521172e2da..0dc98280f6fa 100644
--- a/build.conf
+++ b/build.conf
@@ -13,7 +13,7 @@ board=bpi-r2
#board=bpi-r64
#board=bpi-r2pro
#board=bpi-r3
-#board=bpi-r4
+board=bpi-r4
#r64 with rtl8367
#boardversion=v0.1
--
2.30.2

22
patch/kernel/archive/filogic-6.16/patches.armbian/0071-defconfig-r4-disable-STRICT_DEVMEM-to-allow-register.patch Normal file
View File

@ -0,0 +1,22 @@
From cc587f5c5de71d50be7d030529e381e1f7c5028a Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Thu, 12 Jun 2025 20:38:59 +0200
Subject: [PATCH 71/84] defconfig: r4: disable STRICT_DEVMEM to allow
register-reads
---
arch/arm64/configs/mt7988a_bpi-r4_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/mt7988a_bpi-r4_defconfig b/arch/arm64/configs/mt7988a_bpi-r4_defconfig
index 29bc60ce564f..8447280fcd8b 100644
--- a/arch/arm64/configs/mt7988a_bpi-r4_defconfig
+++ b/arch/arm64/configs/mt7988a_bpi-r4_defconfig
@@ -1308,3 +1308,4 @@ CONFIG_MEDIATEK_2P5GE_PHY=m
#CONFIG_FB_MODE_HELPERS=y
#CONFIG_DRM_PANEL_MIPI_DBI=m
#CONFIG_BACKLIGHT_PWM=m
+CONFIG_STRICT_DEVMEM=n
--
2.30.2

125
patch/kernel/archive/filogic-6.16/patches.armbian/0072-net-ethernet-mtk_eth_soc-add-register-definitions-fo.patch Normal file
View File

@ -0,0 +1,125 @@
From 3dd0307c7129a0b1cc7616eec7500d12f1955f2c Mon Sep 17 00:00:00 2001
From: Mason Chang <mason-cw.chang@mediatek.com>
Date: Tue, 18 Mar 2025 14:09:26 +0800
Subject: [PATCH 72/84] net: ethernet: mtk_eth_soc: add register definitions
for rss and lro
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 25 +++++++++++++++-
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 32 +++++++++++++++------
2 files changed, 47 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index e5f0b9220aa1..98d700c55d73 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -52,13 +52,18 @@ static const struct mtk_reg_map mtk_reg_map = {
.rx_ptr = 0x0900,
.rx_cnt_cfg = 0x0904,
.pcrx_ptr = 0x0908,
+ .lro_ctrl_dw0 = 0x0980,
.glo_cfg = 0x0a04,
.rst_idx = 0x0a08,
.delay_irq = 0x0a0c,
.irq_status = 0x0a20,
.irq_mask = 0x0a28,
.adma_rx_dbg0 = 0x0a38,
- .int_grp = 0x0a50,
+ .lro_alt_score_delta = 0x0a4c,
+ .int_grp = 0x0a50,
+ .lro_rx1_dly_int = 0x0a70,
+ .lro_ring_dip_dw0 = 0x0b04,
+ .lro_ring_ctrl_dw1 = 0x0b28,
},
.qdma = {
.qtx_cfg = 0x1800,
@@ -115,6 +120,7 @@ static const struct mtk_reg_map mt7986_reg_map = {
.tx_irq_mask = 0x461c,
.tx_irq_status = 0x4618,
.pdma = {
+ .rss_glo_cfg = 0x2800,
.rx_ptr = 0x4100,
.rx_cnt_cfg = 0x4104,
.pcrx_ptr = 0x4108,
@@ -125,6 +131,12 @@ static const struct mtk_reg_map mt7986_reg_map = {
.irq_mask = 0x4228,
.adma_rx_dbg0 = 0x4238,
.int_grp = 0x4250,
+ .int_grp3 = 0x422c,
+ .lro_ctrl_dw0 = 0x4180,
+ .lro_alt_score_delta = 0x424c,
+ .lro_rx1_dly_int = 0x4270,
+ .lro_ring_dip_dw0 = 0x4304,
+ .lro_ring_ctrl_dw1 = 0x4328,
},
.qdma = {
.qtx_cfg = 0x4400,
@@ -172,10 +184,21 @@ static const struct mtk_reg_map mt7988_reg_map = {
.glo_cfg = 0x6a04,
.rst_idx = 0x6a08,
.delay_irq = 0x6a0c,
+ .rx_cfg = 0x6a10,
.irq_status = 0x6a20,
.irq_mask = 0x6a28,
.adma_rx_dbg0 = 0x6a38,
.int_grp = 0x6a50,
+ .int_grp3 = 0x6a58,
+ .tx_delay_irq = 0x6ab0,
+ .rx_delay_irq = 0x6ac0,
+ .lro_ctrl_dw0 = 0x6c08,
+ .lro_alt_score_delta = 0x6c1c,
+ .lro_ring_dip_dw0 = 0x6c14,
+ .lro_ring_ctrl_dw1 = 0x6c38,
+ .lro_alt_dbg = 0x6c40,
+ .lro_alt_dbg_data = 0x6c44,
+ .rss_glo_cfg = 0x7000,
},
.qdma = {
.qtx_cfg = 0x4400,
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 91b2375f9405..eb2328596c8b 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -1189,16 +1189,30 @@ struct mtk_reg_map {
u32 tx_irq_mask;
u32 tx_irq_status;
struct {
- u32 rx_ptr; /* rx base pointer */
- u32 rx_cnt_cfg; /* rx max count configuration */
- u32 pcrx_ptr; /* rx cpu pointer */
- u32 glo_cfg; /* global configuration */
- u32 rst_idx; /* reset index */
- u32 delay_irq; /* delay interrupt */
- u32 irq_status; /* interrupt status */
- u32 irq_mask; /* interrupt mask */
+ u32 rx_ptr; /* rx base pointer */
+ u32 rx_cnt_cfg; /* rx max count configuration */
+ u32 pcrx_ptr; /* rx cpu pointer */
+ u32 pdrx_ptr; /* rx dma pointer */
+ u32 glo_cfg; /* global configuration */
+ u32 rst_idx; /* reset index */
+ u32 rx_cfg; /* rx dma configuration */
+ u32 delay_irq; /* delay interrupt */
+ u32 irq_status; /* interrupt status */
+ u32 irq_mask; /* interrupt mask */
u32 adma_rx_dbg0;
- u32 int_grp;
+ u32 int_grp; /* interrupt group1 */
+ u32 int_grp3; /* interrupt group3 */
+ u32 tx_delay_irq; /* tx delay interrupt */
+ u32 rx_delay_irq; /* rx delay interrupt */
+ u32 lro_ctrl_dw0; /* lro ctrl dword0 */
+ u32 lro_alt_score_delta; /* lro auto-learn score delta */
+ u32 lro_rx1_dly_int; /* lro rx ring1 delay interrupt */
+ u32 lro_ring_dip_dw0; /* lro ring dip dword0 */
+ u32 lro_ring_ctrl_dw1; /* lro ring ctrl dword1 */
+ u32 lro_alt_dbg; /* lro auto-learn debug */
+ u32 lro_alt_dbg_data; /* lro auto-learn debug data */
+ u32 rss_glo_cfg; /* rss global configuration */
+
} pdma;
struct {
u32 qtx_cfg; /* tx queue configuration */
--
2.30.2

1300
patch/kernel/archive/filogic-6.16/patches.armbian/0073-net-ethernet-mtk_eth_soc-add-rss-support.patch Normal file
View File

File diff suppressed because it is too large Load Diff

31
patch/kernel/archive/filogic-6.16/patches.armbian/0074-net-mediatek-mtk_eth_soc-drop-RSS-capabilty-for-mt79.patch Normal file
View File

@ -0,0 +1,31 @@
From 4a4061dcab5bf9a5b35bd51f7538cac720c9719d Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Sat, 12 Jul 2025 14:58:39 +0200
Subject: [PATCH 74/84] net: mediatek: mtk_eth_soc: drop RSS capabilty for
mt798[16]
---
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index a163a04bb927..025f4a8119f7 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -1219,11 +1219,11 @@ enum mkt_eth_capabilities {
#define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \
- MTK_RSTCTRL_PPE1 | MTK_SRAM | MTK_PDMA_INT | MTK_RSS)
+ MTK_RSTCTRL_PPE1 | MTK_SRAM | MTK_PDMA_INT)
#define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
- MTK_RSTCTRL_PPE1 | MTK_SRAM | MTK_PDMA_INT | MTK_RSS)
+ MTK_RSTCTRL_PPE1 | MTK_SRAM | MTK_PDMA_INT)
#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_GMAC1_SGMII | \
MTK_GMAC2_2P5GPHY | MTK_GMAC2_SGMII | MTK_GMAC2_USXGMII | \
--
2.30.2

87
patch/kernel/archive/filogic-6.16/patches.armbian/0075-net-mtk_eth_soc-fix-mtk_-get-set-_rxfh-callback-head.patch Normal file
View File

@ -0,0 +1,87 @@
From c28e7f6075c7bd6e0dcf29cddd285ce4ec8ada85 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Fri, 20 Dec 2024 14:40:39 +0100
Subject: [PATCH 75/84] net: mtk_eth_soc: fix mtk_{get,set}_rxfh callback
header
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 31 ++++++++++-----------
1 file changed, 15 insertions(+), 16 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 18895e307824..5d2cfd026935 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -4994,32 +4994,31 @@ static u32 mtk_get_rxfh_indir_size(struct net_device *dev)
return MTK_RSS_MAX_INDIRECTION_TABLE;
}
-static int mtk_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
- u8 *hfunc)
+static int mtk_get_rxfh(struct net_device *dev, struct ethtool_rxfh_param *rxfh)
{
struct mtk_mac *mac = netdev_priv(dev);
struct mtk_eth *eth = mac->hw;
struct mtk_rss_params *rss_params = &eth->rss_params;
int i;
- if (hfunc)
- *hfunc = ETH_RSS_HASH_TOP; /* Toeplitz */
+ if (rxfh->hfunc)
+ rxfh->hfunc = ETH_RSS_HASH_TOP; /* Toeplitz */
- if (key) {
- memcpy(key, rss_params->hash_key,
+ if (rxfh->key) {
+ memcpy(rxfh->key, rss_params->hash_key,
sizeof(rss_params->hash_key));
}
- if (indir) {
+ if (rxfh->indir) {
for (i = 0; i < MTK_RSS_MAX_INDIRECTION_TABLE; i++)
- indir[i] = rss_params->indirection_table[i];
+ rxfh->indir[i] = rss_params->indirection_table[i];
}
return 0;
}
-static int mtk_set_rxfh(struct net_device *dev, const u32 *indir,
- const u8 *key, const u8 hfunc)
+static int mtk_set_rxfh(struct net_device *dev, struct ethtool_rxfh_param *rxfh,
+ struct netlink_ext_ack *extack)
{
struct mtk_mac *mac = netdev_priv(dev);
struct mtk_eth *eth = mac->hw;
@@ -5027,21 +5026,21 @@ static int mtk_set_rxfh(struct net_device *dev, const u32 *indir,
const struct mtk_reg_map *reg_map = eth->soc->reg_map;
int i;
- if (hfunc != ETH_RSS_HASH_NO_CHANGE &&
- hfunc != ETH_RSS_HASH_TOP)
+ if (rxfh->hfunc != ETH_RSS_HASH_NO_CHANGE &&
+ rxfh->hfunc != ETH_RSS_HASH_TOP)
return -EOPNOTSUPP;
- if (key) {
- memcpy(rss_params->hash_key, key,
+ if (rxfh->key) {
+ memcpy(rss_params->hash_key, rxfh->key,
sizeof(rss_params->hash_key));
for (i = 0; i < MTK_RSS_HASH_KEYSIZE / sizeof(u32); i++)
mtk_w32(eth, rss_params->hash_key[i],
MTK_RSS_HASH_KEY_DW(i));
}
- if (indir) {
+ if (rxfh->indir) {
for (i = 0; i < MTK_RSS_MAX_INDIRECTION_TABLE; i++)
- rss_params->indirection_table[i] = indir[i];
+ rss_params->indirection_table[i] = rxfh->indir[i];
for (i = 0; i < MTK_RSS_MAX_INDIRECTION_TABLE / 16; i++)
mtk_w32(eth, mtk_rss_indr_table(rss_params, i),
MTK_RSS_INDR_TABLE_DW(i));
--
2.30.2

514
patch/kernel/archive/filogic-6.16/patches.armbian/0076-net-ethernet-mtk_eth_soc-Add-LRO-support.patch Normal file
View File

@ -0,0 +1,514 @@
From d1b69872d8379a4860bfd0eebcb9bcbb85c3686c Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Fri, 21 Mar 2025 11:22:43 +0100
Subject: [PATCH 76/84] net: ethernet: mtk_eth_soc: Add LRO support
based on
https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/e5b6f723b733f1ddc613e9d9e8db7a82e0b42e5c
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 213 ++++++++++++++++++--
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 47 +++--
2 files changed, 220 insertions(+), 40 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 5d2cfd026935..799dc58e2581 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -2819,7 +2819,7 @@ static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
if (!ring->data)
return -ENOMEM;
- if (mtk_page_pool_enabled(eth)) {
+ if (mtk_page_pool_enabled(eth) && rcu_access_pointer(eth->prog)) {
struct page_pool *pp;
pp = mtk_create_page_pool(eth, &ring->xdp_q, ring_no,
@@ -2966,7 +2966,8 @@ static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, bool in_
static int mtk_hwlro_rx_init(struct mtk_eth *eth)
{
const struct mtk_reg_map *reg_map = eth->soc->reg_map;
- int i;
+ const struct mtk_soc_data *soc = eth->soc;
+ int i, val;
u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0;
u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0;
@@ -2987,7 +2988,7 @@ static int mtk_hwlro_rx_init(struct mtk_eth *eth)
ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L;
ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H;
- for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
+ for (i = 1; i <= MTK_HW_LRO_RING_NUM; i++) {
mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i));
mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i));
mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i));
@@ -3009,8 +3010,22 @@ static int mtk_hwlro_rx_init(struct mtk_eth *eth)
mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME,
MTK_PDMA_LRO_ALT_REFRESH_TIMER);
- /* set HW LRO mode & the max aggregation count for rx packets */
- lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff);
+ if (mtk_is_netsys_v3_or_greater(eth)) {
+ val = mtk_r32(eth, reg_map->pdma.rx_cfg);
+ mtk_w32(eth, val | ((MTK_PDMA_LRO_SDL + MTK_MAX_RX_LENGTH) <<
+ MTK_RX_CFG_SDL_OFFSET), reg_map->pdma.rx_cfg);
+
+ lro_ctrl_dw0 |= MTK_PDMA_LRO_SDL << MTK_CTRL_DW0_SDL_OFFSET;
+
+ /* enable cpu reason black list */
+ lro_ctrl_dw0 |= MTK_LRO_CRSN_BNW;
+
+ /* no use PPE cpu reason */
+ mtk_w32(eth, 0xffffffff, MTK_PDMA_LRO_CTRL_DW1);
+ } else {
+ /* set HW LRO mode & the max aggregation count for rx packets */
+ lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff);
+ }
/* the minimal remaining room of SDL0 in RXD for lro aggregation */
lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL;
@@ -3021,6 +3036,16 @@ static int mtk_hwlro_rx_init(struct mtk_eth *eth)
mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3);
mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0);
+ if (mtk_is_netsys_v2_or_greater(eth)) {
+ i = (soc->rx.desc_size == sizeof(struct mtk_rx_dma_v2)) ? 1 : 0;
+ mtk_m32(eth, MTK_RX_DONE_INT(MTK_HW_LRO_RING(i)),
+ MTK_RX_DONE_INT(MTK_HW_LRO_RING(i)), reg_map->pdma.int_grp);
+ mtk_m32(eth, MTK_RX_DONE_INT(MTK_HW_LRO_RING(i + 1)),
+ MTK_RX_DONE_INT(MTK_HW_LRO_RING(i + 1)), reg_map->pdma.int_grp + 0x4);
+ mtk_m32(eth, MTK_RX_DONE_INT(MTK_HW_LRO_RING(i + 2)),
+ MTK_RX_DONE_INT(MTK_HW_LRO_RING(i + 2)), reg_map->pdma.int_grp3);
+ }
+
return 0;
}
@@ -3044,7 +3069,7 @@ static void mtk_hwlro_rx_uninit(struct mtk_eth *eth)
}
/* invalidate lro rings */
- for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
+ for (i = 1; i <= MTK_HW_LRO_RING_NUM; i++)
mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i));
/* disable HW LRO */
@@ -3093,6 +3118,64 @@ static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac)
return cnt;
}
+static int mtk_hwlro_add_ipaddr_idx(struct net_device *dev, u32 ip4dst)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+ struct mtk_eth *eth = mac->hw;
+ const struct mtk_reg_map *reg_map = eth->soc->reg_map;
+ u32 reg_val;
+ int i;
+
+ /* check for duplicate IP address in the current DIP list */
+ for (i = 1; i <= MTK_HW_LRO_DIP_NUM; i++) {
+ reg_val = mtk_r32(eth, MTK_LRO_DIP_DW0_CFG(i));
+ if (reg_val == ip4dst)
+ break;
+ }
+
+ if (i < MTK_HW_LRO_DIP_NUM + 1) {
+ netdev_warn(dev, "Duplicate IP address at DIP(%d)!\n", i);
+ return -EEXIST;
+ }
+
+ /* find out available DIP index */
+ for (i = 1; i <= MTK_HW_LRO_DIP_NUM; i++) {
+ reg_val = mtk_r32(eth, MTK_LRO_DIP_DW0_CFG(i));
+ if (reg_val == 0UL)
+ break;
+ }
+
+ if (i >= MTK_HW_LRO_DIP_NUM + 1) {
+ netdev_warn(dev, "DIP index is currently out of resource!\n");
+ return -EBUSY;
+ }
+
+ return i;
+}
+
+static int mtk_hwlro_get_ipaddr_idx(struct net_device *dev, u32 ip4dst)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+ struct mtk_eth *eth = mac->hw;
+ const struct mtk_reg_map *reg_map = eth->soc->reg_map;
+ u32 reg_val;
+ int i;
+
+ /* find out DIP index that matches the given IP address */
+ for (i = 1; i <= MTK_HW_LRO_DIP_NUM; i++) {
+ reg_val = mtk_r32(eth, MTK_LRO_DIP_DW0_CFG(i));
+ if (reg_val == ip4dst)
+ break;
+ }
+
+ if (i >= MTK_HW_LRO_DIP_NUM + 1) {
+ netdev_warn(dev, "DIP address is not exist!\n");
+ return -ENOENT;
+ }
+
+ return i;
+}
+
static int mtk_hwlro_add_ipaddr(struct net_device *dev,
struct ethtool_rxnfc *cmd)
{
@@ -3101,15 +3184,19 @@ static int mtk_hwlro_add_ipaddr(struct net_device *dev,
struct mtk_mac *mac = netdev_priv(dev);
struct mtk_eth *eth = mac->hw;
int hwlro_idx;
+ u32 ip4dst;
if ((fsp->flow_type != TCP_V4_FLOW) ||
(!fsp->h_u.tcp_ip4_spec.ip4dst) ||
(fsp->location > 1))
return -EINVAL;
- mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst);
- hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
+ ip4dst = htonl(fsp->h_u.tcp_ip4_spec.ip4dst);
+ hwlro_idx = mtk_hwlro_add_ipaddr_idx(dev, ip4dst);
+ if (hwlro_idx < 0)
+ return hwlro_idx;
+ mac->hwlro_ip[fsp->location] = ip4dst;
mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]);
@@ -3125,13 +3212,17 @@ static int mtk_hwlro_del_ipaddr(struct net_device *dev,
struct mtk_mac *mac = netdev_priv(dev);
struct mtk_eth *eth = mac->hw;
int hwlro_idx;
+ u32 ip4dst;
if (fsp->location > 1)
return -EINVAL;
- mac->hwlro_ip[fsp->location] = 0;
- hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
+ ip4dst = mac->hwlro_ip[fsp->location];
+ hwlro_idx = mtk_hwlro_get_ipaddr_idx(dev, ip4dst);
+ if (hwlro_idx < 0)
+ return hwlro_idx;
+ mac->hwlro_ip[fsp->location] = 0;
mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
@@ -3139,6 +3230,24 @@ static int mtk_hwlro_del_ipaddr(struct net_device *dev,
return 0;
}
+static void mtk_hwlro_netdev_enable(struct net_device *dev)
+{
+ struct mtk_mac *mac = netdev_priv(dev);
+ struct mtk_eth *eth = mac->hw;
+ int i, hwlro_idx;
+
+ for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
+ if (mac->hwlro_ip[i] == 0)
+ continue;
+
+ hwlro_idx = mtk_hwlro_get_ipaddr_idx(dev, mac->hwlro_ip[i]);
+ if (hwlro_idx < 0)
+ continue;
+
+ mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[i]);
+ }
+}
+
static void mtk_hwlro_netdev_disable(struct net_device *dev)
{
struct mtk_mac *mac = netdev_priv(dev);
@@ -3146,8 +3255,14 @@ static void mtk_hwlro_netdev_disable(struct net_device *dev)
int i, hwlro_idx;
for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
+ if (mac->hwlro_ip[i] == 0)
+ continue;
+
+ hwlro_idx = mtk_hwlro_get_ipaddr_idx(dev, mac->hwlro_ip[i]);
+ if (hwlro_idx < 0)
+ continue;
+
mac->hwlro_ip[i] = 0;
- hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i;
mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
}
@@ -3333,6 +3448,8 @@ static int mtk_set_features(struct net_device *dev, netdev_features_t features)
if ((diff & NETIF_F_LRO) && !(features & NETIF_F_LRO))
mtk_hwlro_netdev_disable(dev);
+ else if ((diff & NETIF_F_LRO) && (features & NETIF_F_LRO))
+ mtk_hwlro_netdev_enable(dev);
return 0;
}
@@ -3390,8 +3507,8 @@ static int mtk_dma_init(struct mtk_eth *eth)
return err;
if (eth->hwlro) {
- for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
- err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO);
+ for (i = 0; i < MTK_HW_LRO_RING_NUM; i++) {
+ err = mtk_rx_alloc(eth, MTK_HW_LRO_RING(i), MTK_RX_FLAGS_HWLRO);
if (err)
return err;
}
@@ -3453,8 +3570,8 @@ static void mtk_dma_free(struct mtk_eth *eth)
if (eth->hwlro) {
mtk_hwlro_rx_uninit(eth);
- for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
- mtk_rx_clean(eth, &eth->rx_ring[i], false);
+ for (i = 0; i < MTK_HW_LRO_RING_NUM; i++)
+ mtk_rx_clean(eth, &eth->rx_ring[MTK_HW_LRO_RING(i)], false);
}
if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSS)) {
@@ -3650,16 +3767,21 @@ static int mtk_start_dma(struct mtk_eth *eth)
val |= MTK_RX_BT_32DWORDS;
mtk_w32(eth, val, reg_map->qdma.glo_cfg);
- mtk_w32(eth,
- MTK_RX_DMA_EN | rx_2b_offset |
- MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
- reg_map->pdma.glo_cfg);
+ val = mtk_r32(eth, reg_map->pdma.glo_cfg);
+ val |= MTK_RX_DMA_EN | rx_2b_offset |
+ MTK_RX_BT_32DWORDS | MTK_MULTI_EN;
+ mtk_w32(eth, val, reg_map->pdma.glo_cfg);
} else {
mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN |
MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS,
reg_map->pdma.glo_cfg);
}
+ if (eth->hwlro && mtk_is_netsys_v3_or_greater(eth)) {
+ val = mtk_r32(eth, reg_map->pdma.glo_cfg);
+ mtk_w32(eth, val | MTK_RX_DMA_LRO_EN, reg_map->pdma.glo_cfg);
+ }
+
return 0;
}
@@ -3803,6 +3925,13 @@ static int mtk_open(struct net_device *dev)
}
}
+ if (eth->hwlro) {
+ for (i = 0; i < MTK_HW_LRO_RING_NUM; i++) {
+ napi_enable(&eth->rx_napi[MTK_HW_LRO_RING(i)].napi);
+ mtk_rx_irq_enable(eth, MTK_RX_DONE_INT(MTK_HW_LRO_RING(i)));
+ }
+ }
+
refcount_set(&eth->dma_refcnt, 1);
} else {
refcount_inc(&eth->dma_refcnt);
@@ -3898,6 +4027,14 @@ static int mtk_stop(struct net_device *dev)
}
}
+ if (eth->hwlro) {
+ for (i = 0; i < MTK_HW_LRO_RING_NUM; i++) {
+ mtk_rx_irq_disable(eth, MTK_RX_DONE_INT(MTK_HW_LRO_RING(i)));
+ napi_synchronize(&eth->rx_napi[MTK_HW_LRO_RING(i)].napi);
+ napi_disable(&eth->rx_napi[MTK_HW_LRO_RING(i)].napi);
+ }
+ }
+
cancel_work_sync(&eth->rx_dim.work);
cancel_work_sync(&eth->tx_dim.work);
@@ -4342,6 +4479,14 @@ static int mtk_napi_init(struct mtk_eth *eth)
}
}
+ if (eth->hwlro) {
+ for (i = 0; i < MTK_HW_LRO_RING_NUM; i++) {
+ rx_napi = &eth->rx_napi[MTK_HW_LRO_RING(i)];
+ rx_napi->eth = eth;
+ rx_napi->rx_ring = &eth->rx_ring[MTK_HW_LRO_RING(i)];
+ }
+ }
+
return 0;
}
@@ -4905,7 +5050,7 @@ static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
switch (cmd->cmd) {
case ETHTOOL_GRXRINGS:
if (dev->hw_features & NETIF_F_LRO) {
- cmd->data = MTK_MAX_RX_RING_NUM;
+ cmd->data = MTK_HW_LRO_RING_NUM;
ret = 0;
} else if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSS)) {
cmd->data = MTK_RX_RSS_NUM;
@@ -5661,6 +5806,21 @@ static int mtk_probe(struct platform_device *pdev)
goto err_free_dev;
}
}
+
+ if (eth->hwlro) {
+ for (i = 0; i < MTK_HW_LRO_RING_NUM; i++) {
+ irqname = devm_kasprintf(eth->dev, GFP_KERNEL,
+ "%s LRO RX %d",
+ dev_name(eth->dev), i);
+ err = devm_request_irq(eth->dev,
+ eth->irq_pdma[MTK_HW_LRO_IRQ(i)],
+ mtk_handle_irq_rx, IRQF_SHARED,
+ irqname,
+ &eth->rx_napi[MTK_HW_LRO_RING(i)]);
+ if (err)
+ goto err_free_dev;
+ }
+ }
} else {
irqname = devm_kasprintf(eth->dev, GFP_KERNEL, "%s RX",
dev_name(eth->dev));
@@ -5732,6 +5892,13 @@ static int mtk_probe(struct platform_device *pdev)
mtk_napi_rx);
}
+ if (eth->hwlro) {
+ for (i = 0; i < MTK_HW_LRO_RING_NUM; i++) {
+ netif_napi_add(eth->dummy_dev, &eth->rx_napi[MTK_HW_LRO_RING(i)].napi,
+ mtk_napi_rx);
+ }
+ }
+
platform_set_drvdata(pdev, eth);
schedule_delayed_work(&eth->reset.monitor_work,
MTK_DMA_MONITOR_TIMEOUT);
@@ -5780,6 +5947,12 @@ static void mtk_remove(struct platform_device *pdev)
for (i = 1; i < MTK_RX_RSS_NUM; i++)
netif_napi_del(&eth->rx_napi[MTK_RSS_RING(i)].napi);
}
+
+ if (eth->hwlro) {
+ for (i = 0; i < MTK_HW_LRO_RING_NUM; i++)
+ netif_napi_del(&eth->rx_napi[MTK_HW_LRO_RING(i)].napi);
+ }
+
mtk_cleanup(eth);
free_netdev(eth->dummy_dev);
mtk_mdio_cleanup(eth);
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 025f4a8119f7..f4f6ea355c52 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -36,7 +36,7 @@
#define MTK_DMA_SIZE(x) (SZ_##x)
#define MTK_FQ_DMA_HEAD 32
#define MTK_FQ_DMA_LENGTH 2048
-#define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN)
+#define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
#define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN)
#define MTK_DMA_DUMMY_DESC 0xffffffff
#define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \
@@ -64,10 +64,13 @@
#define MTK_QRX_OFFSET 0x10
-#define MTK_MAX_RX_RING_NUM 4
-#define MTK_HW_LRO_DMA_SIZE 8
+#define MTK_MAX_RX_RING_NUM (8)
+#define MTK_HW_LRO_DMA_SIZE (mtk_is_netsys_v3_or_greater(eth) ? 64 : 8)
+#define IS_HW_LRO_RING(ring_no) (mtk_is_netsys_v3_or_greater(eth) ? \
+ (((ring_no) > 3) && ((ring_no) < 8)) : \
+ (((ring_no) > 0) && ((ring_no) < 4)))
-#define MTK_MAX_LRO_RX_LENGTH (4096 * 3)
+#define MTK_MAX_LRO_RX_LENGTH (4096 * 3 + MTK_MAX_RX_LENGTH)
#define MTK_MAX_LRO_IP_CNT 2
#define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */
#define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */
@@ -183,31 +186,35 @@
#define MTK_CDMM_THRES 0x165c
/* PDMA HW LRO Control Registers */
-#define MTK_PDMA_LRO_CTRL_DW0 0x980
+#define MTK_HW_LRO_DIP_NUM (mtk_is_netsys_v3_or_greater(eth) ? 4 : 3)
#define MTK_HW_LRO_RING_NUM (mtk_is_netsys_v3_or_greater(eth) ? 4 : 3)
+#define MTK_HW_LRO_RING(x) ((x) + (mtk_is_netsys_v3_or_greater(eth) ? 4 : 1))
+#define MTK_HW_LRO_IRQ(x) ((x) + (mtk_is_netsys_v3_or_greater(eth) ? 0 : 1))
+#define MTK_LRO_CRSN_BNW BIT((mtk_is_netsys_v3_or_greater(eth) ? 22 : 6))
#define MTK_LRO_EN BIT(0)
#define MTK_NON_LRO_MULTI_EN BIT(2)
#define MTK_LRO_DLY_INT_EN BIT(5)
-#define MTK_L3_CKS_UPD_EN BIT(7)
-#define MTK_L3_CKS_UPD_EN_V2 BIT(19)
+#define MTK_L3_CKS_UPD_EN BIT(mtk_is_netsys_v3_or_greater(eth) ? 19 : 7)
#define MTK_LRO_ALT_PKT_CNT_MODE BIT(21)
-#define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26)
-#define MTK_LRO_RING_RELINQUISH_REQ_V2 (0xf << 24)
-#define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29)
-#define MTK_LRO_RING_RELINQUISH_DONE_V2 (0xf << 28)
-
-#define MTK_PDMA_LRO_CTRL_DW1 0x984
-#define MTK_PDMA_LRO_CTRL_DW2 0x988
-#define MTK_PDMA_LRO_CTRL_DW3 0x98c
+#define MTK_LRO_RING_RELINQUISH_REQ (mtk_is_netsys_v3_or_greater(eth) ? 0xf << 24 : 0x7 << 26)
+#define MTK_LRO_RING_RELINQUISH_DONE (mtk_is_netsys_v3_or_greater(eth) ? 0xf << 28 : 0x7 << 29)
+
+#define MTK_PDMA_LRO_CTRL_DW0 (reg_map->pdma.lro_ctrl_dw0)
+#define MTK_PDMA_LRO_CTRL_DW1 (reg_map->pdma.lro_ctrl_dw0 + 0x04)
+#define MTK_PDMA_LRO_CTRL_DW2 (reg_map->pdma.lro_ctrl_dw0 + 0x08)
+#define MTK_PDMA_LRO_CTRL_DW3 (reg_map->pdma.lro_ctrl_dw0 + 0x0c)
#define MTK_ADMA_MODE BIT(15)
#define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16)
+#define MTK_CTRL_DW0_SDL_OFFSET (3)
+#define MTK_CTRL_DW0_SDL_MASK BITS(3, 18)
+
#define MTK_RX_DMA_LRO_EN BIT(8)
#define MTK_MULTI_EN BIT(10)
#define MTK_PDMA_SIZE_8DWORDS (1 << 4)
/* PDMA RSS Control Registers */
-#define MTK_RX_NAPI_NUM (4)
+#define MTK_RX_NAPI_NUM (8)
#define MTK_RX_RSS_NUM (eth->soc->rss_num)
#define MTK_RSS_RING(x) (x)
#define MTK_RSS_EN BIT(0)
@@ -243,11 +250,10 @@
#define MTK_PDMA_DELAY_PTIME_MASK 0xff
/* PDMA HW LRO Alter Flow Delta Register */
-#define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c
+#define MTK_PDMA_LRO_ALT_SCORE_DELTA (reg_map->pdma.lro_alt_score_delta)
/* PDMA HW LRO IP Setting Registers */
-#define MTK_LRO_RX_RING0_DIP_DW0 0xb04
-#define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40))
+#define MTK_LRO_DIP_DW0_CFG(x) (reg_map->pdma.lro_ring_dip_dw0 + (x * 0x40))
#define MTK_RING_MYIP_VLD BIT(9)
/* PDMA HW LRO Ring Control Registers */
@@ -1231,7 +1237,7 @@ enum mkt_eth_capabilities {
MTK_MUX_GMAC123_TO_GEPHY_SGMII | \
MTK_MUX_GMAC123_TO_USXGMII | MTK_MUX_GMAC2_TO_2P5GPHY | \
MTK_QDMA | MTK_SRAM | MTK_PDMA_INT | MTK_RSS | \
- MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2)
+ MTK_HWLRO | MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2)
struct mtk_tx_dma_desc_info {
dma_addr_t addr;
@@ -1512,6 +1518,7 @@ struct mtk_mac {
/* the struct describing the SoC. these are declared in the soc_xyz.c files */
extern const struct of_device_id of_mtk_match[];
+extern u32 mtk_hwlro_stats_ebl;
static inline bool mtk_is_netsys_v1(struct mtk_eth *eth)
{
--
2.30.2

101
patch/kernel/archive/filogic-6.16/patches.armbian/0077-readme-add-README.md-for-RSS-LRO.patch Normal file
View File

@ -0,0 +1,101 @@
From 0d853dd76392d669385fd472c1154c2a818ae2e6 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Tue, 10 Jun 2025 23:28:00 +0200
Subject: [PATCH 77/84] readme: add README.md for RSS/LRO
---
README.md | 82 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 82 insertions(+)
create mode 100644 README.md
diff --git a/README.md b/README.md
new file mode 100644
index 000000000000..f6b88d4d502a
--- /dev/null
+++ b/README.md
@@ -0,0 +1,82 @@
+# RSS / LRO
+
+HW-acceleration for ending traffic.
+For routed traffic PPE is needed and hw offloading in nftables.
+Bridged traffic may need addional changes (openwrt use bridger utility).
+
+## RSS
+
+(Receive Side Scaling)
+
+using 4 additional IRQ for spreading load
+
+cat /proc/interrupts | grep ethernet
+
+echo 1 > /proc/irq/105/smp_affinity
+echo 2 > /proc/irq/106/smp_affinity
+echo 4 > /proc/irq/107/smp_affinity
+echo 8 > /proc/irq/108/smp_affinity
+
+moving tx frame-engine irq to different cpu (here 3rd)
+echo 4 > /proc/irq/103/smp_affinity
+
+disable RPS (Receive Packet Steering) for all macs:
+echo 0 > /sys/devices/platform/soc/15100000.ethernet/net/eth0/queues/rx-0/rps_cpus
+
+pay attention on iperf-version (iperf 3.17 is ok, 3.12 is not)
+
+traffic must be created using multiple streams so that it can be splitted, so use multithreaded iperf3
+
+on R4:
+bin/iperf3 -s
+
+on the other side:
+iperf3 -c 192.168.1.1 -i 1 -P 4
+
+you should reach ~9.3 GBit/s
+
+and see spreading load over CPU cores
+
+root@bpi-r4-phy-8G:~# cat /proc/interrupts | grep eth
+103: 20 198366 0 0 GICv3 229 Level 15100000.ethernet
+105: 3611 0 0 0 GICv3 221 Level 15100000.ethernet, 15100000.ethernet
+106: 2 6842 0 0 GICv3 222 Level 15100000.ethernet, 15100000.ethernet
+107: 4 0 27643 0 GICv3 223 Level 15100000.ethernet, 15100000.ethernet
+108: 3 0 0 27925 GICv3 224 Level 15100000.ethernet, 15100000.ethernet
+
+using the default iperf3 from debian bookworm (3.12) results in only 6.7GBit/s
+
+## LRO
+(Large Receive Offload)
+
+Add HW LRO RX rule:
+
+ethtool -N [interface] flow-type tcp4 dst-ip [IP] action 0 loc [0/1]
+
+Delete HW LRO RX rule:
+
+ethtool -N [interface] delete [0/1]
+
+Enable/Disable HW LRO rule:
+
+ethtool -K [interface] lro [on | off]
+
+Show the current offload features:
+
+ethtool -k [interface]
+
+example:
+
+ethtool -N eth2 flow-type tcp4 dst-ip 192.168.1.1 action 0 loc 0
+ethtool -K eth2 lro on
+ethtool -k eth2
+
+using iperf instead of iperf3!
+
+verify with propritary debugfs
+Enable HW LRO rings
+echo 4 1 > /proc/mtketh/hw_lro_auto_tlb
+Enable HW LRO statistics
+echo 5 1 > /proc/mtketh/hw_lro_auto_tlb
+
+cat /proc/mtketh/hw_lro_stats
--
2.30.2

61
patch/kernel/archive/filogic-6.16/patches.armbian/0078-net-ethernet-mtk_eth_soc-support-forced-reset-contro.patch Normal file
View File

@ -0,0 +1,61 @@
From ad2f0a1e65bd58dee78804dc28736ff616381356 Mon Sep 17 00:00:00 2001
From: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
Date: Wed, 27 Nov 2024 10:16:27 +0800
Subject: [PATCH 78/84] net: ethernet: mtk_eth_soc: support forced reset
control
Without this patch, users are unable to control the forced reset
through the proprietary debugfs.
Signed-off-by: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 6 ++++--
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 1 +
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 799dc58e2581..730146eb322e 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -3609,7 +3609,8 @@ static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue)
eth->netdev[mac->id]->stats.tx_errors++;
netif_err(eth, tx_err, dev, "transmit timed out\n");
- schedule_work(&eth->pending_work);
+ if (atomic_read(&eth->reset.force))
+ schedule_work(&eth->pending_work);
}
static int mtk_get_irqs_fe(struct platform_device *pdev, struct mtk_eth *eth)
@@ -4455,7 +4456,7 @@ static void mtk_hw_reset_monitor_work(struct work_struct *work)
goto out;
/* DMA stuck checks */
- if (mtk_hw_check_dma_hang(eth))
+ if (mtk_hw_check_dma_hang(eth) && atomic_read(&eth->reset.force))
schedule_work(&eth->pending_work);
out:
@@ -5617,6 +5618,7 @@ static int mtk_probe(struct platform_device *pdev)
eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
INIT_WORK(&eth->rx_dim.work, mtk_dim_rx);
+ atomic_set(&eth->reset.force, 0);
INIT_DELAYED_WORK(&eth->reset.monitor_work, mtk_hw_reset_monitor_work);
eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index f4f6ea355c52..14c3ce16f733 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -1479,6 +1479,7 @@ struct mtk_eth {
struct {
struct delayed_work monitor_work;
+ atomic_t force;
u32 wdidx;
u8 wdma_hang_count;
u8 qdma_hang_count;
--
2.30.2

3007
patch/kernel/archive/filogic-6.16/patches.armbian/0079-net-mediatek-add-proprietary-debugfs.patch Normal file
View File

File diff suppressed because it is too large Load Diff

52
patch/kernel/archive/filogic-6.16/patches.armbian/0080-enable-debugfs.patch Normal file
View File

@ -0,0 +1,52 @@
From 59da261a6f057fd191d56b4171dcc12f7b6bd077 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Sat, 18 Jan 2025 15:59:43 +0100
Subject: [PATCH 80/84] enable debugfs
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 045619d37d83..84ab560a1b80 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -32,6 +32,7 @@
#include <linux/genalloc.h>
#include "mtk_eth_soc.h"
+#include "mtk_eth_dbg.h"
#include "mtk_wed.h"
static int mtk_msg_level = -1;
@@ -384,7 +385,7 @@ int _mtk_mdio_write_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg,
return 0;
}
-static int _mtk_mdio_write_c45(struct mtk_eth *eth, u32 phy_addr,
+int _mtk_mdio_write_c45(struct mtk_eth *eth, u32 phy_addr,
u32 devad, u32 phy_reg, u32 write_data)
{
int ret;
@@ -442,7 +443,7 @@ int _mtk_mdio_read_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg)
return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK;
}
-static int _mtk_mdio_read_c45(struct mtk_eth *eth, u32 phy_addr,
+int _mtk_mdio_read_c45(struct mtk_eth *eth, u32 phy_addr,
u32 devad, u32 phy_reg)
{
int ret;
@@ -5913,6 +5914,9 @@ static int mtk_probe(struct platform_device *pdev)
}
}
+ mtketh_debugfs_init(eth);
+ debug_proc_init(eth);
+
platform_set_drvdata(pdev, eth);
schedule_delayed_work(&eth->reset.monitor_work,
MTK_DMA_MONITOR_TIMEOUT);
--
2.30.2

31
patch/kernel/archive/filogic-6.16/patches.armbian/0081-net-mediatek-mtk_eth_soc-add-RSS-capabilty-for-mt798.patch Normal file
View File

@ -0,0 +1,31 @@
From 9e860e36b0a842cb3de4136cde7258b34caf3564 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Sat, 12 Jul 2025 14:59:51 +0200
Subject: [PATCH 81/84] net: mediatek: mtk_eth_soc: add RSS capabilty for
mt798[16]
---
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index e19a81d3b141..0cb99f1c1772 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -1281,11 +1281,11 @@ enum mkt_eth_capabilities {
#define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \
- MTK_RSTCTRL_PPE1 | MTK_SRAM | MTK_PDMA_INT)
+ MTK_RSTCTRL_PPE1 | MTK_SRAM | MTK_PDMA_INT | MTK_RSS)
#define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
- MTK_RSTCTRL_PPE1 | MTK_SRAM | MTK_PDMA_INT)
+ MTK_RSTCTRL_PPE1 | MTK_SRAM | MTK_PDMA_INT | MTK_RSS)
#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_GMAC1_SGMII | \
MTK_GMAC2_2P5GPHY | MTK_GMAC2_SGMII | MTK_GMAC2_USXGMII | \
--
2.30.2

53
patch/kernel/archive/filogic-6.16/patches.armbian/0082-net-mediatek-mtk_eth_soc-enable-lro-stats-from-debug.patch Normal file
View File

@ -0,0 +1,53 @@
From cc6820376ccbacfcf7a495b3d6817c1c7e916f3e Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Fri, 7 Mar 2025 13:14:20 +0100
Subject: [PATCH 82/84] net: mediatek: mtk_eth_soc: enable lro stats from
debugfs
echo 4 1 > /proc/mtketh/hw_lro_auto_tlb #enable rings
echo 5 1 > /proc/mtketh/hw_lro_auto_tlb #enable statistics
cat /proc/mtketh/hw_lro_stats
had to disable CONFIG_STRICT_DEVMEM for register values
root@bpi-r4-v11:~
busybox devmem 0x15106C54 #LRO2_RING1_DIP_DW0 Destination IP address
0xC0A80101 #192.168.1.1
root@bpi-r4-v11:~
busybox devmem 0x15106C58 #LRO2_RING1_DIP_DW1 Destination IP address
0x00000000
root@bpi-r4-v11:~
busybox devmem 0x15106C5C #LRO2_RING1_DIP_DW2 Destination IP address
0x00000000
root@bpi-r4-v11:~
busybox devmem 0x15106C60 LRO2_RING1_DIP_DW3 Destination IP address
0x00000000
root@bpi-r4-v11:~
busybox devmem 0x15106c7c
0x00002BC0
=LRO2_RING1_CTRL_DW2 LRO2_MAX_AGGREGATED_CNT_L = 0x00002BC0 (bit8 = 1 and bit9 = 1)
means that both DIP and flow information have been enabled.
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 84ab560a1b80..a500ac80e715 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -2393,6 +2393,12 @@ static int mtk_poll_rx(struct napi_struct *napi, int budget,
if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED)
mtk_ppe_check_skb(eth->ppe[ppe_idx], skb, hash);
+ if (eth->hwlro && mtk_hwlro_stats_ebl &&
+ IS_HW_LRO_RING(ring->ring_no)) {
+ hw_lro_stats_update(ring->ring_no, &trxd);
+ hw_lro_flush_stats_update(ring->ring_no, &trxd);
+ }
+
skb_record_rx_queue(skb, 0);
napi_gro_receive(napi, skb);
--
2.30.2

78
patch/kernel/archive/filogic-6.16/patches.armbian/0083-net-mediatek-change-mt7986-from-RSS-to-LRO-only-1-po.patch Normal file
View File

@ -0,0 +1,78 @@
From 2cd641be6c6440c61c1f730722dab5e359acf6da Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Sat, 12 Apr 2025 14:36:54 +0200
Subject: [PATCH 83/84] net: mediatek change mt7986 from RSS to LRO (only 1
possible) - untested
https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/30c22fcf9e2dd7d04e630969557c8ef3e96bf451
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 15 ++++++++-------
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 +-
2 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index a500ac80e715..eef833f1cd06 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -3036,11 +3036,6 @@ static int mtk_hwlro_rx_init(struct mtk_eth *eth)
lro_ctrl_dw0 |= MTK_PDMA_LRO_SDL << MTK_CTRL_DW0_SDL_OFFSET;
- /* enable cpu reason black list */
- lro_ctrl_dw0 |= MTK_LRO_CRSN_BNW;
-
- /* no use PPE cpu reason */
- mtk_w32(eth, 0xffffffff, MTK_PDMA_LRO_CTRL_DW1);
} else {
/* set HW LRO mode & the max aggregation count for rx packets */
lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff);
@@ -3052,9 +3047,15 @@ static int mtk_hwlro_rx_init(struct mtk_eth *eth)
/* enable HW LRO */
lro_ctrl_dw0 |= MTK_LRO_EN;
+ /* enable cpu reason black list */
+ lro_ctrl_dw0 |= MTK_LRO_CRSN_BNW;
+
mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3);
mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0);
+ /* no use PPE cpu reason */
+ mtk_w32(eth, 0xffffffff, MTK_PDMA_LRO_CTRL_DW1);
+
if (mtk_is_netsys_v2_or_greater(eth)) {
i = (soc->rx.desc_size == sizeof(struct mtk_rx_dma_v2)) ? 1 : 0;
mtk_m32(eth, MTK_RX_DONE_INT(MTK_HW_LRO_RING(i)),
@@ -6142,7 +6143,7 @@ static const struct mtk_soc_data mt7981_data = {
},
.rx = {
.desc_size = sizeof(struct mtk_rx_dma),
- .dma_l4_valid = RX_DMA_L4_VALID_V2,
+ .dma_l4_valid = RX_DMA_L4_VALID,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
.dma_size = MTK_DMA_SIZE(2K),
@@ -6172,7 +6173,7 @@ static const struct mtk_soc_data mt7986_data = {
},
.rx = {
.desc_size = sizeof(struct mtk_rx_dma),
- .dma_l4_valid = RX_DMA_L4_VALID_V2,
+ .dma_l4_valid = RX_DMA_L4_VALID,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
.dma_size = MTK_DMA_SIZE(2K),
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 0cb99f1c1772..5ecd6381ad6e 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -1285,7 +1285,7 @@ enum mkt_eth_capabilities {
#define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
- MTK_RSTCTRL_PPE1 | MTK_SRAM | MTK_PDMA_INT | MTK_RSS)
+ MTK_RSTCTRL_PPE1 | MTK_SRAM | MTK_PDMA_INT | MTK_HWLRO)
#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_GMAC1_SGMII | \
MTK_GMAC2_2P5GPHY | MTK_GMAC2_SGMII | MTK_GMAC2_USXGMII | \
--
2.30.2

47
patch/kernel/archive/filogic-6.16/patches.armbian/0084-net-mediatek-mtk_eth_soc-check-if-irqs-were-loaded-t.patch Normal file
View File

@ -0,0 +1,47 @@
From 2c586e5b7bf54b2f94ffc6bb00618afad3725cf8 Mon Sep 17 00:00:00 2001
From: Frank Wunderlich <frank-w@public-files.de>
Date: Sat, 12 Jul 2025 15:45:22 +0200
Subject: [PATCH 84/84] net: mediatek: mtk_eth_soc: check if irqs were loaded
to keep backwards compatibility
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index eef833f1cd06..106bbeb21ea0 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -3340,6 +3340,11 @@ static int mtk_hwlro_get_fdir_all(struct net_device *dev,
return 0;
}
+static bool mtk_rss_available(struct mtk_eth *eth)
+{
+ return (eth->soc->rss_num && eth->irq_pdma[eth->soc->rss_num - 1]>=0);
+}
+
static u32 mtk_rss_indr_table(struct mtk_rss_params *rss_params, int index)
{
u32 val = 0;
@@ -4620,7 +4625,7 @@ static int mtk_hw_init(struct mtk_eth *eth, bool reset)
mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp);
mtk_w32(eth, MTK_RX_DONE_INT(0), reg_map->qdma.int_grp + 4);
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_PDMA_INT)) {
+ if (mtk_rss_available(eth)) {
mtk_w32(eth, 0x210FFFF2, MTK_FE_INT_GRP);
} else {
mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp);
@@ -5805,7 +5810,7 @@ static int mtk_probe(struct platform_device *pdev)
if (err)
goto err_free_dev;
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_PDMA_INT)) {
+ if (mtk_rss_available(eth)) {
irqname = devm_kasprintf(eth->dev, GFP_KERNEL, "%s PDMA RX %d",
dev_name(eth->dev), 0);
err = devm_request_irq(eth->dev, eth->irq_pdma[0],
--
2.30.2

10
patch/kernel/archive/filogic-6.16/series.armbian
View File

@ -1,10 +0,0 @@
#
# This file is made manually by simply copying text
# from the target series.* files.
# Add (-) at the beginning of the line if the patch should not be applied.
# At the same time, the patch does not need to be deleted.
#
# diff between frank-w's BPI-Router-Linux-kernel/ v.6.16-rsslro, and a tree with the v6.16.12 tree rebased into it
# Note, some patches appear to have been backported into the 6.16-stable branch
patches.armbian/0001-6.16.12.diff
patches.armbian/mt7988a-bananapi-bpi-r4-sd.patch

1
patch/kernel/archive/filogic-6.16/series.armbian Symbolic link
View File

@ -0,0 +1 @@
series.conf

96
patch/kernel/archive/filogic-6.16/series.conf
View File

@ -4,7 +4,97 @@
# Add (-) at the beginning of the line if the patch should not be applied.
# At the same time, the patch does not need to be deleted.
#
# diff between frank-w's BPI-Router-Linux-kernel/ v.6.16-rsslro, and a tree with the v6.16.12 tree rebased into it
# Note, some patches appear to have been backported into the 6.16-stable branch
patches.armbian/0001-6.16.12.diff
# patch series derived from:
# `git format-patch -o ~/build/armbian-build/patch/kernel/archive/filogic-6.16/patches.armbian/ v6.16.12..6.16.12-rsslro`
# where 6.16.12-rsslro was from taking https://github.com/frank-w/BPI-Router-Linux branch:6.16-rsslro
# then `git rebase v6.16.12` where this tag was from https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git tag:v6.16.12
# two patches are then skipped for being empty, 0001 & 0017
-patches.armbian/0001-v6-coverletter-net-next-rework-IRQ-handling-in-mtk_e.patch
patches.armbian/0002-net-ethernet-mtk_eth_soc-support-named-IRQs.patch
patches.armbian/0003-net-ethernet-mtk_eth_soc-add-consts-for-irq-index.patch
patches.armbian/0004-net-ethernet-mtk_eth_soc-skip-first-IRQ-if-not-used.patch
patches.armbian/0005-net-ethernet-mtk_eth_soc-only-use-legacy-mode-on-mis.patch
patches.armbian/0006-build.sh-add-build-script-config-defconfig-and-fit-s.patch
patches.armbian/0007-build.sh-add-additional-build-script-config-defconfi.patch
patches.armbian/0008-defconfig-r3-fix-warning-about-BASE_SMALL.patch
patches.armbian/0009-build.conf-change-upload-target.patch
patches.armbian/0010-arm-dts-mt7623-swap-mmc-and-put-uart2-first.patch
patches.armbian/0011-arm64-dts-disable-dtbs-for-dtbs_check.patch
patches.armbian/0012-dt-bindings-interconnect-add-mt7988-cci-compatible.patch
patches.armbian/0013-arm64-dts-mediatek-mt7988-add-cci-node.patch
patches.armbian/0014-arm64-dts-mediatek-mt7988a-bpi-r4-add-proc-supply-fo.patch
patches.armbian/0015-arm64-dts-mediatek-mt7988a-bpi-r4-drop-unused-pins.patch
patches.armbian/0016-arm64-dts-mediatek-mt7988a-bpi-r4-add-gpio-leds.patch
-patches.armbian/0017-v9-coverletter-further-mt7988-devicetree-work.patch
patches.armbian/0018-dt-bindings-net-mediatek-net-update-mac-subnode-patt.patch
patches.armbian/0019-dt-bindings-net-mediatek-net-allow-up-to-8-IRQs.patch
patches.armbian/0020-dt-bindings-net-mediatek-net-allow-irq-names.patch
patches.armbian/0021-dt-bindings-net-mediatek-net-add-sram-property.patch
patches.armbian/0022-dt-bindings-net-dsa-mediatek-mt7530-add-dsa-port-def.patch
patches.armbian/0023-dt-bindings-net-dsa-mediatek-mt7530-add-internal-mdi.patch
patches.armbian/0024-arm64-dts-mediatek-mt7986-add-sram-node.patch
patches.armbian/0025-arm64-dts-mediatek-mt7986-add-interrupts-for-RSS-and.patch
patches.armbian/0026-arm64-dts-mediatek-mt7988-add-basic-ethernet-nodes.patch
patches.armbian/0027-arm64-dts-mediatek-mt7988-add-switch-node.patch
patches.armbian/0028-arm64-dts-mediatek-mt7988a-bpi-r4-add-aliases-for-et.patch
patches.armbian/0029-arm64-dts-mediatek-mt7988a-bpi-r4-add-sfp-cages-and-.patch
patches.armbian/0030-arm64-dts-mediatek-mt7988a-bpi-r4-configure-switch-p.patch
patches.armbian/0031-arm64-dts-mediatek-mt7988a-bpi-r4-drop-readonly-from.patch
patches.armbian/0032-dt-bindings-net-pcs-mediatek-sgmiisys-add-phys-and-r.patch
patches.armbian/0033-dt-binding-sgmiisys-re-add-pcs-cells.patch
patches.armbian/0034-dts-re-add-sgmiisys.patch
patches.armbian/0035-arm64-dts-mt7988-add-cpufreq-calibration-efuse-subno.patch
patches.armbian/0036-net-ethernet-mtk_eth_soc-move-desc-assignment-below-.patch
patches.armbian/0037-dts-enable-mt818-36-for-cci-testing.patch
patches.armbian/0038-Revert-dts-enable-mt818-36-for-cci-testing.patch
patches.armbian/0039-enable-bpi-r3-DTBs-for-testing.patch
patches.armbian/0040-only-enable-mediatek-for-arm-to-increase-dtbs_check.patch
patches.armbian/0041-enable-some-arm64-dts-to-check-binding.patch
patches.armbian/0042-defconfig-r4-add-sram-driver.patch
patches.armbian/0043-net-ethernet-mtk_eth_soc-improve-support-for-named-i.patch
patches.armbian/0044-net-ethernet-mtk_eth_soc-fix-kernel-doc-comment.patch
patches.armbian/0045-net-ethernet-mtk_eth_soc-use-generic-allocator-for-S.patch
patches.armbian/0046-defconfig-r3-add-sram.patch
patches.armbian/0047-WIP-dts64-r4-add-ubi-partition-to-spin-nand.patch
patches.armbian/0048-add-mtd-rw-driver.patch
patches.armbian/0049-arm64-dts-add-usxgmii-pcs-and-link-both-pcs.patch
patches.armbian/0050-arm64-dts-update-bpi-r4.dtsi-to-actual-state.patch
patches.armbian/0051-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch
patches.armbian/0052-net-phylink-keep-and-use-MAC-supported_interfaces-in.patch
patches.armbian/0053-net-phy-introduce-phy_interface_copy-helper.patch
patches.armbian/0054-net-phylink-introduce-internal-phylink-PCS-handling.patch
patches.armbian/0055-net-phylink-add-phylink_release_pcs-to-externally-re.patch
patches.armbian/0056-net-pcs-implement-Firmware-node-support-for-PCS-driv.patch
patches.armbian/0057-net-phylink-support-late-PCS-provider-attach.patch
patches.armbian/0058-dt-bindings-net-ethernet-controller-permit-to-define.patch
patches.armbian/0059-net-pcs-airoha-add-PCS-driver-for-Airoha-SoC.patch
patches.armbian/0060-dt-bindings-net-pcs-Document-support-for-Airoha-Ethe.patch
patches.armbian/0061-net-pcs-pcs-mtk-lynxi-add-platform-driver-for-MT7988.patch
patches.armbian/0062-dt-bindings-net-pcs-add-bindings-for-MediaTek-USXGMI.patch
patches.armbian/0063-net-pcs-add-driver-for-MediaTek-USXGMII-PCS.patch
patches.armbian/0064-net-ethernet-mtk_eth_soc-add-more-DMA-monitor-for-MT.patch
patches.armbian/0065-hwrng-add-driver-for-MediaTek-TRNG-SMC.patch
patches.armbian/0066-dts64-enable-sata-and-disable-pcie-slot-CN8-shared.patch
patches.armbian/0067-arm64-dts-mt7622-fix-sata.patch
patches.armbian/0068-kdeb-try-to-add-kernels-for-bpi-boards-to-deb-packag.patch
patches.armbian/0069-kdeb-fix-deb-build-for-R3-R4.patch
patches.armbian/0070-build.conf-change-to-r4.patch
patches.armbian/0071-defconfig-r4-disable-STRICT_DEVMEM-to-allow-register.patch
patches.armbian/0072-net-ethernet-mtk_eth_soc-add-register-definitions-fo.patch
patches.armbian/0073-net-ethernet-mtk_eth_soc-add-rss-support.patch
patches.armbian/0074-net-mediatek-mtk_eth_soc-drop-RSS-capabilty-for-mt79.patch
patches.armbian/0075-net-mtk_eth_soc-fix-mtk_-get-set-_rxfh-callback-head.patch
patches.armbian/0076-net-ethernet-mtk_eth_soc-Add-LRO-support.patch
patches.armbian/0077-readme-add-README.md-for-RSS-LRO.patch
patches.armbian/0078-net-ethernet-mtk_eth_soc-support-forced-reset-contro.patch
patches.armbian/0079-net-mediatek-add-proprietary-debugfs.patch
patches.armbian/0080-enable-debugfs.patch
patches.armbian/0081-net-mediatek-mtk_eth_soc-add-RSS-capabilty-for-mt798.patch
patches.armbian/0082-net-mediatek-mtk_eth_soc-enable-lro-stats-from-debug.patch
patches.armbian/0083-net-mediatek-change-mt7986-from-RSS-to-LRO-only-1-po.patch
patches.armbian/0084-net-mediatek-mtk_eth_soc-check-if-irqs-were-loaded-t.patch
# this patch is not from frank-w's tree, but rather is an adaptation to the armbian build framework
# vs the OpenWRT framework's method of building the relevant FDTs as used by the bootloader.
patches.armbian/mt7988a-bananapi-bpi-r4-sd.patch