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rockchip64-6.18: add patch to fix av1 decoding on rk3588

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Jianfeng Liu 2025-12-08 22:05:28 +08:00 committed by Igor
parent 22a5c46fdd
commit 3dbd4e8e09
1 changed files with 49 additions and 0 deletions
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49
patch/kernel/archive/rockchip64-6.18/media-0004-media-verisilicon-AV1-Fix-enable-cdef-computation.patch Normal file
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@ -0,0 +1,49 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Date: Mon, 22 Sep 2025 13:15:02 +0200
Subject: media: verisilicon: AV1: Fix enable cdef computation
Testing V4L2_AV1_SEQUENCE_FLAG_ENABLE_CDEF flag isn't enough
to know if cdef bit has to be set.
If any of the used cdef fields isn't zero then we must enable
cdef feature on the hardware.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Fixes: 727a400686a2c ("media: verisilicon: Add Rockchip AV1 decoder")
---
drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
index 111111111111..222222222222 100644
--- a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
+++ b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
@@ -1396,8 +1396,16 @@ static void rockchip_vpu981_av1_dec_set_cdef(struct hantro_ctx *ctx)
u16 luma_sec_strength = 0;
u32 chroma_pri_strength = 0;
u16 chroma_sec_strength = 0;
+ bool enable_cdef;
int i;
+ enable_cdef = !(cdef->bits == 0 &&
+ cdef->damping_minus_3 == 0 &&
+ cdef->y_pri_strength[0] == 0 &&
+ cdef->y_sec_strength[0] == 0 &&
+ cdef->uv_pri_strength[0] == 0 &&
+ cdef->uv_sec_strength[0] == 0);
+ hantro_reg_write(vpu, &av1_enable_cdef, enable_cdef);
hantro_reg_write(vpu, &av1_cdef_bits, cdef->bits);
hantro_reg_write(vpu, &av1_cdef_damping, cdef->damping_minus_3);
@@ -1953,8 +1961,6 @@ static void rockchip_vpu981_av1_dec_set_parameters(struct hantro_ctx *ctx)
!!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_SHOW_FRAME));
hantro_reg_write(vpu, &av1_switchable_motion_mode,
!!(ctrls->frame->flags & V4L2_AV1_FRAME_FLAG_IS_MOTION_MODE_SWITCHABLE));
- hantro_reg_write(vpu, &av1_enable_cdef,
- !!(ctrls->sequence->flags & V4L2_AV1_SEQUENCE_FLAG_ENABLE_CDEF));
hantro_reg_write(vpu, &av1_allow_masked_compound,
!!(ctrls->sequence->flags
& V4L2_AV1_SEQUENCE_FLAG_ENABLE_MASKED_COMPOUND));
--
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