[ rockchip-dev ] remove obviously deprecated and move the rest away that kernel can compile

patch/kernel/rockchip-dev/1008-rockchip-dwc2-usb-partial-power-down.patch

@@ -1,44 +0,0 @@
-From 04fbf78e4e569bf872f1ffcb0a6f9b89569dc913 Mon Sep 17 00:00:00 2001
-From: Hal Emmerich <hal@halemmerich.com>
-Date: Thu, 19 Jul 2018 21:48:08 -0500
-Subject: [PATCH] usb: dwc2: disable power_down on rockchip devices
-
- The bug would let the usb controller enter partial power down,
- which was formally known as hibernate, upon boot if nothing was plugged
- in to the port. Partial power down couldn't be exited properly, so any
- usb devices plugged in after boot would not be usable.
-
- Before the name change, params.hibernation was false by default, so
- _dwc2_hcd_suspend() would skip entering hibernation. With the
- rename, _dwc2_hcd_suspend() was changed to use  params.power_down
- to decide whether or not to enter partial power down.
-
- Since params.power_down is non-zero by default, it needs to be set
- to 0 for rockchip devices to restore functionality.
-
- This bug was reported in the linux-usb thread:
- REGRESSION: usb: dwc2: USB device not seen after boot
-
- The commit that caused this regression is:
- 6d23ee9caa6790aea047f9aca7f3c03cb8d96eb6
-
-Signed-off-by: Hal Emmerich <hal@halemmerich.com>
----
- drivers/usb/dwc2/params.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
-index f03e418..492607a 100644
---- a/drivers/usb/dwc2/params.c
-+++ b/drivers/usb/dwc2/params.c
-@@ -82,6 +82,7 @@ static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
- 	p->host_perio_tx_fifo_size = 256;
- 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
- 		GAHBCFG_HBSTLEN_SHIFT;
-+	p->power_down = 0;
- }
- 
- static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
--- 
-2.11.0
-

patch/kernel/rockchip-dev/1009-drivers-clk-rk3288-support-for-dedicating-NPLL-to-a-.patch

@@ -1,228 +0,0 @@
-From bc16cd0aa3cdaaff27b9bf2d3282ccfff81d8784 Mon Sep 17 00:00:00 2001
-From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
-Date: Sat, 29 Sep 2018 02:56:32 +0200
-Subject: [PATCH 5/6] drivers: clk-rk3288: support for dedicating NPLL to a VOP
-
-This patch is taken from Urja Rannikko ( @urjaman ) patchset here :
-https://github.com/urjaman/arch-c201/blob/master/linux-c201/0020-RK3288-HDMI-clock-hacks-combined.patch
-https://www.spinics.net/lists/arm-kernel/msg673156.html
-
-I'm not really sure what this does exactly. It basically sets the
-parent clock of the newly added clocks, if the newly added property
-"rockchip,npll-for-vop" is detected and set.
-
-I have no clear idea how HDMI Neuronal PLL (and PLL in general) work,
-so I cannot comment on what it's doing and if it's a good idea in
-general.
-
-The only thing I know from this patchset is that it works and have
-resolved some purple line issue at the left of my HDMI screen, when
-connected to MiQi or Tinkerboard devices.
-
-Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
----
- drivers/clk/rockchip/clk-rk3288.c | 98 ++++++++++++++++++++++++++++++++-------
- drivers/clk/rockchip/clk.h        |  3 ++
- 2 files changed, 85 insertions(+), 16 deletions(-)
-
-diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
-index fd2058f7d..b5b56169d 100644
---- a/drivers/clk/rockchip/clk-rk3288.c
-+++ b/drivers/clk/rockchip/clk-rk3288.c
-@@ -83,22 +83,43 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
- 	RK3066_PLL_RATE( 768000000, 1, 64, 2),
- 	RK3066_PLL_RATE( 742500000, 8, 495, 2),
- 	RK3066_PLL_RATE( 696000000, 1, 58, 2),
-+	RK3066_PLL_RATE_NB(621000000, 1, 207, 8, 1),
- 	RK3066_PLL_RATE( 600000000, 1, 50, 2),
- 	RK3066_PLL_RATE_NB(594000000, 1, 198, 8, 1),
- 	RK3066_PLL_RATE( 552000000, 1, 46, 2),
- 	RK3066_PLL_RATE( 504000000, 1, 84, 4),
- 	RK3066_PLL_RATE( 500000000, 3, 125, 2),
- 	RK3066_PLL_RATE( 456000000, 1, 76, 4),
-+	RK3066_PLL_RATE( 428000000, 1, 107, 6),
- 	RK3066_PLL_RATE( 408000000, 1, 68, 4),
- 	RK3066_PLL_RATE( 400000000, 3, 100, 2),
-+	RK3066_PLL_RATE_NB( 394000000, 1, 197, 12, 1),
- 	RK3066_PLL_RATE( 384000000, 2, 128, 4),
- 	RK3066_PLL_RATE( 360000000, 1, 60, 4),
-+	RK3066_PLL_RATE_NB( 356000000, 1, 178, 12, 1),
-+	RK3066_PLL_RATE_NB( 324000000, 1, 189, 14, 1),
- 	RK3066_PLL_RATE( 312000000, 1, 52, 4),
--	RK3066_PLL_RATE( 300000000, 1, 50, 4),
--	RK3066_PLL_RATE( 297000000, 2, 198, 8),
-+	RK3066_PLL_RATE_NB( 308000000, 1, 154, 12, 1),
-+	RK3066_PLL_RATE_NB( 303000000, 1, 202, 16, 1),
-+	RK3066_PLL_RATE( 300000000, 1, 75, 6),
-+	RK3066_PLL_RATE_NB( 297750000, 2, 397, 16, 1),
-+	RK3066_PLL_RATE_NB( 293250000, 2, 391, 16, 1),
-+	RK3066_PLL_RATE_NB( 292500000, 1, 195, 16, 1),
-+	RK3066_PLL_RATE( 273600000, 1, 114, 10),
-+	RK3066_PLL_RATE_NB( 273000000, 1, 182, 16, 1),
-+	RK3066_PLL_RATE_NB( 270000000, 1, 180, 16, 1),
-+	RK3066_PLL_RATE_NB( 266250000, 2, 355, 16, 1),
-+	RK3066_PLL_RATE_NB( 256500000, 1, 171, 16, 1),
- 	RK3066_PLL_RATE( 252000000, 1, 84, 8),
--	RK3066_PLL_RATE( 216000000, 1, 72, 8),
--	RK3066_PLL_RATE( 148500000, 2, 99, 8),
-+	RK3066_PLL_RATE_NB( 250500000, 1, 167, 16, 1),
-+	RK3066_PLL_RATE_NB( 243428571, 1, 142, 14, 1),
-+	RK3066_PLL_RATE( 238000000, 1, 119, 12),
-+	RK3066_PLL_RATE_NB( 219750000, 2, 293, 16, 1),
-+	RK3066_PLL_RATE_NB( 216000000, 1, 144, 16, 1),
-+	RK3066_PLL_RATE_NB( 213000000, 1, 142, 16, 1),
-+	RK3066_PLL_RATE( 195428571, 1, 114, 14),
-+	RK3066_PLL_RATE( 160000000, 1, 80, 12),
-+	RK3066_PLL_RATE( 157500000, 1, 105, 16),
- 	RK3066_PLL_RATE( 126000000, 1, 84, 16),
- 	RK3066_PLL_RATE(  48000000, 1, 64, 32),
- 	{ /* sentinel */ },
-@@ -194,10 +215,14 @@ PNAME(mux_ddrphy_p)		= { "dpll_ddr", "gpll_ddr" };
- PNAME(mux_aclk_cpu_src_p)	= { "cpll_aclk_cpu", "gpll_aclk_cpu" };
- 
- PNAME(mux_pll_src_cpll_gpll_p)		= { "cpll", "gpll" };
--PNAME(mux_pll_src_npll_cpll_gpll_p)	= { "npll", "cpll", "gpll" };
--PNAME(mux_pll_src_cpll_gpll_npll_p)	= { "cpll", "gpll", "npll" };
-+PNAME_ED(mux_pll_src_npll_cpll_gpll_p)	= { "npll", "cpll", "gpll" };
-+
-+PNAME_ED(mux_pll_src_cgn_pll_nonvop_p)	= { "cpll", "gpll", "npll" };
-+PNAME_ED(mux_pll_src_cgn_pll_vop0_p) = { "cpll", "gpll", "npll" };
-+PNAME_ED(mux_pll_src_cgn_pll_vop1_p) = { "cpll", "gpll", "npll" };
-+
- PNAME(mux_pll_src_cpll_gpll_usb480m_p)	= { "cpll", "gpll", "usbphy480m_src" };
--PNAME(mux_pll_src_cpll_gll_usb_npll_p)	= { "cpll", "gpll", "usbphy480m_src", "npll" };
-+PNAME_ED(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "usbphy480m_src", "npll" };
- 
- PNAME(mux_mmc_src_p)	= { "cpll", "gpll", "xin24m", "xin24m" };
- PNAME(mux_i2s_pre_p)	= { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
-@@ -443,24 +468,24 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
- 			RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
- 			RK3288_CLKGATE_CON(3), 4, GFLAGS),
- 
--	COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,
-+	COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cgn_pll_vop0_p, 0,
- 			RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
- 			RK3288_CLKGATE_CON(3), 1, GFLAGS),
--	COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,
-+	COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cgn_pll_vop1_p, 0,
- 			RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS,
- 			RK3288_CLKGATE_CON(3), 3, GFLAGS),
- 
- 	COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
- 			RK3288_CLKSEL_CON(28), 15, 1, MFLAGS,
- 			RK3288_CLKGATE_CON(3), 12, GFLAGS),
--	COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0,
-+	COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cgn_pll_nonvop_p, 0,
- 			RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS,
- 			RK3288_CLKGATE_CON(3), 13, GFLAGS),
- 
--	COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0,
-+	COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cgn_pll_nonvop_p, 0,
- 			RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS,
- 			RK3288_CLKGATE_CON(3), 14, GFLAGS),
--	COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0,
-+	COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cgn_pll_nonvop_p, 0,
- 			RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,
- 			RK3288_CLKGATE_CON(3), 15, GFLAGS),
- 
-@@ -469,16 +494,16 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
- 	GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
- 			RK3288_CLKGATE_CON(5), 11, GFLAGS),
- 
--	COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0,
-+	COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cgn_pll_nonvop_p, 0,
- 			RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS,
- 			RK3288_CLKGATE_CON(13), 13, GFLAGS),
- 	DIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0,
- 			RK3288_CLKSEL_CON(40), 12, 2, DFLAGS),
- 
--	COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0,
-+	COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", mux_pll_src_cgn_pll_nonvop_p, 0,
- 			RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
- 			RK3288_CLKGATE_CON(13), 14, GFLAGS),
--	COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0,
-+	COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cgn_pll_nonvop_p, 0,
- 			RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
- 			RK3288_CLKGATE_CON(13), 15, GFLAGS),
- 
-@@ -552,7 +577,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
- 	COMPOSITE(0, "sclk_tspout", mux_tspout_p, 0,
- 			RK3288_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS,
- 			RK3288_CLKGATE_CON(4), 11, GFLAGS),
--	COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
-+	COMPOSITE(0, "sclk_tsp", mux_pll_src_cgn_pll_nonvop_p, 0,
- 			RK3288_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
- 			RK3288_CLKGATE_CON(4), 10, GFLAGS),
- 
-@@ -912,6 +937,7 @@ static void __init rk3288_clk_init(struct device_node *np)
- {
- 	struct rockchip_clk_provider *ctx;
- 	struct clk *clk;
-+	s32 npll_vop = -1;
- 
- 	rk3288_cru_base = of_iomap(np, 0);
- 	if (!rk3288_cru_base) {
-@@ -919,6 +945,46 @@ static void __init rk3288_clk_init(struct device_node *np)
- 		return;
- 	}
- 
-+	if (!of_property_read_s32(np, "rockchip,npll-for-vop", &npll_vop)) {
-+		if ((npll_vop < -1) || (npll_vop > 1)) {
-+			pr_warn("%s: invalid VOP to dedicate NPLL to: %d\n",
-+				__func__, npll_vop);
-+		} else if (npll_vop >= 0) {
-+			unsigned int vop_clk_id;
-+			const char ** npll_names;
-+			const char ** non_npll_names;
-+			int i;
-+
-+			/* Firstly, not-VOP needs to not use npll */
-+			mux_pll_src_npll_cpll_gpll_p[0] = "dummy_npll";
-+			mux_pll_src_cgn_pll_nonvop_p[2] = "dummy_npll";
-+			mux_pll_src_cpll_gll_usb_npll_p[3] = "dummy_npll";
-+
-+			/* Then the npll VOP needs to only use npll, and the other one not use npll. */
-+			if (npll_vop) {
-+				vop_clk_id = DCLK_VOP1;
-+				npll_names = mux_pll_src_cgn_pll_vop1_p;
-+				non_npll_names = mux_pll_src_cgn_pll_vop0_p;
-+			} else {
-+				vop_clk_id = DCLK_VOP0;
-+				npll_names = mux_pll_src_cgn_pll_vop0_p;
-+				non_npll_names = mux_pll_src_cgn_pll_vop1_p;
-+			}
-+			npll_names[0] = "dummy_cpll";
-+			npll_names[1] = "dummy_gpll";
-+			non_npll_names[2] = "dummy_npll";
-+
-+			/* Lastly the npll-dedicated-VOP needs to be able to control npll. */
-+			for (i = 0; i < ARRAY_SIZE(rk3288_clk_branches); i++) {
-+				if (rk3288_clk_branches[i].id == vop_clk_id) {
-+					rk3288_clk_branches[i].flags |= CLK_SET_RATE_PARENT;
-+					break;
-+				}
-+			}
-+			pr_debug("%s: npll dedicated for VOP %d\n", __func__, npll_vop);
-+		}
-+	}
-+
- 	ctx = rockchip_clk_init(np, rk3288_cru_base, CLK_NR_CLKS);
- 	if (IS_ERR(ctx)) {
- 		pr_err("%s: rockchip clk init failed\n", __func__);
-diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
-index 6b53fff4c..dbda9d281 100644
---- a/drivers/clk/rockchip/clk.h
-+++ b/drivers/clk/rockchip/clk.h
-@@ -382,6 +382,9 @@ struct clk *rockchip_clk_register_muxgrf(const char *name,
- 
- #define PNAME(x) static const char *const x[] __initconst
- 
-+/* For when you want to be able to modify the pointers. */
-+#define PNAME_ED(x) static const char * x[] __initdata
-+
- enum rockchip_clk_branch_type {
- 	branch_composite,
- 	branch_mux,
--- 
-2.16.4
-

patch/kernel/rockchip-dev/3002_RK3288-add-missing-interleaved-pcm-attribute.patch

@@ -1,37 +0,0 @@
-From 24d6638302b48328a58c13439276d4531af4ca7d Mon Sep 17 00:00:00 2001
-From: Katsuhiro Suzuki <katsuhiro@katsuster.net>
-Date: Tue, 11 Sep 2018 01:39:32 +0900
-Subject: ASoC: rockchip: add missing INTERLEAVED PCM attribute
-
-This patch adds SNDRV_PCM_INFO_INTERLEAVED into PCM hardware info.
-
-Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- sound/soc/rockchip/rockchip_pcm.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
-(limited to 'sound/soc/rockchip')
-
-Armbian Note: this patch has been backported from 4.20 to 4.19 due to break in rockchip HDMI/I2S audio. This
-can be safely removed once there is a new kernel bump.
-Origin: <https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/sound/soc/rockchip?h=linux-4.20.y&id=24d6638302b48328a58c13439276d4531af4ca7d>
-
-diff --git a/sound/soc/rockchip/rockchip_pcm.c b/sound/soc/rockchip/rockchip_pcm.c
-index f77538319221..9e7b5fa4cf59 100644
---- a/sound/soc/rockchip/rockchip_pcm.c
-+++ b/sound/soc/rockchip/rockchip_pcm.c
-@@ -21,7 +21,8 @@ static const struct snd_pcm_hardware snd_rockchip_hardware = {
- 	.info			= SNDRV_PCM_INFO_MMAP |
- 				  SNDRV_PCM_INFO_MMAP_VALID |
- 				  SNDRV_PCM_INFO_PAUSE |
--				  SNDRV_PCM_INFO_RESUME,
-+				  SNDRV_PCM_INFO_RESUME |
-+				  SNDRV_PCM_INFO_INTERLEAVED,
- 	.period_bytes_min	= 32,
- 	.period_bytes_max	= 8192,
- 	.periods_min		= 1,
--- 
-cgit 1.2-0.3.lf.el7
-
-