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xt-q8l-v10: bump to u-boot v2021.01

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* fix SPL not booting due to signed/unsigned integer comparison
 * gpio7 now uses dm-pre-reloc to correctly compile TPL
 * adjusted minor thing is defconfig, more room for stacks
 * includes patch for efuse for next v2021.04
This commit is contained in:
Paolo Sabatino 2021-04-05 13:48:30 +00:00
parent e4d895607e
commit 2dbdae2845
5 changed files with 274 additions and 13 deletions
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2
config/sources/families/rockchip.conf
View File

@ -7,7 +7,7 @@ BOOTDELAY=1
if [[ $BOARD == miqi ]]; then
BOOTBRANCH='tag:v2017.11'
elif [[ $BOARD == xt-q8l-v10 ]]; then
BOOTBRANCH='tag:v2020.10'
BOOTBRANCH='tag:v2021.01'
else
BOOTBRANCH='tag:v2018.11'
fi

238
patch/u-boot/u-boot-rockchip/board_xt-q8l-v10/u-boot-1000-enable-rockchip-efuse-for-rk3288-rk322x-rk3328-v2021.04.patch.disabled Normal file
View File

@ -0,0 +1,238 @@
From 4eaea4d482ef3b8f995d2928d9cc9f3661222cf5 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Mon, 5 Apr 2021 12:20:52 +0000
Subject: [PATCH] enable rockchip efuse for rk3288, rk322x, rk3328
---
arch/arm/dts/rk3288.dtsi | 3 +-
arch/arm/mach-rockchip/misc.c | 1 +
drivers/misc/rockchip-efuse.c | 142 +++++++++++++++++++++++++++++++++-
3 files changed, 140 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index 22bb06cec5..381391360c 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -919,8 +919,7 @@
efuse: efuse@ffb40000 {
compatible = "rockchip,rk3288-efuse";
- reg = <0xffb40000 0x10000>;
- status = "disabled";
+ reg = <0xffb40000 0x20>;
};
gic: interrupt-controller@ffc01000 {
diff --git a/arch/arm/mach-rockchip/misc.c b/arch/arm/mach-rockchip/misc.c
index 87eebd9872..eb7c2ec992 100644
--- a/arch/arm/mach-rockchip/misc.c
+++ b/arch/arm/mach-rockchip/misc.c
@@ -18,6 +18,7 @@
#include <misc.h>
#include <u-boot/crc.h>
#include <u-boot/sha256.h>
+#include <hash.h>
#include <asm/arch-rockchip/misc.h>
diff --git a/drivers/misc/rockchip-efuse.c b/drivers/misc/rockchip-efuse.c
index 083ee65e0a..0fcbcfc69a 100644
--- a/drivers/misc/rockchip-efuse.c
+++ b/drivers/misc/rockchip-efuse.c
@@ -14,6 +14,7 @@
#include <linux/bitops.h>
#include <linux/delay.h>
#include <misc.h>
+#include <stdlib.h>
#define RK3399_A_SHIFT 16
#define RK3399_A_MASK 0x3ff
@@ -27,6 +28,24 @@
#define RK3399_STROBE BIT(1)
#define RK3399_CSB BIT(0)
+#define RK3288_A_SHIFT 6
+#define RK3288_A_MASK 0x3ff
+#define RK3288_NFUSES 32
+#define RK3288_BYTES_PER_FUSE 1
+#define RK3288_PGENB BIT(3)
+#define RK3288_LOAD BIT(2)
+#define RK3288_STROBE BIT(1)
+#define RK3288_CSB BIT(0)
+
+#define RK3328_INT_STATUS 0x0018
+#define RK3328_DOUT 0x0020
+#define RK3328_AUTO_CTRL 0x0024
+#define RK3328_INT_FINISH BIT(0)
+#define RK3328_AUTO_ENB BIT(0)
+#define RK3328_AUTO_RD BIT(1)
+
+typedef int (*EFUSE_READ)(struct udevice *dev, int offset, void *buf, int size);
+
struct rockchip_efuse_regs {
u32 ctrl; /* 0x00 efuse control register */
u32 dout; /* 0x04 efuse data out register */
@@ -35,6 +54,10 @@ struct rockchip_efuse_regs {
u32 jtag_pass; /* 0x10 JTAG password */
u32 strobe_finish_ctrl;
/* 0x14 efuse strobe finish control register */
+ u32 int_status;/* 0x18 */
+ u32 reserved; /* 0x1c */
+ u32 dout2; /* 0x20 */
+ u32 auto_ctrl; /* 0x24 */
};
struct rockchip_efuse_plat {
@@ -53,7 +76,7 @@ static int dump_efuses(struct cmd_tbl *cmdtp, int flag,
*/
struct udevice *dev;
- u8 fuses[128];
+ u8 fuses[128] = {0};
int ret;
/* retrieve the device */
@@ -77,7 +100,7 @@ static int dump_efuses(struct cmd_tbl *cmdtp, int flag,
}
U_BOOT_CMD(
- rk3399_dump_efuses, 1, 1, dump_efuses,
+ rockchip_dump_efuses, 1, 1, dump_efuses,
"Dump the content of the efuses",
""
);
@@ -127,10 +150,110 @@ static int rockchip_rk3399_efuse_read(struct udevice *dev, int offset,
return 0;
}
+static int rockchip_rk3288_efuse_read(struct udevice *dev, int offset,
+ void *buf, int size)
+{
+ struct rockchip_efuse_plat *plat = dev_get_plat(dev);
+ struct rockchip_efuse_regs *efuse =
+ (struct rockchip_efuse_regs *)plat->base;
+ u8 *buffer = buf;
+ int max_size = RK3288_NFUSES * RK3288_BYTES_PER_FUSE;
+
+ if (size > (max_size - offset))
+ size = max_size - offset;
+
+ /* Switch to read mode */
+ writel(RK3288_LOAD | RK3288_PGENB, &efuse->ctrl);
+ udelay(1);
+
+ while (size--) {
+ writel(readl(&efuse->ctrl) &
+ (~(RK3288_A_MASK << RK3288_A_SHIFT)),
+ &efuse->ctrl);
+ /* set addr */
+ writel(readl(&efuse->ctrl) |
+ ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT),
+ &efuse->ctrl);
+ udelay(1);
+ /* strobe low to high */
+ writel(readl(&efuse->ctrl) |
+ RK3288_STROBE, &efuse->ctrl);
+ ndelay(60);
+ /* read data */
+ *buffer++ = readl(&efuse->dout);
+ /* reset strobe to low */
+ writel(readl(&efuse->ctrl) &
+ (~RK3288_STROBE), &efuse->ctrl);
+ udelay(1);
+ }
+
+ /* Switch to standby mode */
+ writel(RK3288_PGENB | RK3288_CSB, &efuse->ctrl);
+
+ return 0;
+}
+
+static int rockchip_rk3328_efuse_read(struct udevice *dev, int offset,
+ void *buf, int size)
+{
+ struct rockchip_efuse_plat *plat = dev_get_plat(dev);
+ struct rockchip_efuse_regs *efuse =
+ (struct rockchip_efuse_regs *)plat->base;
+ unsigned int addr_start, addr_end, addr_offset, addr_len;
+ u32 out_value, status;
+ u8 *buffer;
+ int ret = 0, i = 0, j = 0;
+
+ /* Max non-secure Byte */
+ if (size > 32)
+ size = 32;
+
+ /* 128 Byte efuse, 96 Byte for secure, 32 Byte for non-secure */
+ offset += 96;
+ addr_start = rounddown(offset, RK3399_BYTES_PER_FUSE) /
+ RK3399_BYTES_PER_FUSE;
+ addr_end = roundup(offset + size, RK3399_BYTES_PER_FUSE) /
+ RK3399_BYTES_PER_FUSE;
+ addr_offset = offset % RK3399_BYTES_PER_FUSE;
+ addr_len = addr_end - addr_start;
+
+ buffer = calloc(1, sizeof(*buffer) * addr_len * RK3399_BYTES_PER_FUSE);
+ if (!buffer)
+ return -ENOMEM;
+
+ for (j = 0; j < addr_len; j++) {
+ writel(RK3328_AUTO_RD | RK3328_AUTO_ENB |
+ ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT),
+ &efuse->auto_ctrl);
+ udelay(5);
+ status = readl(&efuse->int_status);
+ if (!(status & RK3328_INT_FINISH)) {
+ ret = -EIO;
+ goto err;
+ }
+ out_value = readl(&efuse->dout2);
+ writel(RK3328_INT_FINISH, &efuse->int_status);
+
+ memcpy(&buffer[i], &out_value, RK3399_BYTES_PER_FUSE);
+ i += RK3399_BYTES_PER_FUSE;
+ }
+ memcpy(buf, buffer + addr_offset, size);
+err:
+ free(buffer);
+
+ return ret;
+}
+
static int rockchip_efuse_read(struct udevice *dev, int offset,
void *buf, int size)
{
- return rockchip_rk3399_efuse_read(dev, offset, buf, size);
+ EFUSE_READ efuse_read = NULL;
+
+ efuse_read = (EFUSE_READ)dev_get_driver_data(dev);
+ if (!efuse_read)
+ return -ENOSYS;
+
+ return (*efuse_read)(dev, offset, buf, size);
}
static const struct misc_ops rockchip_efuse_ops = {
@@ -146,7 +269,18 @@ static int rockchip_efuse_of_to_plat(struct udevice *dev)
}
static const struct udevice_id rockchip_efuse_ids[] = {
- { .compatible = "rockchip,rk3399-efuse" },
+ {
+ .compatible = "rockchip,rk3288-efuse",
+ .data = (ulong)&rockchip_rk3288_efuse_read,
+ },
+ {
+ .compatible = "rockchip,rk3328-efuse",
+ .data = (ulong)&rockchip_rk3328_efuse_read,
+ },
+ {
+ .compatible = "rockchip,rk3399-efuse",
+ .data = (ulong)&rockchip_rk3399_efuse_read,
+ },
{}
};
--
2.25.1

26
patch/u-boot/u-boot-rockchip/board_xt-q8l-v10/u-boot-1004-fix-signed-unsigned-comparison-causing-massive-heada.patch Normal file
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@ -0,0 +1,26 @@
From 3f12642b5947ee63e1e6fe08df558206d1b4daff Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sat, 3 Apr 2021 19:38:20 +0000
Subject: [PATCH] Fix signed/unsigned comparison causing massive headache on
gcc-arm >= 8.0 due to valid images being unable to boot
---
drivers/core/lists.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/core/lists.c b/drivers/core/lists.c
index e06e4e853d..c355f0752f 100644
--- a/drivers/core/lists.c
+++ b/drivers/core/lists.c
@@ -58,7 +58,7 @@ static int bind_drivers_pass(struct udevice *parent, bool pre_reloc_only)
const int n_ents = ll_entry_count(struct driver_info, driver_info);
bool missing_parent = false;
int result = 0;
- uint idx;
+ int idx;
/*
* Do one iteration through the driver_info records. For of-platdata,
--
2.25.1

19
patch/u-boot/u-boot-rockchip/board_xt-q8l-v10/xt-q8l-v10-defconfig.patch
View File

@ -1,34 +1,34 @@
diff --git a/configs/xt-q8l-v10-rk3288_defconfig b/configs/xt-q8l-v10-rk3288_defconfig
new file mode 100644
index 00000000..c19a4a61
index 0000000000..7dbefe26b7
--- /dev/null
+++ b/configs/xt-q8l-v10-rk3288_defconfig
@@ -0,0 +1,98 @@
@@ -0,0 +1,95 @@
+CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x10000000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_ROCKCHIP_RK3288=y
+CONFIG_TARGET_XT_Q8L_V10_RK3288=y
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DEBUG_UART_BASE=0xff690000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SMBIOS_PRODUCT_NAME="xt-q8l-v10"
+CONFIG_DEFAULT_DEVICE_TREE="rk3288-xt-q8l-v10"
+CONFIG_DEBUG_UART=y
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="usb start"
+CONFIG_SILENT_CONSOLE=y
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_R=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x8000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
@ -45,8 +45,8 @@ index 00000000..c19a4a61
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_PARTITION_UUIDS=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3288-xt-q8l-v10"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+# CONFIG_TPL_OF_PLATDATA is not set
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
@ -91,8 +91,6 @@ index 00000000..c19a4a61
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_BPP16=y
+CONFIG_VIDEO_BPP32=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
@ -101,4 +99,3 @@ index 00000000..c19a4a61
+CONFIG_SHA256=y
+CONFIG_ERRNO_STR=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SMBIOS_MANUFACTURER="Rockchip"

2
patch/u-boot/u-boot-rockchip/board_xt-q8l-v10/xt-q8l-v10-device-tree.patch
View File

@ -419,7 +419,7 @@ index 00000000..be7a0806
+
+&pinctrl {
+
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+
+ /*
+ This pin configuration enables the power led and, most important,