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rockchip64: add rk3318-box tvbox board patch and configurations (#3921)

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* rockchip64: add rk3318-box tvbox board patch and configurations
* rockchip64: add missing bcm43342 patch for edge kernel
This commit is contained in:
Paolo 2022-06-23 06:30:54 +00:00 committed by GitHub
parent c38a66f19d
commit 2ca6a9381d
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
36 changed files with 7522 additions and 2 deletions
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11
config/boards/rk3318-box.tvb Normal file
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@ -0,0 +1,11 @@
# Rockchip RK3318 quad core 2/16Gb 1xETH USB3 WiFi
BOARD_NAME="RK3318 Box"
BOARDFAMILY="rockchip64"
BOOTCONFIG="rk3318-box_defconfig"
BOOT_FDT_FILE="rockchip/rk3318-box.dtb"
KERNEL_TARGET="legacy,current,edge"
DEFAULT_CONSOLE="both"
MODULES_BLACKLIST="analogix_dp bcmdhd"
BOOT_SCENARIO="tpl-blob-atf-mainline"
DDR_BLOB="rk33/rk3318_ddr_666Mhz_v1.16.bin"
BOOT_SOC="rk3328"

5
config/optional/boards/rk3318-box/_config/desktop/_all_distributions/environments/_all_environments/armbian/create_desktop_package.sh Executable file
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@ -0,0 +1,5 @@
# Fix for bad device detection for x.org when lima driver is in use
if [[ "$BRANCH" != "legacy" ]]; then
mkdir -p $destination/etc/X11/xorg.conf.d
cp $SRC/packages/bsp/rk3328/40-serverflags.conf $destination/etc/X11/xorg.conf.d
fi

8
config/sources/families/include/rockchip64_common.inc
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@ -439,6 +439,14 @@ family_tweaks_bsp() {
fi
if [[ $BOARD == rk3318-box ]]; then
# Optional board dtbo selection script
mkdir -p $destination/usr/local/bin
install -m 755 $SRC/packages/bsp/rk3318/rk3318-config $destination/usr/sbin
fi
if [[ $BOARD == pinebook-pro ]]; then
# special keys

519
packages/bsp/rk3318/rk3318-config Executable file
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@ -0,0 +1,519 @@
#!/bin/bash
DEVICE_TREE_PATH="/boot/dtb"
ARMBIAN_ENV_TXT="/boot/armbianEnv.txt"
BLACKLIST_MODPROBE_CONF="/etc/modprobe.d/blacklist-rk3318-box.conf"
BACKTITLE="Armbian RK3318/RK3328 device tree board selection | Paolo Sabatino"
TITLE="Board configuration"
MENU_TITLE="Please choose your board"
COLOR_RED="\Z1"
COLOR_BLACK="\Z0"
CONFIRM_FLASH_MISMATCH="\nYour board has a type of internal memory but you \
selected a board without support for that.\n\nYou will not be able to detect \
the internal memory and your system may not boot anymore\n\nAre you sure?"
INFORM_ALTERNATE_WIFI="\nNo Wifi chip has been detected.\n\nThis program will \
enable the alternative SDIO bus. You need to complete the \
configuration, reboot the box and run again ${COLOR_RED}`basename $0`${COLOR_BLACK} to probe the other \
bus."
NOTE_BOARD_SELECTION="${COLOR_RED}Important:${COLOR_BLACK} select the \
board configuration looking on the markings of the board.\nThe right \
configuration solve problems with devices detection like leds,\n\
wifi, bluetooth and improve general stability\n\n"
EFUSE_PATH="/sys/bus/nvmem/devices/rockchip-efuse0/nvmem"
SDIO_WIFI_PATH="/sys/bus/sdio/devices/mmc1:0001:1"
SDIO2_WIFI_PATH="/sys/bus/sdio/devices/mmc4:0001:1"
EMMC_DEVICE_PATH="/sys/bus/mmc/devices/mmc2:0001"
declare -A CHIP_IDS
declare -A WIFI_NAMES
declare -A WIFI_CHIPS
declare -A DT_EMMC_OVERLAYS
declare -A DT_LED_OVERLAYS
declare -A DT_CPU_OVERLAYS
declare -A DT_WIFI_OVERLAYS
# Declarations for the various SoCs IDs
CHIP_IDS+=(["524b3381"]="RK3318")
CHIP_IDS+=(["524b3382"]="RK3328")
# Declarations for the various Wifi IDs
WIFI_NAMES+=(["3030:3030"]="South Silicon Valley 6051p/6256p")
WIFI_NAMES+=(["024c:b703"]="Realtek RTL8703bs")
WIFI_NAMES+=(["024c:8179"]="Realtek RTL8189ES/ETV")
WIFI_NAMES+=(["6666:1111"]="Espressif ESP8089")
WIFI_NAMES+=(["02d0:4334"]="Broadcom BCM4334/AmPak AP6334")
WIFI_NAMES+=(["02d0:4330"]="Broadcom BCM4330/AmPak AP6330")
# Declarations for the various wifi IDs -> kernel modules
# In case the vendor has the same vendor:device ids for more than one
# device (the infamouse ssv6051p/6256p), modules are separated by comma
# and the user is asked which one she pefers.
# Note: this is only for legacy kernel for rockchip_wlan modules which
# load themselves without declaring their device ids.
WIFI_CHIPS+=(["3030:3030"]="ssv6051 ssv6x5x")
WIFI_CHIPS+=(["024c:b703"]="8723cs")
WIFI_CHIPS+=(["024c:8179"]="8189es")
#WIFI_CHIPS+=(["6666:1111"]="")
WIFI_CHIPS+=(["02d0:4334"]="")
WIFI_CHIPS+=(["02d0:4330"]="")
# Declarations for device tree overlays
DT_EMMC_OVERLAYS+=(["rk3318-box-emmc-ddr"]="enable eMMC DDR Mode")
DT_EMMC_OVERLAYS+=(["rk3318-box-emmc-hs200"]="enable eMMC HS200 Mode")
DT_LED_OVERLAYS+=(["n/a"]="Generic/unlisted")
DT_LED_OVERLAYS+=(["rk3318-box-led-conf1"]="YX_RK3328 boards")
DT_LED_OVERLAYS+=(["rk3318-box-led-conf2"]="X88_PRO_B boards")
DT_LED_OVERLAYS+=(["rk3318-box-led-conf3"]="MXQ-RK3328-D4 boards (w/ RK805)")
DT_CPU_OVERLAYS+=(["rk3318-box-cpu-hs"]="RK3318 or RK3328")
#DT_WIFI_OVERLAYS+=(["6666:1111"]="rk3318-box-wlan-esp8089")
DT_WIFI_OVERLAYS+=(["02d0:4334"]="rk3318-box-wlan-ap6334")
DT_WIFI_OVERLAYS+=(["02d0:4330"]="rk3318-box-wlan-ap6330")
DT_WIFI_ALTERNATE_SDIO="rk3318-box-wlan-ext"
KERNEL_VERSION=$(uname -r | cut -d "-" -f 1)
if [[ "$KERNEL_VERSION" < "4.5.0" ]]; then
LEGACY_KERNEL=1
else
LEGACY_KERNEL=0
fi
DT_OVERLAY_PREFIX="$(grep overlay_prefix /boot/armbianEnv.txt | cut -d "=" -f 2)-"
# Query the efuse to get the chip type.
function get_chip_type() {
CHIP_ID=$(od -A none -N 4 -tx1 $EFUSE_PATH | tr -d " ")
CHIP_TYPE=${CHIP_IDS[$CHIP_ID]}
CHIP_TYPE=${CHIP_TYPE:-"unknown"}
echo $CHIP_TYPE
return 0
}
# Get the chip serial, from bytes 7 to 22 of the efuse
function get_chip_serial() {
ASCII_PART=$(od -A none -j 7 -N 9 -tc $EFUSE_PATH | tr -d " ")
BIN_PART=$(od -A none -j 16 -N 7 -tx1 $EFUSE_PATH | tr -d " ")
echo "$ASCII_PART $BIN_PART"
return 0
}
# Get the cpu leakage, byte 23 of the efuse
function get_cpu_leakage() {
LEAKAGE=$(od -A none -j 23 -N 1 -tx1 $EFUSE_PATH | tr -d " ")
echo $LEAKAGE
return 0
}
# Get the logic leakage, byte 25 of the efuse
function get_logic_leakage() {
LEAKAGE=$(od -A none -j 25 -N 1 -tx1 $EFUSE_PATH | tr -d " ")
echo $LEAKAGE
return 0
}
# Get the CPU Version, byte 26 of the efuse
function get_cpu_version() {
CPU_VERSION=$(od -A none -j 26 -N 1 -t dI $EFUSE_PATH | tr -d " ")
CPU_VERSION=$((($CPU_VERSION >> 3) & 7)) # offset: 3 bits, size: 3 bits
echo $CPU_VERSION
return 0
}
function get_sdio_device_path() {
[[ -d "$SDIO_WIFI_PATH" ]] && echo $SDIO_WIFI_PATH
[[ -d "$SDIO2_WIFI_PATH" ]] && echo $SDIO2_WIFI_PATH
return 0
}
# Get the vendor and device ids of the wifi chip
function get_wifi_chip_id() {
SDIO_PATH="$1"
if [ -d "$SDIO_PATH" ]; then
VENDOR=$(cut -c 3- "$SDIO_PATH/vendor")
DEVICE=$(cut -c 3- "$SDIO_PATH/device")
echo "$VENDOR:$DEVICE"
return 0
fi
return 1
}
function get_internal_flash_type() {
if [ -d "$EMMC_DEVICE_PATH" ]; then
echo "eMMC"
elif [ -d "$NAND_DEVICE_PATH" ]; then
echo "NAND"
fi
return 0
}
function select_wifi_module() {
MODULES=$1
declare -a DIALOG_ENTRIES
declare -a MODULES
IDX=0
for MODULE in $WIFI_MODULE; do
MODULES[$IDX]="$MODULE"
DIALOG_ENTRIES+=("$IDX" "$MODULE")
IDX=$((IDX + 1))
done
MENU_TITLE="${BOARD_INFO}Please choose the wifi module suitable for your configuration:\n"
MENU_CMD=(dialog --colors --backtitle "$BACKTITLE" --title "$TITLE" --default-item "0" --menu "$MENU_TITLE" 24 0 20)
SELECTION=$("${MENU_CMD[@]}" "${DIALOG_ENTRIES[@]}" 2>&1 >/dev/tty)
if [[ $? -ne 0 ]]; then
return 1
fi
WIFI_MODULE="${MODULES[$SELECTION]}"
echo $WIFI_MODULE
return 0
}
# Blacklists all the modules buth whitelist only that one
# that has been detected
function apply_wifi_blacklist() {
# Detect wifi chip on legacy kernel and unblacklist it
WIFI_MODULE=$1
if [ ! -f $BLACKLIST_MODPROBE_CONF ]; then
touch $BLACKLIST_MODPROBE_CONF
fi
if [ -n "$WIFI_MODULE" ]; then
for MODULES in "${WIFI_CHIPS[@]}"; do
for MODULE in $MODULES; do
sed -i "/blacklist $MODULE/d" $BLACKLIST_MODPROBE_CONF
done
done
declare -A BLACKLIST_MODULES
for MODULES in "${WIFI_CHIPS[@]}"; do
for MODULE in $MODULES; do
if [ "$MODULE" != "$WIFI_MODULE" ]; then
BLACKLIST_MODULES+=([$MODULE]=1)
fi
done
done
for MODULE in "${!BLACKLIST_MODULES[@]}"; do
echo "blacklist $MODULE" >> $BLACKLIST_MODPROBE_CONF
done
echo "#blacklist $WIFI_MODULE" >> $BLACKLIST_MODPROBE_CONF
fi
# unsupported wifi_chip_type: blacklist all known wifi
# modules if the blacklist file exists. If the blacklist file does not exist just skip over
if [ -z $WIFI_MODULE ]; then
if [ -f $BLACKLIST_MODPROBE_CONF ]; then
for MODULE in "${WIFI_CHIPS[@]}"; do
sed -i "s/#blacklist $MODULE/blacklist $MODULE/g" $BLACKLIST_MODPROBE_CONF
done
fi
fi
}
function select_soc() {
declare -a DIALOG_ENTRIES
# SoC section
SELECTION="0"
[[ "$CHIP_TYPE" = "RK3328" ]] && SELECTION="2"
DIALOG_ENTRIES=("0" "RK3318 (max 1.1Ghz, slower but safer)")
DIALOG_ENTRIES+=("1" "RK3318 (max 1.3Ghz)")
DIALOG_ENTRIES+=("2" "RK3328 (max 1.3Ghz)")
MENU_TITLE="${BOARD_INFO}Select the SoC type:\n"
MENU_CMD=(dialog --colors --backtitle "$BACKTITLE" --title "$TITLE" --default-item "$SELECTION" --menu "$MENU_TITLE" 24 0 20)
SELECTION=$("${MENU_CMD[@]}" "${DIALOG_ENTRIES[@]}" 2>&1 >/dev/tty)
RET=$?
if [ "$RET" -eq 1 ]; then
echo "Cancelled"
return 1
fi
if [ "$RET" -ne 0 ]; then
echo "dialog utility returned an unexpected error code: $RET"
return 1
fi
[[ "$SELECTION" -eq 0 ]] && SELECTION=""
[[ "$SELECTION" -eq 1 ]] && SELECTION="rk3318-box-cpu-hs"
[[ "$SELECTION" -eq 2 ]] && SELECTION="rk3318-box-cpu-hs"
echo $SELECTION
return 0
}
function select_emmc_options() {
declare -a DIALOG_ENTRIES
for KEY in "${!DT_EMMC_OVERLAYS[@]}"; do
DIALOG_ENTRIES+=("$KEY" "${DT_EMMC_OVERLAYS[$KEY]}" "off")
done
MENU_TITLE="${BOARD_INFO}Select the internal eMMC additional speed options\nDefault mode (High Speed) is always enabled. Enabling additional modes may increase throughput, but not all boards/chips support them.\n"
MENU_CMD=(dialog --colors --backtitle "$BACKTITLE" --title "$TITLE" --checklist "$MENU_TITLE" 24 0 20)
SELECTION=$("${MENU_CMD[@]}" "${DIALOG_ENTRIES[@]}" 2>&1 >/dev/tty)
RET=$?
if [[ "$RET" -eq 1 ]]; then
echo "Cancelled"
return 1
fi
if [[ "$RES" -ne 0 ]]; then
echo "dialog utility returned an unexpected error code: $RET"
return 1
fi
echo $SELECTION
return 0
}
function select_led_configuration() {
declare -a DIALOG_ENTRIES
for KEY in "${!DT_LED_OVERLAYS[@]}"; do
DIALOG_ENTRIES+=($KEY "${DT_LED_OVERLAYS[$KEY]}")
done
MENU_TITLE="${BOARD_INFO}${NOTE_BOARD_SELECTION}"
MENU_CMD=(dialog --colors --backtitle "$BACKTITLE" --title "$TITLE" --menu "$MENU_TITLE" 24 0 20)
SELECTION=$("${MENU_CMD[@]}" "${DIALOG_ENTRIES[@]}" 2>&1 >/dev/tty)
RET=$?
if [[ "$RET" -eq 1 ]]; then
echo "Cancelled"
return 1
fi
if [[ "$RET" -ne 0 ]]; then
echo "dialog utility returned an unexpected error code: $RET"
return 1
fi
[[ "$SELECTION" = "n/a" ]] && SELECTION=""
echo $SELECTION
return 0
}
function inform_wifi_alternate() {
dialog --colors --msgbox "$INFORM_ALTERNATE_WIFI" 40 0
}
# ----- Entry point -----
USER_ID=$(id -u)
if [[ $USER_ID -ne 0 ]]; then
echo "Please run this script with administrative privileges"
exit 2
fi
declare -a DT_OVERLAYS_TO_APPLY
CHIP_TYPE=$(get_chip_type)
CHIP_SERIAL=$(get_chip_serial)
CPU_LEAKAGE=$(get_cpu_leakage)
LOGIC_LEAKAGE=$(get_logic_leakage)
CPU_VERSION=$(get_cpu_version)
FLASH_TYPE=$(get_internal_flash_type)
WIFI_PATH=$(get_sdio_device_path)
[[ -z "$WIFI_PATH" ]] && inform_wifi_alternate && DT_OVERLAYS_TO_APPLY+=($DT_WIFI_ALTERNATE_SDIO)
[[ "$WIFI_PATH" = "$SDIO2_WIFI_PATH" ]] && DT_OVERLAYS_TO_APPLY+=($DT_WIFI_ALTERNATE_SDIO)
WIFI_ID=$(get_wifi_chip_id $WIFI_PATH)
if [[ -z "$WIFI_ID" ]]; then
WIFI_NAME="not available"
else
WIFI_NAME="${WIFI_NAMES[$WIFI_ID]:-"unknown"} - Device ID: ${WIFI_ID}"
fi
if [[ -z "$FLASH_TYPE" ]]; then
FLASH_NAME="not detected"
else
FLASH_NAME="$FLASH_TYPE"
fi
BOARD_INFO="\nDetected board features:\n\
Chip type: ${COLOR_RED}\Zb${CHIP_TYPE}\Zn${COLOR_BLACK} - \
Serial: $CHIP_SERIAL\n\
CPU Leakage: 0x$CPU_LEAKAGE - Logic Leakage: 0x$LOGIC_LEAKAGE - CPU Version: 0x$CPU_VERSION\n\
Internal flash: ${COLOR_RED}\Zb${FLASH_NAME}\Zn${COLOR_BLACK}\n\
Wifi device: $WIFI_NAME\n\n"
### --- SOC selection ---
SELECTION=$(select_soc) || exit 1
DT_OVERLAYS_TO_APPLY+=($SELECTION)
#SELECTION=$(select_flash) || exit 1
#DT_OVERLAYS_TO_APPLY+=($SELECTION)
SELECTION=$(select_emmc_options) || exit 1
DT_OVERLAYS_TO_APPLY+=($SELECTION)
SELECTION=$(select_led_configuration) || exit 1
DT_OVERLAYS_TO_APPLY+=($SELECTION)
# Apply overlays for wifi chips
if [[ -n $WIFI_ID ]] && [[ -n "${DT_WIFI_OVERLAYS[$WIFI_ID]}" ]]; then
DT_OVERLAYS_TO_APPLY+=(${DT_WIFI_OVERLAYS[$WIFI_ID]})
fi
sed -i '/^overlays=/d' $ARMBIAN_ENV_TXT
if [[ $? -ne 0 ]]; then
echo "An error occurred while removing existing fdtfile entry from $ARMBIAN_ENV_TXT"
exit 1
fi
echo "overlays=${DT_OVERLAYS_TO_APPLY[@]}" >> $ARMBIAN_ENV_TXT
if [[ $? -ne 0 ]]; then
echo "An error occurred while adding overlays entry in $ARMBIAN_ENV_TXT"
exit 1
fi
# Apply the wifi blacklist only with legacy kernel
if [[ $LEGACY_KERNEL -eq 1 ]] && [[ -n "$WIFI_ID" ]]; then
WIFI_MODULE="${WIFI_CHIPS[$WIFI_ID]}"
if [[ -n $WIFI_MODULE ]]; then
echo "$WIFI_MODULE" | grep " " > /dev/null 2>&1
if [[ $? -eq 0 ]]; then
WIFI_MODULE=$(select_wifi_module "$WIFI_MODULE")
if [[ $? -ne 0 ]]; then
WIFI_MODULE=""
fi
fi
if [[ -n "$WIFI_MODULE" ]]; then
apply_wifi_blacklist "$WIFI_MODULE"
fi
fi
fi
echo ""
echo ""
echo "Device tree overlays enabled: ${DT_OVERLAYS_TO_APPLY[@]}"
# Print the outcome of wifi chip selection only with legacy kernel
# Mainline kernel is supposed to work ok by itself with hardware recognition
if [[ $LEGACY_KERNEL -eq 1 ]]; then
if [[ -n "$WIFI_MODULE" ]]; then
echo "Forcefully enabled wifi module $WIFI_MODULE"
fi
if [[ -n "$WIFI_ID" ]] && [[ ! -v WIFI_CHIPS[$WIFI_ID] ]]; then
echo "Wifi chip $WIFI_ID has been detected, but currently it is unsupported"
echo "Please report to: https://forum.armbian.com/topic/12656-wip-armbian-for-rk322x-devices/"
fi
fi
echo "Reboot the device to make changes effective!"
echo ""

13
packages/bsp/rk3328/40-serverflags.conf Normal file
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@ -0,0 +1,13 @@
Section "ServerFlags"
Option "AutoAddGPU" "off"
Option "Debug" "dmabuf_capable"
EndSection
Section "OutputClass"
Identifier "Lima"
Driver "modesetting"
MatchDriver "rockchip"
Option "AccelMethod" "glamor"
Option "PrimaryGPU" "true"
EndSection

737
patch/kernel/archive/rockchip64-4.4/board-tvbox-rk3318.patch Normal file
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@ -0,0 +1,737 @@
diff --git a/arch/arm64/boot/dts/rockchip/rk3318-box.dts b/arch/arm64/boot/dts/rockchip/rk3318-box.dts
new file mode 100644
index 00000000..93e102c0
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3318-box.dts
@@ -0,0 +1,719 @@
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "rk3328.dtsi"
+
+/ {
+ model = "Rockchip RK3318 BOX";
+ compatible = "rockchip,rk3318-box", "rockchip,rk3328-box", "rockchip,rk3328";
+
+ chosen {
+ bootargs = "swiotlb=1 kpti=0";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ drm_logo: drm-logo@00000000 {
+ compatible = "rockchip,drm-logo";
+ reg = <0x0 0x0 0x0 0x0>;
+ };
+
+ secure_memory: secure-memory@20000000 {
+ compatible = "rockchip,secure-memory";
+ reg = <0x0 0x20000000 0x0 0x0>;
+ };
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x1000000>;
+ linux,cma-default;
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+
+ vcc_18: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vccio_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ vcc_io: regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vccio_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+
+ xin32k: xin32k {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ #clock-cells = <0>;
+ };
+
+ external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac_clkin";
+ #clock-cells = <0x00>;
+ };
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_phy";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_sys: vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0m1_gpio>;
+ regulator-name = "vcc_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ /*
+ * USB3 vbus
+ */
+ vcc_host_vbus: vcc-host-vbus {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb30_host_drv>;
+ regulator-name = "vcc_host_vbus";
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_sys>;
+ };
+
+ /*
+ * USB2 OTG vbus
+ */
+ vcc_otg_vbus: vcc-otg-vbus {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb20_host_drv>;
+ regulator-name = "vcc_otg_vbus";
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vdd_arm: vdd-arm {
+ compatible = "pwm-regulator";
+ rockchip,pwm_id = <0>;
+ rockchip,pwm_voltage = <1100000>;
+ pwms = <&pwm0 0 5000 1>;
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-ramp-delay = <12500>;
+ regulator-settling-time-up-us = <250>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_logic: vdd-log {
+ compatible = "pwm-regulator";
+ rockchip,pwm_id = <1>;
+ rockchip,pwm_voltage = <1200000>;
+ pwms = <&pwm1 0 5000 1>;
+ regulator-name = "vdd_log";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-settling-time-up-us = <250>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ working {
+ gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-on";
+ default-state = "on";
+ };
+
+ };
+
+ ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&ir_int>;
+ pinctrl-names = "default";
+ };
+
+ hdmi-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <128>;
+ simple-audio-card,name = "HDMI";
+ simple-audio-card,cpu {
+ sound-dai = <&i2s0>;
+ };
+ simple-audio-card,codec {
+ sound-dai = <&hdmi>;
+ };
+ };
+
+ spdif-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "SPDIF";
+ simple-audio-card,cpu {
+ sound-dai = <&spdif>;
+ };
+ simple-audio-card,codec {
+ sound-dai = <&spdif_out>;
+ };
+ };
+
+ spdif_out: spdif-out {
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ };
+
+ wireless-bluetooth {
+ compatible = "bluetooth-platdata";
+ uart_rts_gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default", "rts_gpio";
+ pinctrl-0 = <&uart0_rts>;
+ pinctrl-1 = <&uart0_rts_gpio>;
+ BT,power_gpio = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>;
+ BT,wake_host_irq = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+ };
+
+ wireless-wlan {
+ compatible = "wlan-platdata";
+ rockchip,grf = <&grf>;
+ wifi_chip_type = "ap6330";
+ sdio_vref = <1800>;
+ WIFI,host_wake_irq = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
+ };
+
+ fd628_dev {
+ compatible = "fd628_dev";
+ fd628_gpio_clk = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+ fd628_gpio_dat = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ rkvdec_opp_table: rkvdec-opp-table {
+ compatible = "operating-points-v2";
+ rockchip,leakage-voltage-sel = <
+ 1 10 0
+ 11 254 1>;
+ nvmem-cells = <0x47>;
+ nvmem-cell-names = "rkvdec_leakage";
+
+ opp-100000000 {
+ opp-hz = <0x00 100000000>;
+ opp-microvolt = <975000>;
+ opp-microvolt-L0 = <975000>;
+ opp-microvolt-L1 = <950000>;
+ };
+
+ opp-200000000 {
+ opp-hz = <0x00 200000000>;
+ opp-microvolt = <975000>;
+ opp-microvolt-L0 = <975000>;
+ opp-microvolt-L1 = <950000>;
+ };
+
+ opp-500000000 {
+ opp-hz = <0x00 500000000>;
+ opp-microvolt = <1075000>;
+ opp-microvolt-L0 = <1075000>;
+ opp-microvolt-L1 = <1050000>;
+ };
+ };
+
+};
+
+&codec {
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&dfi {
+ status = "okay";
+};
+
+&dmc {
+ center-supply = <&vdd_logic>;
+ status = "disabled";
+};
+
+&display_subsystem {
+
+ logo-memory-region = <&drm_logo>;
+ secure-memory-region = <&secure_memory>;
+ ports = <&vop_out>;
+
+ status = "okay";
+
+ route {
+ route_hdmi: route-hdmi {
+ status = "okay";
+ connect = <&vop_out_hdmi>;
+ };
+ route_tve: route-tve {
+ status = "okay";
+ connect = <&vop_out_tve>;
+ };
+ };
+
+};
+
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ non-removable;
+ disable-wp;
+ non-removable;
+ num-slots = <0x01>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ mmc-ddr-1_8v;
+ supports-emmc;
+ status = "okay";
+};
+
+&gmac2phy {
+ phy-supply = <&vcc_phy>;
+
+ phy-mode = "rmii";
+ phy-is-integrated;
+ clock_in_out = "output";
+ assigned-clocks = <&cru SCLK_MAC2PHY>;
+ assigned-clock-rate = <50000000>;
+ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+
+ status = "okay";
+
+};
+
+&gpu {
+ status = "okay";
+ mali-supply = <&vdd_logic>;
+};
+
+&h265e {
+ status = "okay";
+};
+
+&h265e_mmu {
+ status = "okay";
+};
+
+&hdmi {
+ #sound-dai-cells = <0>;
+ ddc-i2c-scl-high-time-ns = <9625>;
+ ddc-i2c-scl-low-time-ns = <10000>;
+ status = "okay";
+};
+
+&hdmiphy {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2s0 {
+ #sound-dai-cells = <0>;
+ rockchip,bclk-fs = <128>;
+ status = "okay";
+};
+
+&i2s1 {
+ status = "okay";
+};
+
+
+&iep {
+ status = "disabled";
+};
+
+&iep_mmu {
+ status = "okay";
+};
+
+&io_domains {
+ status = "okay";
+
+ vccio1-supply = <&vcc_io>;
+ vccio2-supply = <&vcc_18>;
+ vccio3-supply = <&vcc_io>;
+ vccio4-supply = <&vcc_18>;
+ vccio5-supply = <&vcc_io>;
+ vccio6-supply = <&vcc_io>;
+ pmuio-supply = <&vcc_io>;
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&clk_32k_out>;
+
+ clk_32k {
+ clk_32k_out: clk-32k-out {
+ rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ ir {
+ ir_int: ir-int {
+ rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none_4ma>,
+ <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none_4ma>;
+ };
+ };
+
+ usb2 {
+ usb20_host_drv: usb20-host-drv {
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb3 {
+ usb30_host_drv: usb30-host-drv {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wireless-bluetooth {
+ uart0_gpios: uart0-gpios {
+ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&rkvdec {
+ status = "okay";
+ operating-points-v2 = <&rkvdec_opp_table>;
+ vcodec-supply = <&vdd_logic>;
+};
+
+&rkvdec_mmu {
+ status = "okay";
+};
+
+&sdio {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ disable-wp;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+ supports-sdio;
+ //sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ card-detect-delay = <800>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
+ supports-sd;
+ vmmc-supply = <&vcc_sd>;
+ status = "okay";
+};
+
+&spdif {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdifm0_tx>;
+ status = "okay";
+};
+
+&threshold {
+ temperature = <80000>; /* millicelsius */
+};
+
+&target {
+ temperature = <95000>; /* millicelsius */
+};
+
+&soc_crit {
+ temperature = <100000>; /* millicelsius */
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <0>;
+ rockchip,hw-tshut-polarity = <0>;
+ rockchip,hw-tshut-temp = <110000>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+ dma-names = "tx", "rx";
+};
+
+&u2phy {
+ status = "okay";
+};
+
+&u2phy_host {
+ vbus-supply = <&vcc_otg_vbus>;
+ status = "okay";
+};
+
+&u2phy_otg {
+ vbus-supply = <&vcc_otg_vbus>;
+ status = "okay";
+};
+
+&u3phy {
+ status = "okay";
+};
+
+&u3phy_utmi {
+ vbus-supply = <&vcc_host_vbus>;
+ status = "okay";
+};
+
+&u3phy_pipe {
+ vbus-supply = <&vcc_host_vbus>;
+ status = "okay";
+};
+
+&usb20_otg {
+ vusb_d-supply = <&vcc_otg_vbus>;
+ vusb_a-supply = <&vcc_otg_vbus>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usbdrd3 {
+ status = "okay";
+};
+
+&usbdrd_dwc3 {
+ status = "okay";
+};
+
+&vop {
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vpu_service {
+ status = "okay";
+ vcodec-supply = <&vdd_logic>;
+};
+
+&vpu_mmu {
+ status = "okay";
+};
+
+&vepu {
+ status = "okay";
+};
+
+&vepu_mmu {
+ status = "okay";
+};
+
+&venc_srv {
+ status = "okay";
+};
+
+&wdt {
+ status = "disabled";
+};
+
+&saradc {
+ vref-supply = <&vcc_18>;
+ status = "okay";
+};
+
+&rga {
+ status = "okay";
+};
+
+&pwm0 {
+ status = "okay";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm0_pin_pull_up>;
+};
+
+&pwm1 {
+ status = "okay";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm1_pin_pull_up>;
+};
+
+&pdm {
+ status = "okay";
+};
+
+&vdpu {
+ status = "okay";
+ allocator = <0>;
+};
+
+&dfi {
+ status = "okay";
+};
+
+&rockchip_suspend {
+ status = "okay";
+ rockchip,virtual-poweroff = <1>;
+ rockchip,sleep-mode-config = <
+ (0
+ |RKPM_SLP_CTR_VOL_PWM0
+ |RKPM_SLP_CTR_VOL_PWM1
+ )
+ >;
+};
+
+&cpu0_opp_table {
+ /delete-node/ opp-1392000000;
+ /delete-node/ opp-1512000000;
+};
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index e2aa7e9c..497e3b7c 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -25,6 +25,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb-dmic-pdm-v11.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-fpga.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-voice-module-board-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308b-evb-amic-v10.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-box.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-ai-va-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-ai-va-v11.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-ai-va-v11-i2s-dmic.dtb

31
patch/kernel/archive/rockchip64-4.4/brcmfmac-add-ap6334-fw-load.patch Normal file
View File

@ -0,0 +1,31 @@
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/sdio.c b/drivers/net/wireless/brcm80211/brcmfmac/sdio.c
index b082b885..a23d6aab 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/sdio.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/sdio.c
@@ -611,6 +611,8 @@ static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = {
#define BCM4330_NVRAM_NAME "brcm/brcmfmac4330-sdio.txt"
#define BCM4334_FIRMWARE_NAME "brcm/brcmfmac4334-sdio.bin"
#define BCM4334_NVRAM_NAME "brcm/brcmfmac4334-sdio.txt"
+#define BCM4334_AP6334_FIRMWARE_NAME "brcm/brcmfmac4334-sdio.bin"
+#define BCM4334_AP6334_NVRAM_NAME "brcm/brcmfmac4334-sdio.rockchip,rk3318-box.txt"
#define BCM43340_FIRMWARE_NAME "brcm/brcmfmac43340-sdio.bin"
#define BCM43340_NVRAM_NAME "brcm/brcmfmac43340-sdio.txt"
#define BCM4335_FIRMWARE_NAME "brcm/brcmfmac4335-sdio.bin"
@@ -640,6 +642,7 @@ MODULE_FIRMWARE(BCM4330_FIRMWARE_NAME);
MODULE_FIRMWARE(BCM4330_NVRAM_NAME);
MODULE_FIRMWARE(BCM4334_FIRMWARE_NAME);
MODULE_FIRMWARE(BCM4334_NVRAM_NAME);
+MODULE_FIRMWARE(BCM4334_AP6334_NVRAM_NAME);
MODULE_FIRMWARE(BCM43340_FIRMWARE_NAME);
MODULE_FIRMWARE(BCM43340_NVRAM_NAME);
MODULE_FIRMWARE(BCM4335_FIRMWARE_NAME);
@@ -677,7 +680,8 @@ static const struct brcmf_firmware_names brcmf_fwname_data[] = {
{ BRCM_CC_43241_CHIP_ID, 0xFFFFFFC0, BRCMF_FIRMWARE_NVRAM(BCM43241B5) },
{ BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4329) },
{ BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4330) },
- { BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4334) },
+ { BRCM_CC_4334_CHIP_ID, 0xFFFFFFF7, BRCMF_FIRMWARE_NVRAM(BCM4334) },
+ { BRCM_CC_4334_CHIP_ID, 0x8, BRCMF_FIRMWARE_NVRAM(BCM4334_AP6334) },
{ BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43340) },
{ BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4335) },
{ BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, BRCMF_FIRMWARE_NVRAM(BCM43362) },

1060
patch/kernel/archive/rockchip64-5.15/add-board-tvbox-rk3318.patch Normal file
View File

File diff suppressed because it is too large Load Diff

3
patch/kernel/archive/rockchip64-5.15/add-boards-to-dts-makefile.patch
View File

@ -2,11 +2,12 @@ diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchi
index 26661c7b7..1462ed38b 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -1,4 +1,22 @@
@@ -1,4 +1,23 @@
# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-pc.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-rock-pi-s.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-box.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2-rev00.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2-rev06.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2-rev20.dtb

102
patch/kernel/archive/rockchip64-5.15/overlays-02-add-rk3318-box-led-conf1.patch Normal file
View File

@ -0,0 +1,102 @@
From c7140e73b84431eb1e8cb31bdfce4c9d8a908de0 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sat, 17 Apr 2021 16:26:46 +0000
Subject: [PATCH 2/4] rk3318-box: add led configuration for YX_RK3328 boards
and clones
---
arch/arm64/boot/dts/rockchip/overlay/Makefile | 3 +-
.../rockchip/overlay/README.rockchip-overlays | 4 +-
.../overlay/rockchip-rk3318-box-led-conf1.dts | 54 +++++++++++++++++++
3 files changed, 58 insertions(+), 3 deletions(-)
create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-led-conf1.dts
diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile
index 9c07d64a1..8e9ff2ef1 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/Makefile
+++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile
@@ -10,7 +10,8 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-spi-spidev.dtbo \
rockchip-uart4.dtbo \
rockchip-dwc3-0-host.dtbo \
- rockchip-w1-gpio.dtbo
+ rockchip-w1-gpio.dtbo \
+ rockchip-rk3318-box-led-conf1.dtbo
scr-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-fixup.scr
diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-led-conf1.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-led-conf1.dts
new file mode 100644
index 000000000..1f5e5b7f8
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-led-conf1.dts
@@ -0,0 +1,54 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+
+ fragment@0 {
+ target-path = "/gpio-leds";
+ __overlay__ {
+
+ working {
+ gpios = <&gpio2 RK_PC7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc2";
+ };
+
+ /*
+ * no auxiliary led on YX_RK3328 boards
+ *
+ auxiliary {
+ gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+ label = "auxiliary";
+ linux,default-trigger = "mmc2";
+ default-state = "off";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_led_aux>;
+ };
+ */
+
+ };
+ };
+
+ /*
+ * TODO: needs to find the GPIO for this
+ *
+ fragment@1 {
+ target = <&gpio_keys>;
+ __overlay__ {
+
+ reset {
+ gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ debounce-interval = <200>;
+ wakeup-source;
+ };
+
+ };
+ };
+ */
+
+};
--
2.25.1
diff --git a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
index d6979437a..1de0a95e8 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
+++ b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
@@ -119,3 +119,7 @@ Activates 1-Wire GPIO master
Requires an external pull-up resistor on the data pin
or enabling the internal pull-up
+### rk3318-box-led-conf1
+
+Activates led/gpio configuration for rk3318 tv box boards with signature
+YX_RK3328 and clones

64
patch/kernel/archive/rockchip64-5.15/overlays-03-add-rk3318-box-emmc-ddr.patch Normal file
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@ -0,0 +1,64 @@
From 026b39ef85792467bdf1681e5abfca9a5231516f Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sat, 17 Apr 2021 16:29:00 +0000
Subject: [PATCH 3/4] rk3318-box: add eMMC DDR support device tree overlay for
rk3318-box
---
arch/arm64/boot/dts/rockchip/overlay/Makefile | 3 ++-
.../dts/rockchip/overlay/README.rockchip-overlays | 6 ++++++
.../overlay/rockchip-rk3318-box-emmc-ddr.dts | 14 ++++++++++++++
3 files changed, 22 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-emmc-ddr.dts
diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile
index 8e9ff2ef1..565ef20ac 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/Makefile
+++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile
@@ -11,7 +11,8 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-uart4.dtbo \
rockchip-dwc3-0-host.dtbo \
rockchip-w1-gpio.dtbo \
- rockchip-rk3318-box-led-conf1.dtbo
+ rockchip-rk3318-box-led-conf1.dtbo \
+ rockchip-rk3318-box-emmc-ddr.dtbo
scr-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-fixup.scr
diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-emmc-ddr.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-emmc-ddr.dts
new file mode 100644
index 000000000..b8f139099
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-emmc-ddr.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+ fragment@0 {
+ target = <&emmc>;
+ __overlay__ {
+ status = "okay";
+ mmc-ddr-1_8v;
+ };
+ };
+
+};
--
2.25.1
diff --git a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
index 1c645a9b8..01fa6f4ee 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
+++ b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
@@ -123,3 +123,9 @@ or enabling the internal pull-up
Activates led/gpio configuration for rk3318 tv box boards with signature
YX_RK3328 and clones
+
+### rk3318-box-emmc-ddr
+
+Activates eMMC DDR capability for rk3318 tv box boards. Probably all the eMMC chips
+nowadays support DDR mode, but its reliability heavily depends upon the quality
+of board wiring

163
patch/kernel/archive/rockchip64-5.15/overlays-04-add-rk3318-box-wlan-ap6334.patch Normal file
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@ -0,0 +1,163 @@
From 918d83519ccba3e540f6a9e0c201fcccf106988f Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sat, 17 Apr 2021 16:30:58 +0000
Subject: [PATCH 4/4] rk3318-box: add device tree overlay to support AP6334 and
clones
---
arch/arm64/boot/dts/rockchip/overlay/Makefile | 3 +-
.../rockchip/overlay/README.rockchip-overlays | 5 +++
.../rockchip-rk3318-box-wlan-ap6334.dts | 31 +++++++++++++++++++
3 files changed, 38 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ap6334.dts
diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile
index 565ef20ac..be038cc38 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/Makefile
+++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile
@@ -12,7 +12,8 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-dwc3-0-host.dtbo \
rockchip-w1-gpio.dtbo \
rockchip-rk3318-box-led-conf1.dtbo \
- rockchip-rk3318-box-emmc-ddr.dtbo
+ rockchip-rk3318-box-emmc-ddr.dtbo \
+ rockchip-rk3318-box-wlan-ap6334.dtbo
scr-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-fixup.scr
diff --git a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
index 01fa6f4ee..0e7eaeea2 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
+++ b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
@@ -129,3 +129,8 @@ YX_RK3328 and clones
Activates eMMC DDR capability for rk3318 tv box boards. Probably all the eMMC chips
nowadays support DDR mode, but its reliability heavily depends upon the quality
of board wiring
+
+### rk3318-box-wlan-ap6334
+
+Set up additional device tree bits to properly support ap6334 (broadcom BCM4334)
+wifi chip and clones
diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ap6334.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ap6334.dts
new file mode 100644
index 000000000..b7befaaeb
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ap6334.dts
@@ -0,0 +1,117 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+
+ fragment@0 {
+ target = <&sdio>;
+ __overlay__ {
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ //sd-uhs-ddr50;
+
+ brcmf_sdio: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ //brcm,drive-strength = <4>;
+ interrupt-parent = <&gpio1>;
+ interrupt-names = "host_wake";
+ interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio_host_wake>;
+ };
+
+ };
+ };
+
+ fragment@1 {
+ target = <&sdio_ext>;
+ __overlay__ {
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ //sd-uhs-ddr50;
+
+ brcmf_ext: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ //brcm,drive-strength = <8>;
+ interrupt-parent = <&gpio3>;
+ interrupt-names = "host_wake";
+ interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio_host_wake_ext>;
+ };
+
+ };
+ };
+
+ fragment@2 {
+ target = <&uart0>;
+ __overlay__ {
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>;
+
+ bluetooth {
+ compatible = "brcm,bcm4334b0-bt", "brcm,bcm4330-bt";
+ max-speed = <4000000>;
+ shutdown-gpios = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>;
+ device-wakeup-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>;
+ //host-wakeup-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+ vbat-supply = <&vcc_io>;
+ vddio-supply = <&vcc_18>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_reg_on_h>, <&bt_host_wake_l>, <&bt_device_wake_l>;
+ /*
+ interrupt-names = "host-wakeup";
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PD2 IRQ_TYPE_NONE>;
+ */
+ brcm,bt-pcm-int-params = [01 02 00 01 01];
+ };
+
+ };
+
+ };
+
+ fragment@3 {
+ target = <&pinctrl>;
+ __overlay__ {
+
+ bluetooth {
+
+
+ bt_reg_on_h: bt-enable {
+ rockchip,pins = <1 RK_PC5 0 &pcfg_pull_down>;
+ };
+
+ bt_device_wake_l: bt-device-wake {
+ rockchip,pins = <1 RK_PC7 0 &pcfg_pull_none>;
+ };
+
+ bt_host_wake_l: bt-host-wake {
+ rockchip,pins = <1 RK_PD2 0 &pcfg_pull_none>;
+ };
+
+ };
+
+ };
+ };
+
+};

82
patch/kernel/archive/rockchip64-5.15/overlays-05-add-rk3318-box-wlan-ext.patch Normal file
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@ -0,0 +1,82 @@
From 8b6cf9530ef8923895df798428a9b45534c9fd98 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sun, 18 Apr 2021 10:59:09 +0000
Subject: [PATCH] rk3318-box: add overlay for wifi over sdmmc_ext
---
arch/arm64/boot/dts/rockchip/overlay/Makefile | 3 +-
.../rockchip/overlay/README.rockchip-overlays | 6 ++++
.../overlay/rockchip-rk3318-box-wlan-ext.dts | 29 +++++++++++++++++++
3 files changed, 37 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ext.dts
diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile
index be038cc38..5e3318b57 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/Makefile
+++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile
@@ -13,7 +13,8 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-w1-gpio.dtbo \
rockchip-rk3318-box-led-conf1.dtbo \
rockchip-rk3318-box-emmc-ddr.dtbo \
- rockchip-rk3318-box-wlan-ap6334.dtbo
+ rockchip-rk3318-box-wlan-ap6334.dtbo \
+ rockchip-rk3318-box-wlan-ext.dtbo
scr-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-fixup.scr
diff --git a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
index 0e7eaeea2..b414e3069 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
+++ b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
@@ -134,3 +134,9 @@ of board wiring
Set up additional device tree bits to properly support ap6334 (broadcom BCM4334)
wifi chip and clones
+
+### rk3318-box-wlan-ext
+
+Use sdmmc_ext device for sdio devices, enabled wifi on some boards (notably
+X88 Pro) which have wifi chip attached to sdmmc_ext controller.
+
diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ext.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ext.dts
new file mode 100644
index 000000000..7f43fc20f
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ext.dts
@@ -0,0 +1,33 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+
+ fragment@0 {
+ target = <&sdio>;
+ __overlay__ {
+ mmc-pwrseq = <>;
+ status = "disabled";
+ };
+ };
+
+ fragment@1 {
+ target = <&sdio_ext>;
+ __overlay__ {
+ mmc-pwrseq = <&sdio_pwrseq>;
+ status = "okay";
+ };
+ };
+
+ fragment@2 {
+ target = <&sdmmc_ext>;
+ __overlay__ {
+ status = "disabled";
+ };
+ };
+
+};
--
2.25.1

150
patch/kernel/archive/rockchip64-5.15/overlays-06-add-rk3318-box-wlan-ap6330.patch Normal file
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@ -0,0 +1,150 @@
From db8c01c4dc0a1bbbdd35c0021b3975f11ce7a881 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Tue, 20 Apr 2021 16:24:58 +0000
Subject: [PATCH] rk3318-box: add overlay for full support to Ampak AP6330
---
arch/arm64/boot/dts/rockchip/overlay/Makefile | 3 +-
.../rockchip/overlay/README.rockchip-overlays | 4 +
.../rockchip-rk3318-box-wlan-ap6330.dts | 99 +++++++++++++++++++
3 files changed, 105 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ap6330.dts
diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile
index 5e3318b57..9bf45a074 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/Makefile
+++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile
@@ -14,7 +14,8 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-rk3318-box-led-conf1.dtbo \
rockchip-rk3318-box-emmc-ddr.dtbo \
rockchip-rk3318-box-wlan-ap6334.dtbo \
- rockchip-rk3318-box-wlan-ext.dtbo
+ rockchip-rk3318-box-wlan-ext.dtbo \
+ rockchip-rk3318-box-wlan-ap6330.dtbo
scr-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-fixup.scr
diff --git a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
index b414e3069..7b5073498 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
+++ b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
@@ -140,3 +140,7 @@ wifi chip and clones
Use sdmmc_ext device for sdio devices, enabled wifi on some boards (notably
X88 Pro) which have wifi chip attached to sdmmc_ext controller.
+### rk3318-box-wlan-ap6330
+
+Set up additional device tree bits properly support ap6330 (broaccom BCM4330)
+wifi + bt chip and clones.
diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ap6330.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ap6330.dts
new file mode 100644
index 000000000..9bc02a217
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ap6330.dts
@@ -0,0 +1,106 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+
+ fragment@0 {
+ target = <&sdio>;
+ __overlay__ {
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ brcmf_sdio: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ //brcm,drive-strength = <2>;
+ interrupt-parent = <&gpio1>;
+ interrupt-names = "host_wake";
+ interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio_host_wake>;
+ };
+
+ };
+ };
+
+ fragment@1 {
+ target = <&sdio_ext>;
+ __overlay__ {
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ brcmf_ext: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ //brcm,drive-strength = <2>;
+ interrupt-parent = <&gpio3>;
+ interrupt-names = "host_wake";
+ interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio_host_wake_ext>;
+ };
+
+ };
+ };
+
+ fragment@2 {
+ target = <&uart0>;
+ __overlay__ {
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>;
+
+ bluetooth {
+ compatible = "brcm,bcm4330-bt";
+ max-speed = <4000000>;
+ shutdown-gpios = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>;
+ device-wakeup-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>;
+ //host-wakeup-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+ vbat-supply = <&vcc_io>;
+ vddio-supply = <&vcc_18>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_reg_on_h>, <&bt_host_wake_l>, <&bt_device_wake_l>;
+ /*
+ interrupt-names = "host-wakeup";
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>;
+ */
+ brcm,bt-pcm-int-params = [01 02 00 01 01];
+ };
+
+
+ };
+
+ };
+
+ fragment@3 {
+ target = <&pinctrl>;
+ __overlay__ {
+
+ bluetooth {
+
+
+ bt_reg_on_h: bt-enable {
+ rockchip,pins = <1 RK_PC5 0 &pcfg_pull_none>;
+ };
+
+ bt_device_wake_l: bt-device-wake {
+ rockchip,pins = <1 RK_PC7 0 &pcfg_pull_none>;
+ };
+
+ bt_host_wake_l: bt-host-wake {
+ rockchip,pins = <1 RK_PD2 0 &pcfg_pull_none>;
+ };
+
+ };
+
+ };
+ };
+
+};

69
patch/kernel/archive/rockchip64-5.15/overlays-07-add-rk3318-box-cpu-hs.patch Normal file
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@ -0,0 +1,69 @@
From 41d39d8f7d7e9c40994750495c6783fbc71348ca Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Wed, 21 Apr 2021 10:58:39 +0000
Subject: [PATCH] rk3318-box: add additional device tree overlay with high
speed bins
---
arch/arm64/boot/dts/rockchip/overlay/Makefile | 3 ++-
.../rockchip/overlay/README.rockchip-overlays | 4 ++++
.../overlay/rockchip-rk3318-box-cpu-hs.dts | 21 +++++++++++++++++++
3 files changed, 27 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-cpu-hs.dts
diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile
index 9bf45a074..42b19bd85 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/Makefile
+++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile
@@ -15,7 +15,8 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-rk3318-box-emmc-ddr.dtbo \
rockchip-rk3318-box-wlan-ap6334.dtbo \
rockchip-rk3318-box-wlan-ext.dtbo \
- rockchip-rk3318-box-wlan-ap6330.dtbo
+ rockchip-rk3318-box-wlan-ap6330.dtbo \
+ rockchip-rk3318-box-cpu-hs.dtbo
scr-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-fixup.scr
diff --git a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
index 7b5073498..2fc9b00fe 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
+++ b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
@@ -144,3 +144,7 @@ X88 Pro) which have wifi chip attached to sdmmc_ext controller.
Set up additional device tree bits properly support ap6330 (broaccom BCM4330)
wifi + bt chip and clones.
+
+### rk3318-box-cpu-hs
+
+Enable additional cpu "high-speed" bins up to 1.3ghz
diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-cpu-hs.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-cpu-hs.dts
new file mode 100644
index 000000000..e6bc1adec
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-cpu-hs.dts
@@ -0,0 +1,24 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+ fragment@0 {
+ target-path = "/opp_table0/opp-1200000000";
+ __overlay__ {
+
+ status = "okay";
+
+ };
+ };
+
+ fragment@1 {
+ target-path = "/opp_table0/opp-1296000000";
+ __overlay__ {
+
+ status = "okay";
+
+ };
+ };
+
+};

66
patch/kernel/archive/rockchip64-5.15/overlays-08-add-rk3318-box-emmc-hs200.patch Normal file
View File

@ -0,0 +1,66 @@
From 0c9a276d459db0c16468cf2bae502eefd379c61b Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Wed, 21 Apr 2021 11:02:43 +0000
Subject: [PATCH] rk3318-box: add emmc hs200 device tree overlay
---
arch/arm64/boot/dts/rockchip/overlay/Makefile | 3 ++-
.../dts/rockchip/overlay/README.rockchip-overlays | 6 ++++++
.../overlay/rockchip-rk3318-box-emmc-hs200.dts | 14 ++++++++++++++
3 files changed, 22 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-emmc-hs200.dts
diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile
index 42b19bd85..f227d5997 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/Makefile
+++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile
@@ -16,7 +16,8 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-rk3318-box-wlan-ap6334.dtbo \
rockchip-rk3318-box-wlan-ext.dtbo \
rockchip-rk3318-box-wlan-ap6330.dtbo \
- rockchip-rk3318-box-cpu-hs.dtbo
+ rockchip-rk3318-box-cpu-hs.dtbo \
+ rockchip-rk3318-box-emmc-hs200.dtbo
scr-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-fixup.scr
diff --git a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
index 2fc9b00fe..1b547bea7 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
+++ b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
@@ -130,6 +130,12 @@ Activates eMMC DDR capability for rk3318 tv box boards. Probably all the eMMC ch
nowadays support DDR mode, but its reliability heavily depends upon the quality
of board wiring
+### rk3318-box-emmc-hs200
+
+Activates eMMC HS200 capability for rk3318 tv box boards.
+It should in autodetect mode, but some board have faulty or cheap circuitry that
+enable the mode but then it doesn't work correctly.
+
### rk3318-box-wlan-ap6334
Set up additional device tree bits to properly support ap6334 (broadcom BCM4334)
diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-emmc-hs200.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-emmc-hs200.dts
new file mode 100644
index 000000000..55f8f7eb6
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-emmc-hs200.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+ fragment@0 {
+ target = <&emmc>;
+ __overlay__ {
+ status = "okay";
+ mmc-hs200-1_8v;
+ };
+ };
+
+};
--
2.25.1

105
patch/kernel/archive/rockchip64-5.15/overlays-09-add-rk3318-box-led-conf2.patch Normal file
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@ -0,0 +1,105 @@
From 984e45a2fe4643ff96b43e0057c7e019aa8be7d6 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Fri, 23 Apr 2021 13:11:51 +0000
Subject: [PATCH] rk3318-box: add X88_PRO_B led/gpio configuration
---
arch/arm64/boot/dts/rockchip/overlay/Makefile | 1 +
.../rockchip/overlay/README.rockchip-overlays | 5 ++
.../overlay/rockchip-rk3318-box-led-conf2.dts | 64 +++++++++++++++++++
3 files changed, 70 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-led-conf2.dts
diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile
index f227d5997..c28c7a5eb 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/Makefile
+++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile
@@ -12,6 +12,7 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-dwc3-0-host.dtbo \
rockchip-w1-gpio.dtbo \
rockchip-rk3318-box-led-conf1.dtbo \
+ rockchip-rk3318-box-led-conf2.dtbo \
rockchip-rk3318-box-emmc-ddr.dtbo \
rockchip-rk3318-box-wlan-ap6334.dtbo \
rockchip-rk3318-box-wlan-ext.dtbo \
diff --git a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
index 1b547bea7..4172bd731 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
+++ b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
@@ -124,6 +124,11 @@ or enabling the internal pull-up
Activates led/gpio configuration for rk3318 tv box boards with signature
YX_RK3328 and clones
+### rk3318-box-led-conf2
+
+Activates led/gpio configuration for rk3318 tv box boards withs signature
+X88_PRO_B and clones
+
### rk3318-box-emmc-ddr
Activates eMMC DDR capability for rk3318 tv box boards. Probably all the eMMC chips
diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-led-conf2.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-led-conf2.dts
new file mode 100644
index 000000000..9a8146b9a
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-led-conf2.dts
@@ -0,0 +1,59 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+
+ fragment@0 {
+ target-path = "/gpio-leds";
+ __overlay__ {
+
+ working {
+ gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "mmc2";
+ };
+
+ /*
+ * no auxiliary led on X88_PRO_B boards
+ *
+ auxiliary {
+ gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+ label = "auxiliary";
+ linux,default-trigger = "mmc2";
+ default-state = "off";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_led_aux>;
+ };
+ */
+
+ };
+ };
+
+ fragment@1 {
+ target = <&vcc_otg_vbus>;
+ __overlay__ {
+
+ gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
+
+ };
+
+ };
+
+ fragment@2 {
+ target = <&working_led>;
+ __overlay__ {
+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none_2ma>;
+ };
+ };
+
+ fragment@3 {
+ target = <&io_domains>;
+ __overlay__ {
+ vccio6-supply = <&vcc_18>;
+ };
+ };
+
+};

331
patch/kernel/archive/rockchip64-5.15/overlays-10-add-rk3318-box-led-conf3.patch Normal file
View File

@ -0,0 +1,331 @@
From 506d63cda173ca0f992bdbf4b4d2f3e1e20f905c Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Mon, 18 Oct 2021 18:30:28 +0000
Subject: [PATCH] rk3318-box: add led-conf3 to support MXQ-RK3328-D4 boards
with RK805 PMIC
---
arch/arm64/boot/dts/rockchip/overlay/Makefile | 1 +
.../rockchip/overlay/README.rockchip-overlays | 7 +
.../overlay/rockchip-rk3318-box-led-conf3.dts | 279 ++++++++++++++++++
3 files changed, 287 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-led-conf3.dts
diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile
index c28c7a5eb..f11aa6d57 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/Makefile
+++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile
@@ -13,6 +13,7 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-w1-gpio.dtbo \
rockchip-rk3318-box-led-conf1.dtbo \
rockchip-rk3318-box-led-conf2.dtbo \
+ rockchip-rk3318-box-led-conf3.dtbo \
rockchip-rk3318-box-emmc-ddr.dtbo \
rockchip-rk3318-box-wlan-ap6334.dtbo \
rockchip-rk3318-box-wlan-ext.dtbo \
diff --git a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
index 4172bd731..27f945d38 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
+++ b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
@@ -129,6 +129,13 @@ YX_RK3328 and clones
Activates led/gpio configuration for rk3318 tv box boards withs signature
X88_PRO_B and clones
+### rk3318-box-led-conf3
+
+This device tree overlay is suitable for MXQ-RK3328-D4_A board which
+has an integrated PMIC (RK805). The dtbo is very important to achieve
+1.3 Ghz speed for CPU and stable voltages for other parts of the
+system. Also enables gpio leds and keys.
+
### rk3318-box-emmc-ddr
Activates eMMC DDR capability for rk3318 tv box boards. Probably all the eMMC chips
diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-led-conf3.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-led-conf3.dts
new file mode 100644
index 000000000..4641f7588
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-led-conf3.dts
@@ -0,0 +1,279 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+&{/regulators/regulator@0} {
+ status = "disabled";
+};
+
+&{/regulators/regulator@1} {
+ status = "disabled";
+};
+
+&{/vdd-arm} {
+ status = "disabled";
+};
+
+&{/vdd-log} {
+ status = "disabled";
+};
+
+&{/xin32k} {
+ status = "disabled";
+};
+
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clock-frequency = <1000000>;
+ i2c-scl-rising-time-ns = <83>;
+ i2c-scl-falling-time-ns = <5>;
+ status = "okay";
+
+ rk805: rk805@18 {
+ compatible = "rockchip,rk805";
+ reg = <0x18>;
+ status = "okay";
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-parent = <&gpio2>;
+ interrupts = <RK_PA6 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk805-clkout2";
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc5-supply = <&rk805_vcc_io>;
+ vcc6-supply = <&rk805_vcc_io>;
+
+ rtc {
+ status = "okay";
+ };
+
+ pwrkey {
+ status = "okay";
+ };
+
+ gpio {
+ status = "okay";
+ };
+
+ regulators {
+ compatible = "rk805-regulator";
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <12500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <12500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_io: rk805_vcc_io: DCDC_REG4 {
+ regulator-name = "vccio_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vdd_18: vcc_18: LDO_REG1 {
+ regulator-name = "vccio_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_18emmc: LDO_REG2 {
+ regulator-name = "vcc_18emmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_11: LDO_REG3 {
+ regulator-name = "vdd_11";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1100000>;
+ };
+ };
+ };
+ };
+
+};
+
+&pinctrl {
+
+ leds {
+ ir_led: ir-led {
+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+};
+
+&gpio_led {
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_led>;
+
+ working {
+ gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ linux,default-trigger = "default-on";
+ mode = <35>;
+ };
+
+ auxiliary {
+ gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "mmc2";
+ default-state = "off";
+ mode = <5>;
+ };
+
+ ir {
+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "ir";
+ default-state = "off";
+ mode = <0>;
+ };
+
+};
+
+&io_domains {
+ vccio1-supply = <&vcc_io>;
+ vccio2-supply = <&vcc_18emmc>;
+ vccio3-supply = <&vcc_io>;
+ vccio4-supply = <&vdd_18>;
+ vccio5-supply = <&vcc_io>;
+ vccio6-supply = <&vcc_io>;
+ pmuio-supply = <&vcc_io>;
+};
+
+&{/} {
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+
+ power {
+ label = "Power button";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&dmc {
+ center-supply = <&vdd_logic>;
+};
+
+&gpu {
+ mali-supply = <&vdd_logic>;
+};
+
+&vpu {
+ vcodec-supply = <&vdd_logic>;
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_arm>;
+};
+
+
+&vcc_sd {
+ vin-supply = <&vcc_io>;
+};
+
+&emmc {
+ vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vcc_18emmc>;
+};
+
+&saradc {
+ vref-supply = <&vcc_18>;
+};
+
+&pwm0 {
+ status = "disabled";
+};
+
+&pwm1 {
+ status = "disabled";
+};
+
--
2.30.2

322
patch/kernel/archive/rockchip64-5.15/rk3328-hw-cursor-plane.patch.disabled Normal file
View File

@ -0,0 +1,322 @@
From 6eb43deb95d99178419b480181fd18a9b4d9f8fe Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sun, 24 Oct 2021 17:06:13 +0000
Subject: [PATCH] rk3328: hardware dedicated cursor plane
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 214 +++++++++++++++++++-
drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 3 +
drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 20 +-
3 files changed, 234 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index f5b9028a1..9a4afba29 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1104,6 +1104,201 @@ static void vop_plane_atomic_async_update(struct drm_plane *plane,
}
}
+static void vop_cursor_atomic_update(struct drm_plane *plane,
+ struct drm_atomic_state *state)
+{
+
+ struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
+ plane);
+ struct drm_crtc *crtc = new_state->crtc;
+ struct vop_win *vop_win = to_vop_win(plane);
+ const struct vop_win_data *win = vop_win->data;
+ struct vop *vop = to_vop(new_state->crtc);
+ struct drm_framebuffer *fb = new_state->fb;
+ unsigned int actual_h;
+ unsigned int dsp_stx, dsp_sty;
+ uint32_t dsp_st;
+ struct drm_rect *src = &new_state->src;
+ struct drm_rect *dest = &new_state->dst;
+ struct drm_gem_object *obj;
+ struct rockchip_gem_object *rk_obj;
+ dma_addr_t dma_addr;
+ uint32_t val;
+ bool rb_swap;
+ int win_index = VOP_WIN_TO_INDEX(vop_win);
+ int format;
+
+ /*
+ * can't update plane when vop is disabled.
+ */
+ if (WARN_ON(!crtc))
+ return;
+
+ if (WARN_ON(!vop->is_enabled))
+ return;
+
+ if (!new_state->visible) {
+ vop_plane_atomic_disable(plane, state);
+ return;
+ }
+
+ obj = fb->obj[0];
+ rk_obj = to_rockchip_obj(obj);
+
+ actual_h = drm_rect_height(src) >> 16;
+
+ dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
+ dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
+ dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
+
+ dma_addr = rk_obj->dma_addr;
+
+ /*
+ * For y-mirroring we need to move address
+ * to the beginning of the last line.
+ */
+ if (new_state->rotation & DRM_MODE_REFLECT_Y)
+ dma_addr += (actual_h - 1) * fb->pitches[0];
+
+ spin_lock(&vop->reg_lock);
+
+ if (!(vop->win_enabled & BIT(win_index))) {
+
+ format = vop_convert_format(fb->format->format);
+
+ VOP_WIN_SET(vop, win, format, format);
+
+ rb_swap = has_rb_swapped(fb->format->format);
+ VOP_WIN_SET(vop, win, rb_swap, rb_swap);
+
+ /*
+ * Blending win0 with the background color doesn't seem to work
+ * correctly. We only get the background color, no matter the contents
+ * of the win0 framebuffer. However, blending pre-multiplied color
+ * with the default opaque black default background color is a no-op,
+ * so we can just disable blending to get the correct result.
+ */
+ if (fb->format->has_alpha && win_index > 0) {
+ VOP_WIN_SET(vop, win, dst_alpha_ctl,
+ DST_FACTOR_M0(ALPHA_SRC_INVERSE));
+ val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
+ SRC_ALPHA_M0(ALPHA_STRAIGHT) |
+ SRC_BLEND_M0(ALPHA_PER_PIX) |
+ SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
+ SRC_FACTOR_M0(ALPHA_ONE);
+ VOP_WIN_SET(vop, win, src_alpha_ctl, val);
+
+ VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL);
+ VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX);
+ VOP_WIN_SET(vop, win, alpha_en, 1);
+ } else {
+ VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
+ VOP_WIN_SET(vop, win, alpha_en, 0);
+ }
+
+ // 32x32 = 0, 64x64 = 1, 96x96 = 2, 128x128 = 3
+ VOP_WIN_SET(vop, win, hwc_size, (new_state->crtc_w >> 5) - 1);
+
+ VOP_WIN_SET(vop, win, enable, 1);
+ vop->win_enabled |= BIT(win_index);
+
+ }
+
+ VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
+ VOP_WIN_SET(vop, win, dsp_st, dsp_st);
+
+ spin_unlock(&vop->reg_lock);
+
+}
+
+static void vop_cursor_atomic_async_update(struct drm_plane *plane,
+ struct drm_atomic_state *state)
+{
+
+ struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
+ plane);
+ struct vop *vop = to_vop(plane->state->crtc);
+ struct drm_framebuffer *old_fb = plane->state->fb;
+
+ plane->state->crtc_x = new_state->crtc_x;
+ plane->state->crtc_y = new_state->crtc_y;
+ plane->state->crtc_h = new_state->crtc_h;
+ plane->state->crtc_w = new_state->crtc_w;
+ plane->state->src_x = new_state->src_x;
+ plane->state->src_y = new_state->src_y;
+ plane->state->src_h = new_state->src_h;
+ plane->state->src_w = new_state->src_w;
+ swap(plane->state->fb, new_state->fb);
+
+ if (vop->is_enabled) {
+ vop_cursor_atomic_update(plane, state);
+ spin_lock(&vop->reg_lock);
+ vop_cfg_done(vop);
+ spin_unlock(&vop->reg_lock);
+
+ /*
+ * A scanout can still be occurring, so we can't drop the
+ * reference to the old framebuffer. To solve this we get a
+ * reference to old_fb and set a worker to release it later.
+ * FIXME: if we perform 500 async_update calls before the
+ * vblank, then we can have 500 different framebuffers waiting
+ * to be released.
+ */
+ if (old_fb && plane->state->fb != old_fb) {
+ drm_framebuffer_get(old_fb);
+ WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0);
+ drm_flip_work_queue(&vop->fb_unref_work, old_fb);
+ set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
+ }
+ }
+
+}
+
+static int vop_cursor_atomic_check(struct drm_plane *plane,
+ struct drm_atomic_state *state)
+{
+ struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
+ plane);
+ struct drm_crtc *crtc = new_plane_state->crtc;
+ struct drm_crtc_state *crtc_state;
+ struct drm_framebuffer *fb = new_plane_state->fb;
+ int ret;
+
+ if (!crtc || WARN_ON(!fb))
+ return 0;
+
+ crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
+ if (WARN_ON(!crtc_state))
+ return -EINVAL;
+
+ ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
+ DRM_PLANE_HELPER_NO_SCALING, DRM_PLANE_HELPER_NO_SCALING,
+ true, true);
+
+ if (ret)
+ return ret;
+
+ if (!new_plane_state->visible)
+ return 0;
+
+ ret = vop_convert_format(fb->format->format);
+ if (ret < 0)
+ return ret;
+
+ if (new_plane_state->crtc_w != new_plane_state->crtc_h)
+ return -EINVAL;
+
+ if (new_plane_state->crtc_w != 0 &&
+ new_plane_state->crtc_w != 32 &&
+ new_plane_state->crtc_w != 64 &&
+ new_plane_state->crtc_w != 96 &&
+ new_plane_state->crtc_w != 128)
+ return -EINVAL;
+
+ return 0;
+
+}
+
static const struct drm_plane_helper_funcs plane_helper_funcs = {
.atomic_check = vop_plane_atomic_check,
.atomic_update = vop_plane_atomic_update,
@@ -1113,6 +1308,15 @@ static const struct drm_plane_helper_funcs plane_helper_funcs = {
.prepare_fb = drm_gem_plane_helper_prepare_fb,
};
+static const struct drm_plane_helper_funcs cursor_plane_helper_funcs = {
+ .atomic_check = vop_cursor_atomic_check,
+ .atomic_update = vop_cursor_atomic_update,
+ .atomic_disable = vop_plane_atomic_disable,
+ .atomic_async_check = vop_plane_atomic_async_check,
+ .atomic_async_update = vop_cursor_atomic_async_update,
+ .prepare_fb = drm_gem_plane_helper_prepare_fb,
+};
+
static const struct drm_plane_funcs vop_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
@@ -1772,6 +1976,7 @@ static int vop_create_crtc(struct vop *vop)
struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
struct drm_crtc *crtc = &vop->crtc;
struct device_node *port;
+ const struct drm_plane_helper_funcs *helper_funcs;
int ret;
int i;
@@ -1801,7 +2006,14 @@ static int vop_create_crtc(struct vop *vop)
}
plane = &vop_win->base;
- drm_plane_helper_add(plane, &plane_helper_funcs);
+ helper_funcs = &plane_helper_funcs;
+
+ if ((plane->type == DRM_PLANE_TYPE_CURSOR) && (vop_data->feature & VOP_FEATURE_SPECIAL_CURSOR_PLANE)) {
+ dev_info(dev, "using dedicated hwcursor plane\n");
+ helper_funcs = &cursor_plane_helper_funcs;
+ }
+
+ drm_plane_helper_add(plane, helper_funcs);
vop_plane_add_properties(plane, win_data);
if (plane->type == DRM_PLANE_TYPE_PRIMARY)
primary = plane;
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 857d97cdc..7967359c1 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -182,6 +182,8 @@ struct vop_win_phy {
struct vop_reg alpha_mode;
struct vop_reg alpha_en;
struct vop_reg channel;
+
+ struct vop_reg hwc_size;
};
struct vop_win_yuv2yuv_data {
@@ -211,6 +213,7 @@ struct vop_data {
#define VOP_FEATURE_OUTPUT_RGB10 BIT(0)
#define VOP_FEATURE_INTERNAL_RGB BIT(1)
+#define VOP_FEATURE_SPECIAL_CURSOR_PLANE BIT(2)
u64 feature;
};
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index ca7cc8212..56eb4f774 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -1048,18 +1048,34 @@ static const struct vop_intr rk3328_vop_intr = {
.clear = VOP_REG_MASK_SYNC(RK3328_INTR_CLEAR0, 0xffff, 0),
};
+static const struct vop_win_phy rk3328_cursor_data = {
+ .data_formats = formats_win_lite,
+ .nformats = ARRAY_SIZE(formats_win_lite),
+ .format_modifiers = format_modifiers_win_lite,
+ .enable = VOP_REG(RK3328_HWC_CTRL0, 0x1, 0),
+ .format = VOP_REG(RK3328_HWC_CTRL0, 0x7, 1),
+ .rb_swap = VOP_REG(RK3328_HWC_CTRL0, 0x1, 12),
+ .dsp_st = VOP_REG(RK3328_HWC_DSP_ST, 0x1fff1fff, 0),
+ .yrgb_mst = VOP_REG(RK3328_HWC_MST, 0xffffffff, 0),
+ .src_alpha_ctl = VOP_REG(RK3328_HWC_SRC_ALPHA_CTRL, 0xff, 0),
+ .dst_alpha_ctl = VOP_REG(RK3328_HWC_DST_ALPHA_CTRL, 0xff, 0),
+ .hwc_size = VOP_REG(RK3328_HWC_CTRL0, 0x3, 5),
+};
+
static const struct vop_win_data rk3328_vop_win_data[] = {
{ .base = 0xd0, .phy = &rk3368_win01_data,
.type = DRM_PLANE_TYPE_PRIMARY },
{ .base = 0x1d0, .phy = &rk3368_win01_data,
.type = DRM_PLANE_TYPE_OVERLAY },
{ .base = 0x2d0, .phy = &rk3368_win01_data,
- .type = DRM_PLANE_TYPE_CURSOR },
+ .type = DRM_PLANE_TYPE_OVERLAY },
+ { .base = 0x00, .phy = &rk3328_cursor_data,
+ .type = DRM_PLANE_TYPE_CURSOR }
};
static const struct vop_data rk3328_vop = {
.version = VOP_VERSION(3, 8),
- .feature = VOP_FEATURE_OUTPUT_RGB10,
+ .feature = VOP_FEATURE_OUTPUT_RGB10 | VOP_FEATURE_SPECIAL_CURSOR_PLANE,
.intr = &rk3328_vop_intr,
.common = &rk3328_common,
.modeset = &rk3328_modeset,
--
2.30.2

45
patch/kernel/archive/rockchip64-5.15/wifi-4003-add-bcm43342-chip.patch Normal file
View File

@ -0,0 +1,45 @@
From 01b579a527b5c77e6adfbb2c277fb2c7cc158b8b Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Thu, 10 Feb 2022 21:30:54 +0000
Subject: [PATCH] add broadcom bcm43342 chip id
---
drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c | 2 ++
drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
index 8effeb7a726..f45c1056e42 100644
--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
@@ -611,6 +611,7 @@ BRCMF_FW_DEF(4329, "brcmfmac4329-sdio");
BRCMF_FW_DEF(4330, "brcmfmac4330-sdio");
BRCMF_FW_DEF(4334, "brcmfmac4334-sdio");
BRCMF_FW_DEF(43340, "brcmfmac43340-sdio");
+BRCMF_FW_DEF(43342, "brcmfmac43342-sdio");
BRCMF_FW_DEF(4335, "brcmfmac4335-sdio");
BRCMF_FW_DEF(43362, "brcmfmac43362-sdio");
BRCMF_FW_DEF(4339, "brcmfmac4339-sdio");
@@ -644,6 +645,7 @@ static const struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
BRCMF_FW_ENTRY(BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, 4334),
BRCMF_FW_ENTRY(BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, 43340),
BRCMF_FW_ENTRY(BRCM_CC_43341_CHIP_ID, 0xFFFFFFFF, 43340),
+ BRCMF_FW_ENTRY(BRCM_CC_43342_CHIP_ID, 0xFFFFFFFF, 43342),
BRCMF_FW_ENTRY(BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, 4335),
BRCMF_FW_ENTRY(BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, 43362),
BRCMF_FW_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339),
diff --git a/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h b/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h
index 9d81320164c..71de0dce4f4 100644
--- a/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h
+++ b/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h
@@ -27,6 +27,7 @@
#define BRCM_CC_4334_CHIP_ID 0x4334
#define BRCM_CC_43340_CHIP_ID 43340
#define BRCM_CC_43341_CHIP_ID 43341
+#define BRCM_CC_43342_CHIP_ID 43342
#define BRCM_CC_43362_CHIP_ID 43362
#define BRCM_CC_4335_CHIP_ID 0x4335
#define BRCM_CC_4339_CHIP_ID 0x4339
--
2.30.2

1060
patch/kernel/archive/rockchip64-5.18/add-board-tvbox-rk3318.patch Normal file
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File diff suppressed because it is too large Load Diff

3
patch/kernel/archive/rockchip64-5.18/add-boards-to-dts-makefile.patch
View File

@ -2,11 +2,12 @@ diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchi
index 26661c7b7..1462ed38b 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -1,4 +1,21 @@
@@ -1,4 +1,22 @@
# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-pc.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-rock-pi-s.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-box.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2-rev00.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2-rev06.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2-rev20.dtb

102
patch/kernel/archive/rockchip64-5.18/overlays-02-add-rk3318-box-led-conf1.patch Normal file
View File

@ -0,0 +1,102 @@
From c7140e73b84431eb1e8cb31bdfce4c9d8a908de0 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sat, 17 Apr 2021 16:26:46 +0000
Subject: [PATCH 2/4] rk3318-box: add led configuration for YX_RK3328 boards
and clones
---
arch/arm64/boot/dts/rockchip/overlay/Makefile | 3 +-
.../rockchip/overlay/README.rockchip-overlays | 4 +-
.../overlay/rockchip-rk3318-box-led-conf1.dts | 54 +++++++++++++++++++
3 files changed, 58 insertions(+), 3 deletions(-)
create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-led-conf1.dts
diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile
index 9c07d64a1..8e9ff2ef1 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/Makefile
+++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile
@@ -10,7 +10,8 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-spi-spidev.dtbo \
rockchip-uart4.dtbo \
rockchip-dwc3-0-host.dtbo \
- rockchip-w1-gpio.dtbo
+ rockchip-w1-gpio.dtbo \
+ rockchip-rk3318-box-led-conf1.dtbo
scr-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-fixup.scr
diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-led-conf1.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-led-conf1.dts
new file mode 100644
index 000000000..1f5e5b7f8
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-led-conf1.dts
@@ -0,0 +1,54 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+
+ fragment@0 {
+ target-path = "/gpio-leds";
+ __overlay__ {
+
+ working {
+ gpios = <&gpio2 RK_PC7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc2";
+ };
+
+ /*
+ * no auxiliary led on YX_RK3328 boards
+ *
+ auxiliary {
+ gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+ label = "auxiliary";
+ linux,default-trigger = "mmc2";
+ default-state = "off";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_led_aux>;
+ };
+ */
+
+ };
+ };
+
+ /*
+ * TODO: needs to find the GPIO for this
+ *
+ fragment@1 {
+ target = <&gpio_keys>;
+ __overlay__ {
+
+ reset {
+ gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ debounce-interval = <200>;
+ wakeup-source;
+ };
+
+ };
+ };
+ */
+
+};
--
2.25.1
diff --git a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
index d6979437a..1de0a95e8 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
+++ b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
@@ -119,3 +119,7 @@ Activates 1-Wire GPIO master
Requires an external pull-up resistor on the data pin
or enabling the internal pull-up
+### rk3318-box-led-conf1
+
+Activates led/gpio configuration for rk3318 tv box boards with signature
+YX_RK3328 and clones

64
patch/kernel/archive/rockchip64-5.18/overlays-03-add-rk3318-box-emmc-ddr.patch Normal file
View File

@ -0,0 +1,64 @@
From 026b39ef85792467bdf1681e5abfca9a5231516f Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sat, 17 Apr 2021 16:29:00 +0000
Subject: [PATCH 3/4] rk3318-box: add eMMC DDR support device tree overlay for
rk3318-box
---
arch/arm64/boot/dts/rockchip/overlay/Makefile | 3 ++-
.../dts/rockchip/overlay/README.rockchip-overlays | 6 ++++++
.../overlay/rockchip-rk3318-box-emmc-ddr.dts | 14 ++++++++++++++
3 files changed, 22 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-emmc-ddr.dts
diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile
index 8e9ff2ef1..565ef20ac 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/Makefile
+++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile
@@ -11,7 +11,8 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-uart4.dtbo \
rockchip-dwc3-0-host.dtbo \
rockchip-w1-gpio.dtbo \
- rockchip-rk3318-box-led-conf1.dtbo
+ rockchip-rk3318-box-led-conf1.dtbo \
+ rockchip-rk3318-box-emmc-ddr.dtbo
scr-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-fixup.scr
diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-emmc-ddr.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-emmc-ddr.dts
new file mode 100644
index 000000000..b8f139099
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-emmc-ddr.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+ fragment@0 {
+ target = <&emmc>;
+ __overlay__ {
+ status = "okay";
+ mmc-ddr-1_8v;
+ };
+ };
+
+};
--
2.25.1
diff --git a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
index 1c645a9b8..01fa6f4ee 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
+++ b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
@@ -123,3 +123,9 @@ or enabling the internal pull-up
Activates led/gpio configuration for rk3318 tv box boards with signature
YX_RK3328 and clones
+
+### rk3318-box-emmc-ddr
+
+Activates eMMC DDR capability for rk3318 tv box boards. Probably all the eMMC chips
+nowadays support DDR mode, but its reliability heavily depends upon the quality
+of board wiring

163
patch/kernel/archive/rockchip64-5.18/overlays-04-add-rk3318-box-wlan-ap6334.patch Normal file
View File

@ -0,0 +1,163 @@
From 918d83519ccba3e540f6a9e0c201fcccf106988f Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sat, 17 Apr 2021 16:30:58 +0000
Subject: [PATCH 4/4] rk3318-box: add device tree overlay to support AP6334 and
clones
---
arch/arm64/boot/dts/rockchip/overlay/Makefile | 3 +-
.../rockchip/overlay/README.rockchip-overlays | 5 +++
.../rockchip-rk3318-box-wlan-ap6334.dts | 31 +++++++++++++++++++
3 files changed, 38 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ap6334.dts
diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile
index 565ef20ac..be038cc38 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/Makefile
+++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile
@@ -12,7 +12,8 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-dwc3-0-host.dtbo \
rockchip-w1-gpio.dtbo \
rockchip-rk3318-box-led-conf1.dtbo \
- rockchip-rk3318-box-emmc-ddr.dtbo
+ rockchip-rk3318-box-emmc-ddr.dtbo \
+ rockchip-rk3318-box-wlan-ap6334.dtbo
scr-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-fixup.scr
diff --git a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
index 01fa6f4ee..0e7eaeea2 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
+++ b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
@@ -129,3 +129,8 @@ YX_RK3328 and clones
Activates eMMC DDR capability for rk3318 tv box boards. Probably all the eMMC chips
nowadays support DDR mode, but its reliability heavily depends upon the quality
of board wiring
+
+### rk3318-box-wlan-ap6334
+
+Set up additional device tree bits to properly support ap6334 (broadcom BCM4334)
+wifi chip and clones
diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ap6334.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ap6334.dts
new file mode 100644
index 000000000..b7befaaeb
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ap6334.dts
@@ -0,0 +1,117 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+
+ fragment@0 {
+ target = <&sdio>;
+ __overlay__ {
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ //sd-uhs-ddr50;
+
+ brcmf_sdio: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ //brcm,drive-strength = <4>;
+ interrupt-parent = <&gpio1>;
+ interrupt-names = "host_wake";
+ interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio_host_wake>;
+ };
+
+ };
+ };
+
+ fragment@1 {
+ target = <&sdio_ext>;
+ __overlay__ {
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ //sd-uhs-ddr50;
+
+ brcmf_ext: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ //brcm,drive-strength = <8>;
+ interrupt-parent = <&gpio3>;
+ interrupt-names = "host_wake";
+ interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio_host_wake_ext>;
+ };
+
+ };
+ };
+
+ fragment@2 {
+ target = <&uart0>;
+ __overlay__ {
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>;
+
+ bluetooth {
+ compatible = "brcm,bcm4334b0-bt", "brcm,bcm4330-bt";
+ max-speed = <4000000>;
+ shutdown-gpios = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>;
+ device-wakeup-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>;
+ //host-wakeup-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+ vbat-supply = <&vcc_io>;
+ vddio-supply = <&vcc_18>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_reg_on_h>, <&bt_host_wake_l>, <&bt_device_wake_l>;
+ /*
+ interrupt-names = "host-wakeup";
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PD2 IRQ_TYPE_NONE>;
+ */
+ brcm,bt-pcm-int-params = [01 02 00 01 01];
+ };
+
+ };
+
+ };
+
+ fragment@3 {
+ target = <&pinctrl>;
+ __overlay__ {
+
+ bluetooth {
+
+
+ bt_reg_on_h: bt-enable {
+ rockchip,pins = <1 RK_PC5 0 &pcfg_pull_down>;
+ };
+
+ bt_device_wake_l: bt-device-wake {
+ rockchip,pins = <1 RK_PC7 0 &pcfg_pull_none>;
+ };
+
+ bt_host_wake_l: bt-host-wake {
+ rockchip,pins = <1 RK_PD2 0 &pcfg_pull_none>;
+ };
+
+ };
+
+ };
+ };
+
+};

82
patch/kernel/archive/rockchip64-5.18/overlays-05-add-rk3318-box-wlan-ext.patch Normal file
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@ -0,0 +1,82 @@
From 8b6cf9530ef8923895df798428a9b45534c9fd98 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sun, 18 Apr 2021 10:59:09 +0000
Subject: [PATCH] rk3318-box: add overlay for wifi over sdmmc_ext
---
arch/arm64/boot/dts/rockchip/overlay/Makefile | 3 +-
.../rockchip/overlay/README.rockchip-overlays | 6 ++++
.../overlay/rockchip-rk3318-box-wlan-ext.dts | 29 +++++++++++++++++++
3 files changed, 37 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ext.dts
diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile
index be038cc38..5e3318b57 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/Makefile
+++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile
@@ -13,7 +13,8 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-w1-gpio.dtbo \
rockchip-rk3318-box-led-conf1.dtbo \
rockchip-rk3318-box-emmc-ddr.dtbo \
- rockchip-rk3318-box-wlan-ap6334.dtbo
+ rockchip-rk3318-box-wlan-ap6334.dtbo \
+ rockchip-rk3318-box-wlan-ext.dtbo
scr-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-fixup.scr
diff --git a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
index 0e7eaeea2..b414e3069 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
+++ b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
@@ -134,3 +134,9 @@ of board wiring
Set up additional device tree bits to properly support ap6334 (broadcom BCM4334)
wifi chip and clones
+
+### rk3318-box-wlan-ext
+
+Use sdmmc_ext device for sdio devices, enabled wifi on some boards (notably
+X88 Pro) which have wifi chip attached to sdmmc_ext controller.
+
diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ext.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ext.dts
new file mode 100644
index 000000000..7f43fc20f
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ext.dts
@@ -0,0 +1,33 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+
+ fragment@0 {
+ target = <&sdio>;
+ __overlay__ {
+ mmc-pwrseq = <>;
+ status = "disabled";
+ };
+ };
+
+ fragment@1 {
+ target = <&sdio_ext>;
+ __overlay__ {
+ mmc-pwrseq = <&sdio_pwrseq>;
+ status = "okay";
+ };
+ };
+
+ fragment@2 {
+ target = <&sdmmc_ext>;
+ __overlay__ {
+ status = "disabled";
+ };
+ };
+
+};
--
2.25.1

150
patch/kernel/archive/rockchip64-5.18/overlays-06-add-rk3318-box-wlan-ap6330.patch Normal file
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@ -0,0 +1,150 @@
From db8c01c4dc0a1bbbdd35c0021b3975f11ce7a881 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Tue, 20 Apr 2021 16:24:58 +0000
Subject: [PATCH] rk3318-box: add overlay for full support to Ampak AP6330
---
arch/arm64/boot/dts/rockchip/overlay/Makefile | 3 +-
.../rockchip/overlay/README.rockchip-overlays | 4 +
.../rockchip-rk3318-box-wlan-ap6330.dts | 99 +++++++++++++++++++
3 files changed, 105 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ap6330.dts
diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile
index 5e3318b57..9bf45a074 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/Makefile
+++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile
@@ -14,7 +14,8 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-rk3318-box-led-conf1.dtbo \
rockchip-rk3318-box-emmc-ddr.dtbo \
rockchip-rk3318-box-wlan-ap6334.dtbo \
- rockchip-rk3318-box-wlan-ext.dtbo
+ rockchip-rk3318-box-wlan-ext.dtbo \
+ rockchip-rk3318-box-wlan-ap6330.dtbo
scr-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-fixup.scr
diff --git a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
index b414e3069..7b5073498 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
+++ b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
@@ -140,3 +140,7 @@ wifi chip and clones
Use sdmmc_ext device for sdio devices, enabled wifi on some boards (notably
X88 Pro) which have wifi chip attached to sdmmc_ext controller.
+### rk3318-box-wlan-ap6330
+
+Set up additional device tree bits properly support ap6330 (broaccom BCM4330)
+wifi + bt chip and clones.
diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ap6330.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ap6330.dts
new file mode 100644
index 000000000..9bc02a217
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-wlan-ap6330.dts
@@ -0,0 +1,106 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+
+ fragment@0 {
+ target = <&sdio>;
+ __overlay__ {
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ brcmf_sdio: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ //brcm,drive-strength = <2>;
+ interrupt-parent = <&gpio1>;
+ interrupt-names = "host_wake";
+ interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio_host_wake>;
+ };
+
+ };
+ };
+
+ fragment@1 {
+ target = <&sdio_ext>;
+ __overlay__ {
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ brcmf_ext: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ //brcm,drive-strength = <2>;
+ interrupt-parent = <&gpio3>;
+ interrupt-names = "host_wake";
+ interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio_host_wake_ext>;
+ };
+
+ };
+ };
+
+ fragment@2 {
+ target = <&uart0>;
+ __overlay__ {
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>;
+
+ bluetooth {
+ compatible = "brcm,bcm4330-bt";
+ max-speed = <4000000>;
+ shutdown-gpios = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>;
+ device-wakeup-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>;
+ //host-wakeup-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+ vbat-supply = <&vcc_io>;
+ vddio-supply = <&vcc_18>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_reg_on_h>, <&bt_host_wake_l>, <&bt_device_wake_l>;
+ /*
+ interrupt-names = "host-wakeup";
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>;
+ */
+ brcm,bt-pcm-int-params = [01 02 00 01 01];
+ };
+
+
+ };
+
+ };
+
+ fragment@3 {
+ target = <&pinctrl>;
+ __overlay__ {
+
+ bluetooth {
+
+
+ bt_reg_on_h: bt-enable {
+ rockchip,pins = <1 RK_PC5 0 &pcfg_pull_none>;
+ };
+
+ bt_device_wake_l: bt-device-wake {
+ rockchip,pins = <1 RK_PC7 0 &pcfg_pull_none>;
+ };
+
+ bt_host_wake_l: bt-host-wake {
+ rockchip,pins = <1 RK_PD2 0 &pcfg_pull_none>;
+ };
+
+ };
+
+ };
+ };
+
+};

69
patch/kernel/archive/rockchip64-5.18/overlays-07-add-rk3318-box-cpu-hs.patch Normal file
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@ -0,0 +1,69 @@
From 41d39d8f7d7e9c40994750495c6783fbc71348ca Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Wed, 21 Apr 2021 10:58:39 +0000
Subject: [PATCH] rk3318-box: add additional device tree overlay with high
speed bins
---
arch/arm64/boot/dts/rockchip/overlay/Makefile | 3 ++-
.../rockchip/overlay/README.rockchip-overlays | 4 ++++
.../overlay/rockchip-rk3318-box-cpu-hs.dts | 21 +++++++++++++++++++
3 files changed, 27 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-cpu-hs.dts
diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile
index 9bf45a074..42b19bd85 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/Makefile
+++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile
@@ -15,7 +15,8 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-rk3318-box-emmc-ddr.dtbo \
rockchip-rk3318-box-wlan-ap6334.dtbo \
rockchip-rk3318-box-wlan-ext.dtbo \
- rockchip-rk3318-box-wlan-ap6330.dtbo
+ rockchip-rk3318-box-wlan-ap6330.dtbo \
+ rockchip-rk3318-box-cpu-hs.dtbo
scr-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-fixup.scr
diff --git a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
index 7b5073498..2fc9b00fe 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
+++ b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
@@ -144,3 +144,7 @@ X88 Pro) which have wifi chip attached to sdmmc_ext controller.
Set up additional device tree bits properly support ap6330 (broaccom BCM4330)
wifi + bt chip and clones.
+
+### rk3318-box-cpu-hs
+
+Enable additional cpu "high-speed" bins up to 1.3ghz
diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-cpu-hs.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-cpu-hs.dts
new file mode 100644
index 000000000..e6bc1adec
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-cpu-hs.dts
@@ -0,0 +1,24 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+ fragment@0 {
+ target-path = "/opp_table0/opp-1200000000";
+ __overlay__ {
+
+ status = "okay";
+
+ };
+ };
+
+ fragment@1 {
+ target-path = "/opp_table0/opp-1296000000";
+ __overlay__ {
+
+ status = "okay";
+
+ };
+ };
+
+};

66
patch/kernel/archive/rockchip64-5.18/overlays-08-add-rk3318-box-emmc-hs200.patch Normal file
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@ -0,0 +1,66 @@
From 0c9a276d459db0c16468cf2bae502eefd379c61b Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Wed, 21 Apr 2021 11:02:43 +0000
Subject: [PATCH] rk3318-box: add emmc hs200 device tree overlay
---
arch/arm64/boot/dts/rockchip/overlay/Makefile | 3 ++-
.../dts/rockchip/overlay/README.rockchip-overlays | 6 ++++++
.../overlay/rockchip-rk3318-box-emmc-hs200.dts | 14 ++++++++++++++
3 files changed, 22 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-emmc-hs200.dts
diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile
index 42b19bd85..f227d5997 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/Makefile
+++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile
@@ -16,7 +16,8 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-rk3318-box-wlan-ap6334.dtbo \
rockchip-rk3318-box-wlan-ext.dtbo \
rockchip-rk3318-box-wlan-ap6330.dtbo \
- rockchip-rk3318-box-cpu-hs.dtbo
+ rockchip-rk3318-box-cpu-hs.dtbo \
+ rockchip-rk3318-box-emmc-hs200.dtbo
scr-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-fixup.scr
diff --git a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
index 2fc9b00fe..1b547bea7 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
+++ b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
@@ -130,6 +130,12 @@ Activates eMMC DDR capability for rk3318 tv box boards. Probably all the eMMC ch
nowadays support DDR mode, but its reliability heavily depends upon the quality
of board wiring
+### rk3318-box-emmc-hs200
+
+Activates eMMC HS200 capability for rk3318 tv box boards.
+It should in autodetect mode, but some board have faulty or cheap circuitry that
+enable the mode but then it doesn't work correctly.
+
### rk3318-box-wlan-ap6334
Set up additional device tree bits to properly support ap6334 (broadcom BCM4334)
diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-emmc-hs200.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-emmc-hs200.dts
new file mode 100644
index 000000000..55f8f7eb6
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-emmc-hs200.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+
+ fragment@0 {
+ target = <&emmc>;
+ __overlay__ {
+ status = "okay";
+ mmc-hs200-1_8v;
+ };
+ };
+
+};
--
2.25.1

105
patch/kernel/archive/rockchip64-5.18/overlays-09-add-rk3318-box-led-conf2.patch Normal file
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@ -0,0 +1,105 @@
From 984e45a2fe4643ff96b43e0057c7e019aa8be7d6 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Fri, 23 Apr 2021 13:11:51 +0000
Subject: [PATCH] rk3318-box: add X88_PRO_B led/gpio configuration
---
arch/arm64/boot/dts/rockchip/overlay/Makefile | 1 +
.../rockchip/overlay/README.rockchip-overlays | 5 ++
.../overlay/rockchip-rk3318-box-led-conf2.dts | 64 +++++++++++++++++++
3 files changed, 70 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-led-conf2.dts
diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile
index f227d5997..c28c7a5eb 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/Makefile
+++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile
@@ -12,6 +12,7 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-dwc3-0-host.dtbo \
rockchip-w1-gpio.dtbo \
rockchip-rk3318-box-led-conf1.dtbo \
+ rockchip-rk3318-box-led-conf2.dtbo \
rockchip-rk3318-box-emmc-ddr.dtbo \
rockchip-rk3318-box-wlan-ap6334.dtbo \
rockchip-rk3318-box-wlan-ext.dtbo \
diff --git a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
index 1b547bea7..4172bd731 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
+++ b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
@@ -124,6 +124,11 @@ or enabling the internal pull-up
Activates led/gpio configuration for rk3318 tv box boards with signature
YX_RK3328 and clones
+### rk3318-box-led-conf2
+
+Activates led/gpio configuration for rk3318 tv box boards withs signature
+X88_PRO_B and clones
+
### rk3318-box-emmc-ddr
Activates eMMC DDR capability for rk3318 tv box boards. Probably all the eMMC chips
diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-led-conf2.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-led-conf2.dts
new file mode 100644
index 000000000..9a8146b9a
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-led-conf2.dts
@@ -0,0 +1,59 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+
+ fragment@0 {
+ target-path = "/gpio-leds";
+ __overlay__ {
+
+ working {
+ gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "mmc2";
+ };
+
+ /*
+ * no auxiliary led on X88_PRO_B boards
+ *
+ auxiliary {
+ gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
+ label = "auxiliary";
+ linux,default-trigger = "mmc2";
+ default-state = "off";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_led_aux>;
+ };
+ */
+
+ };
+ };
+
+ fragment@1 {
+ target = <&vcc_otg_vbus>;
+ __overlay__ {
+
+ gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
+
+ };
+
+ };
+
+ fragment@2 {
+ target = <&working_led>;
+ __overlay__ {
+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none_2ma>;
+ };
+ };
+
+ fragment@3 {
+ target = <&io_domains>;
+ __overlay__ {
+ vccio6-supply = <&vcc_18>;
+ };
+ };
+
+};

331
patch/kernel/archive/rockchip64-5.18/overlays-10-add-rk3318-box-led-conf3.patch Normal file
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@ -0,0 +1,331 @@
From 506d63cda173ca0f992bdbf4b4d2f3e1e20f905c Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Mon, 18 Oct 2021 18:30:28 +0000
Subject: [PATCH] rk3318-box: add led-conf3 to support MXQ-RK3328-D4 boards
with RK805 PMIC
---
arch/arm64/boot/dts/rockchip/overlay/Makefile | 1 +
.../rockchip/overlay/README.rockchip-overlays | 7 +
.../overlay/rockchip-rk3318-box-led-conf3.dts | 279 ++++++++++++++++++
3 files changed, 287 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-led-conf3.dts
diff --git a/arch/arm64/boot/dts/rockchip/overlay/Makefile b/arch/arm64/boot/dts/rockchip/overlay/Makefile
index c28c7a5eb..f11aa6d57 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/Makefile
+++ b/arch/arm64/boot/dts/rockchip/overlay/Makefile
@@ -13,6 +13,7 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
rockchip-w1-gpio.dtbo \
rockchip-rk3318-box-led-conf1.dtbo \
rockchip-rk3318-box-led-conf2.dtbo \
+ rockchip-rk3318-box-led-conf3.dtbo \
rockchip-rk3318-box-emmc-ddr.dtbo \
rockchip-rk3318-box-wlan-ap6334.dtbo \
rockchip-rk3318-box-wlan-ext.dtbo \
diff --git a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
index 4172bd731..27f945d38 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
+++ b/arch/arm64/boot/dts/rockchip/overlay/README.rockchip-overlays
@@ -129,6 +129,13 @@ YX_RK3328 and clones
Activates led/gpio configuration for rk3318 tv box boards withs signature
X88_PRO_B and clones
+### rk3318-box-led-conf3
+
+This device tree overlay is suitable for MXQ-RK3328-D4_A board which
+has an integrated PMIC (RK805). The dtbo is very important to achieve
+1.3 Ghz speed for CPU and stable voltages for other parts of the
+system. Also enables gpio leds and keys.
+
### rk3318-box-emmc-ddr
Activates eMMC DDR capability for rk3318 tv box boards. Probably all the eMMC chips
diff --git a/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-led-conf3.dts b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-led-conf3.dts
new file mode 100644
index 000000000..4641f7588
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/overlay/rockchip-rk3318-box-led-conf3.dts
@@ -0,0 +1,279 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+&{/regulators/regulator@0} {
+ status = "disabled";
+};
+
+&{/regulators/regulator@1} {
+ status = "disabled";
+};
+
+&{/vdd-arm} {
+ status = "disabled";
+};
+
+&{/vdd-log} {
+ status = "disabled";
+};
+
+&{/xin32k} {
+ status = "disabled";
+};
+
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clock-frequency = <1000000>;
+ i2c-scl-rising-time-ns = <83>;
+ i2c-scl-falling-time-ns = <5>;
+ status = "okay";
+
+ rk805: rk805@18 {
+ compatible = "rockchip,rk805";
+ reg = <0x18>;
+ status = "okay";
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-parent = <&gpio2>;
+ interrupts = <RK_PA6 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk805-clkout2";
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc5-supply = <&rk805_vcc_io>;
+ vcc6-supply = <&rk805_vcc_io>;
+
+ rtc {
+ status = "okay";
+ };
+
+ pwrkey {
+ status = "okay";
+ };
+
+ gpio {
+ status = "okay";
+ };
+
+ regulators {
+ compatible = "rk805-regulator";
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <12500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <12500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_io: rk805_vcc_io: DCDC_REG4 {
+ regulator-name = "vccio_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vdd_18: vcc_18: LDO_REG1 {
+ regulator-name = "vccio_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_18emmc: LDO_REG2 {
+ regulator-name = "vcc_18emmc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_11: LDO_REG3 {
+ regulator-name = "vdd_11";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1100000>;
+ };
+ };
+ };
+ };
+
+};
+
+&pinctrl {
+
+ leds {
+ ir_led: ir-led {
+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+};
+
+&gpio_led {
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_led>;
+
+ working {
+ gpios = <&rk805 1 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ linux,default-trigger = "default-on";
+ mode = <35>;
+ };
+
+ auxiliary {
+ gpios = <&rk805 0 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "mmc2";
+ default-state = "off";
+ mode = <5>;
+ };
+
+ ir {
+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "ir";
+ default-state = "off";
+ mode = <0>;
+ };
+
+};
+
+&io_domains {
+ vccio1-supply = <&vcc_io>;
+ vccio2-supply = <&vcc_18emmc>;
+ vccio3-supply = <&vcc_io>;
+ vccio4-supply = <&vdd_18>;
+ vccio5-supply = <&vcc_io>;
+ vccio6-supply = <&vcc_io>;
+ pmuio-supply = <&vcc_io>;
+};
+
+&{/} {
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+
+ power {
+ label = "Power button";
+ linux,code = <KEY_POWER>;
+ gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&dmc {
+ center-supply = <&vdd_logic>;
+};
+
+&gpu {
+ mali-supply = <&vdd_logic>;
+};
+
+&vpu {
+ vcodec-supply = <&vdd_logic>;
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_arm>;
+};
+
+
+&vcc_sd {
+ vin-supply = <&vcc_io>;
+};
+
+&emmc {
+ vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vcc_18emmc>;
+};
+
+&saradc {
+ vref-supply = <&vcc_18>;
+};
+
+&pwm0 {
+ status = "disabled";
+};
+
+&pwm1 {
+ status = "disabled";
+};
+
--
2.30.2

322
patch/kernel/archive/rockchip64-5.18/rk3328-hw-cursor-plane.patch.disabled Normal file
View File

@ -0,0 +1,322 @@
From 6eb43deb95d99178419b480181fd18a9b4d9f8fe Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sun, 24 Oct 2021 17:06:13 +0000
Subject: [PATCH] rk3328: hardware dedicated cursor plane
---
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 214 +++++++++++++++++++-
drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 3 +
drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 20 +-
3 files changed, 234 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index f5b9028a1..9a4afba29 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1104,6 +1104,201 @@ static void vop_plane_atomic_async_update(struct drm_plane *plane,
}
}
+static void vop_cursor_atomic_update(struct drm_plane *plane,
+ struct drm_atomic_state *state)
+{
+
+ struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
+ plane);
+ struct drm_crtc *crtc = new_state->crtc;
+ struct vop_win *vop_win = to_vop_win(plane);
+ const struct vop_win_data *win = vop_win->data;
+ struct vop *vop = to_vop(new_state->crtc);
+ struct drm_framebuffer *fb = new_state->fb;
+ unsigned int actual_h;
+ unsigned int dsp_stx, dsp_sty;
+ uint32_t dsp_st;
+ struct drm_rect *src = &new_state->src;
+ struct drm_rect *dest = &new_state->dst;
+ struct drm_gem_object *obj;
+ struct rockchip_gem_object *rk_obj;
+ dma_addr_t dma_addr;
+ uint32_t val;
+ bool rb_swap;
+ int win_index = VOP_WIN_TO_INDEX(vop_win);
+ int format;
+
+ /*
+ * can't update plane when vop is disabled.
+ */
+ if (WARN_ON(!crtc))
+ return;
+
+ if (WARN_ON(!vop->is_enabled))
+ return;
+
+ if (!new_state->visible) {
+ vop_plane_atomic_disable(plane, state);
+ return;
+ }
+
+ obj = fb->obj[0];
+ rk_obj = to_rockchip_obj(obj);
+
+ actual_h = drm_rect_height(src) >> 16;
+
+ dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
+ dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
+ dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
+
+ dma_addr = rk_obj->dma_addr;
+
+ /*
+ * For y-mirroring we need to move address
+ * to the beginning of the last line.
+ */
+ if (new_state->rotation & DRM_MODE_REFLECT_Y)
+ dma_addr += (actual_h - 1) * fb->pitches[0];
+
+ spin_lock(&vop->reg_lock);
+
+ if (!(vop->win_enabled & BIT(win_index))) {
+
+ format = vop_convert_format(fb->format->format);
+
+ VOP_WIN_SET(vop, win, format, format);
+
+ rb_swap = has_rb_swapped(fb->format->format);
+ VOP_WIN_SET(vop, win, rb_swap, rb_swap);
+
+ /*
+ * Blending win0 with the background color doesn't seem to work
+ * correctly. We only get the background color, no matter the contents
+ * of the win0 framebuffer. However, blending pre-multiplied color
+ * with the default opaque black default background color is a no-op,
+ * so we can just disable blending to get the correct result.
+ */
+ if (fb->format->has_alpha && win_index > 0) {
+ VOP_WIN_SET(vop, win, dst_alpha_ctl,
+ DST_FACTOR_M0(ALPHA_SRC_INVERSE));
+ val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
+ SRC_ALPHA_M0(ALPHA_STRAIGHT) |
+ SRC_BLEND_M0(ALPHA_PER_PIX) |
+ SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
+ SRC_FACTOR_M0(ALPHA_ONE);
+ VOP_WIN_SET(vop, win, src_alpha_ctl, val);
+
+ VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL);
+ VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX);
+ VOP_WIN_SET(vop, win, alpha_en, 1);
+ } else {
+ VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
+ VOP_WIN_SET(vop, win, alpha_en, 0);
+ }
+
+ // 32x32 = 0, 64x64 = 1, 96x96 = 2, 128x128 = 3
+ VOP_WIN_SET(vop, win, hwc_size, (new_state->crtc_w >> 5) - 1);
+
+ VOP_WIN_SET(vop, win, enable, 1);
+ vop->win_enabled |= BIT(win_index);
+
+ }
+
+ VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
+ VOP_WIN_SET(vop, win, dsp_st, dsp_st);
+
+ spin_unlock(&vop->reg_lock);
+
+}
+
+static void vop_cursor_atomic_async_update(struct drm_plane *plane,
+ struct drm_atomic_state *state)
+{
+
+ struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
+ plane);
+ struct vop *vop = to_vop(plane->state->crtc);
+ struct drm_framebuffer *old_fb = plane->state->fb;
+
+ plane->state->crtc_x = new_state->crtc_x;
+ plane->state->crtc_y = new_state->crtc_y;
+ plane->state->crtc_h = new_state->crtc_h;
+ plane->state->crtc_w = new_state->crtc_w;
+ plane->state->src_x = new_state->src_x;
+ plane->state->src_y = new_state->src_y;
+ plane->state->src_h = new_state->src_h;
+ plane->state->src_w = new_state->src_w;
+ swap(plane->state->fb, new_state->fb);
+
+ if (vop->is_enabled) {
+ vop_cursor_atomic_update(plane, state);
+ spin_lock(&vop->reg_lock);
+ vop_cfg_done(vop);
+ spin_unlock(&vop->reg_lock);
+
+ /*
+ * A scanout can still be occurring, so we can't drop the
+ * reference to the old framebuffer. To solve this we get a
+ * reference to old_fb and set a worker to release it later.
+ * FIXME: if we perform 500 async_update calls before the
+ * vblank, then we can have 500 different framebuffers waiting
+ * to be released.
+ */
+ if (old_fb && plane->state->fb != old_fb) {
+ drm_framebuffer_get(old_fb);
+ WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0);
+ drm_flip_work_queue(&vop->fb_unref_work, old_fb);
+ set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
+ }
+ }
+
+}
+
+static int vop_cursor_atomic_check(struct drm_plane *plane,
+ struct drm_atomic_state *state)
+{
+ struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
+ plane);
+ struct drm_crtc *crtc = new_plane_state->crtc;
+ struct drm_crtc_state *crtc_state;
+ struct drm_framebuffer *fb = new_plane_state->fb;
+ int ret;
+
+ if (!crtc || WARN_ON(!fb))
+ return 0;
+
+ crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
+ if (WARN_ON(!crtc_state))
+ return -EINVAL;
+
+ ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
+ DRM_PLANE_HELPER_NO_SCALING, DRM_PLANE_HELPER_NO_SCALING,
+ true, true);
+
+ if (ret)
+ return ret;
+
+ if (!new_plane_state->visible)
+ return 0;
+
+ ret = vop_convert_format(fb->format->format);
+ if (ret < 0)
+ return ret;
+
+ if (new_plane_state->crtc_w != new_plane_state->crtc_h)
+ return -EINVAL;
+
+ if (new_plane_state->crtc_w != 0 &&
+ new_plane_state->crtc_w != 32 &&
+ new_plane_state->crtc_w != 64 &&
+ new_plane_state->crtc_w != 96 &&
+ new_plane_state->crtc_w != 128)
+ return -EINVAL;
+
+ return 0;
+
+}
+
static const struct drm_plane_helper_funcs plane_helper_funcs = {
.atomic_check = vop_plane_atomic_check,
.atomic_update = vop_plane_atomic_update,
@@ -1113,6 +1308,15 @@ static const struct drm_plane_helper_funcs plane_helper_funcs = {
.prepare_fb = drm_gem_plane_helper_prepare_fb,
};
+static const struct drm_plane_helper_funcs cursor_plane_helper_funcs = {
+ .atomic_check = vop_cursor_atomic_check,
+ .atomic_update = vop_cursor_atomic_update,
+ .atomic_disable = vop_plane_atomic_disable,
+ .atomic_async_check = vop_plane_atomic_async_check,
+ .atomic_async_update = vop_cursor_atomic_async_update,
+ .prepare_fb = drm_gem_plane_helper_prepare_fb,
+};
+
static const struct drm_plane_funcs vop_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
@@ -1772,6 +1976,7 @@ static int vop_create_crtc(struct vop *vop)
struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
struct drm_crtc *crtc = &vop->crtc;
struct device_node *port;
+ const struct drm_plane_helper_funcs *helper_funcs;
int ret;
int i;
@@ -1801,7 +2006,14 @@ static int vop_create_crtc(struct vop *vop)
}
plane = &vop_win->base;
- drm_plane_helper_add(plane, &plane_helper_funcs);
+ helper_funcs = &plane_helper_funcs;
+
+ if ((plane->type == DRM_PLANE_TYPE_CURSOR) && (vop_data->feature & VOP_FEATURE_SPECIAL_CURSOR_PLANE)) {
+ dev_info(dev, "using dedicated hwcursor plane\n");
+ helper_funcs = &cursor_plane_helper_funcs;
+ }
+
+ drm_plane_helper_add(plane, helper_funcs);
vop_plane_add_properties(plane, win_data);
if (plane->type == DRM_PLANE_TYPE_PRIMARY)
primary = plane;
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 857d97cdc..7967359c1 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -182,6 +182,8 @@ struct vop_win_phy {
struct vop_reg alpha_mode;
struct vop_reg alpha_en;
struct vop_reg channel;
+
+ struct vop_reg hwc_size;
};
struct vop_win_yuv2yuv_data {
@@ -211,6 +213,7 @@ struct vop_data {
#define VOP_FEATURE_OUTPUT_RGB10 BIT(0)
#define VOP_FEATURE_INTERNAL_RGB BIT(1)
+#define VOP_FEATURE_SPECIAL_CURSOR_PLANE BIT(2)
u64 feature;
};
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index ca7cc8212..56eb4f774 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -1048,18 +1048,34 @@ static const struct vop_intr rk3328_vop_intr = {
.clear = VOP_REG_MASK_SYNC(RK3328_INTR_CLEAR0, 0xffff, 0),
};
+static const struct vop_win_phy rk3328_cursor_data = {
+ .data_formats = formats_win_lite,
+ .nformats = ARRAY_SIZE(formats_win_lite),
+ .format_modifiers = format_modifiers_win_lite,
+ .enable = VOP_REG(RK3328_HWC_CTRL0, 0x1, 0),
+ .format = VOP_REG(RK3328_HWC_CTRL0, 0x7, 1),
+ .rb_swap = VOP_REG(RK3328_HWC_CTRL0, 0x1, 12),
+ .dsp_st = VOP_REG(RK3328_HWC_DSP_ST, 0x1fff1fff, 0),
+ .yrgb_mst = VOP_REG(RK3328_HWC_MST, 0xffffffff, 0),
+ .src_alpha_ctl = VOP_REG(RK3328_HWC_SRC_ALPHA_CTRL, 0xff, 0),
+ .dst_alpha_ctl = VOP_REG(RK3328_HWC_DST_ALPHA_CTRL, 0xff, 0),
+ .hwc_size = VOP_REG(RK3328_HWC_CTRL0, 0x3, 5),
+};
+
static const struct vop_win_data rk3328_vop_win_data[] = {
{ .base = 0xd0, .phy = &rk3368_win01_data,
.type = DRM_PLANE_TYPE_PRIMARY },
{ .base = 0x1d0, .phy = &rk3368_win01_data,
.type = DRM_PLANE_TYPE_OVERLAY },
{ .base = 0x2d0, .phy = &rk3368_win01_data,
- .type = DRM_PLANE_TYPE_CURSOR },
+ .type = DRM_PLANE_TYPE_OVERLAY },
+ { .base = 0x00, .phy = &rk3328_cursor_data,
+ .type = DRM_PLANE_TYPE_CURSOR }
};
static const struct vop_data rk3328_vop = {
.version = VOP_VERSION(3, 8),
- .feature = VOP_FEATURE_OUTPUT_RGB10,
+ .feature = VOP_FEATURE_OUTPUT_RGB10 | VOP_FEATURE_SPECIAL_CURSOR_PLANE,
.intr = &rk3328_vop_intr,
.common = &rk3328_common,
.modeset = &rk3328_modeset,
--
2.30.2

45
patch/kernel/archive/rockchip64-5.18/wifi-4003-add-bcm43342-chip.patch Normal file
View File

@ -0,0 +1,45 @@
From 01b579a527b5c77e6adfbb2c277fb2c7cc158b8b Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Thu, 10 Feb 2022 21:30:54 +0000
Subject: [PATCH] add broadcom bcm43342 chip id
---
drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c | 2 ++
drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
index 8effeb7a726..f45c1056e42 100644
--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
@@ -611,6 +611,7 @@ BRCMF_FW_DEF(4329, "brcmfmac4329-sdio");
BRCMF_FW_DEF(4330, "brcmfmac4330-sdio");
BRCMF_FW_DEF(4334, "brcmfmac4334-sdio");
BRCMF_FW_DEF(43340, "brcmfmac43340-sdio");
+BRCMF_FW_DEF(43342, "brcmfmac43342-sdio");
BRCMF_FW_DEF(4335, "brcmfmac4335-sdio");
BRCMF_FW_DEF(43362, "brcmfmac43362-sdio");
BRCMF_FW_DEF(4339, "brcmfmac4339-sdio");
@@ -644,6 +645,7 @@ static const struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
BRCMF_FW_ENTRY(BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, 4334),
BRCMF_FW_ENTRY(BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, 43340),
BRCMF_FW_ENTRY(BRCM_CC_43341_CHIP_ID, 0xFFFFFFFF, 43340),
+ BRCMF_FW_ENTRY(BRCM_CC_43342_CHIP_ID, 0xFFFFFFFF, 43342),
BRCMF_FW_ENTRY(BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, 4335),
BRCMF_FW_ENTRY(BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, 43362),
BRCMF_FW_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339),
diff --git a/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h b/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h
index 9d81320164c..71de0dce4f4 100644
--- a/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h
+++ b/drivers/net/wireless/broadcom/brcm80211/include/brcm_hw_ids.h
@@ -27,6 +27,7 @@
#define BRCM_CC_4334_CHIP_ID 0x4334
#define BRCM_CC_43340_CHIP_ID 43340
#define BRCM_CC_43341_CHIP_ID 43341
+#define BRCM_CC_43342_CHIP_ID 43342
#define BRCM_CC_43362_CHIP_ID 43362
#define BRCM_CC_4335_CHIP_ID 0x4335
#define BRCM_CC_4339_CHIP_ID 0x4339
--
2.30.2

123
patch/u-boot/u-boot-rockchip64/board_rk3318-box/rk3318-box-add-defconfig.patch Normal file
View File

@ -0,0 +1,123 @@
diff --git a/configs/rk3318-box_defconfig b/configs/rk3318-box_defconfig
new file mode 100644
index 00000000..b6a038f7
--- /dev/null
+++ b/configs/rk3318-box_defconfig
@@ -0,0 +1,117 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_ROCKCHIP_RK3328=y
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_BOX_RK3318=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_DEBUG_UART_BASE=0xFF130000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEFAULT_DEVICE_TREE="rk3318-box"
+CONFIG_DEBUG_UART=y
+CONFIG_LOCALVERSION="-armbian"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_USE_PREBOOT=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3318-box.dts"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_PARTITION_UUIDS=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_TPL_OF_PLATDATA=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+# CONFIG_SPI_FLASH is not set
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SPI_MEM=y
+CONFIG_SYSRESET=y
+# CONFIG_TPL_SYSRESET is not set
+CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC3=y
+# CONFIG_USB_DWC3_GADGET is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_DM_VIDEO=y
+# CONFIG_BACKLIGHT is not set
+# CONFIG_PANEL is not set
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+CONFIG_VIDEO_BRIDGE=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y

735
patch/u-boot/u-boot-rockchip64/board_rk3318-box/rk3318-box-add-dts.patch Normal file
View File

@ -0,0 +1,735 @@
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index cf4f4ae8..3475d564 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -107,6 +107,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
rk3308-roc-cc.dtb
dtb-$(CONFIG_ROCKCHIP_RK3328) += \
+ rk3318-box.dtb \
rk3328-evb.dtb \
rk3328-nanopi-r2-rev00.dtb \
rk3328-orangepi-r1-plus.dtb \
diff --git a/arch/arm/dts/rk3318-box-u-boot.dtsi b/arch/arm/dts/rk3318-box-u-boot.dtsi
new file mode 100644
index 00000000..e9ab052c
--- /dev/null
+++ b/arch/arm/dts/rk3318-box-u-boot.dtsi
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 Armbian project (jock)
+ */
+
+#include "rk3328-u-boot.dtsi"
+#include "rk3328-sdram-ddr3-666.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdmmc_ext, &emmc;
+ };
+
+};
+
+&gpio0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&sdmmc0m1_pin {
+ u-boot,dm-pre-reloc;
+};
+
+&pcfg_pull_up_4ma {
+ u-boot,dm-pre-reloc;
+};
+
+&usb_host0_xhci {
+ vbus-supply = <&vcc_host_vbus>;
+ status = "okay";
+};
+
+&vcc_sd {
+ u-boot,dm-pre-reloc;
+};
+
+&sdmmc {
+ u-boot,dm-pre-reloc;
+};
+
+&sdio {
+ status="disabled";
+};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+};
+
+&sdmmc_ext {
+ u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+
+ sdmmc0-1 {
+ sdmmc0m1_pwren: sdmmc0m1-pwren {
+ rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc0m1_pin: sdmmc0m1-pin {
+ rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
+ };
+ };
+
+};
+
+&vdd_arm {
+ regulator-init-microvolt = <1200000>;
+};
diff --git a/arch/arm/dts/rk3318-box.dts b/arch/arm/dts/rk3318-box.dts
new file mode 100644
index 00000000..d4678c7c
--- /dev/null
+++ b/arch/arm/dts/rk3318-box.dts
@@ -0,0 +1,634 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2020 Armbian project (jock)
+ */
+
+/dts-v1/;
+#include "rk3328.dtsi"
+
+/ {
+ model = "Rockchip RK3318 BOX";
+ compatible = "rockchip,rk3318-box", "rockchip,rk3328-box", "rockchip,rk3328";
+
+ aliases {
+ mmc0 = &sdmmc;
+ mmc1 = &sdio;
+ mmc2 = &emmc;
+ mmc3 = &sdmmc_ext;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ xin32k: xin32k {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ #clock-cells = <0>;
+ };
+
+ gmac_clkin: gmac-clkin {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac_clkin";
+ #clock-cells = <0x00>;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+
+ vcc_18: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vccio_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ vcc_io: regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vccio_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_phy";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc_sys: vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc_sd: sdmmc-regulator {
+ compatible = "regulator-fixed";
+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0m1_pin>;
+ regulator-name = "vcc_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_io>;
+ };
+
+ /*
+ * USB3 vbus
+ */
+ vcc_host_vbus: vcc-host-vbus {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb30_host_drv>;
+ regulator-name = "vcc_host_vbus";
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_sys>;
+ };
+
+ /*
+ * USB2 OTG vbus
+ */
+ vcc_otg_vbus: vcc-otg-vbus {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb20_host_drv>;
+ regulator-name = "vcc_otg_vbus";
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vdd_arm: vdd-arm {
+ compatible = "pwm-regulator";
+ pwms = <&pwm0 0 5000 1>;
+ pwm-supply = <&vcc_sys>;
+ regulator-name = "vdd_arm";
+ regulator-init-microvolt = <1000000>;
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-ramp-delay = <12500>;
+ regulator-settling-time-up-us = <250>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ };
+
+ vdd_logic: vdd-log {
+ compatible = "pwm-regulator";
+ pwms = <&pwm1 0 5000 1>;
+ pwm-supply = <&vcc_sys>;
+ regulator-name = "vdd_log";
+ regulator-init-microvolt = <1000000>;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-ramp-delay = <12500>;
+ regulator-settling-time-up-us = <250>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&working_led>;
+
+ working {
+ gpios = <&gpio2 RK_PC7 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "default-on";
+ default-state = "on";
+ };
+
+ };
+
+ ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&ir_int>;
+ pinctrl-names = "default";
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+
+ /*
+ * On the module itself this is one of these (depending
+ * on the actual card populated):
+ * - SDIO_RESET_L_WL_REG_ON
+ * - PDN (power down when low)
+ */
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+ };
+
+ fd628_dev {
+ compatible = "fd628_dev";
+ fd628_gpio_clk = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+ fd628_gpio_dat = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ analog-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,name = "ANALOG";
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&codec>;
+ };
+ };
+
+ hdmi-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <128>;
+ simple-audio-card,name = "HDMI";
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s0>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&hdmi>;
+ };
+ };
+
+};
+
+&codec {
+ status = "okay";
+ mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>;
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_arm>;
+};
+
+/*
+&dmc {
+ center-supply = <&vdd_logic>;
+ status = "disabled";
+};
+*/
+
+&display_subsystem {
+ status = "okay";
+};
+
+&emmc {
+
+ supports-emmc;
+ no-sdio;
+ no-sd;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ disable-wp;
+ non-removable;
+ bus-width = <8>;
+ num-slots = <0x01>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+
+ vmmc-supply = <&vcc_io>;
+ vqmmc-supply = <&vcc_18>;
+
+ status = "okay";
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
+ supports-sd;
+ vmmc-supply = <&vcc_sd>;
+ status = "okay";
+};
+
+&sdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ disable-wp;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ num-slots = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+ supports-sdio;
+ status = "okay";
+
+ brcmf: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ brcm,drive-strength = <4>;
+ interrupt-parent = <&gpio1>;
+ interrupt-names = "host_wake";
+ interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio_host_wake>;
+ };
+
+};
+
+&sdmmc_ext {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0ext_clk &sdmmc0ext_cmd &sdmmc0ext_dectn &sdmmc0ext_bus4>;
+ supports-sd;
+ vmmc-supply = <&vcc_sd>;
+ status = "okay";
+};
+
+&gmac2phy {
+ phy-supply = <&vcc_phy>;
+
+ phy-mode = "rmii";
+
+ clock_in_out = "output";
+ assigned-clocks = <&cru SCLK_MAC2PHY>;
+ assigned-clock-rate = <50000000>;
+ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+
+ status = "okay";
+
+};
+
+&gpu {
+ status = "okay";
+ mali-supply = <&vdd_logic>;
+};
+
+/*
+&h265e {
+ status = "okay";
+};
+*/
+
+&h265e_mmu {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+/*
+&spdif {
+ pinctrl-0 = <&spdifm0_tx>;
+ status = "okay";
+};
+
+&spdif_out {
+ status = "okay";
+};
+
+&spdif_sound {
+ status = "okay";
+};
+*/
+
+&hdmiphy {
+ status = "okay";
+};
+
+&i2s0 {
+ status = "okay";
+};
+
+&i2s1 {
+ status = "okay";
+};
+
+&io_domains {
+ status = "okay";
+
+ vccio1-supply = <&vcc_io>;
+ vccio2-supply = <&vcc_18>;
+ vccio3-supply = <&vcc_io>;
+ vccio4-supply = <&vcc_18>;
+ vccio5-supply = <&vcc_io>;
+ vccio6-supply = <&vcc_io>;
+ pmuio-supply = <&vcc_io>;
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&clk_32k_out>;
+
+ clk_32k {
+ clk_32k_out: clk-32k-out {
+ rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ working_led: working-led {
+ rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none_2ma>;
+ };
+ };
+
+ ir {
+ ir_int: ir-int {
+ rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none_4ma>;/*,
+ <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none_4ma>;*/
+ };
+ };
+
+ usb2 {
+ usb20_host_drv: usb20-host-drv {
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb3 {
+ usb30_host_drv: usb30-host-drv {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wireless-bluetooth {
+ uart0_gpios: uart0-gpios {
+ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ wireless-wlan {
+ sdio_host_wake: sdio-host-wake {
+ rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+};
+
+/*
+&rkvdec {
+ status = "okay";
+ vcodec-supply = <&vdd_logic>;
+};
+*/
+
+&rkvdec_mmu {
+ status = "okay";
+};
+
+&threshold {
+ temperature = <80000>; /* millicelsius */
+};
+
+&target {
+ temperature = <95000>; /* millicelsius */
+};
+
+&soc_crit {
+ temperature = <100000>; /* millicelsius */
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <0>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart0 {
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts>;
+ status = "okay";
+
+ bluetooth {
+ compatbile = "brcm,bcm43341-bt";
+ max-speed = <1500000>;
+ shutdown-gpios = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>;
+ interrupt-names = "host-wakeup";
+ interrupts = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+ brcm,bt-pcm-int-params = [01 02 00 01 01];
+ };
+
+};
+
+&uart2 {
+ /delete-property/ dmas;
+ /delete-property/ dma-names;
+
+ status = "okay";
+};
+
+&u2phy {
+ status = "okay";
+
+ u2phy_host: host-port {
+ status = "okay";
+ };
+
+ u2phy_otg: otg-port {
+ status = "okay";
+ };
+};
+
+&usb20_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+/*
+&u3phy {
+ vbus-supply = <&vcc_host_vbus>;
+ status = "okay";
+};
+
+&u3phy_utmi {
+ status = "okay";
+};
+
+&u3phy_pipe {
+ status = "okay";
+};
+*/
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+/*
+&usbdrd3 {
+ status = "okay";
+};
+
+&usbdrd_dwc3 {
+ dr_mode = "host";
+ status = "okay";
+};
+*/
+
+&vop {
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vpu {
+ status = "okay";
+ vcodec-supply = <&vdd_logic>;
+};
+
+&vpu_mmu {
+ status = "okay";
+};
+
+/*
+&vepu {
+ status = "okay";
+};
+*/
+
+&vepu_mmu {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc_18>;
+ status = "okay";
+};
+
+/*
+&rga {
+ status = "okay";
+};
+*/
+
+&pwm0 {
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&cpu0_opp_table {
+
+ opp-1512000000 {
+ status = "disabled";
+ };
+
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+&analog_sound {
+ status = "okay";
+};

218
patch/u-boot/u-boot-rockchip64/board_rk3318-box/rk3318-box-add-makefile.patch Normal file
View File

@ -0,0 +1,218 @@
diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig
index d13a1690..f2d8dab4 100644
--- a/arch/arm/mach-rockchip/rk3328/Kconfig
+++ b/arch/arm/mach-rockchip/rk3328/Kconfig
@@ -10,6 +10,13 @@ config TARGET_EVB_RK3328
with full function and phisical connectors support like
usb2.0 host ports, LVDS, JTAG, MAC, SDcard, HDMI, USB-2-serial...
+config TARGET_BOX_RK3318
+ bool "Generic RK3318 Box"
+ help
+ Generic RK3318/RK3328 Tvbox appliance,
+ with full function and phisical connectors support like
+ usb2.0 and usb3.0 ports, MAC, SDcard, HDMI, eMMC, WiFi, ...
+
endchoice
config ROCKCHIP_BOOT_MODE_REG
@@ -40,5 +47,6 @@ config TPL_STACK
default 0xff098000
source "board/rockchip/evb_rk3328/Kconfig"
+source "board/rockchip/rk3318_box/Kconfig"
endif
diff --git a/board/rockchip/rk3318_box/Kconfig b/board/rockchip/rk3318_box/Kconfig
new file mode 100644
index 00000000..4b146413
--- /dev/null
+++ b/board/rockchip/rk3318_box/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_BOX_RK3318
+
+config SYS_BOARD
+ default "rk3318_box"
+
+config SYS_VENDOR
+ default "rockchip"
+
+config SYS_CONFIG_NAME
+ default "rk3318-box"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
diff --git a/board/rockchip/rk3318_box/MAINTAINERS b/board/rockchip/rk3318_box/MAINTAINERS
new file mode 100644
index 00000000..e7dd59ff
--- /dev/null
+++ b/board/rockchip/rk3318_box/MAINTAINERS
@@ -0,0 +1,26 @@
+EVB-RK3328
+M: Kever Yang <kever.yang@rock-chips.com>
+S: Maintained
+F: board/rockchip/evb_rk3328
+F: include/configs/evb_rk3328.h
+F: configs/evb-rk3328_defconfig
+
+ROC-RK3328-CC
+M: Loic Devulder <ldevulder@suse.com>
+M: Chen-Yu Tsai <wens@csie.org>
+S: Maintained
+F: configs/roc-cc-rk3328_defconfig
+F: arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
+
+ROCK64-RK3328
+M: Matwey V. Kornilov <matwey.kornilov@gmail.com>
+S: Maintained
+F: configs/rock64-rk3328_defconfig
+F: arch/arm/dts/rk3328-rock64-u-boot.dtsi
+
+ROCKPIE-RK3328
+M: Banglang Huang <banglang.huang@foxmail.com>
+S: Maintained
+F: configs/rock-pi-e-rk3328_defconfig
+F: arch/arm/dts/rk3328-rock-pi-e.dts
+F: arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
diff --git a/board/rockchip/rk3318_box/Makefile b/board/rockchip/rk3318_box/Makefile
new file mode 100644
index 00000000..5eba9dfb
--- /dev/null
+++ b/board/rockchip/rk3318_box/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += rk3318-box.o
diff --git a/board/rockchip/rk3318_box/README b/board/rockchip/rk3318_box/README
new file mode 100644
index 00000000..6cbb66a4
--- /dev/null
+++ b/board/rockchip/rk3318_box/README
@@ -0,0 +1,70 @@
+Introduction
+============
+
+RK3328 key features we might use in U-Boot:
+* CPU: ARMv8 64bit quad-core Cortex-A53
+* IRAM: 36KB
+* DRAM: 4GB-16MB dual-channel
+* eMMC: support eMMC 5.0/5.1, suport HS400, HS200, DDR50
+* SD/MMC: support SD 3.0, MMC 4.51
+* USB: USB2.0 EHCI host port *2
+* Display: RGB/HDMI/DP/MIPI/EDP
+
+evb key features:
+* regulator: pwm regulator for CPU B/L
+* PMIC: rk808
+* debug console: UART2
+
+In order to support Arm Trust Firmware(ATF), we need to use the
+miniloader from rockchip which:
+* do DRAM init
+* load and verify ATF image
+* load and verify U-Boot image
+
+Here is the step-by-step to boot to U-Boot on rk3328.
+
+Get the Source and prebuild binary
+==================================
+
+ > mkdir ~/evb_rk3328
+ > cd ~/evb_rk3328
+ > git clone https://github.com/ARM-software/arm-trusted-firmware.git
+ > git clone https://github.com/rockchip-linux/rkbin
+ > git clone https://github.com/rockchip-linux/rkflashtool
+
+Compile ATF
+===============
+
+ > cd arm-trusted-firmware
+ > make realclean
+ > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3328 bl31
+
+Compile U-Boot
+==================
+
+ > cd ../u-boot
+ > make CROSS_COMPILE=aarch64-linux-gnu- evb-rk3328_defconfig all
+
+Compile rkflashtool
+=======================
+
+ > cd ../rkflashtool
+ > make
+
+Package image for miniloader
+================================
+ > cd ..
+ > cp arm-trusted-firmware/build/rk3328/release/bl31.bin rkbin/rk33
+ > ./rkbin/tools/trust_merger rkbin/tools/RK3328TRUST.ini
+ > ./rkbin/tools/loaderimage --pack --uboot u-boot/u-boot-dtb.bin uboot.img
+ > mkdir image
+ > mv trust.img ./image/
+ > mv uboot.img ./image/rk3328evb-uboot.bin
+
+Flash image
+===============
+Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
+
+ > ./rkflashtool/rkflashloader rk3328evb
+
+You should be able to get U-Boot log message in console/UART2 now.
diff --git a/board/rockchip/rk3318_box/rk3318-box.c b/board/rockchip/rk3318_box/rk3318-box.c
new file mode 100644
index 00000000..779bc646
--- /dev/null
+++ b/board/rockchip/rk3318_box/rk3318-box.c
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
diff --git a/include/configs/rk3318-box.h b/include/configs/rk3318-box.h
new file mode 100644
index 00000000..6587d30b
--- /dev/null
+++ b/include/configs/rk3318-box.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __RK3318_BOX_H
+#define __RK3318_BOX_H
+
+#include <configs/rk3328_common.h>
+
+#undef BOOT_TARGET_DEVICES
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 1) \
+ func(MMC, mmc, 3) \
+ func(USB, usb, 0) \
+ func(MMC, mmc, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dchp, na)
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ ENV_MEM_LAYOUT_SETTINGS \
+ "stdin=serial,usbkbd\0" \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "partitions=" PARTS_DEFAULT \
+ BOOTENV
+
+#endif