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Port meson sm1 emmc related patches from edge to current (#4523)

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Igor Pečovnik 2022-12-06 21:52:37 +01:00 committed by GitHub
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patch/kernel/archive/meson64-5.19/general-meson-gx-mmc-set-core-clock-phase-to-270-degres.patch → patch/kernel/archive/meson64-5.19/general-meson-gx-mmc-set-core-clock-phase-to-270-degres.patch.disabled
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109
patch/kernel/archive/meson64-5.19/general-meson-mmc-1-arm64-amlogic-mmc-meson-gx-Add-core-tx-rx-eMMC-SD-SD.patch Normal file
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@ -0,0 +1,109 @@
From 3774482f10291d3cbd6b22514f976edc8732759e Mon Sep 17 00:00:00 2001
From: Vyacheslav Bocharov <adeep@lexina.in>
Date: Mon, 7 Nov 2022 16:19:08 +0300
Subject: [PATCH 1/3] arm64: amlogic: mmc: meson-gx: Add core, tx, rx
eMMC/SD/SDIO phase clock settings from devicetree data
The mmc driver has the same phase values for all meson platforms. However,
some platforms (and even some boards) require different values. This patch
transfers the values from the set in the code to the variables in the
device-tree file.
Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>
---
drivers/mmc/host/meson-gx-mmc.c | 19 +++++++++-----
include/dt-bindings/mmc/meson-gx-mmc.h | 35 ++++++++++++++++++++++++++
2 files changed, 48 insertions(+), 6 deletions(-)
create mode 100644 include/dt-bindings/mmc/meson-gx-mmc.h
diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index fc462995cf94..4fb09cfaa60f 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -27,6 +27,7 @@
#include <linux/interrupt.h>
#include <linux/bitfield.h>
#include <linux/pinctrl/consumer.h>
+#include <dt-bindings/mmc/meson-gx-mmc.h>
#define DRIVER_NAME "meson-gx-mmc"
@@ -36,8 +37,6 @@
#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
#define CLK_TX_PHASE_MASK GENMASK(11, 10)
#define CLK_RX_PHASE_MASK GENMASK(13, 12)
-#define CLK_PHASE_0 0
-#define CLK_PHASE_180 2
#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
#define CLK_V2_ALWAYS_ON BIT(24)
@@ -424,13 +423,21 @@ static int meson_mmc_clk_init(struct meson_host *host)
const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
const char *clk_parent[1];
u32 clk_reg;
-
+ u32 phase[3]; // <core_phase, tx_phase, rx_phase>
+
+ if (!(host->dev && host->dev->of_node) || (device_property_read_u32_array(host->dev,
+ "amlogic,mmc-phase", phase, 3) < 0)) {
+ dev_dbg(host->dev, "get amlogic,mmc-phase failed, use default phase settings\n");
+ phase[0] = CLK_PHASE_180;
+ phase[1] = CLK_PHASE_0;
+ phase[2] = CLK_PHASE_0;
+ }
/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
clk_reg = CLK_ALWAYS_ON(host);
clk_reg |= CLK_DIV_MASK;
- clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
- clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
- clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
+ clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, phase[0]);
+ clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, phase[1]);
+ clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, phase[2]);
writel(clk_reg, host->regs + SD_EMMC_CLOCK);
/* get the mux parents */
diff --git a/include/dt-bindings/mmc/meson-gx-mmc.h b/include/dt-bindings/mmc/meson-gx-mmc.h
new file mode 100644
index 000000000000..cfc4a9d75b2b
--- /dev/null
+++ b/include/dt-bindings/mmc/meson-gx-mmc.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (c) 2022 Vyacheslav Bocharov
+ * Author: Vyacheslav Bocharov <adeep@lexina.in>
+ */
+
+#ifndef _DT_BINDINGS_MESON_GX_MMC_H
+#define _DT_BINDINGS_MESON_GX_MMC_H
+
+/*
+ * Cfg_rx_phase: RX clock phase
+ * bits: 9:8 R/W
+ * default: 0
+ * Recommended value: 0
+ *
+ * Cfg_tx_phase: TX clock phase
+ * bits: 9:8 R/W
+ * default: 0
+ * Recommended value: 2
+ *
+ * Cfg_co_phase: Core clock phase
+ * bits: 9:8 R/W
+ * default: 0
+ * Recommended value: 2
+ *
+ * values: 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.
+ */
+
+#define CLK_PHASE_0 0
+#define CLK_PHASE_90 1
+#define CLK_PHASE_180 2
+#define CLK_PHASE_270 3
+
+
+#endif
--
2.30.2

44
patch/kernel/archive/meson64-5.19/general-meson-mmc-2-arm64-amlogic-dts-meson-update-meson-axg-device-tree.patch Normal file
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@ -0,0 +1,44 @@
From facd1f172280739e8342fa6418755f62c76a01ce Mon Sep 17 00:00:00 2001
From: Vyacheslav Bocharov <adeep@lexina.in>
Date: Mon, 7 Nov 2022 16:19:08 +0300
Subject: [PATCH 2/3] arm64: amlogic: dts: meson: update meson-axg device-tree
for new core, tx, rx phase clock settings.
Use phase 270 for core MMC clock on axg meson boards.
Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 04f797b5a012..0af4784d84c7 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -13,6 +13,7 @@
#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
#include <dt-bindings/power/meson-axg-power.h>
+#include <dt-bindings/mmc/meson-gx-mmc.h>
/ {
compatible = "amlogic,meson-axg";
@@ -1891,6 +1892,7 @@ sd_emmc_b: sd@5000 {
<&clkc CLKID_SD_EMMC_B_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
+ amlogic,mmc-phase = <CLK_PHASE_270 CLK_PHASE_0 CLK_PHASE_0>;
resets = <&reset RESET_SD_EMMC_B>;
};
@@ -1904,6 +1906,7 @@ sd_emmc_c: mmc@7000 {
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_C>;
+ amlogic,mmc-phase = <CLK_PHASE_270 CLK_PHASE_0 CLK_PHASE_0>;
};
usb2_phy1: phy@9020 {
--
2.30.2

45
patch/kernel/archive/meson64-5.19/general-meson-mmc-3-arm64-dts-docs-Update-mmc-meson-gx-documentation-for.patch Normal file
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@ -0,0 +1,45 @@
From 74f23d8b8f7e1284689597961dde9a7d25774d2e Mon Sep 17 00:00:00 2001
From: Vyacheslav Bocharov <adeep@lexina.in>
Date: Thu, 10 Nov 2022 14:52:47 +0300
Subject: [PATCH 3/3] arm64: dts: docs: Update mmc meson-gx documentation for
new config option amlogic,mmc-phase
- amlogic,mmc-phases: 3-element array of clock phases for core, tx, rx
clock with values:
0: CLK_PHASE_0 - 0 phase
1: CLK_PHASE_90 - 90 phase
2: CLK_PHASE_180 - 180 phase
3: CLK_PHASE_270 - 270 phase
By default driver use <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0> value.
Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>
---
Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
index ccc5358db131..98c89c5b3455 100644
--- a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
+++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
@@ -25,6 +25,12 @@ Required properties:
Optional properties:
- amlogic,dram-access-quirk: set when controller's internal DMA engine cannot access the
DRAM memory, like on the G12A dedicated SDIO controller.
+- amlogic,mmc-phases: 3-element array of clock phases for core, tx, rx clock with values:
+ 0: CLK_PHASE_0 - 0 phase
+ 1: CLK_PHASE_90 - 90 phase
+ 2: CLK_PHASE_180 - 180 phase
+ 3: CLK_PHASE_270 - 270 phase
+ By default driver use <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0> value.
Example:
@@ -36,4 +42,5 @@ Example:
clock-names = "core", "clkin0", "clkin1";
pinctrl-0 = <&emmc_pins>;
resets = <&reset RESET_SD_EMMC_A>;
+ amlogic,mmc-phases = <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0>;
};
--
2.30.2