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Add Orange Pi 3 LTS Support (#3628)

Browse Source 
* Orange Pi 3 LTS
* Enable build targets

Co-authored-by: Igor Pecovnik <igor.pecovnik@gmail.com>
This commit is contained in:
Ukhellfire 2022-04-12 19:13:37 +01:00 committed by GitHub
parent c031d0fec9
commit 2a8e1ecac1
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
38 changed files with 439335 additions and 4 deletions
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8
config/boards/orangepi3-lts.conf Executable file
View File

@ -0,0 +1,8 @@
# Allwinner H6 quad core 2GB RAM SoC GBE USB3
BOARD_NAME="Orange Pi 3 LTS"
BOARDFAMILY="sun50iw6"
BOOTCONFIG="orangepi_3_lts_defconfig"
KERNEL_TARGET="current,edge"
MODULES="sprdbt_tty sprdwl_ng"
MODULES_BLACKLIST_LEGACY="bcmdhd"
ATFBRANCH="tag:v2.2"

26
config/kernel/linux-sunxi64-current.config
View File

@ -2186,6 +2186,7 @@ CONFIG_EEPROM_EE1004=m
# CONFIG_MISC_RTSX_USB is not set
CONFIG_UACCE=m
# CONFIG_PVPANIC is not set
CONFIG_SUNXI_ADDR_MGT=m
# end of Misc devices
#
@ -2748,6 +2749,26 @@ CONFIG_USB_NET_RNDIS_WLAN=m
CONFIG_VIRT_WIFI=m
# CONFIG_WAN is not set
CONFIG_IEEE802154_DRIVERS=m
CONFIG_SPARD_WLAN_SUPPORT=y
#
# UNISOC WCN Device Drivers(for new chip...)
#
# CONFIG_SC23XX is not set
# CONFIG_WCN_BSP_DRIVER_BUILDIN is not set
# CONFIG_RK_WIFI_DEVICE_UWE5621 is not set
# CONFIG_RK_WIFI_DEVICE_UWE5622 is not set
CONFIG_AW_WIFI_DEVICE_UWE5622=y
CONFIG_AW_BIND_VERIFY=y
# end of UNISOC WCN Device Drivers(for new chip...)
CONFIG_WLAN_UWE5622=m
CONFIG_SPRDWL_NG=m
CONFIG_UNISOC_WIFI_PS=y
CONFIG_TTY_OVERY_SDIO=m
# CONFIG_MAC80211_HWSIM is not set
CONFIG_USB_NET_RNDIS_WLAN=m
CONFIG_VIRT_WIFI=m
#
# Wireless WAN
@ -3803,7 +3824,7 @@ CONFIG_MFD_SUN4I_GPADC=y
# CONFIG_MFD_BCM590XX is not set
CONFIG_MFD_BD9571MWV=m
CONFIG_MFD_AC100=y
CONFIG_MFD_AC200=y
CONFIG_MFD_AC200=m
CONFIG_MFD_AXP20X=y
CONFIG_MFD_AXP20X_I2C=y
CONFIG_MFD_AXP20X_RSB=y
@ -5147,6 +5168,7 @@ CONFIG_SND_SOC_NAU8315=m
CONFIG_SND_SOC_NAU8822=m
# CONFIG_SND_SOC_NAU8824 is not set
# CONFIG_SND_SOC_TPA6130A2 is not set
CONFIG_SND_SOC_ACX00=y
CONFIG_SND_SOC_LPASS_WSA_MACRO=m
CONFIG_SND_SOC_LPASS_VA_MACRO=m
CONFIG_SND_SOC_LPASS_RX_MACRO=m
@ -6136,7 +6158,7 @@ CONFIG_COMMON_CLK_SI544=m
# CONFIG_COMMON_CLK_S2MPS11 is not set
CONFIG_COMMON_CLK_AXI_CLKGEN=m
# CONFIG_COMMON_CLK_XGENE is not set
# CONFIG_COMMON_CLK_PWM is not set
CONFIG_COMMON_CLK_PWM=y
# CONFIG_COMMON_CLK_VC5 is not set
CONFIG_COMMON_CLK_BD718XX=m
# CONFIG_COMMON_CLK_FIXED_MMIO is not set

26
config/kernel/linux-sunxi64-edge.config
View File

@ -2198,6 +2198,7 @@ CONFIG_EEPROM_EE1004=m
# CONFIG_MISC_RTSX_USB is not set
CONFIG_UACCE=m
# CONFIG_PVPANIC is not set
CONFIG_SUNXI_ADDR_MGT=m
# end of Misc devices
#
@ -2769,6 +2770,26 @@ CONFIG_USB_NET_RNDIS_WLAN=m
CONFIG_VIRT_WIFI=m
# CONFIG_WAN is not set
CONFIG_IEEE802154_DRIVERS=m
CONFIG_SPARD_WLAN_SUPPORT=y
#
# UNISOC WCN Device Drivers(for new chip...)
#
# CONFIG_SC23XX is not set
# CONFIG_WCN_BSP_DRIVER_BUILDIN is not set
# CONFIG_RK_WIFI_DEVICE_UWE5621 is not set
# CONFIG_RK_WIFI_DEVICE_UWE5622 is not set
CONFIG_AW_WIFI_DEVICE_UWE5622=y
CONFIG_AW_BIND_VERIFY=y
# end of UNISOC WCN Device Drivers(for new chip...)
CONFIG_WLAN_UWE5622=m
CONFIG_SPRDWL_NG=m
CONFIG_UNISOC_WIFI_PS=y
CONFIG_TTY_OVERY_SDIO=m
# CONFIG_MAC80211_HWSIM is not set
CONFIG_USB_NET_RNDIS_WLAN=m
CONFIG_VIRT_WIFI=m
#
# Wireless WAN
@ -3829,7 +3850,7 @@ CONFIG_MFD_SUN4I_GPADC=y
# CONFIG_MFD_BCM590XX is not set
CONFIG_MFD_BD9571MWV=m
CONFIG_MFD_AC100=y
CONFIG_MFD_AC200=y
CONFIG_MFD_AC200=m
CONFIG_MFD_AXP20X=y
CONFIG_MFD_AXP20X_I2C=y
CONFIG_MFD_AXP20X_RSB=y
@ -5183,6 +5204,7 @@ CONFIG_SND_SOC_NAU8821=m
CONFIG_SND_SOC_NAU8822=m
# CONFIG_SND_SOC_NAU8824 is not set
# CONFIG_SND_SOC_TPA6130A2 is not set
CONFIG_SND_SOC_ACX00=y
CONFIG_SND_SOC_LPASS_WSA_MACRO=m
CONFIG_SND_SOC_LPASS_VA_MACRO=m
CONFIG_SND_SOC_LPASS_RX_MACRO=m
@ -6177,7 +6199,7 @@ CONFIG_COMMON_CLK_SI544=m
# CONFIG_COMMON_CLK_S2MPS11 is not set
CONFIG_COMMON_CLK_AXI_CLKGEN=m
# CONFIG_COMMON_CLK_XGENE is not set
# CONFIG_COMMON_CLK_PWM is not set
CONFIG_COMMON_CLK_PWM=y
# CONFIG_COMMON_CLK_VC5 is not set
CONFIG_COMMON_CLK_BD718XX=m
# CONFIG_COMMON_CLK_FIXED_MMIO is not set

32
config/sources/families/sun50iw6.conf
View File

@ -5,3 +5,35 @@ OVERLAY_PREFIX='sun50i-h6'
[[ -z $CPUMAX ]] && CPUMAX=1810000
GOVERNOR=ondemand
ASOUND_STATE='asound.state.sun50iw2-dev'
case $BRANCH in
current)
if [[ ${BOARD} == orangepi3-lts ]]; then
ASOUND_STATE='asound.state.sun50iw6-current'
fi
;;
edge)
if [[ ${BOARD} == orangepi3-lts ]]; then
ASOUND_STATE='asound.state.sun50iw6-current'
fi
;;
esac
family_tweaks_s()
{
if [[ $BUILD_DESKTOP == yes && $BOARD == orangepi3-lts ]]; then
sed -i "s/auto-profiles = yes/auto-profiles = no/" ${SDCARD}/usr/share/pulseaudio/alsa-mixer/profile-sets/default.conf
echo "load-module module-alsa-sink device=hw:0,0 sink_name=AudioCodec-Playback sink_properties=\"device.description='Audio Codec'\"" >> ${SDCARD}/etc/pulse/default.pa
echo "load-module module-alsa-sink device=hw:1,0 sink_name=HDMI-Playback sink_properties=\"device.description='HDMI Audio'\"" >> ${SDCARD}/etc/pulse/default.pa
fi
}

4
config/targets-cli-beta.conf
View File

@ -50,6 +50,10 @@ orangepi-r1plus edge jammy cli
orangepi3 edge jammy cli beta yes
# Orangepi 3 LTS
orangepi3-lts edge jammy cli beta yes
# Orangepi 4
orangepi4 edge jammy cli beta yes

7
config/targets.conf
View File

@ -257,6 +257,13 @@ orangepi3 current focal desktop s
orangepi3 edge jammy cli stable yes
# orangepi 3 LTS
orangepi3-lts current bullseye cli stable adv
orangepi3-lts current focal cli stable yes
orangepi3-lts current focal desktop stable adv xfce config_base 3dsupport,browsers,chat,desktop_tools,editors,email,internet,multimedia,office,programming,remote_desktop
orangepi3-lts edge jammy cli stable yes
# Orangepi 4
orangepi4 current focal cli stable yes
orangepi4 current bullseye cli stable adv

566
packages/blobs/asound.state/asound.state.sun50iw6-current Normal file
View File

@ -0,0 +1,566 @@
state.allwinnerac200c {
control.1 {
iface MIXER
name 'I2S Mixer ADC Volume'
value.0 1
value.1 1
comment {
access 'read write'
type INTEGER
count 2
range '0 - 1'
dbmin -9999999
dbmax 0
dbvalue.0 0
dbvalue.1 0
}
}
control.2 {
iface MIXER
name 'I2S Mixer DAC Volume'
value.0 1
value.1 1
comment {
access 'read write'
type INTEGER
count 2
range '0 - 1'
dbmin -9999999
dbmax 0
dbvalue.0 0
dbvalue.1 0
}
}
control.3 {
iface MIXER
name 'DAC Mixer ADC Volume'
value.0 1
value.1 1
comment {
access 'read write'
type INTEGER
count 2
range '0 - 1'
dbmin -9999999
dbmax 0
dbvalue.0 0
dbvalue.1 0
}
}
control.4 {
iface MIXER
name 'DAC Mxier DAC Volume'
value.0 1
value.1 1
comment {
access 'read write'
type INTEGER
count 2
range '0 - 1'
dbmin -9999999
dbmax 0
dbvalue.0 0
dbvalue.1 0
}
}
control.5 {
iface MIXER
name 'Line Out Mixer Volume'
value 7
comment {
access 'read write'
type INTEGER
count 1
range '0 - 7'
dbmin -450
dbmax 600
dbvalue.0 600
}
}
control.6 {
iface MIXER
name 'MIC Out Mixer Volume'
value.0 7
value.1 7
comment {
access 'read write'
type INTEGER
count 2
range '0 - 7'
dbmin -450
dbmax 600
dbvalue.0 600
dbvalue.1 600
}
}
control.7 {
iface MIXER
name 'ADC Input Volume'
value 7
comment {
access 'read write'
type INTEGER
count 1
range '0 - 7'
dbmin -450
dbmax 600
dbvalue.0 600
}
}
control.8 {
iface MIXER
name 'Master Volume'
value 30
comment {
access 'read write'
type INTEGER
count 1
range '0 - 31'
dbmin -9999999
dbmax -150
dbvalue.0 -300
}
}
control.9 {
iface MIXER
name 'MIC1 Boost Volume'
value 7
comment {
access 'read write'
type INTEGER
count 1
range '0 - 7'
dbmin 0
dbmax 4200
dbvalue.0 4200
}
}
control.10 {
iface MIXER
name 'MIC2 Boost Volume'
value 7
comment {
access 'read write'
type INTEGER
count 1
range '0 - 7'
dbmin 0
dbmax 4200
dbvalue.0 4200
}
}
control.11 {
iface MIXER
name 'Left Output Mixer MIC1 Switch'
value false
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.12 {
iface MIXER
name 'Left Output Mixer MIC2 Switch'
value false
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.13 {
iface MIXER
name 'Left Output Mixer PhonePN Switch'
value false
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.14 {
iface MIXER
name 'Left Output Mixer PhoneN Switch'
value false
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.15 {
iface MIXER
name 'Left Output Mixer LINEINL Switch'
value false
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.16 {
iface MIXER
name 'Left Output Mixer DACL Switch'
value true
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.17 {
iface MIXER
name 'Left Output Mixer DACR Switch'
value false
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.18 {
iface MIXER
name 'Right Output Mixer MIC1 Switch'
value false
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.19 {
iface MIXER
name 'Right Output Mixer MIC2 Switch'
value false
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.20 {
iface MIXER
name 'Right Output Mixer PhonePN Switch'
value false
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.21 {
iface MIXER
name 'Right Output Mixer PhoneP Switch'
value false
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.22 {
iface MIXER
name 'Right Output Mixer LINEINR Switch'
value false
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.23 {
iface MIXER
name 'Right Output Mixer DACR Switch'
value true
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.24 {
iface MIXER
name 'Right Output Mixer DACL Switch'
value false
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.25 {
iface MIXER
name 'Left Input Mixer MIC1 Switch'
value true
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.26 {
iface MIXER
name 'Left Input Mixer MIC2 Switch'
value false
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.27 {
iface MIXER
name 'Left Input Mixer PhonePN Switch'
value false
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.28 {
iface MIXER
name 'Left Input Mixer PhoneN Switch'
value false
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.29 {
iface MIXER
name 'Left Input Mixer LINEINL Switch'
value false
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.30 {
iface MIXER
name 'Left Input Mixer OMixerL Switch'
value false
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.31 {
iface MIXER
name 'Left Input Mixer OMixerR Switch'
value false
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.32 {
iface MIXER
name 'Right Input Mixer MIC1 Switch'
value true
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.33 {
iface MIXER
name 'Right Input Mixer MIC2 Switch'
value false
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.34 {
iface MIXER
name 'Right Input Mixer PhonePN Switch'
value false
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.35 {
iface MIXER
name 'Right Input Mixer PhoneP Switch'
value false
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.36 {
iface MIXER
name 'Right Input Mixer LINEINR Switch'
value false
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.37 {
iface MIXER
name 'Right Input Mixer OMixerR Switch'
value false
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.38 {
iface MIXER
name 'Right Input Mixer OMixerL Switch'
value false
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.39 {
iface MIXER
name 'Left DAC Mixer I2SDACL Switch'
value true
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.40 {
iface MIXER
name 'Left DAC Mixer ADCL Switch'
value false
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.41 {
iface MIXER
name 'Right DAC Mixer I2SDACR Switch'
value true
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.42 {
iface MIXER
name 'Right DAC Mixer ADCR Switch'
value false
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.43 {
iface MIXER
name 'Left I2S Mixer I2SDACL Switch'
value false
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.44 {
iface MIXER
name 'Left I2S Mixer ADCL Switch'
value true
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.45 {
iface MIXER
name 'Right I2S Mixer I2SDACR Switch'
value false
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.46 {
iface MIXER
name 'Right I2S Mixer ADCR Switch'
value true
comment {
access 'read write'
type BOOLEAN
count 1
}
}
control.47 {
iface MIXER
name 'Left LINEOUT Mux'
value 'Left OMixer'
comment {
access 'read write'
type ENUMERATED
count 1
item.0 'Left OMixer'
item.1 'LR OMixer'
}
}
control.48 {
iface MIXER
name 'Right LINEOUT Mux'
value 'Right OMixer'
comment {
access 'read write'
type ENUMERATED
count 1
item.0 'Right OMixer'
item.1 'LR OMixer'
}
}
}
state.sun50ih6hdmi {
control.1 {
iface PCM
name 'Playback Channel Map'
value.0 0
value.1 0
value.2 0
value.3 0
value.4 0
value.5 0
value.6 0
value.7 0
comment {
access read
type INTEGER
count 8
range '0 - 36'
}
}
control.2 {
iface PCM
name ELD
value '100008006c1000010000000000000000410c1000323450464c333534332f5433090701000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000'
comment {
access 'read volatile'
type BYTES
count 128
}
}
}

70
patch/kernel/archive/sunxi-5.15/0001-move-sun50i-h6-pwm-settings-to-its-own-overlay.patch Normal file
View File

@ -0,0 +1,70 @@
From 444ae2245cdccb154ca7d21ba91d9e8e22389dd1 Mon Sep 17 00:00:00 2001
From: afaulkner420 <afaulkner420@gmail.com>
Date: Fri, 25 Mar 2022 19:23:56 +0000
Subject: [PATCH 01/11] Move sun50i-h6-pwm settings to its own overlay
---
.../allwinner/overlay/sun50i-h6-fixup.scr-cmd | 14 -----------
.../dts/allwinner/overlay/sun50i-h6-pwm.dts | 25 +++++++++++++++++++
2 files changed, 25 insertions(+), 14 deletions(-)
create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-pwm.dts
diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd
index d8e79ba45..f757db7aa 100644
--- a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd
+++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd
@@ -54,20 +54,6 @@ if test "${param_pps_falling_edge}" = "1"; then
fdt set /pps@0 assert-falling-edge
fi
-for f in ${overlays}; do
- if test "${f}" = "pwm"; then
- setenv bootargs_new ""
- for arg in ${bootargs}; do
- if test "${arg}" = "console=ttyS0,115200"; then
- echo "Warning: Disabling ttyS0 console due to enabled PWM overlay"
- else
- setenv bootargs_new "${bootargs_new} ${arg}"
- fi
- done
- setenv bootargs "${bootargs_new}"
- fi
-done
-
if test -n "${param_w1_pin}"; then
setenv tmp_bank "${param_w1_pin}"
setenv tmp_pin "${param_w1_pin}"
diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-pwm.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-pwm.dts
new file mode 100644
index 000000000..a8aa74ed1
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-pwm.dts
@@ -0,0 +1,25 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+ compatible = "allwinner,sun50i-h6-pwm";
+
+ fragment@0 {
+ target = <&pio>;
+ __overlay__ {
+ pwm_pin: pwm-pin {
+ pins = "PD22";
+ function = "pwm";
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&pwm>;
+ __overlay__ {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_pin>;
+ status = "okay";
+ };
+ };
+};
--
2.25.1

24
patch/kernel/archive/sunxi-5.15/0002-compile-the-pwm-overlay.patch Normal file
View File

@ -0,0 +1,24 @@
From 51112a4620dea5d3c77ca09572a249f5f877a1ce Mon Sep 17 00:00:00 2001
From: afaulkner420 <afaulkner420@gmail.com>
Date: Fri, 25 Mar 2022 19:26:16 +0000
Subject: [PATCH 02/11] Compile the pwm overlay
---
arch/arm64/boot/dts/allwinner/overlay/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile
index 87f5addec..7cabe8f42 100644
--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile
+++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile
@@ -38,6 +38,7 @@ dtbo-$(CONFIG_ARCH_SUNXI) += \
sun50i-h6-i2c0.dtbo \
sun50i-h6-i2c1.dtbo \
sun50i-h6-i2c2.dtbo \
+ sun50i-h6-pwm.dtbo \
sun50i-h6-ruart.dtbo \
sun50i-h6-spi-add-cs1.dtbo \
sun50i-h6-spi-jedec-nor.dtbo \
--
2.25.1

1552
patch/kernel/archive/sunxi-5.15/0003-add-dump_reg-and-sunxi-sysinfo-drivers.patch Normal file
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File diff suppressed because it is too large Load Diff

613
patch/kernel/archive/sunxi-5.15/0004-add-sunxi-addr-driver-used-to-fix-uwe5622-bluetooth-.patch Normal file
View File

@ -0,0 +1,613 @@
From 29cfa9437eaa2ff862ab0f06852383b181b60743 Mon Sep 17 00:00:00 2001
From: afaulkner420 <afaulkner420@gmail.com>
Date: Fri, 25 Mar 2022 20:18:18 +0000
Subject: [PATCH 04/11] Add sunxi-addr driver - Used to fix uwe5622 bluetooth
MAC addresses
---
drivers/misc/Kconfig | 1 +
drivers/misc/Makefile | 1 +
drivers/misc/sunxi-addr/Kconfig | 6 +
drivers/misc/sunxi-addr/Makefile | 5 +
drivers/misc/sunxi-addr/sha256.c | 178 +++++++++++++
drivers/misc/sunxi-addr/sunxi-addr.c | 358 +++++++++++++++++++++++++++
6 files changed, 549 insertions(+)
create mode 100755 drivers/misc/sunxi-addr/Kconfig
create mode 100755 drivers/misc/sunxi-addr/Makefile
create mode 100755 drivers/misc/sunxi-addr/sha256.c
create mode 100755 drivers/misc/sunxi-addr/sunxi-addr.c
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 24cb809ae..52843042f 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -494,4 +494,5 @@ source "drivers/misc/cardreader/Kconfig"
source "drivers/misc/habanalabs/Kconfig"
source "drivers/misc/uacce/Kconfig"
source "drivers/misc/pvpanic/Kconfig"
+source "drivers/misc/sunxi-addr/Kconfig"
endmenu
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index f3eaa577a..0f9280509 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -60,3 +60,4 @@ obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o
obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o
obj-$(CONFIG_HI6421V600_IRQ) += hi6421v600-irq.o
obj-$(CONFIG_MODEM_POWER) += modem-power.o
+obj-$(CONFIG_SUNXI_ADDR_MGT) += sunxi-addr/
\ No newline at end of file
diff --git a/drivers/misc/sunxi-addr/Kconfig b/drivers/misc/sunxi-addr/Kconfig
new file mode 100755
index 000000000..801dd2c02
--- /dev/null
+++ b/drivers/misc/sunxi-addr/Kconfig
@@ -0,0 +1,6 @@
+config SUNXI_ADDR_MGT
+ tristate "Allwinner Network MAC Addess Manager"
+ depends on BT || ETHERNET || WLAN
+ depends on NVMEM_SUNXI_SID
+ help
+ allwinner network mac address management
diff --git a/drivers/misc/sunxi-addr/Makefile b/drivers/misc/sunxi-addr/Makefile
new file mode 100755
index 000000000..f01fd4783
--- /dev/null
+++ b/drivers/misc/sunxi-addr/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for wifi mac addr manager drivers
+#
+sunxi_addr-objs := sunxi-addr.o sha256.o
+obj-$(CONFIG_SUNXI_ADDR_MGT) += sunxi_addr.o
diff --git a/drivers/misc/sunxi-addr/sha256.c b/drivers/misc/sunxi-addr/sha256.c
new file mode 100755
index 000000000..78825810c
--- /dev/null
+++ b/drivers/misc/sunxi-addr/sha256.c
@@ -0,0 +1,178 @@
+/*
+ * Local implement of sha256.
+ *
+ * Copyright (C) 2013 Allwinner.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/string.h>
+
+/****************************** MACROS ******************************/
+#define ROTRIGHT(a, b) (((a) >> (b)) | ((a) << (32 - (b))))
+#define CH(x, y, z) (((x) & (y)) ^ (~(x) & (z)))
+#define MAJ(x, y, z) (((x) & (y)) ^ ((x) & (z)) ^ ((y) & (z)))
+#define EP0(x) (ROTRIGHT(x, 2) ^ ROTRIGHT(x, 13) ^ ROTRIGHT(x, 22))
+#define EP1(x) (ROTRIGHT(x, 6) ^ ROTRIGHT(x, 11) ^ ROTRIGHT(x, 25))
+#define SIG0(x) (ROTRIGHT(x, 7) ^ ROTRIGHT(x, 18) ^ ((x) >> 3))
+#define SIG1(x) (ROTRIGHT(x, 17) ^ ROTRIGHT(x, 19) ^ ((x) >> 10))
+
+/**************************** VARIABLES *****************************/
+static const uint32_t k[64] = {
+ 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5,
+ 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5,
+ 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3,
+ 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174,
+ 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc,
+ 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da,
+ 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7,
+ 0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967,
+ 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13,
+ 0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85,
+ 0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3,
+ 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070,
+ 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5,
+ 0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3,
+ 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208,
+ 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2
+};
+
+struct sha256_ctx {
+ uint8_t data[64]; /* current 512-bit chunk of message data, just like a buffer */
+ uint32_t datalen; /* sign the data length of current chunk */
+ uint64_t bitlen; /* the bit length of the total message */
+ uint32_t state[8]; /* store the middle state of hash abstract */
+};
+
+/*********************** FUNCTION DEFINITIONS ***********************/
+static void sha256_transform(struct sha256_ctx *ctx, const uint8_t *data)
+{
+ uint32_t a, b, c, d, e, f, g, h, i, j, t1, t2, m[64];
+
+ /* initialization */
+ for (i = 0, j = 0; i < 16; ++i, j += 4)
+ m[i] = (data[j] << 24) | (data[j + 1] << 16) |
+ (data[j + 2] << 8) | (data[j + 3]);
+ for ( ; i < 64; ++i)
+ m[i] = SIG1(m[i - 2]) + m[i - 7] + SIG0(m[i - 15]) + m[i - 16];
+
+ a = ctx->state[0];
+ b = ctx->state[1];
+ c = ctx->state[2];
+ d = ctx->state[3];
+ e = ctx->state[4];
+ f = ctx->state[5];
+ g = ctx->state[6];
+ h = ctx->state[7];
+
+ for (i = 0; i < 64; ++i) {
+ t1 = h + EP1(e) + CH(e, f, g) + k[i] + m[i];
+ t2 = EP0(a) + MAJ(a, b, c);
+ h = g;
+ g = f;
+ f = e;
+ e = d + t1;
+ d = c;
+ c = b;
+ b = a;
+ a = t1 + t2;
+ }
+
+ ctx->state[0] += a;
+ ctx->state[1] += b;
+ ctx->state[2] += c;
+ ctx->state[3] += d;
+ ctx->state[4] += e;
+ ctx->state[5] += f;
+ ctx->state[6] += g;
+ ctx->state[7] += h;
+}
+
+static void sha256_init(struct sha256_ctx *ctx)
+{
+ ctx->datalen = 0;
+ ctx->bitlen = 0;
+ ctx->state[0] = 0x6a09e667;
+ ctx->state[1] = 0xbb67ae85;
+ ctx->state[2] = 0x3c6ef372;
+ ctx->state[3] = 0xa54ff53a;
+ ctx->state[4] = 0x510e527f;
+ ctx->state[5] = 0x9b05688c;
+ ctx->state[6] = 0x1f83d9ab;
+ ctx->state[7] = 0x5be0cd19;
+}
+
+static void sha256_update(struct sha256_ctx *ctx, const uint8_t *data, size_t len)
+{
+ uint32_t i;
+
+ for (i = 0; i < len; ++i) {
+ ctx->data[ctx->datalen] = data[i];
+ ctx->datalen++;
+ if (ctx->datalen == 64) {
+ /* 64 byte = 512 bit means the buffer ctx->data has
+ * fully stored one chunk of message,
+ * so do the sha256 hash map for the current chunk.
+ */
+ sha256_transform(ctx, ctx->data);
+ ctx->bitlen += 512;
+ ctx->datalen = 0;
+ }
+ }
+}
+
+static void sha256_final(struct sha256_ctx *ctx, uint8_t *hash)
+{
+ uint32_t i;
+
+ i = ctx->datalen;
+
+ /* Pad whatever data is left in the buffer. */
+ if (ctx->datalen < 56) {
+ ctx->data[i++] = 0x80; /* pad 10000000 = 0x80 */
+ while (i < 56)
+ ctx->data[i++] = 0x00;
+ } else {
+ ctx->data[i++] = 0x80;
+ while (i < 64)
+ ctx->data[i++] = 0x00;
+ sha256_transform(ctx, ctx->data);
+ memset(ctx->data, 0, 56);
+ }
+
+ /* Append to the padding the total message's length in bits and transform. */
+ ctx->bitlen += ctx->datalen * 8;
+ ctx->data[63] = ctx->bitlen;
+ ctx->data[62] = ctx->bitlen >> 8;
+ ctx->data[61] = ctx->bitlen >> 16;
+ ctx->data[60] = ctx->bitlen >> 24;
+ ctx->data[59] = ctx->bitlen >> 32;
+ ctx->data[58] = ctx->bitlen >> 40;
+ ctx->data[57] = ctx->bitlen >> 48;
+ ctx->data[56] = ctx->bitlen >> 56;
+ sha256_transform(ctx, ctx->data);
+
+ /* copying the final state to the output hash(use big endian). */
+ for (i = 0; i < 4; ++i) {
+ hash[i] = (ctx->state[0] >> (24 - i * 8)) & 0x000000ff;
+ hash[i + 4] = (ctx->state[1] >> (24 - i * 8)) & 0x000000ff;
+ hash[i + 8] = (ctx->state[2] >> (24 - i * 8)) & 0x000000ff;
+ hash[i + 12] = (ctx->state[3] >> (24 - i * 8)) & 0x000000ff;
+ hash[i + 16] = (ctx->state[4] >> (24 - i * 8)) & 0x000000ff;
+ hash[i + 20] = (ctx->state[5] >> (24 - i * 8)) & 0x000000ff;
+ hash[i + 24] = (ctx->state[6] >> (24 - i * 8)) & 0x000000ff;
+ hash[i + 28] = (ctx->state[7] >> (24 - i * 8)) & 0x000000ff;
+ }
+}
+
+int hmac_sha256(const uint8_t *plaintext, ssize_t psize, uint8_t *output)
+{
+ struct sha256_ctx ctx;
+
+ sha256_init(&ctx);
+ sha256_update(&ctx, plaintext, psize);
+ sha256_final(&ctx, output);
+ return 0;
+}
diff --git a/drivers/misc/sunxi-addr/sunxi-addr.c b/drivers/misc/sunxi-addr/sunxi-addr.c
new file mode 100755
index 000000000..a812e4e82
--- /dev/null
+++ b/drivers/misc/sunxi-addr/sunxi-addr.c
@@ -0,0 +1,358 @@
+/*
+ * The driver of SUNXI NET MAC ADDR Manager.
+ *
+ * Copyright (C) 2013 Allwinner.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#define DEBUG
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/miscdevice.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#define ADDR_MGT_DBG(fmt, arg...) printk(KERN_DEBUG "[ADDR_MGT] %s: " fmt "\n",\
+ __func__, ## arg)
+#define ADDR_MGT_ERR(fmt, arg...) printk(KERN_ERR "[ADDR_MGT] %s: " fmt "\n",\
+ __func__, ## arg)
+
+#define MODULE_CUR_VERSION "v1.0.9"
+
+#define MATCH_STR_LEN 20
+#define ADDR_VAL_LEN 6
+#define ADDR_STR_LEN 18
+#define ID_LEN 16
+#define HASH_LEN 32
+
+#define TYPE_ANY 0
+#define TYPE_BURN 1
+#define TYPE_IDGEN 2
+#define TYPE_USER 3
+#define TYPE_RAND 4
+
+#define ADDR_FMT_STR 0
+#define ADDR_FMT_VAL 1
+
+#define IS_TYPE_INVALID(x) ((x < TYPE_ANY) || (x > TYPE_RAND))
+
+#define ADDR_CLASS_ATTR_ADD(name) \
+static ssize_t addr_##name##_show(struct class *class, \
+ struct class_attribute *attr, char *buffer) \
+{ \
+ char addr[ADDR_STR_LEN]; \
+ if (IS_TYPE_INVALID(get_addr_by_name(ADDR_FMT_STR, addr, #name))) \
+ return 0; \
+ return sprintf(buffer, "%.17s\n", addr); \
+} \
+static ssize_t addr_##name##_store(struct class *class, \
+ struct class_attribute *attr, \
+ const char *buffer, size_t count) \
+{ \
+ if (count != ADDR_STR_LEN) { \
+ ADDR_MGT_ERR("Length wrong."); \
+ return -EINVAL; \
+ } \
+ set_addr_by_name(TYPE_USER, ADDR_FMT_STR, buffer, #name); \
+ return count; \
+} \
+static CLASS_ATTR_RW(addr_##name);
+
+struct addr_mgt_info {
+ unsigned int type_def;
+ unsigned int type_cur;
+ unsigned int flag;
+ char *addr;
+ char *name;
+};
+
+static struct addr_mgt_info info[] = {
+ {TYPE_ANY, TYPE_ANY, 1, NULL, "wifi"},
+ {TYPE_ANY, TYPE_ANY, 0, NULL, "bt" },
+ {TYPE_ANY, TYPE_ANY, 1, NULL, "eth" },
+};
+
+extern int hmac_sha256(const uint8_t *plaintext, ssize_t psize, uint8_t *output);
+extern int sunxi_get_soc_chipid(unsigned char *chipid);
+
+static int addr_parse(int fmt, const char *addr, int check)
+{
+ char val_buf[ADDR_VAL_LEN];
+ char cmp_buf[ADDR_VAL_LEN];
+ int ret = ADDR_VAL_LEN;
+
+ if (fmt == ADDR_FMT_STR)
+ ret = sscanf(addr, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
+ &val_buf[0], &val_buf[1], &val_buf[2],
+ &val_buf[3], &val_buf[4], &val_buf[5]);
+ else
+ memcpy(val_buf, addr, ADDR_VAL_LEN);
+
+ if (ret != ADDR_VAL_LEN)
+ return -1;
+
+ if (check && (val_buf[0] & 0x3))
+ return -1;
+
+ memset(cmp_buf, 0x00, ADDR_VAL_LEN);
+ if (memcmp(val_buf, cmp_buf, ADDR_VAL_LEN) == 0)
+ return -1;
+
+ memset(cmp_buf, 0xFF, ADDR_VAL_LEN);
+ if (memcmp(val_buf, cmp_buf, ADDR_VAL_LEN) == 0)
+ return -1;
+
+ return 0;
+}
+
+static struct addr_mgt_info *addr_find_by_name(char *name)
+{
+ int i = 0;
+ for (i = 0; i < ARRAY_SIZE(info); i++) {
+ if (strcmp(info[i].name, name) == 0)
+ return &info[i];
+ }
+ return NULL;
+}
+
+static int get_addr_by_name(int fmt, char *addr, char *name)
+{
+ struct addr_mgt_info *t;
+
+ t = addr_find_by_name(name);
+ if (t == NULL) {
+ ADDR_MGT_ERR("can't find addr named: %s", name);
+ return -1;
+ }
+
+ if (IS_TYPE_INVALID(t->type_cur)) {
+ ADDR_MGT_ERR("addr type invalid");
+ return -1;
+ }
+
+ if (addr_parse(ADDR_FMT_VAL, t->addr, t->flag)) {
+ ADDR_MGT_ERR("addr parse fail(%s)", t->addr);
+ return -1;
+ }
+
+ if (fmt == ADDR_FMT_STR)
+ sprintf(addr, "%02X:%02X:%02X:%02X:%02X:%02X",
+ t->addr[0], t->addr[1], t->addr[2],
+ t->addr[3], t->addr[4], t->addr[5]);
+ else
+ memcpy(addr, t->addr, ADDR_VAL_LEN);
+
+ return t->type_cur;
+}
+
+static int set_addr_by_name(int type, int fmt, const char *addr, char *name)
+{
+ struct addr_mgt_info *t;
+
+ t = addr_find_by_name(name);
+ if (t == NULL) {
+ ADDR_MGT_ERR("can't find addr named: %s", name);
+ return -1;
+ }
+
+ if (addr_parse(fmt, addr, t->flag)) {
+ ADDR_MGT_ERR("addr parse fail(%s)", addr);
+ return -1;
+ }
+
+ t->type_cur = type;
+ if (fmt == ADDR_FMT_STR)
+ sscanf(addr, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
+ &t->addr[0], &t->addr[1], &t->addr[2],
+ &t->addr[3], &t->addr[4], &t->addr[5]);
+ else
+ memcpy(t->addr, addr, ADDR_VAL_LEN);
+
+ return 0;
+}
+
+int get_custom_mac_address(int fmt, char *name, char *addr)
+{
+ return get_addr_by_name(fmt, addr, name);
+}
+EXPORT_SYMBOL_GPL(get_custom_mac_address);
+
+static int addr_factory(struct device_node *np,
+ int idx, int type, char *mac, char *name)
+{
+ int ret, i;
+ char match[MATCH_STR_LEN];
+ const char *p;
+ char id[ID_LEN], hash[HASH_LEN], cmp_buf[ID_LEN];
+ struct timespec64 curtime;
+
+ switch (type) {
+ case TYPE_BURN:
+ sprintf(match, "addr_%s", name);
+ ret = of_property_read_string_index(np, match, 0, &p);
+ if (ret)
+ return -1;
+
+ ret = sscanf(p, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
+ &mac[0], &mac[1], &mac[2],
+ &mac[3], &mac[4], &mac[5]);
+
+ if (ret != ADDR_VAL_LEN)
+ return -1;
+ break;
+ case TYPE_IDGEN:
+ if (idx > HASH_LEN / ADDR_VAL_LEN - 1)
+ return -1;
+ if (sunxi_get_soc_chipid(id))
+ return -1;
+ memset(cmp_buf, 0x00, ID_LEN);
+ if (memcmp(id, cmp_buf, ID_LEN) == 0)
+ return -1;
+ if (hmac_sha256(id, ID_LEN, hash))
+ return -1;
+ memcpy(mac, &hash[idx * ADDR_VAL_LEN], ADDR_VAL_LEN);
+ break;
+ case TYPE_RAND:
+ for (i = 0; i < ADDR_VAL_LEN; i++) {
+ ktime_get_real_ts64(&curtime);
+ mac[i] = (char)curtime.tv_nsec;
+ }
+ break;
+ default:
+ ADDR_MGT_ERR("unsupport type: %d", type);
+ return -1;
+ }
+ return 0;
+}
+
+static int addr_init(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ int type, i, j;
+ char match[MATCH_STR_LEN];
+ char addr[ADDR_VAL_LEN];
+ int type_tab[] = {TYPE_BURN, TYPE_IDGEN, TYPE_RAND};
+
+ /* init addr type and value */
+ for (i = 0; i < ARRAY_SIZE(info); i++) {
+ sprintf(match, "type_addr_%s", info[i].name);
+ if (of_property_read_u32(np, match, &type)) {
+ ADDR_MGT_DBG("Failed to get type_def_%s, use default: %d",
+ info[i].name, info[i].type_def);
+ } else {
+ info[i].type_def = type;
+ info[i].type_cur = type;
+ }
+
+ if (IS_TYPE_INVALID(info[i].type_def))
+ return -1;
+ if (info[i].type_def != TYPE_ANY) {
+ if (addr_factory(np, i, info[i].type_def, addr, info[i].name))
+ return -1;
+ } else {
+ for (j = 0; j < ARRAY_SIZE(type_tab); j++) {
+ if (!addr_factory(np, i, type_tab[j], addr, info[i].name)) {
+ info[i].type_cur = type_tab[j];
+ break;
+ }
+ }
+ }
+
+ if (info[i].flag)
+ addr[0] &= 0xFC;
+
+ if (addr_parse(ADDR_FMT_VAL, addr, info[i].flag))
+ return -1;
+ else {
+ info[i].addr = devm_kzalloc(&pdev->dev, ADDR_VAL_LEN, GFP_KERNEL);
+ memcpy(info[i].addr, addr, ADDR_VAL_LEN);
+ }
+ }
+ return 0;
+}
+
+static ssize_t summary_show(struct class *class,
+ struct class_attribute *attr, char *buffer)
+{
+ int i = 0, ret = 0;
+
+ ret += sprintf(&buffer[ret], "name cfg cur address\n");
+ for (i = 0; i < ARRAY_SIZE(info); i++) {
+ ret += sprintf(&buffer[ret],
+ "%4s %d %d %02X:%02X:%02X:%02X:%02X:%02X\n",
+ info[i].name, info[i].type_def, info[i].type_cur,
+ info[i].addr[0], info[i].addr[1], info[i].addr[2],
+ info[i].addr[3], info[i].addr[4], info[i].addr[5]);
+ }
+ return ret;
+}
+static CLASS_ATTR_RO(summary);
+
+ADDR_CLASS_ATTR_ADD(wifi);
+ADDR_CLASS_ATTR_ADD(bt);
+ADDR_CLASS_ATTR_ADD(eth);
+
+static struct attribute *addr_class_attrs[] = {
+ &class_attr_summary.attr,
+ &class_attr_addr_wifi.attr,
+ &class_attr_addr_bt.attr,
+ &class_attr_addr_eth.attr,
+ NULL
+};
+ATTRIBUTE_GROUPS(addr_class);
+
+static struct class addr_class = {
+ .name = "addr_mgt",
+ .owner = THIS_MODULE,
+ .class_groups = addr_class_groups,
+};
+
+static const struct of_device_id addr_mgt_ids[] = {
+ { .compatible = "allwinner,sunxi-addr_mgt" },
+ { /* Sentinel */ }
+};
+
+static int addr_mgt_probe(struct platform_device *pdev)
+{
+ int status;
+
+ ADDR_MGT_DBG("module version: %s", MODULE_CUR_VERSION);
+ status = class_register(&addr_class);
+ if (status < 0) {
+ ADDR_MGT_ERR("class register error, status: %d.", status);
+ return -1;
+ }
+
+ if (addr_init(pdev)) {
+ ADDR_MGT_ERR("failed to init addr.");
+ class_unregister(&addr_class);
+ return -1;
+ }
+ ADDR_MGT_DBG("success.");
+ return 0;
+}
+
+static int addr_mgt_remove(struct platform_device *pdev)
+{
+ class_unregister(&addr_class);
+ return 0;
+}
+
+static struct platform_driver addr_mgt_driver = {
+ .probe = addr_mgt_probe,
+ .remove = addr_mgt_remove,
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "sunxi-addr-mgt",
+ .of_match_table = addr_mgt_ids,
+ },
+};
+
+module_platform_driver_probe(addr_mgt_driver, addr_mgt_probe);
+
+MODULE_AUTHOR("Allwinnertech");
+MODULE_DESCRIPTION("Network MAC Addess Manager");
+MODULE_LICENSE("GPL");
--
2.25.1

2348
patch/kernel/archive/sunxi-5.15/0005-net-phy-support-yt8531c.patch Normal file
View File

File diff suppressed because it is too large Load Diff

101
patch/kernel/archive/sunxi-5.15/0006-h6-dts-overlay-fix-spidev.patch Normal file
View File

@ -0,0 +1,101 @@
From 8ed1a098ef9d7a2febbb24d2e101928a3623a50c Mon Sep 17 00:00:00 2001
From: afaulkner420 <afaulkner420@gmail.com>
Date: Fri, 25 Mar 2022 20:22:40 +0000
Subject: [PATCH 06/11] h6: dts: overlay: fix spidev
---
.../overlay/sun50i-h6-spi-spidev.dts | 6 +--
.../overlay/sun50i-h6-spi-spidev1.dts | 47 ++++++++++---------
2 files changed, 27 insertions(+), 26 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev.dts
index bac3adcba..848c076d0 100644
--- a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev.dts
+++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev.dts
@@ -2,7 +2,7 @@
/plugin/;
/ {
- compatible = "allwinner,sun50i-h6";
+ compatible = "allwinner,sun8i-h3-spi";
fragment@0 {
target-path = "/aliases";
@@ -18,7 +18,7 @@ __overlay__ {
#address-cells = <1>;
#size-cells = <0>;
spidev@0 {
- compatible = "spidev";
+ compatible = "rohm,dh2228fv";
status = "disabled";
reg = <0>;
spi-max-frequency = <1000000>;
@@ -32,7 +32,7 @@ __overlay__ {
#address-cells = <1>;
#size-cells = <0>;
spidev@0 {
- compatible = "spidev";
+ compatible = "rohm,dh2228fv";
status = "disabled";
reg = <0>;
spi-max-frequency = <1000000>;
diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev1.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev1.dts
index e19448434..aee7da0a6 100644
--- a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev1.dts
+++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev1.dts
@@ -3,28 +3,29 @@
/plugin/;
/ {
- compatible = "allwinner,sun8i-h6";
+ compatible = "allwinner,sun8i-h3-spi";
- fragment@0 {
- target-path = "/aliases";
- __overlay__ {
- /* Path to the SPI controller nodes */
- spi1 = "/soc/spi@5011000";
- };
- };
- fragment@1 {
- target = <&spi1>;
- __overlay__ {
- pinctrl-names = "default";
- pinctrl-0 = <&spi1_pins>;
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
- spidev@0 {
- compatible = "spidev";
- reg = <0x0>;
- spi-max-frequency = <1000000>;
- };
- };
- };
+ fragment@0 {
+ target-path = "/aliases";
+ __overlay__ {
+ /* Path to the SPI controller nodes */
+ spi1 = "/soc/spi@5011000";
+ };
+ };
+
+ fragment@1 {
+ target = <&spi1>;
+ __overlay__ {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>;
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ reg = <0x0>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+ };
};
--
2.25.1

211816
patch/kernel/archive/sunxi-5.15/0007-wireless-add-uwe5622-driver.patch Normal file
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File diff suppressed because it is too large Load Diff

28
patch/kernel/archive/sunxi-5.15/0008-uwe5622-bluetooth-fix-firmware-init-fail.patch Normal file
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@ -0,0 +1,28 @@
From 70a0c21f9bc1eed754cce584fe382883dc412db0 Mon Sep 17 00:00:00 2001
From: afaulkner420 <afaulkner420@gmail.com>
Date: Fri, 25 Mar 2022 20:31:26 +0000
Subject: [PATCH 08/11] uwe5622: bluetooth: Fix firmware init fail
---
net/bluetooth/hci_core.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/net/bluetooth/hci_core.c b/net/bluetooth/hci_core.c
index c67390367..b2ee9b6a8 100644
--- a/net/bluetooth/hci_core.c
+++ b/net/bluetooth/hci_core.c
@@ -932,7 +932,11 @@ static int __hci_init(struct hci_dev *hdev)
err = __hci_req_sync(hdev, hci_init3_req, 0, HCI_INIT_TIMEOUT, NULL);
if (err < 0)
+#if defined(CONFIG_RK_WIFI_DEVICE_UWE5621) || defined(CONFIG_AW_WIFI_DEVICE_UWE5622)
+ ;
+#else
return err;
+#endif
err = __hci_req_sync(hdev, hci_init4_req, 0, HCI_INIT_TIMEOUT, NULL);
if (err < 0)
--
2.25.1

1878
patch/kernel/archive/sunxi-5.15/0009-allwinner-h6-support-ac200-audio-codec.patch Normal file
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48
patch/kernel/archive/sunxi-5.15/0010-allwinner-add-sunxi_get_soc_chipid-and-sunxi_get_ser.patch Normal file
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@ -0,0 +1,48 @@
diff --git a/drivers/nvmem/sunxi_sid.c b/drivers/nvmem/sunxi_sid.c
index 37a6abb0e..c81fac63d 100644
--- a/drivers/nvmem/sunxi_sid.c
+++ b/drivers/nvmem/sunxi_sid.c
@@ -37,6 +37,25 @@ struct sunxi_sid {
u32 value_offset;
};
+static unsigned int sunxi_soc_chipid[4];
+static unsigned int sunxi_serial[4];
+
+int sunxi_get_soc_chipid(unsigned char *chipid)
+{
+ memcpy(chipid, sunxi_soc_chipid, 16);
+
+ return 0;
+}
+EXPORT_SYMBOL(sunxi_get_soc_chipid);
+
+int sunxi_get_serial(unsigned char *serial)
+{
+ memcpy(serial, sunxi_serial, 16);
+
+ return 0;
+}
+EXPORT_SYMBOL(sunxi_get_serial);
+
static int sunxi_sid_read(void *context, unsigned int offset,
void *val, size_t bytes)
{
@@ -167,6 +186,15 @@ static int sunxi_sid_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, nvmem);
+ nvmem_cfg->reg_read(sid, 0, &sunxi_soc_chipid[0], sizeof(int));
+ nvmem_cfg->reg_read(sid, 4, &sunxi_soc_chipid[1], sizeof(int));
+ nvmem_cfg->reg_read(sid, 8, &sunxi_soc_chipid[2], sizeof(int));
+ nvmem_cfg->reg_read(sid, 12, &sunxi_soc_chipid[3], sizeof(int));
+
+ sunxi_serial[0] = sunxi_soc_chipid[3];
+ sunxi_serial[1] = sunxi_soc_chipid[2];
+ sunxi_serial[2] = (sunxi_soc_chipid[1] >> 16) & 0x0ffff;
+
return 0;
}
-
2.25.1

598
patch/kernel/archive/sunxi-5.15/0011-add-initial-support-for-orangepi3-lts.patch Normal file
View File

@ -0,0 +1,598 @@
diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
index a14ad689b..1c02d15b0 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -41,6 +41,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-beelink-gs1.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3-lts.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
new file mode 100644
index 000000000..cc5a73026
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
@@ -0,0 +1,398 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2019 Ondřej Jirman <megous@megous.com>
+
+/dts-v1/;
+
+#include "sun50i-h6.dtsi"
+#include "sun50i-h6-cpu-opp.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "OrangePi 3 LTS";
+ compatible = "xunlong,orangepi-3-lts", "allwinner,sun50i-h6";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial9 = &r_uart;
+ ethernet0 = &emac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ ext_osc32k: ext_osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "ext_osc32k";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status {
+ label = "green-led";
+ gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
+ default-state = "on";
+ };
+
+ power {
+ label = "red-led";
+ gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
+ };
+ };
+
+ reg_vcc5v: vcc5v {
+ /* board wide 5V supply directly from the DC jack */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_vcc33_wifi: vcc33-wifi {
+ /* Always on 3.3V regulator for WiFi and BT */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc33-wifi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+ };
+
+ reg_vcc_wifi_io: vcc-wifi-io {
+ /* Always on 1.8V/300mA regulator for WiFi and BT IO */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-wifi-io";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ vin-supply = <&reg_vcc33_wifi>;
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rtc 1>;
+ clock-names = "ext_clock";
+ reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
+ post-power-on-delay-ms = <200>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&reg_dcdca>;
+};
+
+&de {
+ status = "okay";
+};
+
+&dwc3 {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&reg_dcdcc>;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ext_rgmii_pins>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&ext_rgmii_phy>;
+ phy-supply = <&reg_gmac_3v3>;
+ allwinner,rx-delay-ps = <200>;
+ allwinner,tx-delay-ps = <300>;
+ status = "okay";
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+
+ reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */
+ reset-assert-us = <15000>;
+ reset-deassert-us = <40000>;
+ };
+};
+
+&i2s1 {
+ status = "okay";
+};
+
+&mmc0 {
+ vmmc-supply = <&reg_cldo1>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ bus-width = <4>;
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <&reg_vcc33_wifi>;
+ vqmmc-supply = <&reg_vcc_wifi_io>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ vmmc-supply = <&reg_cldo1>;
+ vqmmc-supply = <&reg_bldo2>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ mmc-hs200-1_8v;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&pio {
+ vcc-pc-supply = <&reg_bldo2>;
+ vcc-pd-supply = <&reg_cldo1>;
+ vcc-pg-supply = <&reg_vcc_wifi_io>;
+};
+
+&r_rsb {
+ status = "okay";
+
+ axp805: pmic@745 {
+ compatible = "x-powers,axp805", "x-powers,axp806";
+ reg = <0x745>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ x-powers,self-working-mode;
+ vina-supply = <&reg_vcc5v>;
+ vinb-supply = <&reg_vcc5v>;
+ vinc-supply = <&reg_vcc5v>;
+ vind-supply = <&reg_vcc5v>;
+ vine-supply = <&reg_vcc5v>;
+ aldoin-supply = <&reg_vcc5v>;
+ bldoin-supply = <&reg_vcc5v>;
+ cldoin-supply = <&reg_vcc5v>;
+
+ regulators {
+ reg_aldo1: aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pl-led-ir";
+ };
+
+ reg_aldo2: aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc33-audio-tv-ephy-mac";
+ regulator-enable-ramp-delay = <100000>;
+ };
+
+ /* ALDO3 is shorted to CLDO1 */
+ reg_aldo3: aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-1";
+ };
+
+ reg_bldo1: bldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc18-dram-bias-pll";
+ };
+
+ reg_bldo2: bldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-efuse-pcie-hdmi-pc";
+ };
+
+ reg_blod3: bldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-pm-pg";
+ };
+
+ bldo4 {
+ /* unused */
+ };
+
+ reg_cldo1: cldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-2";
+ };
+
+ cldo2 {
+ /* unused */
+ };
+
+ cldo3 {
+ /* unused */
+ };
+
+ reg_dcdca: dcdca {
+ regulator-always-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1160000>;
+ regulator-ramp-delay = <2500>;
+ regulator-name = "vdd-cpu";
+ };
+
+ reg_dcdcc: dcdcc {
+ regulator-enable-ramp-delay = <32000>;
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1080000>;
+ regulator-ramp-delay = <2500>;
+ regulator-name = "vdd-gpu";
+ };
+
+ reg_dcdcd: dcdcd {
+ regulator-always-on;
+ regulator-min-microvolt = <960000>;
+ regulator-max-microvolt = <960000>;
+ regulator-name = "vdd-sys";
+ };
+
+ reg_dcdce: dcdce {
+ regulator-always-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-dram";
+ };
+
+ sw {
+ /* unused */
+ };
+ };
+ };
+};
+
+&pwm {
+ status = "okay";
+};
+
+&ac200_pwm_clk {
+ status = "okay";
+};
+
+&i2s3 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&r_ir {
+ status = "okay";
+};
+
+&rtc {
+ clocks = <&ext_osc32k>;
+};
+
+&sound_hdmi {
+ status = "okay";
+};
+
+&sound_ac200 {
+ status = "okay";
+};
+
+/delete-node/ &spi0;
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ph_pins>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "disabled";
+};
+
+&usb2otg {
+ /*
+ * This board doesn't have a controllable VBUS even though it
+ * does have an ID pin. Using it as anything but a USB host is
+ * unsafe.
+ */
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb2phy {
+ usb0_id_det-gpios = <&pio 2 15 GPIO_ACTIVE_HIGH>; /* PC15 */
+ usb0_vbus-supply = <&reg_vcc5v>;
+ usb3_vbus-supply = <&reg_vcc5v>;
+ status = "okay";
+};
+
+&usb3phy {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 40be5ad6d..d5a3e046f 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -91,6 +91,13 @@ osc24M: osc24M_clk {
clock-output-names = "osc24M";
};
+ ext_osc32k: ext_osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "ext_osc32k";
+ };
+
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
@@ -126,6 +133,28 @@ cpu {
};
};
+ sound_ac200: sound_ac200 {
+ status = "disabled";
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,frame-master = <&i2s3_master>;
+ simple-audio-card,bitclock-master = <&i2s3_master>;
+ simple-audio-card,name = "allwinner,ac200-codec";
+ simple-audio-card,mclk-fs = <512>;
+ i2s3_master: simple-audio-card,cpu {
+ sound-dai = <&i2s3>;
+ system-clock-frequency = <22579200>;
+ dai-tdm-slot-num = <2>;
+ dai-tdm-slot-width = <32>;
+ };
+ simple-audio-card,codec {
+ sound-dai = <&ac200_codec>;
+ system-clock-frequency = <22579200>;
+ dai-tdm-slot-num = <2>;
+ dai-tdm-slot-width = <32>;
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
arm,no-tick-in-suspend;
@@ -370,7 +399,6 @@ pwm: pwm@300a000 {
pio: pinctrl@300b000 {
compatible = "allwinner,sun50i-h6-pinctrl";
reg = <0x0300b000 0x400>;
- interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
@@ -520,6 +548,11 @@ uart3_rts_cts_pins: uart3-rts-cts-pins {
pins = "PD25", "PD26";
function = "uart3";
};
+
+ i2s3_pins: i2s3-pins {
+ pins = "PB12", "PB13", "PB14", "PB15", "PB16";
+ function = "i2s3";
+ };
};
iommu: iommu@30f0000 {
@@ -718,6 +751,7 @@ i2c3: i2c@5002c00 {
ac200: mfd@10 {
compatible = "x-powers,ac200";
reg = <0x10>;
+ clocks = <&ac200_pwm_clk>;
interrupt-parent = <&pio>;
interrupts = <1 20 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
@@ -725,11 +759,16 @@ ac200: mfd@10 {
ac200_ephy: phy {
compatible = "x-powers,ac200-ephy";
- clocks = <&ac200_pwm_clk>;
nvmem-cells = <&ephy_calibration>;
nvmem-cell-names = "calibration";
status = "disabled";
};
+
+ ac200_codec: codec {
+ #sound-dai-cells = <0>;
+ compatible = "x-powers,ac200-codec";
+ status = "okay";
+ };
};
};
@@ -766,6 +805,21 @@ i2s1: i2s@5091000 {
status = "disabled";
};
+ i2s3: i2s@508f000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun50i-h6-i2s";
+ reg = <0x0508f000 0x1000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S3>, <&ccu CLK_I2S3>;
+ clock-names = "apb", "mod";
+ dmas = <&dma 6>, <&dma 6>;
+ resets = <&ccu RST_BUS_I2S3>;
+ dma-names = "rx", "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s3_pins>;
+ status = "disabled";
+ };
+
spdif: spdif@5093000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun50i-h6-spdif";
@@ -1061,6 +1115,7 @@ rtc: rtc@7000000 {
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clock-output-names = "osc32k", "osc32k-out", "iosc";
+ clocks = <&ext_osc32k>;
#clock-cells = <1>;
};
@@ -1126,17 +1181,18 @@ r_uart_pins: r-uart-pins {
};
r_ir: ir@7040000 {
- compatible = "allwinner,sun50i-h6-ir",
- "allwinner,sun6i-a31-ir";
- reg = <0x07040000 0x400>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&r_ccu CLK_R_APB1_IR>,
- <&r_ccu CLK_IR>;
- clock-names = "apb", "ir";
- resets = <&r_ccu RST_R_APB1_IR>;
- pinctrl-names = "default";
- pinctrl-0 = <&r_ir_rx_pin>;
- status = "disabled";
+ compatible = "allwinner,sun50i-h6-ir",
+ "allwinner,sun6i-a31-ir";
+ reg = <0x07040000 0x400>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_R_APB1_IR>,
+ <&r_ccu CLK_IR>;
+ clock-names = "apb", "ir";
+ resets = <&r_ccu RST_R_APB1_IR>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";
};
r_i2c: i2c@7081400 {
@@ -1178,6 +1234,25 @@ ths: thermal-sensor@5070400 {
nvmem-cell-names = "calibration";
#thermal-sensor-cells = <1>;
};
+
+ sunxi-info {
+ compatible = "allwinner,sun50i-h6-sys-info";
+ status = "okay";
+ };
+
+ addr_mgt: addr-mgt {
+ compatible = "allwinner,sunxi-addr_mgt";
+ type_addr_wifi = <0x2>;
+ type_addr_bt = <0x2>;
+ type_addr_eth = <0x2>;
+ status = "okay";
+ };
+
+ dump_reg: dump_reg@20000 {
+ compatible = "allwinner,sunxi-dump-reg";
+ reg = <0x0 0x03001000 0x0 0x0f20>;
+ status = "okay";
+ };
};
thermal-zones {
--
2.25.1

40
patch/kernel/archive/sunxi-5.15/0012-fix-h6-emmc.patch Normal file
View File

@ -0,0 +1,40 @@
From 9010972a9691d468eb68ab85c73c80bb572a5334 Mon Sep 17 00:00:00 2001
From: Ukhellfire <afaulkner420@gmail.com>
Date: Thu, 24 Mar 2022 22:21:00 +0000
Subject: [PATCH] Fix H6 emmc
We have the wrong MMC CAP voltage for the emmc on this board
---
drivers/mmc/host/sunxi-mmc.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index dd1c2a610..9a641c7d2 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -1221,6 +1221,7 @@ static const struct of_device_id sunxi_mmc_of_match[] = {
{ .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg },
{ .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg },
{ .compatible = "allwinner,sun50i-h5-emmc", .data = &sun50i_h5_emmc_cfg },
+ { .compatible = "allwinner,sun50i-h6-emmc", .data = &sun50i_a64_emmc_cfg },
{ .compatible = "allwinner,sun50i-a100-mmc", .data = &sun50i_a100_cfg },
{ .compatible = "allwinner,sun50i-a100-emmc", .data = &sun50i_a100_emmc_cfg },
{ /* sentinel */ }
@@ -1434,7 +1435,7 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
MMC_CAP_SDIO_IRQ;
/*
- * Some H5 devices do not have signal traces precise enough to
+ * Some H5 and H6 devices do not have signal traces precise enough to
* use HS DDR mode for their eMMC chips.
*
* We still enable HS DDR modes for all the other controller
@@ -1443,6 +1444,8 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
if ((host->cfg->clk_delays || host->use_new_timings) &&
!of_device_is_compatible(pdev->dev.of_node,
"allwinner,sun50i-h5-emmc") &&
+ !of_device_is_compatible(pdev->dev.of_node,
+ "allwinner,sun50i-h6-emmc") &&
!of_machine_is_compatible("allwinner,sun7i-a20") &&
!of_machine_is_compatible("olimex,a64-olinuxino-2ge8g"))
mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;

23
patch/kernel/archive/sunxi-5.15/0013-x-fix-h6-emmc-dts.patch Normal file
View File

@ -0,0 +1,23 @@
From cfafb3f609842d63de13ccaa356b3861ac52c603 Mon Sep 17 00:00:00 2001
From: Ukhellfire <afaulkner420@gmail.com>
Date: Fri, 25 Mar 2022 07:10:57 +0000
Subject: [PATCH] Fix H6 emmc
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 40be5ad6d..3c6e9e875 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -566,8 +566,7 @@
};
mmc2: mmc@4022000 {
- compatible = "allwinner,sun50i-h6-emmc",
- "allwinner,sun50i-a64-emmc";
+ compatible = "allwinner,sun50i-h6-emmc";
reg = <0x04022000 0x1000>;
clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
clock-names = "ahb", "mmc";

33
patch/kernel/archive/sunxi-5.15/0014-add-uwe-bsp-to-orangepi3-lts-dts-file.patch Normal file
View File

@ -0,0 +1,33 @@
From 2b25d82f81c4eda2cfed56cd98e3178ccdb7d752 Mon Sep 17 00:00:00 2001
From: afaulkner420 <afaulkner420@gmail.com>
Date: Fri, 25 Mar 2022 23:26:02 +0000
Subject: [PATCH] add uwe-bsp to OPi3-LTS dts file
---
.../boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
index cc5a73026..83fa87039 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
@@ -180,6 +180,16 @@ &mmc1 {
bus-width = <4>;
non-removable;
status = "okay";
+
+ uwe-bsp {
+ compatible = "unisoc,uwe_bsp";
+ keep-power-on;
+ data-irq;
+ //adma-tx;
+ adma-rx;
+ //blksz-512;
+ status = "okay";
+ };
};
&mmc2 {
--
2.25.1

46
patch/kernel/archive/sunxi-5.15/999-rollback-rsb.patch Normal file
View File

@ -0,0 +1,46 @@
From 409dfdd8ad3dfc0f69ca1abbfad3d955b00f6a01 Mon Sep 17 00:00:00 2001
From: Ukhellfire <afaulkner420@gmail.com>
Date: Fri, 1 Apr 2022 09:44:19 +0100
Subject: [PATCH] Rollback to r_i2c
---
.../dts/allwinner/sun50i-h6-orangepi-3-lts.dts | 16 +++-------------
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
index 83fa87039..0b07f8ca2 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
@@ -180,16 +180,6 @@
bus-width = <4>;
non-removable;
status = "okay";
-
- uwe-bsp {
- compatible = "unisoc,uwe_bsp";
- keep-power-on;
- data-irq;
- //adma-tx;
- adma-rx;
- //blksz-512;
- status = "okay";
- };
};
&mmc2 {
@@ -218,12 +208,12 @@
vcc-pg-supply = <&reg_vcc_wifi_io>;
};
-&r_rsb {
+&r_i2c {
status = "okay";
- axp805: pmic@745 {
+ axp805: pmic@36 {
compatible = "x-powers,axp805", "x-powers,axp806";
- reg = <0x745>;
+ reg = <0x36>;
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;

70
patch/kernel/archive/sunxi-5.16/0001-move-sun50i-h6-pwm-settings-to-its-own-overlay.patch Normal file
View File

@ -0,0 +1,70 @@
From 444ae2245cdccb154ca7d21ba91d9e8e22389dd1 Mon Sep 17 00:00:00 2001
From: afaulkner420 <afaulkner420@gmail.com>
Date: Fri, 25 Mar 2022 19:23:56 +0000
Subject: [PATCH 01/11] Move sun50i-h6-pwm settings to its own overlay
---
.../allwinner/overlay/sun50i-h6-fixup.scr-cmd | 14 -----------
.../dts/allwinner/overlay/sun50i-h6-pwm.dts | 25 +++++++++++++++++++
2 files changed, 25 insertions(+), 14 deletions(-)
create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-pwm.dts
diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd
index d8e79ba45..f757db7aa 100644
--- a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd
+++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd
@@ -54,20 +54,6 @@ if test "${param_pps_falling_edge}" = "1"; then
fdt set /pps@0 assert-falling-edge
fi
-for f in ${overlays}; do
- if test "${f}" = "pwm"; then
- setenv bootargs_new ""
- for arg in ${bootargs}; do
- if test "${arg}" = "console=ttyS0,115200"; then
- echo "Warning: Disabling ttyS0 console due to enabled PWM overlay"
- else
- setenv bootargs_new "${bootargs_new} ${arg}"
- fi
- done
- setenv bootargs "${bootargs_new}"
- fi
-done
-
if test -n "${param_w1_pin}"; then
setenv tmp_bank "${param_w1_pin}"
setenv tmp_pin "${param_w1_pin}"
diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-pwm.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-pwm.dts
new file mode 100644
index 000000000..a8aa74ed1
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-pwm.dts
@@ -0,0 +1,25 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+ compatible = "allwinner,sun50i-h6-pwm";
+
+ fragment@0 {
+ target = <&pio>;
+ __overlay__ {
+ pwm_pin: pwm-pin {
+ pins = "PD22";
+ function = "pwm";
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&pwm>;
+ __overlay__ {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_pin>;
+ status = "okay";
+ };
+ };
+};
--
2.25.1

24
patch/kernel/archive/sunxi-5.16/0002-compile-the-pwm-overlay.patch Normal file
View File

@ -0,0 +1,24 @@
From 51112a4620dea5d3c77ca09572a249f5f877a1ce Mon Sep 17 00:00:00 2001
From: afaulkner420 <afaulkner420@gmail.com>
Date: Fri, 25 Mar 2022 19:26:16 +0000
Subject: [PATCH 02/11] Compile the pwm overlay
---
arch/arm64/boot/dts/allwinner/overlay/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile
index 87f5addec..7cabe8f42 100644
--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile
+++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile
@@ -38,6 +38,7 @@ dtbo-$(CONFIG_ARCH_SUNXI) += \
sun50i-h6-i2c0.dtbo \
sun50i-h6-i2c1.dtbo \
sun50i-h6-i2c2.dtbo \
+ sun50i-h6-pwm.dtbo \
sun50i-h6-ruart.dtbo \
sun50i-h6-spi-add-cs1.dtbo \
sun50i-h6-spi-jedec-nor.dtbo \
--
2.25.1

1552
patch/kernel/archive/sunxi-5.16/0003-add-dump_reg-and-sunxi-sysinfo-drivers.patch Normal file
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File diff suppressed because it is too large Load Diff

613
patch/kernel/archive/sunxi-5.16/0004-add-sunxi-addr-driver-used-to-fix-uwe5622-bluetooth-.patch Normal file
View File

@ -0,0 +1,613 @@
From 29cfa9437eaa2ff862ab0f06852383b181b60743 Mon Sep 17 00:00:00 2001
From: afaulkner420 <afaulkner420@gmail.com>
Date: Fri, 25 Mar 2022 20:18:18 +0000
Subject: [PATCH 04/11] Add sunxi-addr driver - Used to fix uwe5622 bluetooth
MAC addresses
---
drivers/misc/Kconfig | 1 +
drivers/misc/Makefile | 1 +
drivers/misc/sunxi-addr/Kconfig | 6 +
drivers/misc/sunxi-addr/Makefile | 5 +
drivers/misc/sunxi-addr/sha256.c | 178 +++++++++++++
drivers/misc/sunxi-addr/sunxi-addr.c | 358 +++++++++++++++++++++++++++
6 files changed, 549 insertions(+)
create mode 100755 drivers/misc/sunxi-addr/Kconfig
create mode 100755 drivers/misc/sunxi-addr/Makefile
create mode 100755 drivers/misc/sunxi-addr/sha256.c
create mode 100755 drivers/misc/sunxi-addr/sunxi-addr.c
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 24cb809ae..52843042f 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -494,4 +494,5 @@ source "drivers/misc/cardreader/Kconfig"
source "drivers/misc/habanalabs/Kconfig"
source "drivers/misc/uacce/Kconfig"
source "drivers/misc/pvpanic/Kconfig"
+source "drivers/misc/sunxi-addr/Kconfig"
endmenu
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index f3eaa577a..0f9280509 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -60,3 +60,4 @@ obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o
obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o
obj-$(CONFIG_HI6421V600_IRQ) += hi6421v600-irq.o
obj-$(CONFIG_MODEM_POWER) += modem-power.o
+obj-$(CONFIG_SUNXI_ADDR_MGT) += sunxi-addr/
\ No newline at end of file
diff --git a/drivers/misc/sunxi-addr/Kconfig b/drivers/misc/sunxi-addr/Kconfig
new file mode 100755
index 000000000..801dd2c02
--- /dev/null
+++ b/drivers/misc/sunxi-addr/Kconfig
@@ -0,0 +1,6 @@
+config SUNXI_ADDR_MGT
+ tristate "Allwinner Network MAC Addess Manager"
+ depends on BT || ETHERNET || WLAN
+ depends on NVMEM_SUNXI_SID
+ help
+ allwinner network mac address management
diff --git a/drivers/misc/sunxi-addr/Makefile b/drivers/misc/sunxi-addr/Makefile
new file mode 100755
index 000000000..f01fd4783
--- /dev/null
+++ b/drivers/misc/sunxi-addr/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for wifi mac addr manager drivers
+#
+sunxi_addr-objs := sunxi-addr.o sha256.o
+obj-$(CONFIG_SUNXI_ADDR_MGT) += sunxi_addr.o
diff --git a/drivers/misc/sunxi-addr/sha256.c b/drivers/misc/sunxi-addr/sha256.c
new file mode 100755
index 000000000..78825810c
--- /dev/null
+++ b/drivers/misc/sunxi-addr/sha256.c
@@ -0,0 +1,178 @@
+/*
+ * Local implement of sha256.
+ *
+ * Copyright (C) 2013 Allwinner.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/string.h>
+
+/****************************** MACROS ******************************/
+#define ROTRIGHT(a, b) (((a) >> (b)) | ((a) << (32 - (b))))
+#define CH(x, y, z) (((x) & (y)) ^ (~(x) & (z)))
+#define MAJ(x, y, z) (((x) & (y)) ^ ((x) & (z)) ^ ((y) & (z)))
+#define EP0(x) (ROTRIGHT(x, 2) ^ ROTRIGHT(x, 13) ^ ROTRIGHT(x, 22))
+#define EP1(x) (ROTRIGHT(x, 6) ^ ROTRIGHT(x, 11) ^ ROTRIGHT(x, 25))
+#define SIG0(x) (ROTRIGHT(x, 7) ^ ROTRIGHT(x, 18) ^ ((x) >> 3))
+#define SIG1(x) (ROTRIGHT(x, 17) ^ ROTRIGHT(x, 19) ^ ((x) >> 10))
+
+/**************************** VARIABLES *****************************/
+static const uint32_t k[64] = {
+ 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5,
+ 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5,
+ 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3,
+ 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174,
+ 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc,
+ 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da,
+ 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7,
+ 0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967,
+ 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13,
+ 0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85,
+ 0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3,
+ 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070,
+ 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5,
+ 0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3,
+ 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208,
+ 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2
+};
+
+struct sha256_ctx {
+ uint8_t data[64]; /* current 512-bit chunk of message data, just like a buffer */
+ uint32_t datalen; /* sign the data length of current chunk */
+ uint64_t bitlen; /* the bit length of the total message */
+ uint32_t state[8]; /* store the middle state of hash abstract */
+};
+
+/*********************** FUNCTION DEFINITIONS ***********************/
+static void sha256_transform(struct sha256_ctx *ctx, const uint8_t *data)
+{
+ uint32_t a, b, c, d, e, f, g, h, i, j, t1, t2, m[64];
+
+ /* initialization */
+ for (i = 0, j = 0; i < 16; ++i, j += 4)
+ m[i] = (data[j] << 24) | (data[j + 1] << 16) |
+ (data[j + 2] << 8) | (data[j + 3]);
+ for ( ; i < 64; ++i)
+ m[i] = SIG1(m[i - 2]) + m[i - 7] + SIG0(m[i - 15]) + m[i - 16];
+
+ a = ctx->state[0];
+ b = ctx->state[1];
+ c = ctx->state[2];
+ d = ctx->state[3];
+ e = ctx->state[4];
+ f = ctx->state[5];
+ g = ctx->state[6];
+ h = ctx->state[7];
+
+ for (i = 0; i < 64; ++i) {
+ t1 = h + EP1(e) + CH(e, f, g) + k[i] + m[i];
+ t2 = EP0(a) + MAJ(a, b, c);
+ h = g;
+ g = f;
+ f = e;
+ e = d + t1;
+ d = c;
+ c = b;
+ b = a;
+ a = t1 + t2;
+ }
+
+ ctx->state[0] += a;
+ ctx->state[1] += b;
+ ctx->state[2] += c;
+ ctx->state[3] += d;
+ ctx->state[4] += e;
+ ctx->state[5] += f;
+ ctx->state[6] += g;
+ ctx->state[7] += h;
+}
+
+static void sha256_init(struct sha256_ctx *ctx)
+{
+ ctx->datalen = 0;
+ ctx->bitlen = 0;
+ ctx->state[0] = 0x6a09e667;
+ ctx->state[1] = 0xbb67ae85;
+ ctx->state[2] = 0x3c6ef372;
+ ctx->state[3] = 0xa54ff53a;
+ ctx->state[4] = 0x510e527f;
+ ctx->state[5] = 0x9b05688c;
+ ctx->state[6] = 0x1f83d9ab;
+ ctx->state[7] = 0x5be0cd19;
+}
+
+static void sha256_update(struct sha256_ctx *ctx, const uint8_t *data, size_t len)
+{
+ uint32_t i;
+
+ for (i = 0; i < len; ++i) {
+ ctx->data[ctx->datalen] = data[i];
+ ctx->datalen++;
+ if (ctx->datalen == 64) {
+ /* 64 byte = 512 bit means the buffer ctx->data has
+ * fully stored one chunk of message,
+ * so do the sha256 hash map for the current chunk.
+ */
+ sha256_transform(ctx, ctx->data);
+ ctx->bitlen += 512;
+ ctx->datalen = 0;
+ }
+ }
+}
+
+static void sha256_final(struct sha256_ctx *ctx, uint8_t *hash)
+{
+ uint32_t i;
+
+ i = ctx->datalen;
+
+ /* Pad whatever data is left in the buffer. */
+ if (ctx->datalen < 56) {
+ ctx->data[i++] = 0x80; /* pad 10000000 = 0x80 */
+ while (i < 56)
+ ctx->data[i++] = 0x00;
+ } else {
+ ctx->data[i++] = 0x80;
+ while (i < 64)
+ ctx->data[i++] = 0x00;
+ sha256_transform(ctx, ctx->data);
+ memset(ctx->data, 0, 56);
+ }
+
+ /* Append to the padding the total message's length in bits and transform. */
+ ctx->bitlen += ctx->datalen * 8;
+ ctx->data[63] = ctx->bitlen;
+ ctx->data[62] = ctx->bitlen >> 8;
+ ctx->data[61] = ctx->bitlen >> 16;
+ ctx->data[60] = ctx->bitlen >> 24;
+ ctx->data[59] = ctx->bitlen >> 32;
+ ctx->data[58] = ctx->bitlen >> 40;
+ ctx->data[57] = ctx->bitlen >> 48;
+ ctx->data[56] = ctx->bitlen >> 56;
+ sha256_transform(ctx, ctx->data);
+
+ /* copying the final state to the output hash(use big endian). */
+ for (i = 0; i < 4; ++i) {
+ hash[i] = (ctx->state[0] >> (24 - i * 8)) & 0x000000ff;
+ hash[i + 4] = (ctx->state[1] >> (24 - i * 8)) & 0x000000ff;
+ hash[i + 8] = (ctx->state[2] >> (24 - i * 8)) & 0x000000ff;
+ hash[i + 12] = (ctx->state[3] >> (24 - i * 8)) & 0x000000ff;
+ hash[i + 16] = (ctx->state[4] >> (24 - i * 8)) & 0x000000ff;
+ hash[i + 20] = (ctx->state[5] >> (24 - i * 8)) & 0x000000ff;
+ hash[i + 24] = (ctx->state[6] >> (24 - i * 8)) & 0x000000ff;
+ hash[i + 28] = (ctx->state[7] >> (24 - i * 8)) & 0x000000ff;
+ }
+}
+
+int hmac_sha256(const uint8_t *plaintext, ssize_t psize, uint8_t *output)
+{
+ struct sha256_ctx ctx;
+
+ sha256_init(&ctx);
+ sha256_update(&ctx, plaintext, psize);
+ sha256_final(&ctx, output);
+ return 0;
+}
diff --git a/drivers/misc/sunxi-addr/sunxi-addr.c b/drivers/misc/sunxi-addr/sunxi-addr.c
new file mode 100755
index 000000000..a812e4e82
--- /dev/null
+++ b/drivers/misc/sunxi-addr/sunxi-addr.c
@@ -0,0 +1,358 @@
+/*
+ * The driver of SUNXI NET MAC ADDR Manager.
+ *
+ * Copyright (C) 2013 Allwinner.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#define DEBUG
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/miscdevice.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#define ADDR_MGT_DBG(fmt, arg...) printk(KERN_DEBUG "[ADDR_MGT] %s: " fmt "\n",\
+ __func__, ## arg)
+#define ADDR_MGT_ERR(fmt, arg...) printk(KERN_ERR "[ADDR_MGT] %s: " fmt "\n",\
+ __func__, ## arg)
+
+#define MODULE_CUR_VERSION "v1.0.9"
+
+#define MATCH_STR_LEN 20
+#define ADDR_VAL_LEN 6
+#define ADDR_STR_LEN 18
+#define ID_LEN 16
+#define HASH_LEN 32
+
+#define TYPE_ANY 0
+#define TYPE_BURN 1
+#define TYPE_IDGEN 2
+#define TYPE_USER 3
+#define TYPE_RAND 4
+
+#define ADDR_FMT_STR 0
+#define ADDR_FMT_VAL 1
+
+#define IS_TYPE_INVALID(x) ((x < TYPE_ANY) || (x > TYPE_RAND))
+
+#define ADDR_CLASS_ATTR_ADD(name) \
+static ssize_t addr_##name##_show(struct class *class, \
+ struct class_attribute *attr, char *buffer) \
+{ \
+ char addr[ADDR_STR_LEN]; \
+ if (IS_TYPE_INVALID(get_addr_by_name(ADDR_FMT_STR, addr, #name))) \
+ return 0; \
+ return sprintf(buffer, "%.17s\n", addr); \
+} \
+static ssize_t addr_##name##_store(struct class *class, \
+ struct class_attribute *attr, \
+ const char *buffer, size_t count) \
+{ \
+ if (count != ADDR_STR_LEN) { \
+ ADDR_MGT_ERR("Length wrong."); \
+ return -EINVAL; \
+ } \
+ set_addr_by_name(TYPE_USER, ADDR_FMT_STR, buffer, #name); \
+ return count; \
+} \
+static CLASS_ATTR_RW(addr_##name);
+
+struct addr_mgt_info {
+ unsigned int type_def;
+ unsigned int type_cur;
+ unsigned int flag;
+ char *addr;
+ char *name;
+};
+
+static struct addr_mgt_info info[] = {
+ {TYPE_ANY, TYPE_ANY, 1, NULL, "wifi"},
+ {TYPE_ANY, TYPE_ANY, 0, NULL, "bt" },
+ {TYPE_ANY, TYPE_ANY, 1, NULL, "eth" },
+};
+
+extern int hmac_sha256(const uint8_t *plaintext, ssize_t psize, uint8_t *output);
+extern int sunxi_get_soc_chipid(unsigned char *chipid);
+
+static int addr_parse(int fmt, const char *addr, int check)
+{
+ char val_buf[ADDR_VAL_LEN];
+ char cmp_buf[ADDR_VAL_LEN];
+ int ret = ADDR_VAL_LEN;
+
+ if (fmt == ADDR_FMT_STR)
+ ret = sscanf(addr, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
+ &val_buf[0], &val_buf[1], &val_buf[2],
+ &val_buf[3], &val_buf[4], &val_buf[5]);
+ else
+ memcpy(val_buf, addr, ADDR_VAL_LEN);
+
+ if (ret != ADDR_VAL_LEN)
+ return -1;
+
+ if (check && (val_buf[0] & 0x3))
+ return -1;
+
+ memset(cmp_buf, 0x00, ADDR_VAL_LEN);
+ if (memcmp(val_buf, cmp_buf, ADDR_VAL_LEN) == 0)
+ return -1;
+
+ memset(cmp_buf, 0xFF, ADDR_VAL_LEN);
+ if (memcmp(val_buf, cmp_buf, ADDR_VAL_LEN) == 0)
+ return -1;
+
+ return 0;
+}
+
+static struct addr_mgt_info *addr_find_by_name(char *name)
+{
+ int i = 0;
+ for (i = 0; i < ARRAY_SIZE(info); i++) {
+ if (strcmp(info[i].name, name) == 0)
+ return &info[i];
+ }
+ return NULL;
+}
+
+static int get_addr_by_name(int fmt, char *addr, char *name)
+{
+ struct addr_mgt_info *t;
+
+ t = addr_find_by_name(name);
+ if (t == NULL) {
+ ADDR_MGT_ERR("can't find addr named: %s", name);
+ return -1;
+ }
+
+ if (IS_TYPE_INVALID(t->type_cur)) {
+ ADDR_MGT_ERR("addr type invalid");
+ return -1;
+ }
+
+ if (addr_parse(ADDR_FMT_VAL, t->addr, t->flag)) {
+ ADDR_MGT_ERR("addr parse fail(%s)", t->addr);
+ return -1;
+ }
+
+ if (fmt == ADDR_FMT_STR)
+ sprintf(addr, "%02X:%02X:%02X:%02X:%02X:%02X",
+ t->addr[0], t->addr[1], t->addr[2],
+ t->addr[3], t->addr[4], t->addr[5]);
+ else
+ memcpy(addr, t->addr, ADDR_VAL_LEN);
+
+ return t->type_cur;
+}
+
+static int set_addr_by_name(int type, int fmt, const char *addr, char *name)
+{
+ struct addr_mgt_info *t;
+
+ t = addr_find_by_name(name);
+ if (t == NULL) {
+ ADDR_MGT_ERR("can't find addr named: %s", name);
+ return -1;
+ }
+
+ if (addr_parse(fmt, addr, t->flag)) {
+ ADDR_MGT_ERR("addr parse fail(%s)", addr);
+ return -1;
+ }
+
+ t->type_cur = type;
+ if (fmt == ADDR_FMT_STR)
+ sscanf(addr, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
+ &t->addr[0], &t->addr[1], &t->addr[2],
+ &t->addr[3], &t->addr[4], &t->addr[5]);
+ else
+ memcpy(t->addr, addr, ADDR_VAL_LEN);
+
+ return 0;
+}
+
+int get_custom_mac_address(int fmt, char *name, char *addr)
+{
+ return get_addr_by_name(fmt, addr, name);
+}
+EXPORT_SYMBOL_GPL(get_custom_mac_address);
+
+static int addr_factory(struct device_node *np,
+ int idx, int type, char *mac, char *name)
+{
+ int ret, i;
+ char match[MATCH_STR_LEN];
+ const char *p;
+ char id[ID_LEN], hash[HASH_LEN], cmp_buf[ID_LEN];
+ struct timespec64 curtime;
+
+ switch (type) {
+ case TYPE_BURN:
+ sprintf(match, "addr_%s", name);
+ ret = of_property_read_string_index(np, match, 0, &p);
+ if (ret)
+ return -1;
+
+ ret = sscanf(p, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
+ &mac[0], &mac[1], &mac[2],
+ &mac[3], &mac[4], &mac[5]);
+
+ if (ret != ADDR_VAL_LEN)
+ return -1;
+ break;
+ case TYPE_IDGEN:
+ if (idx > HASH_LEN / ADDR_VAL_LEN - 1)
+ return -1;
+ if (sunxi_get_soc_chipid(id))
+ return -1;
+ memset(cmp_buf, 0x00, ID_LEN);
+ if (memcmp(id, cmp_buf, ID_LEN) == 0)
+ return -1;
+ if (hmac_sha256(id, ID_LEN, hash))
+ return -1;
+ memcpy(mac, &hash[idx * ADDR_VAL_LEN], ADDR_VAL_LEN);
+ break;
+ case TYPE_RAND:
+ for (i = 0; i < ADDR_VAL_LEN; i++) {
+ ktime_get_real_ts64(&curtime);
+ mac[i] = (char)curtime.tv_nsec;
+ }
+ break;
+ default:
+ ADDR_MGT_ERR("unsupport type: %d", type);
+ return -1;
+ }
+ return 0;
+}
+
+static int addr_init(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ int type, i, j;
+ char match[MATCH_STR_LEN];
+ char addr[ADDR_VAL_LEN];
+ int type_tab[] = {TYPE_BURN, TYPE_IDGEN, TYPE_RAND};
+
+ /* init addr type and value */
+ for (i = 0; i < ARRAY_SIZE(info); i++) {
+ sprintf(match, "type_addr_%s", info[i].name);
+ if (of_property_read_u32(np, match, &type)) {
+ ADDR_MGT_DBG("Failed to get type_def_%s, use default: %d",
+ info[i].name, info[i].type_def);
+ } else {
+ info[i].type_def = type;
+ info[i].type_cur = type;
+ }
+
+ if (IS_TYPE_INVALID(info[i].type_def))
+ return -1;
+ if (info[i].type_def != TYPE_ANY) {
+ if (addr_factory(np, i, info[i].type_def, addr, info[i].name))
+ return -1;
+ } else {
+ for (j = 0; j < ARRAY_SIZE(type_tab); j++) {
+ if (!addr_factory(np, i, type_tab[j], addr, info[i].name)) {
+ info[i].type_cur = type_tab[j];
+ break;
+ }
+ }
+ }
+
+ if (info[i].flag)
+ addr[0] &= 0xFC;
+
+ if (addr_parse(ADDR_FMT_VAL, addr, info[i].flag))
+ return -1;
+ else {
+ info[i].addr = devm_kzalloc(&pdev->dev, ADDR_VAL_LEN, GFP_KERNEL);
+ memcpy(info[i].addr, addr, ADDR_VAL_LEN);
+ }
+ }
+ return 0;
+}
+
+static ssize_t summary_show(struct class *class,
+ struct class_attribute *attr, char *buffer)
+{
+ int i = 0, ret = 0;
+
+ ret += sprintf(&buffer[ret], "name cfg cur address\n");
+ for (i = 0; i < ARRAY_SIZE(info); i++) {
+ ret += sprintf(&buffer[ret],
+ "%4s %d %d %02X:%02X:%02X:%02X:%02X:%02X\n",
+ info[i].name, info[i].type_def, info[i].type_cur,
+ info[i].addr[0], info[i].addr[1], info[i].addr[2],
+ info[i].addr[3], info[i].addr[4], info[i].addr[5]);
+ }
+ return ret;
+}
+static CLASS_ATTR_RO(summary);
+
+ADDR_CLASS_ATTR_ADD(wifi);
+ADDR_CLASS_ATTR_ADD(bt);
+ADDR_CLASS_ATTR_ADD(eth);
+
+static struct attribute *addr_class_attrs[] = {
+ &class_attr_summary.attr,
+ &class_attr_addr_wifi.attr,
+ &class_attr_addr_bt.attr,
+ &class_attr_addr_eth.attr,
+ NULL
+};
+ATTRIBUTE_GROUPS(addr_class);
+
+static struct class addr_class = {
+ .name = "addr_mgt",
+ .owner = THIS_MODULE,
+ .class_groups = addr_class_groups,
+};
+
+static const struct of_device_id addr_mgt_ids[] = {
+ { .compatible = "allwinner,sunxi-addr_mgt" },
+ { /* Sentinel */ }
+};
+
+static int addr_mgt_probe(struct platform_device *pdev)
+{
+ int status;
+
+ ADDR_MGT_DBG("module version: %s", MODULE_CUR_VERSION);
+ status = class_register(&addr_class);
+ if (status < 0) {
+ ADDR_MGT_ERR("class register error, status: %d.", status);
+ return -1;
+ }
+
+ if (addr_init(pdev)) {
+ ADDR_MGT_ERR("failed to init addr.");
+ class_unregister(&addr_class);
+ return -1;
+ }
+ ADDR_MGT_DBG("success.");
+ return 0;
+}
+
+static int addr_mgt_remove(struct platform_device *pdev)
+{
+ class_unregister(&addr_class);
+ return 0;
+}
+
+static struct platform_driver addr_mgt_driver = {
+ .probe = addr_mgt_probe,
+ .remove = addr_mgt_remove,
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "sunxi-addr-mgt",
+ .of_match_table = addr_mgt_ids,
+ },
+};
+
+module_platform_driver_probe(addr_mgt_driver, addr_mgt_probe);
+
+MODULE_AUTHOR("Allwinnertech");
+MODULE_DESCRIPTION("Network MAC Addess Manager");
+MODULE_LICENSE("GPL");
--
2.25.1

2348
patch/kernel/archive/sunxi-5.16/0005-net-phy-support-yt8531c.patch Normal file
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File diff suppressed because it is too large Load Diff

101
patch/kernel/archive/sunxi-5.16/0006-h6-dts-overlay-fix-spidev.patch Normal file
View File

@ -0,0 +1,101 @@
From 8ed1a098ef9d7a2febbb24d2e101928a3623a50c Mon Sep 17 00:00:00 2001
From: afaulkner420 <afaulkner420@gmail.com>
Date: Fri, 25 Mar 2022 20:22:40 +0000
Subject: [PATCH 06/11] h6: dts: overlay: fix spidev
---
.../overlay/sun50i-h6-spi-spidev.dts | 6 +--
.../overlay/sun50i-h6-spi-spidev1.dts | 47 ++++++++++---------
2 files changed, 27 insertions(+), 26 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev.dts
index bac3adcba..848c076d0 100644
--- a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev.dts
+++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev.dts
@@ -2,7 +2,7 @@
/plugin/;
/ {
- compatible = "allwinner,sun50i-h6";
+ compatible = "allwinner,sun8i-h3-spi";
fragment@0 {
target-path = "/aliases";
@@ -18,7 +18,7 @@ __overlay__ {
#address-cells = <1>;
#size-cells = <0>;
spidev@0 {
- compatible = "spidev";
+ compatible = "rohm,dh2228fv";
status = "disabled";
reg = <0>;
spi-max-frequency = <1000000>;
@@ -32,7 +32,7 @@ __overlay__ {
#address-cells = <1>;
#size-cells = <0>;
spidev@0 {
- compatible = "spidev";
+ compatible = "rohm,dh2228fv";
status = "disabled";
reg = <0>;
spi-max-frequency = <1000000>;
diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev1.dts b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev1.dts
index e19448434..aee7da0a6 100644
--- a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev1.dts
+++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev1.dts
@@ -3,28 +3,29 @@
/plugin/;
/ {
- compatible = "allwinner,sun8i-h6";
+ compatible = "allwinner,sun8i-h3-spi";
- fragment@0 {
- target-path = "/aliases";
- __overlay__ {
- /* Path to the SPI controller nodes */
- spi1 = "/soc/spi@5011000";
- };
- };
- fragment@1 {
- target = <&spi1>;
- __overlay__ {
- pinctrl-names = "default";
- pinctrl-0 = <&spi1_pins>;
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
- spidev@0 {
- compatible = "spidev";
- reg = <0x0>;
- spi-max-frequency = <1000000>;
- };
- };
- };
+ fragment@0 {
+ target-path = "/aliases";
+ __overlay__ {
+ /* Path to the SPI controller nodes */
+ spi1 = "/soc/spi@5011000";
+ };
+ };
+
+ fragment@1 {
+ target = <&spi1>;
+ __overlay__ {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>;
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spidev@0 {
+ compatible = "rohm,dh2228fv";
+ reg = <0x0>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+ };
};
--
2.25.1

211816
patch/kernel/archive/sunxi-5.16/0007-wireless-add-uwe5622-driver.patch Normal file
View File

File diff suppressed because it is too large Load Diff

28
patch/kernel/archive/sunxi-5.16/0008-uwe5622-bluetooth-fix-firmware-init-fail.patch Normal file
View File

@ -0,0 +1,28 @@
From 70a0c21f9bc1eed754cce584fe382883dc412db0 Mon Sep 17 00:00:00 2001
From: afaulkner420 <afaulkner420@gmail.com>
Date: Fri, 25 Mar 2022 20:31:26 +0000
Subject: [PATCH 08/11] uwe5622: bluetooth: Fix firmware init fail
---
net/bluetooth/hci_core.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/net/bluetooth/hci_core.c b/net/bluetooth/hci_core.c
index c67390367..b2ee9b6a8 100644
--- a/net/bluetooth/hci_core.c
+++ b/net/bluetooth/hci_core.c
@@ -932,7 +932,11 @@ static int __hci_init(struct hci_dev *hdev)
err = __hci_req_sync(hdev, hci_init3_req, 0, HCI_INIT_TIMEOUT, NULL);
if (err < 0)
+#if defined(CONFIG_RK_WIFI_DEVICE_UWE5621) || defined(CONFIG_AW_WIFI_DEVICE_UWE5622)
+ ;
+#else
return err;
+#endif
err = __hci_req_sync(hdev, hci_init4_req, 0, HCI_INIT_TIMEOUT, NULL);
if (err < 0)
--
2.25.1

1878
patch/kernel/archive/sunxi-5.16/0009-allwinner-h6-support-ac200-audio-codec.patch Normal file
View File

File diff suppressed because it is too large Load Diff

48
patch/kernel/archive/sunxi-5.16/0010-allwinner-add-sunxi_get_soc_chipid-and-sunxi_get_ser.patch Normal file
View File

@ -0,0 +1,48 @@
diff --git a/drivers/nvmem/sunxi_sid.c b/drivers/nvmem/sunxi_sid.c
index 37a6abb0e..c81fac63d 100644
--- a/drivers/nvmem/sunxi_sid.c
+++ b/drivers/nvmem/sunxi_sid.c
@@ -37,6 +37,25 @@ struct sunxi_sid {
u32 value_offset;
};
+static unsigned int sunxi_soc_chipid[4];
+static unsigned int sunxi_serial[4];
+
+int sunxi_get_soc_chipid(unsigned char *chipid)
+{
+ memcpy(chipid, sunxi_soc_chipid, 16);
+
+ return 0;
+}
+EXPORT_SYMBOL(sunxi_get_soc_chipid);
+
+int sunxi_get_serial(unsigned char *serial)
+{
+ memcpy(serial, sunxi_serial, 16);
+
+ return 0;
+}
+EXPORT_SYMBOL(sunxi_get_serial);
+
static int sunxi_sid_read(void *context, unsigned int offset,
void *val, size_t bytes)
{
@@ -167,6 +186,15 @@ static int sunxi_sid_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, nvmem);
+ nvmem_cfg->reg_read(sid, 0, &sunxi_soc_chipid[0], sizeof(int));
+ nvmem_cfg->reg_read(sid, 4, &sunxi_soc_chipid[1], sizeof(int));
+ nvmem_cfg->reg_read(sid, 8, &sunxi_soc_chipid[2], sizeof(int));
+ nvmem_cfg->reg_read(sid, 12, &sunxi_soc_chipid[3], sizeof(int));
+
+ sunxi_serial[0] = sunxi_soc_chipid[3];
+ sunxi_serial[1] = sunxi_soc_chipid[2];
+ sunxi_serial[2] = (sunxi_soc_chipid[1] >> 16) & 0x0ffff;
+
return 0;
}
-
2.25.1

598
patch/kernel/archive/sunxi-5.16/0011-add-initial-support-for-orangepi3-lts.patch Normal file
View File

@ -0,0 +1,598 @@
diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
index a14ad689b..1c02d15b0 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -41,6 +41,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-beelink-gs1.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3-lts.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
new file mode 100644
index 000000000..cc5a73026
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
@@ -0,0 +1,398 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2019 Ondřej Jirman <megous@megous.com>
+
+/dts-v1/;
+
+#include "sun50i-h6.dtsi"
+#include "sun50i-h6-cpu-opp.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "OrangePi 3 LTS";
+ compatible = "xunlong,orangepi-3-lts", "allwinner,sun50i-h6";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial9 = &r_uart;
+ ethernet0 = &emac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ ext_osc32k: ext_osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "ext_osc32k";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ status {
+ label = "green-led";
+ gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
+ default-state = "on";
+ };
+
+ power {
+ label = "red-led";
+ gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
+ };
+ };
+
+ reg_vcc5v: vcc5v {
+ /* board wide 5V supply directly from the DC jack */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_vcc33_wifi: vcc33-wifi {
+ /* Always on 3.3V regulator for WiFi and BT */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc33-wifi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+ };
+
+ reg_vcc_wifi_io: vcc-wifi-io {
+ /* Always on 1.8V/300mA regulator for WiFi and BT IO */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-wifi-io";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ vin-supply = <&reg_vcc33_wifi>;
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rtc 1>;
+ clock-names = "ext_clock";
+ reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
+ post-power-on-delay-ms = <200>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&reg_dcdca>;
+};
+
+&de {
+ status = "okay";
+};
+
+&dwc3 {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&reg_dcdcc>;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ext_rgmii_pins>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&ext_rgmii_phy>;
+ phy-supply = <&reg_gmac_3v3>;
+ allwinner,rx-delay-ps = <200>;
+ allwinner,tx-delay-ps = <300>;
+ status = "okay";
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+
+ reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */
+ reset-assert-us = <15000>;
+ reset-deassert-us = <40000>;
+ };
+};
+
+&i2s1 {
+ status = "okay";
+};
+
+&mmc0 {
+ vmmc-supply = <&reg_cldo1>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ bus-width = <4>;
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <&reg_vcc33_wifi>;
+ vqmmc-supply = <&reg_vcc_wifi_io>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ vmmc-supply = <&reg_cldo1>;
+ vqmmc-supply = <&reg_bldo2>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ mmc-hs200-1_8v;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&pio {
+ vcc-pc-supply = <&reg_bldo2>;
+ vcc-pd-supply = <&reg_cldo1>;
+ vcc-pg-supply = <&reg_vcc_wifi_io>;
+};
+
+&r_rsb {
+ status = "okay";
+
+ axp805: pmic@745 {
+ compatible = "x-powers,axp805", "x-powers,axp806";
+ reg = <0x745>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ x-powers,self-working-mode;
+ vina-supply = <&reg_vcc5v>;
+ vinb-supply = <&reg_vcc5v>;
+ vinc-supply = <&reg_vcc5v>;
+ vind-supply = <&reg_vcc5v>;
+ vine-supply = <&reg_vcc5v>;
+ aldoin-supply = <&reg_vcc5v>;
+ bldoin-supply = <&reg_vcc5v>;
+ cldoin-supply = <&reg_vcc5v>;
+
+ regulators {
+ reg_aldo1: aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pl-led-ir";
+ };
+
+ reg_aldo2: aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc33-audio-tv-ephy-mac";
+ regulator-enable-ramp-delay = <100000>;
+ };
+
+ /* ALDO3 is shorted to CLDO1 */
+ reg_aldo3: aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-1";
+ };
+
+ reg_bldo1: bldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc18-dram-bias-pll";
+ };
+
+ reg_bldo2: bldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-efuse-pcie-hdmi-pc";
+ };
+
+ reg_blod3: bldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io-pm-pg";
+ };
+
+ bldo4 {
+ /* unused */
+ };
+
+ reg_cldo1: cldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-2";
+ };
+
+ cldo2 {
+ /* unused */
+ };
+
+ cldo3 {
+ /* unused */
+ };
+
+ reg_dcdca: dcdca {
+ regulator-always-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1160000>;
+ regulator-ramp-delay = <2500>;
+ regulator-name = "vdd-cpu";
+ };
+
+ reg_dcdcc: dcdcc {
+ regulator-enable-ramp-delay = <32000>;
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1080000>;
+ regulator-ramp-delay = <2500>;
+ regulator-name = "vdd-gpu";
+ };
+
+ reg_dcdcd: dcdcd {
+ regulator-always-on;
+ regulator-min-microvolt = <960000>;
+ regulator-max-microvolt = <960000>;
+ regulator-name = "vdd-sys";
+ };
+
+ reg_dcdce: dcdce {
+ regulator-always-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-dram";
+ };
+
+ sw {
+ /* unused */
+ };
+ };
+ };
+};
+
+&pwm {
+ status = "okay";
+};
+
+&ac200_pwm_clk {
+ status = "okay";
+};
+
+&i2s3 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&r_ir {
+ status = "okay";
+};
+
+&rtc {
+ clocks = <&ext_osc32k>;
+};
+
+&sound_hdmi {
+ status = "okay";
+};
+
+&sound_ac200 {
+ status = "okay";
+};
+
+/delete-node/ &spi0;
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ph_pins>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "disabled";
+};
+
+&usb2otg {
+ /*
+ * This board doesn't have a controllable VBUS even though it
+ * does have an ID pin. Using it as anything but a USB host is
+ * unsafe.
+ */
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb2phy {
+ usb0_id_det-gpios = <&pio 2 15 GPIO_ACTIVE_HIGH>; /* PC15 */
+ usb0_vbus-supply = <&reg_vcc5v>;
+ usb3_vbus-supply = <&reg_vcc5v>;
+ status = "okay";
+};
+
+&usb3phy {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 40be5ad6d..d5a3e046f 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -91,6 +91,13 @@ osc24M: osc24M_clk {
clock-output-names = "osc24M";
};
+ ext_osc32k: ext_osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "ext_osc32k";
+ };
+
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
@@ -126,6 +133,28 @@ cpu {
};
};
+ sound_ac200: sound_ac200 {
+ status = "disabled";
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,frame-master = <&i2s3_master>;
+ simple-audio-card,bitclock-master = <&i2s3_master>;
+ simple-audio-card,name = "allwinner,ac200-codec";
+ simple-audio-card,mclk-fs = <512>;
+ i2s3_master: simple-audio-card,cpu {
+ sound-dai = <&i2s3>;
+ system-clock-frequency = <22579200>;
+ dai-tdm-slot-num = <2>;
+ dai-tdm-slot-width = <32>;
+ };
+ simple-audio-card,codec {
+ sound-dai = <&ac200_codec>;
+ system-clock-frequency = <22579200>;
+ dai-tdm-slot-num = <2>;
+ dai-tdm-slot-width = <32>;
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
arm,no-tick-in-suspend;
@@ -370,7 +399,6 @@ pwm: pwm@300a000 {
pio: pinctrl@300b000 {
compatible = "allwinner,sun50i-h6-pinctrl";
reg = <0x0300b000 0x400>;
- interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
@@ -520,6 +548,11 @@ uart3_rts_cts_pins: uart3-rts-cts-pins {
pins = "PD25", "PD26";
function = "uart3";
};
+
+ i2s3_pins: i2s3-pins {
+ pins = "PB12", "PB13", "PB14", "PB15", "PB16";
+ function = "i2s3";
+ };
};
iommu: iommu@30f0000 {
@@ -718,6 +751,7 @@ i2c3: i2c@5002c00 {
ac200: mfd@10 {
compatible = "x-powers,ac200";
reg = <0x10>;
+ clocks = <&ac200_pwm_clk>;
interrupt-parent = <&pio>;
interrupts = <1 20 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
@@ -725,11 +759,16 @@ ac200: mfd@10 {
ac200_ephy: phy {
compatible = "x-powers,ac200-ephy";
- clocks = <&ac200_pwm_clk>;
nvmem-cells = <&ephy_calibration>;
nvmem-cell-names = "calibration";
status = "disabled";
};
+
+ ac200_codec: codec {
+ #sound-dai-cells = <0>;
+ compatible = "x-powers,ac200-codec";
+ status = "okay";
+ };
};
};
@@ -766,6 +805,21 @@ i2s1: i2s@5091000 {
status = "disabled";
};
+ i2s3: i2s@508f000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun50i-h6-i2s";
+ reg = <0x0508f000 0x1000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S3>, <&ccu CLK_I2S3>;
+ clock-names = "apb", "mod";
+ dmas = <&dma 6>, <&dma 6>;
+ resets = <&ccu RST_BUS_I2S3>;
+ dma-names = "rx", "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s3_pins>;
+ status = "disabled";
+ };
+
spdif: spdif@5093000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun50i-h6-spdif";
@@ -1061,6 +1115,7 @@ rtc: rtc@7000000 {
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clock-output-names = "osc32k", "osc32k-out", "iosc";
+ clocks = <&ext_osc32k>;
#clock-cells = <1>;
};
@@ -1126,17 +1181,18 @@ r_uart_pins: r-uart-pins {
};
r_ir: ir@7040000 {
- compatible = "allwinner,sun50i-h6-ir",
- "allwinner,sun6i-a31-ir";
- reg = <0x07040000 0x400>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&r_ccu CLK_R_APB1_IR>,
- <&r_ccu CLK_IR>;
- clock-names = "apb", "ir";
- resets = <&r_ccu RST_R_APB1_IR>;
- pinctrl-names = "default";
- pinctrl-0 = <&r_ir_rx_pin>;
- status = "disabled";
+ compatible = "allwinner,sun50i-h6-ir",
+ "allwinner,sun6i-a31-ir";
+ reg = <0x07040000 0x400>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_R_APB1_IR>,
+ <&r_ccu CLK_IR>;
+ clock-names = "apb", "ir";
+ resets = <&r_ccu RST_R_APB1_IR>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_ir_rx_pin>;
+ status = "disabled";
};
r_i2c: i2c@7081400 {
@@ -1178,6 +1234,25 @@ ths: thermal-sensor@5070400 {
nvmem-cell-names = "calibration";
#thermal-sensor-cells = <1>;
};
+
+ sunxi-info {
+ compatible = "allwinner,sun50i-h6-sys-info";
+ status = "okay";
+ };
+
+ addr_mgt: addr-mgt {
+ compatible = "allwinner,sunxi-addr_mgt";
+ type_addr_wifi = <0x2>;
+ type_addr_bt = <0x2>;
+ type_addr_eth = <0x2>;
+ status = "okay";
+ };
+
+ dump_reg: dump_reg@20000 {
+ compatible = "allwinner,sunxi-dump-reg";
+ reg = <0x0 0x03001000 0x0 0x0f20>;
+ status = "okay";
+ };
};
thermal-zones {
--
2.25.1

40
patch/kernel/archive/sunxi-5.16/0012-fix-h6-emmc.patch Normal file
View File

@ -0,0 +1,40 @@
From 9010972a9691d468eb68ab85c73c80bb572a5334 Mon Sep 17 00:00:00 2001
From: Ukhellfire <afaulkner420@gmail.com>
Date: Thu, 24 Mar 2022 22:21:00 +0000
Subject: [PATCH] Fix H6 emmc
We have the wrong MMC CAP voltage for the emmc on this board
---
drivers/mmc/host/sunxi-mmc.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index dd1c2a610..9a641c7d2 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -1221,6 +1221,7 @@ static const struct of_device_id sunxi_mmc_of_match[] = {
{ .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg },
{ .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg },
{ .compatible = "allwinner,sun50i-h5-emmc", .data = &sun50i_h5_emmc_cfg },
+ { .compatible = "allwinner,sun50i-h6-emmc", .data = &sun50i_a64_emmc_cfg },
{ .compatible = "allwinner,sun50i-a100-mmc", .data = &sun50i_a100_cfg },
{ .compatible = "allwinner,sun50i-a100-emmc", .data = &sun50i_a100_emmc_cfg },
{ /* sentinel */ }
@@ -1434,7 +1435,7 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
MMC_CAP_SDIO_IRQ;
/*
- * Some H5 devices do not have signal traces precise enough to
+ * Some H5 and H6 devices do not have signal traces precise enough to
* use HS DDR mode for their eMMC chips.
*
* We still enable HS DDR modes for all the other controller
@@ -1443,6 +1444,8 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
if ((host->cfg->clk_delays || host->use_new_timings) &&
!of_device_is_compatible(pdev->dev.of_node,
"allwinner,sun50i-h5-emmc") &&
+ !of_device_is_compatible(pdev->dev.of_node,
+ "allwinner,sun50i-h6-emmc") &&
!of_machine_is_compatible("allwinner,sun7i-a20") &&
!of_machine_is_compatible("olimex,a64-olinuxino-2ge8g"))
mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;

23
patch/kernel/archive/sunxi-5.16/0013-x-fix-h6-emmc-dts.patch Normal file
View File

@ -0,0 +1,23 @@
From cfafb3f609842d63de13ccaa356b3861ac52c603 Mon Sep 17 00:00:00 2001
From: Ukhellfire <afaulkner420@gmail.com>
Date: Fri, 25 Mar 2022 07:10:57 +0000
Subject: [PATCH] Fix H6 emmc
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 40be5ad6d..3c6e9e875 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -566,8 +566,7 @@
};
mmc2: mmc@4022000 {
- compatible = "allwinner,sun50i-h6-emmc",
- "allwinner,sun50i-a64-emmc";
+ compatible = "allwinner,sun50i-h6-emmc";
reg = <0x04022000 0x1000>;
clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
clock-names = "ahb", "mmc";

33
patch/kernel/archive/sunxi-5.16/0014-add-uwe-bsp-to-orangepi3-lts-dts-file.patch Normal file
View File

@ -0,0 +1,33 @@
From 2b25d82f81c4eda2cfed56cd98e3178ccdb7d752 Mon Sep 17 00:00:00 2001
From: afaulkner420 <afaulkner420@gmail.com>
Date: Fri, 25 Mar 2022 23:26:02 +0000
Subject: [PATCH] add uwe-bsp to OPi3-LTS dts file
---
.../boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
index cc5a73026..83fa87039 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
@@ -180,6 +180,16 @@ &mmc1 {
bus-width = <4>;
non-removable;
status = "okay";
+
+ uwe-bsp {
+ compatible = "unisoc,uwe_bsp";
+ keep-power-on;
+ data-irq;
+ //adma-tx;
+ adma-rx;
+ //blksz-512;
+ status = "okay";
+ };
};
&mmc2 {
--
2.25.1

46
patch/kernel/archive/sunxi-5.16/999-rollback-rsb.patch Normal file
View File

@ -0,0 +1,46 @@
From 409dfdd8ad3dfc0f69ca1abbfad3d955b00f6a01 Mon Sep 17 00:00:00 2001
From: Ukhellfire <afaulkner420@gmail.com>
Date: Fri, 1 Apr 2022 09:44:19 +0100
Subject: [PATCH] Rollback to r_i2c
---
.../dts/allwinner/sun50i-h6-orangepi-3-lts.dts | 16 +++-------------
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
index 83fa87039..0b07f8ca2 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
@@ -180,16 +180,6 @@
bus-width = <4>;
non-removable;
status = "okay";
-
- uwe-bsp {
- compatible = "unisoc,uwe_bsp";
- keep-power-on;
- data-irq;
- //adma-tx;
- adma-rx;
- //blksz-512;
- status = "okay";
- };
};
&mmc2 {
@@ -218,12 +208,12 @@
vcc-pg-supply = <&reg_vcc_wifi_io>;
};
-&r_rsb {
+&r_i2c {
status = "okay";
- axp805: pmic@745 {
+ axp805: pmic@36 {
compatible = "x-powers,axp805", "x-powers,axp806";
- reg = <0x745>;
+ reg = <0x36>;
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;

234
patch/u-boot/u-boot-sunxi/0001-add-orange-pi-3-lts-support.patch Normal file
View File

@ -0,0 +1,234 @@
From ff63ede2a38b16f2438c4c33f49796c639735753 Mon Sep 17 00:00:00 2001
From: afaulkner420 <afaulkner420@gmail.com>
Date: Fri, 1 Apr 2022 21:58:07 +0100
Subject: [PATCH] add orange pi 3 lts support
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/sun50i-h6-orangepi-3-lts.dts | 179 ++++++++++++++++++++++
configs/orangepi_3_lts_defconfig | 18 +++
3 files changed, 198 insertions(+)
create mode 100644 arch/arm/dts/sun50i-h6-orangepi-3-lts.dts
create mode 100644 configs/orangepi_3_lts_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 028dc4a4..b129fcce 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -649,6 +649,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \
dtb-$(CONFIG_MACH_SUN50I_H6) += \
sun50i-h6-beelink-gs1.dtb \
sun50i-h6-orangepi-3.dtb \
+ sun50i-h6-orangepi-3-lts.dtb \
sun50i-h6-orangepi-lite2.dtb \
sun50i-h6-orangepi-one-plus.dtb \
sun50i-h6-pine-h64.dtb \
diff --git a/arch/arm/dts/sun50i-h6-orangepi-3-lts.dts b/arch/arm/dts/sun50i-h6-orangepi-3-lts.dts
new file mode 100644
index 00000000..94e3c5b5
--- /dev/null
+++ b/arch/arm/dts/sun50i-h6-orangepi-3-lts.dts
@@ -0,0 +1,179 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2018 Amarula Solutions
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+/dts-v1/;
+
+#include "sun50i-h6.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "OrangePi 3 LTS";
+ compatible = "xunlong,orangepi-3-lts", "allwinner,sun50i-h6";
+
+ aliases {
+ serial0 = &uart0;
+ ethernet0 = &emac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ext_rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <&ext_rgmii_phy>;
+ phy-supply = <&reg_aldo2>;
+ allwinner,rx-delay-ps = <200>;
+ allwinner,tx-delay-ps = <200>;
+ status = "okay";
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <&reg_cldo1>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ vmmc-supply = <&reg_cldo1>;
+ non-removable;
+ cap-mmc-hw-reset;
+ bus-width = <8>;
+ status = "okay";
+};
+
+&r_i2c {
+ status = "okay";
+
+ axp805: pmic@36 {
+ compatible = "x-powers,axp805", "x-powers,axp806";
+ reg = <0x36>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ x-powers,self-working-mode;
+
+ regulators {
+ reg_aldo1: aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pl";
+ };
+
+ reg_aldo2: aldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-ac200";
+ };
+
+ reg_aldo3: aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc25-dram";
+ };
+
+ reg_bldo1: bldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-bias-pll";
+ };
+
+ reg_bldo2: bldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-efuse-pcie-hdmi-io";
+ };
+
+ reg_bldo3: bldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-dcxoio";
+ };
+
+ bldo4 {
+ /* unused */
+ };
+
+ reg_cldo1: cldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+ };
+
+ reg_cldo2: cldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-1";
+ };
+
+ reg_cldo3: cldo3 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+ };
+
+ reg_dcdca: dcdca {
+ regulator-always-on;
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1080000>;
+ regulator-name = "vdd-cpu";
+ };
+
+ reg_dcdcc: dcdcc {
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1080000>;
+ regulator-name = "vdd-gpu";
+ };
+
+ reg_dcdcd: dcdcd {
+ regulator-always-on;
+ regulator-min-microvolt = <960000>;
+ regulator-max-microvolt = <960000>;
+ regulator-name = "vdd-sys";
+ };
+
+ reg_dcdce: dcdce {
+ regulator-always-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-dram";
+ };
+
+ sw {
+ /* unused */
+ };
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ph_pins>;
+ status = "okay";
+};
diff --git a/configs/orangepi_3_lts_defconfig b/configs/orangepi_3_lts_defconfig
new file mode 100644
index 00000000..f119c349
--- /dev/null
+++ b/configs/orangepi_3_lts_defconfig
@@ -0,0 +1,18 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN50I_H6=y
+CONFIG_SUNXI_DRAM_H6_LPDDR3=y
+CONFIG_SUNXI_DRAM_DDR3=n
+CONFIG_DRAM_ODT_EN=y
+CONFIG_MMC0_CD_PIN="PF6"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_HDMI_DDC_EN="PH2"
+# CONFIG_PSCI_RESET is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-orangepi-3-lts"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set