Enable DMC for Station M1 in current and dev (#2575)
* Enable DMC for Station M1 in current and dev * Disable unstable 924MHz in Station M1 DMC
This commit is contained in:
Piotr Szczepanik
GitHub
parent
f5a9a1f227
commit
2788adcced
@ -0,0 +1,86 @@
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diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts
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index 3cbbcfc37..4e23a25f9 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts
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@@ -4,12 +4,81 @@
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*/
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/dts-v1/;
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+#include "rk3328-roc-pc-dram-timing.dtsi"
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#include "rk3328.dtsi"
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/ {
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model = "Firefly roc-rk3328-pc";
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compatible = "firefly,roc-rk3328-pc", "rockchip,rk3328";
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+ dfi: dfi@ff790000 {
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+ reg = <0x00 0xff790000 0x00 0x400>;
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+ compatible = "rockchip,rk3328-dfi";
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+ rockchip,grf = <&grf>;
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+ status = "okay";
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+ };
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+
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+ dmc: dmc {
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+ compatible = "rockchip,rk3328-dmc";
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+ center-supply = <&vdd_logic>;
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+ devfreq-events = <&dfi>;
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+ clocks = <&cru SCLK_DDRCLK>;
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+ clock-names = "dmc_clk";
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+ operating-points-v2 = <&dmc_opp_table>;
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+ ddr_timing = <&ddr_timing>;
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+ upthreshold = <40>;
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+ downdifferential = <20>;
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+ auto-min-freq = <786000>;
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+ auto-freq-en = <0>;
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+ #cooling-cells = <2>;
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+ status = "okay";
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+
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+ ddr_power_model: ddr_power_model {
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+ compatible = "ddr_power_model";
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+ dynamic-power-coefficient = <120>;
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+ static-power-coefficient = <200>;
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+ ts = <32000 4700 (-80) 2>;
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+ thermal-zone = "soc-thermal";
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+ };
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+ };
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+
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+ dmc_opp_table: dmc-opp-table {
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+ compatible = "operating-points-v2";
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+
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+ rockchip,leakage-voltage-sel = <
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+ 1 10 0
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+ 11 254 1
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+ >;
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+ nvmem-cells = <&logic_leakage>;
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+ nvmem-cell-names = "ddr_leakage";
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+
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+ opp-786000000 {
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+ opp-hz = /bits/ 64 <786000000>;
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+ opp-microvolt = <1075000>;
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+ opp-microvolt-L0 = <1075000>;
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+ opp-microvolt-L1 = <1050000>;
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+ };
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+ opp-798000000 {
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+ opp-hz = /bits/ 64 <798000000>;
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+ opp-microvolt = <1075000>;
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+ opp-microvolt-L0 = <1075000>;
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+ opp-microvolt-L1 = <1050000>;
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+ };
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+ opp-840000000 {
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+ opp-hz = /bits/ 64 <840000000>;
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+ opp-microvolt = <1075000>;
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+ opp-microvolt-L0 = <1075000>;
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+ opp-microvolt-L1 = <1050000>;
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+ };
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+ opp-924000000 {
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+ status = "disabled"; // unstable
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+ opp-hz = /bits/ 64 <924000000>;
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+ opp-microvolt = <1100000>;
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+ opp-microvolt-L0 = <1100000>;
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+ opp-microvolt-L1 = <1075000>;
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+ };
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+ };
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+
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gmac_clkin: external-gmac-clock {
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compatible = "fixed-clock";
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clock-frequency = <125000000>;
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@ -0,0 +1,229 @@
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diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc-dram-timing.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc-dram-timing.dtsi
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new file mode 100644
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index 000000000000..0ea270539a23
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc-dram-timing.dtsi
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@@ -0,0 +1,223 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
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+ *
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+ */
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+#include <dt-bindings/clock/rockchip-ddr.h>
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+#include <dt-bindings/memory/rk3328-dram.h>
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+
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+/ {
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+ ddr_timing: ddr_timing {
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+ /* CA de-skew, one step is 47.8ps, range 0-15 */
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+ ddr3a1_ddr4a9_de-skew = <0>;
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+ ddr3a0_ddr4a10_de-skew = <0>;
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+ ddr3a3_ddr4a6_de-skew = <1>;
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+ ddr3a2_ddr4a4_de-skew = <1>;
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+ ddr3a5_ddr4a8_de-skew = <0>;
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+ ddr3a4_ddr4a5_de-skew = <2>;
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+ ddr3a7_ddr4a11_de-skew = <0>;
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+ ddr3a6_ddr4a7_de-skew = <2>;
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+ ddr3a9_ddr4a0_de-skew = <1>;
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+ ddr3a8_ddr4a13_de-skew = <0>;
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+ ddr3a11_ddr4a3_de-skew = <2>;
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+ ddr3a10_ddr4cs0_de-skew = <0>;
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+ ddr3a13_ddr4a2_de-skew = <1>;
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+ ddr3a12_ddr4ba1_de-skew = <0>;
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+ ddr3a15_ddr4odt0_de-skew = <0>;
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+ ddr3a14_ddr4a1_de-skew = <1>;
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+ ddr3ba1_ddr4a15_de-skew = <0>;
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+ ddr3ba0_ddr4bg0_de-skew = <0>;
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+ ddr3ras_ddr4cke_de-skew = <0>;
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+ ddr3ba2_ddr4ba0_de-skew = <1>;
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+ ddr3we_ddr4bg1_de-skew = <1>;
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+ ddr3cas_ddr4a12_de-skew = <0>;
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+ ddr3ckn_ddr4ckn_de-skew = <5>;
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+ ddr3ckp_ddr4ckp_de-skew = <5>;
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+ ddr3cke_ddr4a16_de-skew = <1>;
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+ ddr3odt0_ddr4a14_de-skew = <0>;
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+ ddr3cs0_ddr4act_de-skew = <1>;
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+ ddr3reset_ddr4reset_de-skew = <0>;
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+ ddr3cs1_ddr4cs1_de-skew = <0>;
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+ ddr3odt1_ddr4odt1_de-skew = <0>;
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+
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+ /* DATA de-skew
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+ * RX one step is 25.1ps, range 0-15
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+ * TX one step is 47.8ps, range 0-15
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+ */
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+ cs0_dm0_rx_de-skew = <7>;
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+ cs0_dm0_tx_de-skew = <8>;
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+ cs0_dq0_rx_de-skew = <7>;
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+ cs0_dq0_tx_de-skew = <8>;
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+ cs0_dq1_rx_de-skew = <7>;
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+ cs0_dq1_tx_de-skew = <8>;
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+ cs0_dq2_rx_de-skew = <7>;
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+ cs0_dq2_tx_de-skew = <8>;
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+ cs0_dq3_rx_de-skew = <7>;
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+ cs0_dq3_tx_de-skew = <8>;
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+ cs0_dq4_rx_de-skew = <7>;
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+ cs0_dq4_tx_de-skew = <8>;
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+ cs0_dq5_rx_de-skew = <7>;
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+ cs0_dq5_tx_de-skew = <8>;
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+ cs0_dq6_rx_de-skew = <7>;
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+ cs0_dq6_tx_de-skew = <8>;
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+ cs0_dq7_rx_de-skew = <7>;
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+ cs0_dq7_tx_de-skew = <8>;
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+ cs0_dqs0_rx_de-skew = <6>;
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+ cs0_dqs0p_tx_de-skew = <9>;
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+ cs0_dqs0n_tx_de-skew = <9>;
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+
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+ cs0_dm1_rx_de-skew = <7>;
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+ cs0_dm1_tx_de-skew = <7>;
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+ cs0_dq8_rx_de-skew = <7>;
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+ cs0_dq8_tx_de-skew = <8>;
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+ cs0_dq9_rx_de-skew = <7>;
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+ cs0_dq9_tx_de-skew = <7>;
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+ cs0_dq10_rx_de-skew = <7>;
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+ cs0_dq10_tx_de-skew = <8>;
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+ cs0_dq11_rx_de-skew = <7>;
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+ cs0_dq11_tx_de-skew = <7>;
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+ cs0_dq12_rx_de-skew = <7>;
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+ cs0_dq12_tx_de-skew = <8>;
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+ cs0_dq13_rx_de-skew = <7>;
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+ cs0_dq13_tx_de-skew = <7>;
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+ cs0_dq14_rx_de-skew = <7>;
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+ cs0_dq14_tx_de-skew = <8>;
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+ cs0_dq15_rx_de-skew = <7>;
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+ cs0_dq15_tx_de-skew = <7>;
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+ cs0_dqs1_rx_de-skew = <7>;
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+ cs0_dqs1p_tx_de-skew = <9>;
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+ cs0_dqs1n_tx_de-skew = <9>;
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+
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+ cs0_dm2_rx_de-skew = <7>;
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+ cs0_dm2_tx_de-skew = <8>;
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+ cs0_dq16_rx_de-skew = <7>;
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+ cs0_dq16_tx_de-skew = <8>;
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+ cs0_dq17_rx_de-skew = <7>;
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+ cs0_dq17_tx_de-skew = <8>;
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+ cs0_dq18_rx_de-skew = <7>;
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+ cs0_dq18_tx_de-skew = <8>;
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+ cs0_dq19_rx_de-skew = <7>;
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+ cs0_dq19_tx_de-skew = <8>;
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+ cs0_dq20_rx_de-skew = <7>;
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+ cs0_dq20_tx_de-skew = <8>;
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+ cs0_dq21_rx_de-skew = <7>;
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+ cs0_dq21_tx_de-skew = <8>;
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+ cs0_dq22_rx_de-skew = <7>;
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+ cs0_dq22_tx_de-skew = <8>;
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+ cs0_dq23_rx_de-skew = <7>;
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+ cs0_dq23_tx_de-skew = <8>;
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+ cs0_dqs2_rx_de-skew = <6>;
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+ cs0_dqs2p_tx_de-skew = <9>;
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+ cs0_dqs2n_tx_de-skew = <9>;
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+
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+ cs0_dm3_rx_de-skew = <7>;
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+ cs0_dm3_tx_de-skew = <7>;
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+ cs0_dq24_rx_de-skew = <7>;
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+ cs0_dq24_tx_de-skew = <8>;
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+ cs0_dq25_rx_de-skew = <7>;
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+ cs0_dq25_tx_de-skew = <7>;
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+ cs0_dq26_rx_de-skew = <7>;
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+ cs0_dq26_tx_de-skew = <7>;
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+ cs0_dq27_rx_de-skew = <7>;
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+ cs0_dq27_tx_de-skew = <7>;
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+ cs0_dq28_rx_de-skew = <7>;
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+ cs0_dq28_tx_de-skew = <7>;
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+ cs0_dq29_rx_de-skew = <7>;
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+ cs0_dq29_tx_de-skew = <7>;
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+ cs0_dq30_rx_de-skew = <7>;
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+ cs0_dq30_tx_de-skew = <7>;
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+ cs0_dq31_rx_de-skew = <7>;
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+ cs0_dq31_tx_de-skew = <7>;
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+ cs0_dqs3_rx_de-skew = <7>;
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+ cs0_dqs3p_tx_de-skew = <9>;
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+ cs0_dqs3n_tx_de-skew = <9>;
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+
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+ cs1_dm0_rx_de-skew = <7>;
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+ cs1_dm0_tx_de-skew = <8>;
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+ cs1_dq0_rx_de-skew = <7>;
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+ cs1_dq0_tx_de-skew = <8>;
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+ cs1_dq1_rx_de-skew = <7>;
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+ cs1_dq1_tx_de-skew = <8>;
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+ cs1_dq2_rx_de-skew = <7>;
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+ cs1_dq2_tx_de-skew = <8>;
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+ cs1_dq3_rx_de-skew = <7>;
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+ cs1_dq3_tx_de-skew = <8>;
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+ cs1_dq4_rx_de-skew = <7>;
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+ cs1_dq4_tx_de-skew = <8>;
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+ cs1_dq5_rx_de-skew = <7>;
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+ cs1_dq5_tx_de-skew = <8>;
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+ cs1_dq6_rx_de-skew = <7>;
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+ cs1_dq6_tx_de-skew = <8>;
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+ cs1_dq7_rx_de-skew = <7>;
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+ cs1_dq7_tx_de-skew = <8>;
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+ cs1_dqs0_rx_de-skew = <6>;
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+ cs1_dqs0p_tx_de-skew = <9>;
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+ cs1_dqs0n_tx_de-skew = <9>;
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+
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+ cs1_dm1_rx_de-skew = <7>;
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+ cs1_dm1_tx_de-skew = <7>;
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+ cs1_dq8_rx_de-skew = <7>;
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+ cs1_dq8_tx_de-skew = <8>;
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+ cs1_dq9_rx_de-skew = <7>;
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+ cs1_dq9_tx_de-skew = <7>;
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+ cs1_dq10_rx_de-skew = <7>;
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+ cs1_dq10_tx_de-skew = <8>;
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+ cs1_dq11_rx_de-skew = <7>;
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+ cs1_dq11_tx_de-skew = <7>;
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+ cs1_dq12_rx_de-skew = <7>;
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+ cs1_dq12_tx_de-skew = <8>;
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+ cs1_dq13_rx_de-skew = <7>;
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+ cs1_dq13_tx_de-skew = <7>;
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+ cs1_dq14_rx_de-skew = <7>;
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+ cs1_dq14_tx_de-skew = <8>;
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+ cs1_dq15_rx_de-skew = <7>;
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+ cs1_dq15_tx_de-skew = <7>;
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+ cs1_dqs1_rx_de-skew = <7>;
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+ cs1_dqs1p_tx_de-skew = <9>;
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+ cs1_dqs1n_tx_de-skew = <9>;
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+
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+ cs1_dm2_rx_de-skew = <7>;
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+ cs1_dm2_tx_de-skew = <8>;
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+ cs1_dq16_rx_de-skew = <7>;
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+ cs1_dq16_tx_de-skew = <8>;
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+ cs1_dq17_rx_de-skew = <7>;
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+ cs1_dq17_tx_de-skew = <8>;
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+ cs1_dq18_rx_de-skew = <7>;
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+ cs1_dq18_tx_de-skew = <8>;
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+ cs1_dq19_rx_de-skew = <7>;
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+ cs1_dq19_tx_de-skew = <8>;
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+ cs1_dq20_rx_de-skew = <7>;
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+ cs1_dq20_tx_de-skew = <8>;
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+ cs1_dq21_rx_de-skew = <7>;
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+ cs1_dq21_tx_de-skew = <8>;
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+ cs1_dq22_rx_de-skew = <7>;
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+ cs1_dq22_tx_de-skew = <8>;
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+ cs1_dq23_rx_de-skew = <7>;
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+ cs1_dq23_tx_de-skew = <8>;
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+ cs1_dqs2_rx_de-skew = <6>;
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+ cs1_dqs2p_tx_de-skew = <9>;
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+ cs1_dqs2n_tx_de-skew = <9>;
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+
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+ cs1_dm3_rx_de-skew = <7>;
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+ cs1_dm3_tx_de-skew = <7>;
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+ cs1_dq24_rx_de-skew = <7>;
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+ cs1_dq24_tx_de-skew = <8>;
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+ cs1_dq25_rx_de-skew = <7>;
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+ cs1_dq25_tx_de-skew = <7>;
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+ cs1_dq26_rx_de-skew = <7>;
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+ cs1_dq26_tx_de-skew = <7>;
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+ cs1_dq27_rx_de-skew = <7>;
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+ cs1_dq27_tx_de-skew = <7>;
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+ cs1_dq28_rx_de-skew = <7>;
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+ cs1_dq28_tx_de-skew = <7>;
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+ cs1_dq29_rx_de-skew = <7>;
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+ cs1_dq29_tx_de-skew = <7>;
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+ cs1_dq30_rx_de-skew = <7>;
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+ cs1_dq30_tx_de-skew = <7>;
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+ cs1_dq31_rx_de-skew = <7>;
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+ cs1_dq31_tx_de-skew = <7>;
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+ cs1_dqs3_rx_de-skew = <7>;
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+ cs1_dqs3p_tx_de-skew = <9>;
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+ cs1_dqs3n_tx_de-skew = <9>;
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+ };
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+};
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@ -0,0 +1,86 @@
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diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts
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index 3cbbcfc37..4e23a25f9 100644
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--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts
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@@ -4,12 +4,80 @@
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*/
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/dts-v1/;
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+#include "rk3328-roc-pc-dram-timing.dtsi"
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#include "rk3328.dtsi"
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/ {
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model = "Firefly roc-rk3328-pc";
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compatible = "firefly,roc-rk3328-pc", "rockchip,rk3328";
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+ dfi: dfi@ff790000 {
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+ reg = <0x00 0xff790000 0x00 0x400>;
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+ compatible = "rockchip,rk3328-dfi";
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+ rockchip,grf = <&grf>;
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+ status = "okay";
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+ };
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+
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+ dmc: dmc {
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+ compatible = "rockchip,rk3328-dmc";
|
||||
+ center-supply = <&vdd_logic>;
|
||||
+ devfreq-events = <&dfi>;
|
||||
+ clocks = <&cru SCLK_DDRCLK>;
|
||||
+ clock-names = "dmc_clk";
|
||||
+ operating-points-v2 = <&dmc_opp_table>;
|
||||
+ ddr_timing = <&ddr_timing>;
|
||||
+ upthreshold = <40>;
|
||||
+ downdifferential = <20>;
|
||||
+ auto-min-freq = <786000>;
|
||||
+ auto-freq-en = <0>;
|
||||
+ #cooling-cells = <2>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ ddr_power_model: ddr_power_model {
|
||||
+ compatible = "ddr_power_model";
|
||||
+ dynamic-power-coefficient = <120>;
|
||||
+ static-power-coefficient = <200>;
|
||||
+ ts = <32000 4700 (-80) 2>;
|
||||
+ thermal-zone = "soc-thermal";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ dmc_opp_table: dmc-opp-table {
|
||||
+ compatible = "operating-points-v2";
|
||||
+
|
||||
+ rockchip,leakage-voltage-sel = <
|
||||
+ 1 10 0
|
||||
+ 11 254 1
|
||||
+ >;
|
||||
+ nvmem-cells = <&logic_leakage>;
|
||||
+ nvmem-cell-names = "ddr_leakage";
|
||||
+
|
||||
+ opp-786000000 {
|
||||
+ opp-hz = /bits/ 64 <786000000>;
|
||||
+ opp-microvolt = <1075000>;
|
||||
+ opp-microvolt-L0 = <1075000>;
|
||||
+ opp-microvolt-L1 = <1050000>;
|
||||
+ };
|
||||
+ opp-798000000 {
|
||||
+ opp-hz = /bits/ 64 <798000000>;
|
||||
+ opp-microvolt = <1075000>;
|
||||
+ opp-microvolt-L0 = <1075000>;
|
||||
+ opp-microvolt-L1 = <1050000>;
|
||||
+ };
|
||||
+ opp-840000000 {
|
||||
+ opp-hz = /bits/ 64 <840000000>;
|
||||
+ opp-microvolt = <1075000>;
|
||||
+ opp-microvolt-L0 = <1075000>;
|
||||
+ opp-microvolt-L1 = <1050000>;
|
||||
+ };
|
||||
+ opp-924000000 {
|
||||
+ status = "disabled"; // unstable
|
||||
+ opp-hz = /bits/ 64 <924000000>;
|
||||
+ opp-microvolt = <1100000>;
|
||||
+ opp-microvolt-L0 = <1100000>;
|
||||
+ opp-microvolt-L1 = <1075000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
gmac_clkin: external-gmac-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
@ -0,0 +1,229 @@
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc-dram-timing.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc-dram-timing.dtsi
|
||||
new file mode 100644
|
||||
index 000000000000..0ea270539a23
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc-dram-timing.dtsi
|
||||
@@ -0,0 +1,223 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
|
||||
+ *
|
||||
+ */
|
||||
+#include <dt-bindings/clock/rockchip-ddr.h>
|
||||
+#include <dt-bindings/memory/rk3328-dram.h>
|
||||
+
|
||||
+/ {
|
||||
+ ddr_timing: ddr_timing {
|
||||
+ /* CA de-skew, one step is 47.8ps, range 0-15 */
|
||||
+ ddr3a1_ddr4a9_de-skew = <0>;
|
||||
+ ddr3a0_ddr4a10_de-skew = <0>;
|
||||
+ ddr3a3_ddr4a6_de-skew = <1>;
|
||||
+ ddr3a2_ddr4a4_de-skew = <1>;
|
||||
+ ddr3a5_ddr4a8_de-skew = <0>;
|
||||
+ ddr3a4_ddr4a5_de-skew = <2>;
|
||||
+ ddr3a7_ddr4a11_de-skew = <0>;
|
||||
+ ddr3a6_ddr4a7_de-skew = <2>;
|
||||
+ ddr3a9_ddr4a0_de-skew = <1>;
|
||||
+ ddr3a8_ddr4a13_de-skew = <0>;
|
||||
+ ddr3a11_ddr4a3_de-skew = <2>;
|
||||
+ ddr3a10_ddr4cs0_de-skew = <0>;
|
||||
+ ddr3a13_ddr4a2_de-skew = <1>;
|
||||
+ ddr3a12_ddr4ba1_de-skew = <0>;
|
||||
+ ddr3a15_ddr4odt0_de-skew = <0>;
|
||||
+ ddr3a14_ddr4a1_de-skew = <1>;
|
||||
+ ddr3ba1_ddr4a15_de-skew = <0>;
|
||||
+ ddr3ba0_ddr4bg0_de-skew = <0>;
|
||||
+ ddr3ras_ddr4cke_de-skew = <0>;
|
||||
+ ddr3ba2_ddr4ba0_de-skew = <1>;
|
||||
+ ddr3we_ddr4bg1_de-skew = <1>;
|
||||
+ ddr3cas_ddr4a12_de-skew = <0>;
|
||||
+ ddr3ckn_ddr4ckn_de-skew = <5>;
|
||||
+ ddr3ckp_ddr4ckp_de-skew = <5>;
|
||||
+ ddr3cke_ddr4a16_de-skew = <1>;
|
||||
+ ddr3odt0_ddr4a14_de-skew = <0>;
|
||||
+ ddr3cs0_ddr4act_de-skew = <1>;
|
||||
+ ddr3reset_ddr4reset_de-skew = <0>;
|
||||
+ ddr3cs1_ddr4cs1_de-skew = <0>;
|
||||
+ ddr3odt1_ddr4odt1_de-skew = <0>;
|
||||
+
|
||||
+ /* DATA de-skew
|
||||
+ * RX one step is 25.1ps, range 0-15
|
||||
+ * TX one step is 47.8ps, range 0-15
|
||||
+ */
|
||||
+ cs0_dm0_rx_de-skew = <7>;
|
||||
+ cs0_dm0_tx_de-skew = <8>;
|
||||
+ cs0_dq0_rx_de-skew = <7>;
|
||||
+ cs0_dq0_tx_de-skew = <8>;
|
||||
+ cs0_dq1_rx_de-skew = <7>;
|
||||
+ cs0_dq1_tx_de-skew = <8>;
|
||||
+ cs0_dq2_rx_de-skew = <7>;
|
||||
+ cs0_dq2_tx_de-skew = <8>;
|
||||
+ cs0_dq3_rx_de-skew = <7>;
|
||||
+ cs0_dq3_tx_de-skew = <8>;
|
||||
+ cs0_dq4_rx_de-skew = <7>;
|
||||
+ cs0_dq4_tx_de-skew = <8>;
|
||||
+ cs0_dq5_rx_de-skew = <7>;
|
||||
+ cs0_dq5_tx_de-skew = <8>;
|
||||
+ cs0_dq6_rx_de-skew = <7>;
|
||||
+ cs0_dq6_tx_de-skew = <8>;
|
||||
+ cs0_dq7_rx_de-skew = <7>;
|
||||
+ cs0_dq7_tx_de-skew = <8>;
|
||||
+ cs0_dqs0_rx_de-skew = <6>;
|
||||
+ cs0_dqs0p_tx_de-skew = <9>;
|
||||
+ cs0_dqs0n_tx_de-skew = <9>;
|
||||
+
|
||||
+ cs0_dm1_rx_de-skew = <7>;
|
||||
+ cs0_dm1_tx_de-skew = <7>;
|
||||
+ cs0_dq8_rx_de-skew = <7>;
|
||||
+ cs0_dq8_tx_de-skew = <8>;
|
||||
+ cs0_dq9_rx_de-skew = <7>;
|
||||
+ cs0_dq9_tx_de-skew = <7>;
|
||||
+ cs0_dq10_rx_de-skew = <7>;
|
||||
+ cs0_dq10_tx_de-skew = <8>;
|
||||
+ cs0_dq11_rx_de-skew = <7>;
|
||||
+ cs0_dq11_tx_de-skew = <7>;
|
||||
+ cs0_dq12_rx_de-skew = <7>;
|
||||
+ cs0_dq12_tx_de-skew = <8>;
|
||||
+ cs0_dq13_rx_de-skew = <7>;
|
||||
+ cs0_dq13_tx_de-skew = <7>;
|
||||
+ cs0_dq14_rx_de-skew = <7>;
|
||||
+ cs0_dq14_tx_de-skew = <8>;
|
||||
+ cs0_dq15_rx_de-skew = <7>;
|
||||
+ cs0_dq15_tx_de-skew = <7>;
|
||||
+ cs0_dqs1_rx_de-skew = <7>;
|
||||
+ cs0_dqs1p_tx_de-skew = <9>;
|
||||
+ cs0_dqs1n_tx_de-skew = <9>;
|
||||
+
|
||||
+ cs0_dm2_rx_de-skew = <7>;
|
||||
+ cs0_dm2_tx_de-skew = <8>;
|
||||
+ cs0_dq16_rx_de-skew = <7>;
|
||||
+ cs0_dq16_tx_de-skew = <8>;
|
||||
+ cs0_dq17_rx_de-skew = <7>;
|
||||
+ cs0_dq17_tx_de-skew = <8>;
|
||||
+ cs0_dq18_rx_de-skew = <7>;
|
||||
+ cs0_dq18_tx_de-skew = <8>;
|
||||
+ cs0_dq19_rx_de-skew = <7>;
|
||||
+ cs0_dq19_tx_de-skew = <8>;
|
||||
+ cs0_dq20_rx_de-skew = <7>;
|
||||
+ cs0_dq20_tx_de-skew = <8>;
|
||||
+ cs0_dq21_rx_de-skew = <7>;
|
||||
+ cs0_dq21_tx_de-skew = <8>;
|
||||
+ cs0_dq22_rx_de-skew = <7>;
|
||||
+ cs0_dq22_tx_de-skew = <8>;
|
||||
+ cs0_dq23_rx_de-skew = <7>;
|
||||
+ cs0_dq23_tx_de-skew = <8>;
|
||||
+ cs0_dqs2_rx_de-skew = <6>;
|
||||
+ cs0_dqs2p_tx_de-skew = <9>;
|
||||
+ cs0_dqs2n_tx_de-skew = <9>;
|
||||
+
|
||||
+ cs0_dm3_rx_de-skew = <7>;
|
||||
+ cs0_dm3_tx_de-skew = <7>;
|
||||
+ cs0_dq24_rx_de-skew = <7>;
|
||||
+ cs0_dq24_tx_de-skew = <8>;
|
||||
+ cs0_dq25_rx_de-skew = <7>;
|
||||
+ cs0_dq25_tx_de-skew = <7>;
|
||||
+ cs0_dq26_rx_de-skew = <7>;
|
||||
+ cs0_dq26_tx_de-skew = <7>;
|
||||
+ cs0_dq27_rx_de-skew = <7>;
|
||||
+ cs0_dq27_tx_de-skew = <7>;
|
||||
+ cs0_dq28_rx_de-skew = <7>;
|
||||
+ cs0_dq28_tx_de-skew = <7>;
|
||||
+ cs0_dq29_rx_de-skew = <7>;
|
||||
+ cs0_dq29_tx_de-skew = <7>;
|
||||
+ cs0_dq30_rx_de-skew = <7>;
|
||||
+ cs0_dq30_tx_de-skew = <7>;
|
||||
+ cs0_dq31_rx_de-skew = <7>;
|
||||
+ cs0_dq31_tx_de-skew = <7>;
|
||||
+ cs0_dqs3_rx_de-skew = <7>;
|
||||
+ cs0_dqs3p_tx_de-skew = <9>;
|
||||
+ cs0_dqs3n_tx_de-skew = <9>;
|
||||
+
|
||||
+ cs1_dm0_rx_de-skew = <7>;
|
||||
+ cs1_dm0_tx_de-skew = <8>;
|
||||
+ cs1_dq0_rx_de-skew = <7>;
|
||||
+ cs1_dq0_tx_de-skew = <8>;
|
||||
+ cs1_dq1_rx_de-skew = <7>;
|
||||
+ cs1_dq1_tx_de-skew = <8>;
|
||||
+ cs1_dq2_rx_de-skew = <7>;
|
||||
+ cs1_dq2_tx_de-skew = <8>;
|
||||
+ cs1_dq3_rx_de-skew = <7>;
|
||||
+ cs1_dq3_tx_de-skew = <8>;
|
||||
+ cs1_dq4_rx_de-skew = <7>;
|
||||
+ cs1_dq4_tx_de-skew = <8>;
|
||||
+ cs1_dq5_rx_de-skew = <7>;
|
||||
+ cs1_dq5_tx_de-skew = <8>;
|
||||
+ cs1_dq6_rx_de-skew = <7>;
|
||||
+ cs1_dq6_tx_de-skew = <8>;
|
||||
+ cs1_dq7_rx_de-skew = <7>;
|
||||
+ cs1_dq7_tx_de-skew = <8>;
|
||||
+ cs1_dqs0_rx_de-skew = <6>;
|
||||
+ cs1_dqs0p_tx_de-skew = <9>;
|
||||
+ cs1_dqs0n_tx_de-skew = <9>;
|
||||
+
|
||||
+ cs1_dm1_rx_de-skew = <7>;
|
||||
+ cs1_dm1_tx_de-skew = <7>;
|
||||
+ cs1_dq8_rx_de-skew = <7>;
|
||||
+ cs1_dq8_tx_de-skew = <8>;
|
||||
+ cs1_dq9_rx_de-skew = <7>;
|
||||
+ cs1_dq9_tx_de-skew = <7>;
|
||||
+ cs1_dq10_rx_de-skew = <7>;
|
||||
+ cs1_dq10_tx_de-skew = <8>;
|
||||
+ cs1_dq11_rx_de-skew = <7>;
|
||||
+ cs1_dq11_tx_de-skew = <7>;
|
||||
+ cs1_dq12_rx_de-skew = <7>;
|
||||
+ cs1_dq12_tx_de-skew = <8>;
|
||||
+ cs1_dq13_rx_de-skew = <7>;
|
||||
+ cs1_dq13_tx_de-skew = <7>;
|
||||
+ cs1_dq14_rx_de-skew = <7>;
|
||||
+ cs1_dq14_tx_de-skew = <8>;
|
||||
+ cs1_dq15_rx_de-skew = <7>;
|
||||
+ cs1_dq15_tx_de-skew = <7>;
|
||||
+ cs1_dqs1_rx_de-skew = <7>;
|
||||
+ cs1_dqs1p_tx_de-skew = <9>;
|
||||
+ cs1_dqs1n_tx_de-skew = <9>;
|
||||
+
|
||||
+ cs1_dm2_rx_de-skew = <7>;
|
||||
+ cs1_dm2_tx_de-skew = <8>;
|
||||
+ cs1_dq16_rx_de-skew = <7>;
|
||||
+ cs1_dq16_tx_de-skew = <8>;
|
||||
+ cs1_dq17_rx_de-skew = <7>;
|
||||
+ cs1_dq17_tx_de-skew = <8>;
|
||||
+ cs1_dq18_rx_de-skew = <7>;
|
||||
+ cs1_dq18_tx_de-skew = <8>;
|
||||
+ cs1_dq19_rx_de-skew = <7>;
|
||||
+ cs1_dq19_tx_de-skew = <8>;
|
||||
+ cs1_dq20_rx_de-skew = <7>;
|
||||
+ cs1_dq20_tx_de-skew = <8>;
|
||||
+ cs1_dq21_rx_de-skew = <7>;
|
||||
+ cs1_dq21_tx_de-skew = <8>;
|
||||
+ cs1_dq22_rx_de-skew = <7>;
|
||||
+ cs1_dq22_tx_de-skew = <8>;
|
||||
+ cs1_dq23_rx_de-skew = <7>;
|
||||
+ cs1_dq23_tx_de-skew = <8>;
|
||||
+ cs1_dqs2_rx_de-skew = <6>;
|
||||
+ cs1_dqs2p_tx_de-skew = <9>;
|
||||
+ cs1_dqs2n_tx_de-skew = <9>;
|
||||
+
|
||||
+ cs1_dm3_rx_de-skew = <7>;
|
||||
+ cs1_dm3_tx_de-skew = <7>;
|
||||
+ cs1_dq24_rx_de-skew = <7>;
|
||||
+ cs1_dq24_tx_de-skew = <8>;
|
||||
+ cs1_dq25_rx_de-skew = <7>;
|
||||
+ cs1_dq25_tx_de-skew = <7>;
|
||||
+ cs1_dq26_rx_de-skew = <7>;
|
||||
+ cs1_dq26_tx_de-skew = <7>;
|
||||
+ cs1_dq27_rx_de-skew = <7>;
|
||||
+ cs1_dq27_tx_de-skew = <7>;
|
||||
+ cs1_dq28_rx_de-skew = <7>;
|
||||
+ cs1_dq28_tx_de-skew = <7>;
|
||||
+ cs1_dq29_rx_de-skew = <7>;
|
||||
+ cs1_dq29_tx_de-skew = <7>;
|
||||
+ cs1_dq30_rx_de-skew = <7>;
|
||||
+ cs1_dq30_tx_de-skew = <7>;
|
||||
+ cs1_dq31_rx_de-skew = <7>;
|
||||
+ cs1_dq31_tx_de-skew = <7>;
|
||||
+ cs1_dqs3_rx_de-skew = <7>;
|
||||
+ cs1_dqs3p_tx_de-skew = <9>;
|
||||
+ cs1_dqs3n_tx_de-skew = <9>;
|
||||
+ };
|
||||
+};
|
||||
Loading…
Reference in New Issue
Block a user