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Remove deprecated patches (#2922)

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* Remove deprecated patches. They broke Pine H64 booting

* Update kernel config
This commit is contained in:
Igor Pečovnik 2021-06-25 23:32:14 +02:00 committed by GitHub
parent 2f2fd48345
commit 219f2bcbd9
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GPG Key ID: 4AEE18F83AFDEB23
11 changed files with 6 additions and 612 deletions
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7
config/kernel/linux-sunxi64-edge.config
View File

@ -1,6 +1,6 @@
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm64 5.12.9 Kernel Configuration
# Linux/arm64 5.12.13 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0"
CONFIG_CC_IS_GCC=y
@ -2067,7 +2067,12 @@ CONFIG_BLK_DEV_RBD=m
#
# NVME Support
#
CONFIG_NVME_CORE=m
# CONFIG_NVME_MULTIPATH is not set
# CONFIG_NVME_HWMON is not set
CONFIG_NVME_FABRICS=m
# CONFIG_NVME_FC is not set
CONFIG_NVME_TCP=m
# CONFIG_NVME_TARGET is not set
# end of NVME Support

70
patch/kernel/archive/sunxi-5.12/board-pine-h6-pine-h6-0007-mmc-sunxi-add-support-for-the-MMC-controller-on-H6.patch.1
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@ -1,70 +0,0 @@
From 31c6231045f48c5adee02190a5c8fdb75b9de012 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Sat, 2 Dec 2017 15:10:53 +0800
Subject: [PATCH 07/35] mmc: sunxi: add support for the MMC controller on H6
The new Allwinner H6 SoC have 3 MMC controllers. The first and second
ones are similar to the ones on A64, but the third one adds EMCE
(Embedded Crypto Engine) support which does hardware transparent crypto
on the eMMC.
As we still do not have support for EMCE, and the support of it is
disabled by defualt, we just duplicate the A64 mmc configurations and
change the compatible string.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
Documentation/devicetree/bindings/mmc/sunxi-mmc.txt | 2 ++
drivers/mmc/host/sunxi-mmc.c | 16 ++++++++++++++++
2 files changed, 18 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
index 132e000..e6aa5c7 100644
--- a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
+++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
@@ -16,6 +16,8 @@ Required properties:
* "allwinner,sun9i-a80-mmc"
* "allwinner,sun50i-a64-emmc"
* "allwinner,sun50i-a64-mmc"
+ * "allwinner,sun50i-h6-emmc"
+ * "allwinner,sun50i-h6-mmc"
- reg : mmc controller base registers
- clocks : a list with 4 phandle + clock specifier pairs
- clock-names : must contain "ahb", "mmc", "output" and "sample"
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index bad612d..3cb73c1 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -1153,6 +1153,20 @@ static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = {
.can_calibrate = true,
};
+static const struct sunxi_mmc_cfg sun50i_h6_cfg = {
+ .idma_des_size_bits = 16,
+ .clk_delays = NULL,
+ .can_calibrate = true,
+ .mask_data0 = true,
+ .needs_new_timings = true,
+};
+
+static const struct sunxi_mmc_cfg sun50i_h6_emmc_cfg = {
+ .idma_des_size_bits = 13,
+ .clk_delays = NULL,
+ .can_calibrate = true,
+};
+
static const struct of_device_id sunxi_mmc_of_match[] = {
{ .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg },
{ .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg },
@@ -1161,6 +1175,8 @@ static const struct of_device_id sunxi_mmc_of_match[] = {
{ .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg },
{ .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg },
{ .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg },
+ { .compatible = "allwinner,sun50i-h6-mmc", .data = &sun50i_h6_cfg },
+ { .compatible = "allwinner,sun50i-h6-emmc", .data = &sun50i_h6_emmc_cfg },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
--
2.7.4

99
patch/kernel/archive/sunxi-5.12/board-pine-h6-pine-h6-0008-arm64-allwinner-h6-add-device-tree-nodes-for-MMC-con.patch.1
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@ -1,99 +0,0 @@
From 56131b6002a59ef06ca96a6d38131e4f4dc281b9 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Sat, 2 Dec 2017 15:13:12 +0800
Subject: [PATCH 08/35] arm64: allwinner: h6: add device tree nodes for MMC
controllers
The Allwinner H6 SoC have 3 MMC controllers.
Add device tree nodes for them.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 56 ++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index d4697bb..19c7ee8 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -125,12 +125,76 @@
interrupt-controller;
#interrupt-cells = <3>;
+ mmc0_pins: mmc0-pins {
+ pins = "PF0", "PF1", "PF2", "PF3",
+ "PF4", "PF5";
+ function = "mmc0";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ mmc1_pins: mmc1-pins {
+ pins = "PG0", "PG1", "PG2", "PG3",
+ "PG4", "PG5";
+ function = "mmc1";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ mmc2_pins: mmc2-pins {
+ pins = "PC1", "PC4", "PC5", "PC6",
+ "PC7", "PC8", "PC9", "PC10",
+ "PC11", "PC12", "PC13", "PC14";
+ function = "mmc2";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
uart0_ph_pins: uart0-ph {
pins = "PH0", "PH1";
function = "uart0";
};
};
+ mmc0: mmc@4020000 {
+ compatible = "allwinner,sun50i-h6-mmc";
+ reg = <0x04020000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC0>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@4021000 {
+ compatible = "allwinner,sun50i-h6-mmc";
+ reg = <0x04021000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC1>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc@4022000 {
+ compatible = "allwinner,sun50i-h6-emmc";
+ reg = <0x04022000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC2>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
uart0: serial@5000000 {
compatible = "snps,dw-apb-uart";
reg = <0x05000000 0x400>;
--
2.7.4

61
patch/kernel/archive/sunxi-5.12/board-pine-h6-pine-h6-0009-arm64-allwinner-h6-enable-MMC0-2-on-Pine-H64.patch
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@ -1,61 +0,0 @@
From 638eb36c357f0d8b11b16fe9b9aff4b6d92d1089 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Sat, 2 Dec 2017 15:14:53 +0800
Subject: [PATCH 09/35] arm64: allwinner: h6: enable MMC0/2 on Pine H64
The Pine H64 board have a MicroSD slot connected to MMC0 controller of
the H6 SoC and a eMMC slot connected to MMC2.
Enable them in the device tree.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
.../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 32 ++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index dc850a1..3e31f39 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -21,6 +21,38 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_vcc1v8: vcc1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ vqmmc-supply = <&reg_vcc1v8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
};
&uart0 {
--
2.7.4

37
patch/kernel/archive/sunxi-5.12/board-pine-h6-pine-h6-0011-arm64-allwinner-h6-add-PRCM-CCU-device-node.patch.1
View File

@ -1,37 +0,0 @@
From 850cc97f8a8ee366f307b8f3a13c6d73fbc069a0 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Fri, 22 Dec 2017 22:11:44 +0800
Subject: [PATCH 11/35] arm64: allwinner: h6: add PRCM CCU device node
Allwinner H6 has also a PRCM CCU.
Add its device node into the device tree.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 19c7ee8..db0263e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -230,5 +230,15 @@
resets = <&ccu RST_BUS_UART3>;
status = "disabled";
};
+
+ r_ccu: clock@7010000 {
+ compatible = "allwinner,sun50i-h6-r-ccu";
+ reg = <0x07010000 0x400>;
+ clocks = <&osc24M>, <&osc32k>, <&iosc>,
+ <&ccu CLK_PLL_PERIPH0>;
+ clock-names = "hosc", "losc", "iosc", "pll-periph";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
};
};
--
2.7.4

41
patch/kernel/archive/sunxi-5.12/board-pine-h6-pine-h6-0013-arm64-allwinner-h6-add-node-for-R_PIO-pin-controller.patch.1
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@ -1,41 +0,0 @@
From 958d54aad158b794f29f52567b96cd3ed8e0cae2 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Sat, 23 Dec 2017 00:20:21 +0800
Subject: [PATCH 13/35] arm64: allwinner: h6: add node for R_PIO pin controller
Allwinner H6 SoC has a R_PIO pin controller which controls PL and PM
GPIO banks.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index db0263e..41fa2c6 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -240,5 +240,18 @@
#clock-cells = <1>;
#reset-cells = <1>;
};
+
+ r_pio: pinctrl@7022000 {
+ compatible = "allwinner,sun50i-h6-r-pinctrl";
+ reg = <0x07022000 0x400>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
};
};
--
2.7.4

39
patch/kernel/archive/sunxi-5.12/board-pine-h6-pine-h6-0014-arm64-allwinner-h6-add-R_INTC-interrupt-controller.patch.1
View File

@ -1,39 +0,0 @@
From 8b42729766b4ae04e0feafcc58dc6991ace78c02 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Sat, 23 Dec 2017 10:35:22 +0800
Subject: [PATCH 14/35] arm64: allwinner: h6: add R_INTC interrupt controller
Allwinner H6 SoC has also a R_INTC interrupt controller like Allwinner
A64 SoC, but has its base address changed due to the memory map change
in H6.
Add it into the device tree.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 41fa2c6..0ff9406 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -241,6 +241,15 @@
#reset-cells = <1>;
};
+ r_intc: interrupt-controller@7021000 {
+ compatible = "allwinner,sun50i-h6-r-intc",
+ "allwinner,sun6i-a31-r-intc";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x07021000 0x400>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
r_pio: pinctrl@7022000 {
compatible = "allwinner,sun50i-h6-r-pinctrl";
reg = <0x07022000 0x400>;
--
2.7.4

55
patch/kernel/archive/sunxi-5.12/board-pine-h6-pine-h6-0015-arm64-allwinner-h6-add-R_I2C-controller.patch.1
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@ -1,55 +0,0 @@
From ccc7d2a5f907e060a1ed4b6b8f447b0721f36543 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Sat, 23 Dec 2017 10:40:13 +0800
Subject: [PATCH 15/35] arm64: allwinner: h6: add R_I2C controller
Allwinner H6 SoC has a R_I2C controller wired to the PL0/PL1 pins, which
are used in the reference design to connect AXP805 PMIC.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 0ff9406..f3ca411 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -6,7 +6,9 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun50i-h6-ccu.h>
+#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
#include <dt-bindings/reset/sun50i-h6-ccu.h>
+#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
/ {
interrupt-parent = <&gic>;
@@ -261,6 +263,22 @@
#gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <3>;
+
+ r_i2c_pins: r-i2c {
+ pins = "PL0", "PL1";
+ function = "s_i2c";
+ };
+ };
+
+ r_i2c: i2c@7081400 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x07081400 0x400>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_R_APB2_I2C>;
+ resets = <&r_ccu RST_R_APB2_I2C>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
};
};
--
2.7.4

143
patch/kernel/archive/sunxi-5.12/board-pine-h6-pine-h6-0018-arm64-allwinner-h6-enable-AXP805-PMIC-on-Pine-H64.patch
View File

@ -1,143 +0,0 @@
From a1d32a812faa375b9234e215d46383dd3a3ae377 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Sat, 23 Dec 2017 10:46:45 +0800
Subject: [PATCH 18/35] arm64: allwinner: h6: enable AXP805 PMIC on Pine H64
Pine H64 board has an AXP805 PMIC on it.
Enable it in the device tree.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
.../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 115 +++++++++++++++++++++
1 file changed, 115 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index 3e31f39..9177224 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -55,6 +55,121 @@
status = "okay";
};
+&r_i2c {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_i2c_pins>;
+ status = "okay";
+
+ axp805: pmic@36 {
+ compatible = "x-powers,axp805", "x-powers,axp806";
+ reg = <0x36>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ x-powers,master-mode;
+
+ regulators {
+ reg_aldo1: aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pl";
+ };
+
+ reg_aldo2: aldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-ac200";
+ };
+
+ reg_aldo3: aldo3 {
+ /* This regulator is connected with CLDO1 */
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3-1";
+ };
+
+ reg_bldo1: bldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-ddr-bias-pll";
+ };
+
+ reg_bldo2: bldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-efuse-emmc-pcie-hdmi";
+ };
+
+ reg_bldo3: bldo3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-wifi-io";
+ };
+
+ bldo4 {
+ /* unused */
+ };
+
+ reg_cldo1: cldo1 {
+ /* This regulator is connected with ALDO3 */
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3-2";
+ };
+
+ reg_cldo2: cldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-1";
+ };
+
+ reg_cldo3: cldo3 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-2";
+ };
+
+ reg_dcdca: dcdca {
+ regulator-always-on;
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1160000>;
+ regulator-name = "vdd-cpu";
+ };
+
+ reg_dcdcc: dcdcc {
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1080000>;
+ regulator-name = "vdd-gpu";
+ };
+
+ reg_dcdcd: dcdcd {
+ regulator-always-on;
+ regulator-min-microvolt = <960000>;
+ regulator-max-microvolt = <960000>;
+ regulator-name = "vdd-sys";
+ };
+
+ reg_dcdce: dcdce {
+ regulator-always-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-dram";
+ };
+
+ sw {
+ /* unused */
+ };
+ };
+ };
+
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
--
2.7.4

33
patch/kernel/archive/sunxi-5.12/board-pine-h6-pine-h6-0019-arm64-allwinner-h6-add-PCF8563-RTC-on-Pine-H64-board.patch
View File

@ -1,33 +0,0 @@
From ab0899416b23c030d18963a61a2b51864bd7cef0 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Sun, 24 Dec 2017 16:16:31 +0800
Subject: [PATCH 19/35] arm64: allwinner: h6: add PCF8563 RTC on Pine H64 board
Pine H64 board has a PCF8563 dedicated RTC connected to its R_I2C bus.
Add it to the device tree.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index 9177224..e2195b0 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -168,6 +168,11 @@
};
};
+ pcf8563: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ };
};
&uart0 {
--
2.7.4

33
patch/kernel/archive/sunxi-5.12/board-pine-h6-pine-h6-0030-arm64-allwinner-h6-add-CPU-regulator-for-Pine-H64.patch
View File

@ -1,33 +0,0 @@
From 40737606bbbb382e7cd02a42da0526a3741c9b3e Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Fri, 5 Jan 2018 19:40:16 +0800
Subject: [PATCH 30/35] arm64: allwinner: h6: add CPU regulator for Pine H64
Pine H64 uses the DCDCA (poly-phased with DCDCB) output of AXP805 PMIC
to power the ARM cores in it.
Add the regulator to the CPU device node.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index 038e213..7f8e958 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -47,6 +47,10 @@
};
};
+&cpu0 {
+ cpu-supply = <&reg_dcdca>;
+};
+
&dwc3 {
status = "okay";
};
--
2.7.4