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rockchip64: address changes for mainlined rk3308 audio codec

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* the existing patches for rk3308 audio codec have been disabled:
  the rk3308 driver has been mainlined and thus the patches
  don't apply anymore
* add the missing i2s_8ch_0 and _1 i2s nodes
* adjust "acodec" with "codec" device tree labels, to match
  mainline kernel nomenclature
This commit is contained in:
Paolo Sabatino 2024-07-21 15:16:07 +02:00 committed by Igor
parent 4ae0a95814
commit 1f7289d67f
8 changed files with 84 additions and 2 deletions
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2
patch/kernel/archive/rockchip64-6.10/board-rockpis-0001-arm64-dts.patch
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@ -233,7 +233,7 @@ index e9810d2f0407..0d917658d24a 100644
};
};
+&acodec {
+&codec {
+ status = "okay";
+ #sound-dai-cells = <0>;
+};

0
patch/kernel/archive/rockchip64-6.10/board-rockpis-0010-arm64-dts-rockchip-add-i2s_8ch-for-rk3308.patch → patch/kernel/archive/rockchip64-6.10/board-rockpis-0010-arm64-dts-rockchip-add-i2s_8ch-for-rk3308.patch.disabled
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0
patch/kernel/archive/rockchip64-6.10/board-rockpis-0018-ASoC-codecs-Add-RK3308-internal-codec-driver.patch → patch/kernel/archive/rockchip64-6.10/board-rockpis-0018-ASoC-codecs-Add-RK3308-internal-codec-driver.patch.disabled
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0
patch/kernel/archive/rockchip64-6.10/board-rockpis-0019-Sync-rk3308_codec-to-BSP-tree.patch → patch/kernel/archive/rockchip64-6.10/board-rockpis-0019-Sync-rk3308_codec-to-BSP-tree.patch.disabled
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0
patch/kernel/archive/rockchip64-6.10/board-rockpis-0020-arm64-dts-rockchip-Add-acodec-node-for-rk3308.patch → patch/kernel/archive/rockchip64-6.10/board-rockpis-0020-arm64-dts-rockchip-Add-acodec-node-for-rk3308.patch.disabled
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0
patch/kernel/archive/rockchip64-6.10/board-rockpis-0022-ASoC-rk3308_codec-replace-codec-to-component.patch → patch/kernel/archive/rockchip64-6.10/board-rockpis-0022-ASoC-rk3308_codec-replace-codec-to-component.patch.disabled
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2
patch/kernel/archive/rockchip64-6.10/board-rocks0-0001-deviceTree.patch
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@ -184,7 +184,7 @@ index 000000000..aded16959
+ };
+};
+
+&acodec {
+&codec {
+ status = "okay";
+ #sound-dai-cells = <0>;
+};

82
patch/kernel/archive/rockchip64-6.10/rk3308-add-missing-i2s-controllers.patch Normal file
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@ -0,0 +1,82 @@
From 8c92404a280aa7f35a311fb0939b8276371fcba3 Mon Sep 17 00:00:00 2001
From: Paolo Sabatino <paolo.sabatino@gmail.com>
Date: Sun, 21 Jul 2024 14:18:30 +0200
Subject: [PATCH] add missing i2s controllers
---
arch/arm64/boot/dts/rockchip/rk3308.dtsi | 59 ++++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
index c00da150a22f..a9d1cb1debe9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
@@ -578,6 +578,65 @@ dmac1: dma-controller@ff2d0000 {
#dma-cells = <1>;
};
+ i2s_8ch_0: i2s@ff300000 {
+ compatible = "rockchip,rk3308-i2s-tdm";
+ reg = <0x0 0xff300000 0x0 0x1000>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_I2S0_8CH_TX>, <&cru SCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>,
+ <&cru SCLK_I2S0_8CH_TX_SRC>,
+ <&cru SCLK_I2S0_8CH_RX_SRC>,
+ <&cru PLL_VPLL0>,
+ <&cru PLL_VPLL1>;
+ clock-names = "mclk_tx", "mclk_rx", "hclk",
+ "mclk_tx_src", "mclk_rx_src",
+ "mclk_root0", "mclk_root1";
+ dmas = <&dmac1 0>, <&dmac1 1>;
+ dma-names = "tx", "rx";
+ resets = <&cru SRST_I2S0_8CH_TX_M>, <&cru SRST_I2S0_8CH_RX_M>;
+ reset-names = "tx-m", "rx-m";
+ rockchip,cru = <&cru>;
+ rockchip,grf = <&grf>;
+ rockchip,mclk-calibrate;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s_8ch_0_sclktx
+ &i2s_8ch_0_sclkrx
+ &i2s_8ch_0_lrcktx
+ &i2s_8ch_0_lrckrx
+ &i2s_8ch_0_sdi0
+ &i2s_8ch_0_sdi1
+ &i2s_8ch_0_sdi2
+ &i2s_8ch_0_sdi3
+ &i2s_8ch_0_sdo0
+ &i2s_8ch_0_sdo1
+ &i2s_8ch_0_sdo2
+ &i2s_8ch_0_sdo3
+ &i2s_8ch_0_mclk>;
+ status = "disabled";
+ };
+
+ i2s_8ch_1: i2s@ff310000 {
+ compatible = "rockchip,rk3308-i2s-tdm";
+ reg = <0x0 0xff310000 0x0 0x1000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_I2S1_8CH_TX>, <&cru SCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>,
+ <&cru SCLK_I2S1_8CH_TX_SRC>,
+ <&cru SCLK_I2S1_8CH_RX_SRC>,
+ <&cru PLL_VPLL0>,
+ <&cru PLL_VPLL1>;
+ clock-names = "mclk_tx", "mclk_rx", "hclk",
+ "mclk_tx_src", "mclk_rx_src",
+ "mclk_root0", "mclk_root1";
+ dmas = <&dmac1 2>, <&dmac1 3>;
+ dma-names = "tx", "rx";
+ resets = <&cru SRST_I2S1_8CH_TX_M>, <&cru SRST_I2S1_8CH_RX_M>;
+ reset-names = "tx-m", "rx-m";
+ rockchip,cru = <&cru>;
+ rockchip,grf = <&grf>;
+ rockchip,mclk-calibrate;
+ rockchip,io-multiplex;
+ status = "disabled";
+ };
+
/*
* - can be clock producer or consumer
* - up to 8 capture channels and 2 playback channels
--
2.34.1