Bumping sunxi/64, xu4, rockchip and mvebu64 to 5.16.y (#3453)
* Prepare xu4 edge for 5.16.y, move current of imx6 to 5.15.y and edge to 5.16.y - fix bootsplash on 5.16.y * rk322x: advance current to 5.15 and edge to 5.16 * rockchip: advance current kernel to 5.15, edge to 5.16 * - adjust configs - fix bootsplash patches - adjust aufs * Switch sunxi / sunxi64 current to 5.15.y, edge to 5.16.y - cleanup bootsplash patches - adjust configs * Update mvebu64 Co-authored-by: Paolo Sabatino <paolo.sabatino@gmail.com>
This commit is contained in:
Igor Pečovnik
GitHub
parent
a037db891e
commit
1e37959e53
File diff suppressed because it is too large
Load Diff
@ -1,6 +1,6 @@
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#
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# Automatically generated file; DO NOT EDIT.
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# Linux/arm 5.15.1 Kernel Configuration
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# Linux/arm 5.16.8 Kernel Configuration
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#
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CONFIG_CC_VERSION_TEXT="arm-linux-gnueabihf-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0"
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CONFIG_CC_IS_GCC=y
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@ -18,6 +18,7 @@ CONFIG_CC_HAS_ASM_INLINE=y
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CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
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CONFIG_IRQ_WORK=y
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CONFIG_BUILDTIME_TABLE_SORT=y
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CONFIG_THREAD_INFO_IN_TASK=y
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#
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# General setup
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@ -69,7 +70,6 @@ CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
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CONFIG_GENERIC_IRQ_IPI=y
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CONFIG_GENERIC_MSI_IRQ=y
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CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
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CONFIG_HANDLE_DOMAIN_IRQ=y
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CONFIG_IRQ_FORCED_THREADING=y
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CONFIG_SPARSE_IRQ=y
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# CONFIG_GENERIC_IRQ_DEBUGFS is not set
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@ -108,6 +108,7 @@ CONFIG_BPF_JIT_DEFAULT_ON=y
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# CONFIG_BPF_LSM is not set
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# end of BPF subsystem
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CONFIG_PREEMPT_VOLUNTARY_BUILD=y
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# CONFIG_PREEMPT_NONE is not set
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CONFIG_PREEMPT_VOLUNTARY=y
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# CONFIG_PREEMPT is not set
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@ -164,6 +165,7 @@ CONFIG_GENERIC_SCHED_CLOCK=y
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# CONFIG_UCLAMP_TASK is not set
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# end of Scheduler features
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CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
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CONFIG_CGROUPS=y
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CONFIG_PAGE_COUNTER=y
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CONFIG_MEMCG=y
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@ -481,6 +483,7 @@ CONFIG_PXA_SSP=m
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CONFIG_ARCH_QCOM=y
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# CONFIG_ARCH_IPQ40XX is not set
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CONFIG_ARCH_MSM8X60=y
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# CONFIG_ARCH_MSM8916 is not set
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CONFIG_ARCH_MSM8960=y
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CONFIG_ARCH_MSM8974=y
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# CONFIG_ARCH_MDM9615 is not set
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@ -498,6 +501,7 @@ CONFIG_ARCH_STI=y
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CONFIG_SOC_STIH407=y
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CONFIG_ARCH_STM32=y
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CONFIG_MACH_STM32MP157=y
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CONFIG_MACH_STM32MP13=y
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CONFIG_ARCH_SUNXI=y
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CONFIG_MACH_SUN4I=y
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CONFIG_MACH_SUN5I=y
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@ -606,6 +610,7 @@ CONFIG_ARM_ERRATA_814220=y
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CONFIG_HAVE_SMP=y
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CONFIG_SMP=y
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CONFIG_SMP_ON_UP=y
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CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
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CONFIG_ARM_CPU_TOPOLOGY=y
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CONFIG_SCHED_MC=y
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CONFIG_SCHED_SMT=y
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@ -870,6 +875,7 @@ CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
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CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
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CONFIG_HAVE_EXIT_THREAD=y
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CONFIG_ARCH_MMAP_RND_BITS=8
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CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
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CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_OLD_SIGSUSPEND3=y
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@ -1024,6 +1030,7 @@ CONFIG_FLATMEM_MANUAL=y
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CONFIG_FLATMEM=y
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CONFIG_ARCH_KEEP_MEMBLOCK=y
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CONFIG_MEMORY_ISOLATION=y
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CONFIG_EXCLUSIVE_SYSTEM_RAM=y
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CONFIG_SPLIT_PTLOCK_CPUS=4
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CONFIG_MEMORY_BALLOON=y
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CONFIG_BALLOON_COMPACTION=y
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@ -1066,6 +1073,7 @@ CONFIG_ZONE_DMA=y
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# CONFIG_PERCPU_STATS is not set
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# CONFIG_GUP_TEST is not set
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CONFIG_KMAP_LOCAL=y
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CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
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#
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# Data Access Monitoring
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@ -1212,6 +1220,8 @@ CONFIG_BRIDGE_NETFILTER=m
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# Core Netfilter Configuration
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#
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CONFIG_NETFILTER_INGRESS=y
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CONFIG_NETFILTER_EGRESS=y
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CONFIG_NETFILTER_SKIP_EGRESS=y
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CONFIG_NETFILTER_NETLINK=m
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CONFIG_NETFILTER_FAMILY_BRIDGE=y
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CONFIG_NETFILTER_FAMILY_ARP=y
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@ -1623,10 +1633,11 @@ CONFIG_NET_DSA_TAG_DSA=m
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CONFIG_NET_DSA_TAG_EDSA=m
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CONFIG_NET_DSA_TAG_MTK=m
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CONFIG_NET_DSA_TAG_KSZ=m
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CONFIG_NET_DSA_TAG_RTL4_A=m
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CONFIG_NET_DSA_TAG_OCELOT=m
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CONFIG_NET_DSA_TAG_OCELOT_8021Q=m
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CONFIG_NET_DSA_TAG_QCA=m
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CONFIG_NET_DSA_TAG_RTL4_A=m
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CONFIG_NET_DSA_TAG_RTL8_4=m
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CONFIG_NET_DSA_TAG_LAN9303=m
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CONFIG_NET_DSA_TAG_SJA1105=m
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CONFIG_NET_DSA_TAG_TRAILER=m
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@ -1866,8 +1877,6 @@ CONFIG_CAN_M_CAN_PCI=m
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CONFIG_CAN_M_CAN_PLATFORM=m
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CONFIG_CAN_M_CAN_TCAN4X5X=m
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CONFIG_CAN_PEAK_PCIEFD=m
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# CONFIG_CAN_RCAR is not set
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# CONFIG_CAN_RCAR_CANFD is not set
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CONFIG_CAN_SJA1000=m
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CONFIG_CAN_EMS_PCI=m
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CONFIG_CAN_F81601=m
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@ -1970,7 +1979,7 @@ CONFIG_AF_RXRPC_DEBUG=y
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CONFIG_RXKAD=y
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CONFIG_AF_KCM=m
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CONFIG_STREAM_PARSER=y
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CONFIG_MCTP=m
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# CONFIG_MCTP is not set
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CONFIG_FIB_RULES=y
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CONFIG_WIRELESS=y
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CONFIG_WIRELESS_EXT=y
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@ -1988,6 +1997,8 @@ CONFIG_CFG80211_DEBUGFS=y
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CONFIG_CFG80211_CRDA_SUPPORT=y
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CONFIG_CFG80211_WEXT=y
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CONFIG_LIB80211=m
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CONFIG_LIB80211_CRYPT_WEP=m
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CONFIG_LIB80211_CRYPT_CCMP=m
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# CONFIG_LIB80211_DEBUG is not set
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CONFIG_MAC80211=m
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CONFIG_MAC80211_HAS_RC=y
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@ -2373,6 +2384,7 @@ CONFIG_MTD_BLOCK=m
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# CONFIG_SSFDC is not set
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# CONFIG_SM_FTL is not set
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# CONFIG_MTD_OOPS is not set
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CONFIG_MTD_PSTORE=m
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# CONFIG_MTD_SWAP is not set
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# CONFIG_MTD_PARTITIONED_MASTER is not set
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@ -2513,7 +2525,6 @@ CONFIG_OF_KOBJ=y
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CONFIG_OF_DYNAMIC=y
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CONFIG_OF_ADDRESS=y
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CONFIG_OF_IRQ=y
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CONFIG_OF_NET=y
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CONFIG_OF_RESERVED_MEM=y
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CONFIG_OF_RESOLVE=y
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CONFIG_OF_OVERLAY=y
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@ -2535,7 +2546,6 @@ CONFIG_ZRAM_DEF_COMP="lzo-rle"
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# CONFIG_ZRAM_MEMORY_TRACKING is not set
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CONFIG_BLK_DEV_LOOP=m
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CONFIG_BLK_DEV_LOOP_MIN_COUNT=0
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# CONFIG_BLK_DEV_CRYPTOLOOP is not set
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CONFIG_BLK_DEV_DRBD=m
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# CONFIG_DRBD_FAULT_INJECTION is not set
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CONFIG_BLK_DEV_NBD=m
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@ -2725,6 +2735,7 @@ CONFIG_SCSI_UFS_BSG=y
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CONFIG_SCSI_UFS_EXYNOS=m
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# CONFIG_SCSI_UFS_CRYPTO is not set
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# CONFIG_SCSI_UFS_HPB is not set
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# CONFIG_SCSI_UFS_HWMON is not set
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CONFIG_SCSI_HPTIOP=m
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CONFIG_SCSI_MYRB=m
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CONFIG_SCSI_MYRS=m
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@ -2931,6 +2942,7 @@ CONFIG_DM_SWITCH=m
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CONFIG_DM_LOG_WRITES=m
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CONFIG_DM_INTEGRITY=m
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CONFIG_DM_ZONED=m
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CONFIG_DM_AUDIT=y
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CONFIG_TARGET_CORE=m
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CONFIG_TCM_IBLOCK=m
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CONFIG_TCM_FILEIO=m
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@ -2974,6 +2986,7 @@ CONFIG_VXLAN=m
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CONFIG_GENEVE=m
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CONFIG_BAREUDP=m
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CONFIG_GTP=m
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CONFIG_AMT=m
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CONFIG_MACSEC=m
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CONFIG_NETCONSOLE=m
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CONFIG_NETCONSOLE_DYNAMIC=y
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@ -3055,6 +3068,8 @@ CONFIG_AQTION=m
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CONFIG_NET_VENDOR_ARC=y
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CONFIG_ARC_EMAC_CORE=m
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CONFIG_EMAC_ROCKCHIP=m
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CONFIG_NET_VENDOR_ASIX=y
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# CONFIG_SPI_AX88796C is not set
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CONFIG_NET_VENDOR_ATHEROS=y
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CONFIG_ATL2=m
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CONFIG_ATL1=m
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@ -3151,6 +3166,7 @@ CONFIG_I40E=m
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CONFIG_IAVF=m
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CONFIG_I40EVF=m
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CONFIG_ICE=m
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CONFIG_ICE_SWITCHDEV=y
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CONFIG_FM10K=m
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CONFIG_IGC=m
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CONFIG_NET_VENDOR_MICROSOFT=y
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@ -3349,10 +3365,6 @@ CONFIG_DP83869_PHY=m
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CONFIG_VITESSE_PHY=m
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CONFIG_XILINX_GMII2RGMII=m
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CONFIG_MICREL_KS8995MA=m
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#
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# MCTP Device Drivers
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#
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CONFIG_MDIO_DEVICE=y
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CONFIG_MDIO_BUS=y
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CONFIG_FWNODE_MDIO=y
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@ -3542,6 +3554,7 @@ CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
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# CONFIG_B43LEGACY_PIO_MODE is not set
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CONFIG_BRCMUTIL=m
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CONFIG_BRCMSMAC=m
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CONFIG_BRCMSMAC_LEDS=y
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CONFIG_BRCMFMAC=m
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CONFIG_BRCMFMAC_PROTO_BCDC=y
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CONFIG_BRCMFMAC_PROTO_MSGBUF=y
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@ -3624,7 +3637,9 @@ CONFIG_MT7663_USB_SDIO_COMMON=m
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CONFIG_MT7663U=m
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CONFIG_MT7663S=m
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CONFIG_MT7915E=m
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CONFIG_MT7921_COMMON=m
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CONFIG_MT7921E=m
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CONFIG_MT7921S=m
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CONFIG_WLAN_VENDOR_MICROCHIP=y
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# CONFIG_WILC1000_SDIO is not set
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# CONFIG_WILC1000_SPI is not set
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@ -3694,6 +3709,8 @@ CONFIG_RTW88_8723DE=m
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CONFIG_RTW88_8821CE=m
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# CONFIG_RTW88_DEBUG is not set
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# CONFIG_RTW88_DEBUGFS is not set
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CONFIG_RTW89=m
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# CONFIG_RTW89_8852AE is not set
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CONFIG_WLAN_VENDOR_RSI=y
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CONFIG_RSI_91X=m
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CONFIG_RSI_DEBUGFS=y
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@ -3719,7 +3736,6 @@ CONFIG_RTL8723DU=m
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CONFIG_RTL8723DS=m
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CONFIG_RTL8822CS=m
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CONFIG_RTL8822BU=m
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CONFIG_RTL8188EU=m
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CONFIG_RTL8821CU=m
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CONFIG_88XXAU=m
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CONFIG_RTL8192EU=m
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@ -3829,6 +3845,7 @@ CONFIG_KEYBOARD_TWL4030=m
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CONFIG_KEYBOARD_CROS_EC=m
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# CONFIG_KEYBOARD_CAP11XX is not set
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# CONFIG_KEYBOARD_BCM is not set
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CONFIG_KEYBOARD_CYPRESS_SF=m
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CONFIG_INPUT_MOUSE=y
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CONFIG_MOUSE_PS2=y
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CONFIG_MOUSE_PS2_ALPS=y
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@ -4121,7 +4138,6 @@ CONFIG_SERIAL_8250_DWLIB=y
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CONFIG_SERIAL_8250_BCM2835AUX=y
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CONFIG_SERIAL_8250_FSL=y
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CONFIG_SERIAL_8250_DW=y
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# CONFIG_SERIAL_8250_EM is not set
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CONFIG_SERIAL_8250_RT288X=y
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CONFIG_SERIAL_8250_OMAP=y
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CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP=y
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@ -4193,6 +4209,7 @@ CONFIG_NOZOMI=m
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CONFIG_NULL_TTY=m
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CONFIG_HVC_DRIVER=y
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# CONFIG_HVC_DCC is not set
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CONFIG_RPMSG_TTY=m
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CONFIG_SERIAL_DEV_BUS=y
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CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
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CONFIG_VIRTIO_CONSOLE=m
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@ -4203,6 +4220,7 @@ CONFIG_IPMI_PLAT_DATA=y
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CONFIG_IPMI_DEVICE_INTERFACE=m
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CONFIG_IPMI_SI=m
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CONFIG_IPMI_SSIF=m
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CONFIG_IPMI_IPMB=m
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CONFIG_IPMI_WATCHDOG=m
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CONFIG_IPMI_POWEROFF=m
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# CONFIG_IPMB_DEVICE_INTERFACE is not set
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@ -4390,6 +4408,7 @@ CONFIG_SPI_BCM2835AUX=m
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CONFIG_SPI_BITBANG=m
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CONFIG_SPI_CADENCE=m
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# CONFIG_SPI_CADENCE_QUADSPI is not set
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CONFIG_SPI_CADENCE_XSPI=m
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CONFIG_SPI_DESIGNWARE=m
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# CONFIG_SPI_DW_DMA is not set
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CONFIG_SPI_DW_PCI=m
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@ -4544,6 +4563,7 @@ CONFIG_PINCTRL_MSM8976=m
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# CONFIG_PINCTRL_MSM8994 is not set
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# CONFIG_PINCTRL_MSM8996 is not set
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CONFIG_PINCTRL_MSM8998=m
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CONFIG_PINCTRL_QCM2290=m
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# CONFIG_PINCTRL_QCS404 is not set
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CONFIG_PINCTRL_QCOM_SPMI_PMIC=m
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CONFIG_PINCTRL_QCOM_SSBI_PMIC=m
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@ -4555,6 +4575,7 @@ CONFIG_PINCTRL_SC8180X=m
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CONFIG_PINCTRL_SDX55=m
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CONFIG_PINCTRL_SM6115=m
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CONFIG_PINCTRL_SM6125=m
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CONFIG_PINCTRL_SM6350=m
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# CONFIG_PINCTRL_SM8150 is not set
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CONFIG_PINCTRL_SM8250=m
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CONFIG_PINCTRL_SM8350=m
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@ -4569,6 +4590,7 @@ CONFIG_PINCTRL_SAMSUNG=y
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CONFIG_PINCTRL_EXYNOS=y
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CONFIG_PINCTRL_EXYNOS_ARM=y
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CONFIG_PINCTRL_STM32=y
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CONFIG_PINCTRL_STM32MP135=y
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CONFIG_PINCTRL_STM32MP157=y
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CONFIG_PINCTRL_SUNXI=y
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CONFIG_PINCTRL_SUN4I_A10=y
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@ -4930,6 +4952,7 @@ CONFIG_SENSORS_MAX1668=m
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CONFIG_SENSORS_MAX197=m
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CONFIG_SENSORS_MAX31722=m
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CONFIG_SENSORS_MAX31730=m
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CONFIG_SENSORS_MAX6620=m
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CONFIG_SENSORS_MAX6621=m
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CONFIG_SENSORS_MAX6639=m
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CONFIG_SENSORS_MAX6642=m
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@ -5270,7 +5293,6 @@ CONFIG_MFD_HI6421_SPMI=m
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# CONFIG_HTC_I2CPLD is not set
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# CONFIG_LPC_ICH is not set
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# CONFIG_LPC_SCH is not set
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CONFIG_MFD_INTEL_PMT=m
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CONFIG_MFD_IQS62X=m
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# CONFIG_MFD_JANZ_CMODIO is not set
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# CONFIG_MFD_KEMPLD is not set
|
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@ -5342,7 +5364,6 @@ CONFIG_MFD_TPS65910=y
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CONFIG_MFD_TPS65912=y
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CONFIG_MFD_TPS65912_I2C=y
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CONFIG_MFD_TPS65912_SPI=y
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CONFIG_MFD_TPS80031=y
|
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CONFIG_TWL4030_CORE=y
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CONFIG_TWL4030_POWER=y
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CONFIG_MFD_TWL4030_AUDIO=y
|
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@ -5496,7 +5517,6 @@ CONFIG_REGULATOR_TPS6524X=m
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CONFIG_REGULATOR_TPS6586X=m
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CONFIG_REGULATOR_TPS65910=m
|
||||
CONFIG_REGULATOR_TPS65912=m
|
||||
CONFIG_REGULATOR_TPS80031=m
|
||||
CONFIG_REGULATOR_TWL4030=m
|
||||
CONFIG_REGULATOR_VCTRL=m
|
||||
CONFIG_REGULATOR_VEXPRESS=m
|
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@ -5541,12 +5561,15 @@ CONFIG_RC_ST=m
|
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CONFIG_IR_SUNXI=m
|
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CONFIG_IR_SERIAL=m
|
||||
CONFIG_IR_SERIAL_TRANSMITTER=y
|
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# CONFIG_IR_SIR is not set
|
||||
CONFIG_RC_XBOX_DVD=m
|
||||
CONFIG_IR_TOY=m
|
||||
CONFIG_CEC_CORE=m
|
||||
CONFIG_CEC_NOTIFIER=y
|
||||
CONFIG_CEC_PIN=y
|
||||
|
||||
#
|
||||
# CEC support
|
||||
#
|
||||
# CONFIG_MEDIA_CEC_RC is not set
|
||||
# CONFIG_CEC_PIN_ERROR_INJ is not set
|
||||
CONFIG_MEDIA_CEC_SUPPORT=y
|
||||
@ -5560,6 +5583,8 @@ CONFIG_CEC_STM32=m
|
||||
CONFIG_CEC_TEGRA=m
|
||||
CONFIG_USB_PULSE8_CEC=m
|
||||
CONFIG_USB_RAINSHADOW_CEC=m
|
||||
# end of CEC support
|
||||
|
||||
CONFIG_MEDIA_SUPPORT=m
|
||||
CONFIG_MEDIA_SUPPORT_FILTER=y
|
||||
CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
|
||||
@ -5605,10 +5630,6 @@ CONFIG_VIDEOBUF_VMALLOC=m
|
||||
#
|
||||
CONFIG_MEDIA_CONTROLLER_DVB=y
|
||||
CONFIG_MEDIA_CONTROLLER_REQUEST_API=y
|
||||
|
||||
#
|
||||
# Please notice that the enabled Media controller Request API is EXPERIMENTAL
|
||||
#
|
||||
# end of Media controller options
|
||||
|
||||
#
|
||||
@ -6004,6 +6025,7 @@ CONFIG_VIDEO_M52790=m
|
||||
CONFIG_VIDEO_APTINA_PLL=m
|
||||
CONFIG_VIDEO_CCS_PLL=m
|
||||
# CONFIG_VIDEO_HI556 is not set
|
||||
CONFIG_VIDEO_HI846=m
|
||||
CONFIG_VIDEO_IMX208=m
|
||||
CONFIG_VIDEO_IMX214=m
|
||||
CONFIG_VIDEO_IMX219=m
|
||||
@ -6039,6 +6061,7 @@ CONFIG_VIDEO_OV9282=m
|
||||
CONFIG_VIDEO_OV9640=m
|
||||
CONFIG_VIDEO_OV9650=m
|
||||
CONFIG_VIDEO_OV13858=m
|
||||
CONFIG_VIDEO_OV13B10=m
|
||||
CONFIG_VIDEO_VS6624=m
|
||||
CONFIG_VIDEO_MT9M001=m
|
||||
CONFIG_VIDEO_MT9M032=m
|
||||
@ -6470,6 +6493,7 @@ CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
|
||||
CONFIG_DRM_PANEL_DSI_CM=m
|
||||
CONFIG_DRM_PANEL_LVDS=m
|
||||
CONFIG_DRM_PANEL_SIMPLE=m
|
||||
CONFIG_DRM_PANEL_EDP=m
|
||||
CONFIG_DRM_PANEL_ELIDA_KD35T133=m
|
||||
CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m
|
||||
CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m
|
||||
@ -6502,6 +6526,7 @@ CONFIG_DRM_PANEL_RONBO_RB070D30=m
|
||||
CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
|
||||
CONFIG_DRM_PANEL_SAMSUNG_DB7430=m
|
||||
# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set
|
||||
CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m
|
||||
CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m
|
||||
CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
|
||||
# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
|
||||
@ -6512,6 +6537,7 @@ CONFIG_DRM_PANEL_SEIKO_43WVF1G=m
|
||||
CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
|
||||
CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
|
||||
CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m
|
||||
CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m
|
||||
CONFIG_DRM_PANEL_SITRONIX_ST7701=m
|
||||
CONFIG_DRM_PANEL_SITRONIX_ST7703=m
|
||||
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
|
||||
@ -7012,6 +7038,7 @@ CONFIG_SND_SOC_QCOM_COMMON=m
|
||||
CONFIG_SND_SOC_SC7180=m
|
||||
CONFIG_SND_SOC_ROCKCHIP=m
|
||||
CONFIG_SND_SOC_ROCKCHIP_I2S=m
|
||||
CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m
|
||||
CONFIG_SND_SOC_ROCKCHIP_PDM=m
|
||||
CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
|
||||
CONFIG_SND_SOC_ROCKCHIP_MAX98090=m
|
||||
@ -7068,6 +7095,11 @@ CONFIG_SND_SOC_TEGRA210_DMIC=m
|
||||
CONFIG_SND_SOC_TEGRA210_I2S=m
|
||||
CONFIG_SND_SOC_TEGRA186_DSPK=m
|
||||
CONFIG_SND_SOC_TEGRA210_ADMAIF=m
|
||||
CONFIG_SND_SOC_TEGRA210_MVC=m
|
||||
CONFIG_SND_SOC_TEGRA210_SFC=m
|
||||
CONFIG_SND_SOC_TEGRA210_AMX=m
|
||||
CONFIG_SND_SOC_TEGRA210_ADX=m
|
||||
CONFIG_SND_SOC_TEGRA210_MIXER=m
|
||||
CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD=m
|
||||
CONFIG_SND_SOC_TEGRA_MACHINE_DRV=m
|
||||
CONFIG_SND_SOC_TEGRA_RT5640=m
|
||||
@ -7147,6 +7179,8 @@ CONFIG_SND_SOC_CROS_EC_CODEC=m
|
||||
CONFIG_SND_SOC_CS35L34=m
|
||||
CONFIG_SND_SOC_CS35L35=m
|
||||
CONFIG_SND_SOC_CS35L36=m
|
||||
CONFIG_SND_SOC_CS35L41_SPI=m
|
||||
CONFIG_SND_SOC_CS35L41_I2C=m
|
||||
CONFIG_SND_SOC_CS42L42=m
|
||||
CONFIG_SND_SOC_CS42L51=m
|
||||
# CONFIG_SND_SOC_CS42L51_I2C is not set
|
||||
@ -7185,6 +7219,7 @@ CONFIG_SND_SOC_MAX98357A=m
|
||||
# CONFIG_SND_SOC_MAX98504 is not set
|
||||
CONFIG_SND_SOC_MAX9867=m
|
||||
CONFIG_SND_SOC_MAX98927=m
|
||||
CONFIG_SND_SOC_MAX98520=m
|
||||
CONFIG_SND_SOC_MAX98373=m
|
||||
CONFIG_SND_SOC_MAX98373_I2C=m
|
||||
CONFIG_SND_SOC_MAX98373_SDW=m
|
||||
@ -7234,6 +7269,7 @@ CONFIG_SND_SOC_RT711_SDCA_SDW=m
|
||||
CONFIG_SND_SOC_RT715=m
|
||||
CONFIG_SND_SOC_RT715_SDW=m
|
||||
CONFIG_SND_SOC_RT715_SDCA_SDW=m
|
||||
CONFIG_SND_SOC_RT9120=m
|
||||
CONFIG_SND_SOC_SGTL5000=m
|
||||
CONFIG_SND_SOC_SIGMADSP=m
|
||||
CONFIG_SND_SOC_SIGMADSP_REGMAP=m
|
||||
@ -7314,6 +7350,7 @@ CONFIG_SND_SOC_MT6660=m
|
||||
CONFIG_SND_SOC_NAU8315=m
|
||||
CONFIG_SND_SOC_NAU8540=m
|
||||
# CONFIG_SND_SOC_NAU8810 is not set
|
||||
CONFIG_SND_SOC_NAU8821=m
|
||||
CONFIG_SND_SOC_NAU8822=m
|
||||
CONFIG_SND_SOC_NAU8824=m
|
||||
CONFIG_SND_SOC_TPA6130A2=m
|
||||
@ -7326,6 +7363,9 @@ CONFIG_SND_SOC_LPASS_TX_MACRO=m
|
||||
CONFIG_SND_SIMPLE_CARD_UTILS=m
|
||||
CONFIG_SND_SIMPLE_CARD=m
|
||||
CONFIG_SND_AUDIO_GRAPH_CARD=m
|
||||
CONFIG_SND_AUDIO_GRAPH_CARD2=m
|
||||
CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=m
|
||||
# CONFIG_SND_TEST_COMPONENT is not set
|
||||
CONFIG_SND_SYNTH_EMUX=m
|
||||
CONFIG_SND_VIRTIO=m
|
||||
CONFIG_AC97_BUS=m
|
||||
@ -7384,6 +7424,7 @@ CONFIG_HID_KYE=m
|
||||
CONFIG_HID_UCLOGIC=m
|
||||
CONFIG_HID_WALTOP=m
|
||||
CONFIG_HID_VIEWSONIC=m
|
||||
CONFIG_HID_XIAOMI=m
|
||||
CONFIG_HID_GYRATION=m
|
||||
CONFIG_HID_ICADE=m
|
||||
CONFIG_HID_ITE=m
|
||||
@ -7407,6 +7448,8 @@ CONFIG_HID_MAYFLASH=m
|
||||
CONFIG_HID_MICROSOFT=m
|
||||
CONFIG_HID_MONTEREY=m
|
||||
CONFIG_HID_MULTITOUCH=m
|
||||
CONFIG_HID_NINTENDO=m
|
||||
# CONFIG_NINTENDO_FF is not set
|
||||
CONFIG_HID_NTI=m
|
||||
CONFIG_HID_NTRIG=m
|
||||
CONFIG_HID_ORTEK=m
|
||||
@ -8155,7 +8198,6 @@ CONFIG_RTC_DRV_TWL4030=m
|
||||
CONFIG_RTC_DRV_PALMAS=m
|
||||
CONFIG_RTC_DRV_TPS6586X=m
|
||||
CONFIG_RTC_DRV_TPS65910=m
|
||||
CONFIG_RTC_DRV_TPS80031=m
|
||||
# CONFIG_RTC_DRV_S35390A is not set
|
||||
# CONFIG_RTC_DRV_FM3130 is not set
|
||||
# CONFIG_RTC_DRV_RX8010 is not set
|
||||
@ -8236,7 +8278,6 @@ CONFIG_RTC_DRV_FSL_FTM_ALARM=m
|
||||
CONFIG_RTC_DRV_MESON=m
|
||||
CONFIG_RTC_DRV_MESON_VRTC=m
|
||||
CONFIG_RTC_DRV_OMAP=m
|
||||
CONFIG_HAVE_S3C_RTC=y
|
||||
CONFIG_RTC_DRV_S3C=m
|
||||
CONFIG_RTC_DRV_SA1100=m
|
||||
CONFIG_RTC_DRV_PL030=y
|
||||
@ -8339,6 +8380,7 @@ CONFIG_UDMABUF=y
|
||||
|
||||
CONFIG_AUXDISPLAY=y
|
||||
CONFIG_CHARLCD=m
|
||||
CONFIG_LINEDISP=m
|
||||
CONFIG_HD44780_COMMON=m
|
||||
CONFIG_HD44780=m
|
||||
# CONFIG_IMG_ASCII_LCD is not set
|
||||
@ -8377,6 +8419,7 @@ CONFIG_IRQ_BYPASS_MANAGER=m
|
||||
# CONFIG_VIRT_DRIVERS is not set
|
||||
CONFIG_VIRTIO=y
|
||||
CONFIG_VIRTIO_PCI_LIB=y
|
||||
CONFIG_VIRTIO_PCI_LIB_LEGACY=y
|
||||
CONFIG_VIRTIO_MENU=y
|
||||
CONFIG_VIRTIO_PCI=y
|
||||
CONFIG_VIRTIO_PCI_LEGACY=y
|
||||
@ -8604,6 +8647,7 @@ CONFIG_CROS_USBPD_NOTIFY=m
|
||||
CONFIG_MELLANOX_PLATFORM=y
|
||||
CONFIG_MLXREG_HOTPLUG=m
|
||||
CONFIG_MLXREG_IO=m
|
||||
CONFIG_MLXREG_LC=m
|
||||
CONFIG_OLPC_EC=y
|
||||
CONFIG_OLPC_XO175=y
|
||||
CONFIG_OLPC_XO175_EC=m
|
||||
@ -8614,7 +8658,7 @@ CONFIG_COMMON_CLK=y
|
||||
#
|
||||
# Clock driver for ARM Reference designs
|
||||
#
|
||||
CONFIG_ICST=y
|
||||
CONFIG_CLK_ICST=y
|
||||
CONFIG_CLK_SP810=y
|
||||
CONFIG_CLK_VEXPRESS_OSC=y
|
||||
# end of Clock driver for ARM Reference designs
|
||||
@ -8662,6 +8706,7 @@ CONFIG_CLK_IMX7ULP=y
|
||||
# CONFIG_CLK_IMX8MN is not set
|
||||
# CONFIG_CLK_IMX8MP is not set
|
||||
# CONFIG_CLK_IMX8MQ is not set
|
||||
CONFIG_CLK_IMX8ULP=m
|
||||
|
||||
#
|
||||
# Clock support for Amlogic platforms
|
||||
@ -8719,16 +8764,19 @@ CONFIG_MSM_MMCC_8996=m
|
||||
CONFIG_MSM_GCC_8998=m
|
||||
CONFIG_MSM_GPUCC_8998=m
|
||||
CONFIG_MSM_MMCC_8998=m
|
||||
CONFIG_QCM_GCC_2290=m
|
||||
CONFIG_QCS_GCC_404=m
|
||||
# CONFIG_SC_CAMCC_7180 is not set
|
||||
CONFIG_SC_CAMCC_7280=m
|
||||
CONFIG_SC_DISPCC_7180=m
|
||||
CONFIG_SC_DISPCC_7280=m
|
||||
CONFIG_SC_GCC_7180=m
|
||||
CONFIG_SC_GCC_7280=m
|
||||
CONFIG_SC_GCC_8180X=m
|
||||
CONFIG_SC_LPASS_CORECC_7180=m
|
||||
CONFIG_SC_GPUCC_7180=m
|
||||
CONFIG_SC_GPUCC_7280=m
|
||||
CONFIG_SC_LPASSCC_7280=m
|
||||
CONFIG_SC_LPASS_CORECC_7180=m
|
||||
CONFIG_SC_MSS_7180=m
|
||||
CONFIG_SC_VIDEOCC_7180=m
|
||||
CONFIG_SC_VIDEOCC_7280=m
|
||||
@ -8899,9 +8947,11 @@ CONFIG_QCOM_IOMMU=y
|
||||
CONFIG_REMOTEPROC=y
|
||||
# CONFIG_REMOTEPROC_CDEV is not set
|
||||
CONFIG_IMX_REMOTEPROC=m
|
||||
CONFIG_IMX_DSP_REMOTEPROC=m
|
||||
CONFIG_OMAP_REMOTEPROC=m
|
||||
# CONFIG_OMAP_REMOTEPROC_WATCHDOG is not set
|
||||
CONFIG_WKUP_M3_RPROC=m
|
||||
CONFIG_MESON_MX_AO_ARC_REMOTEPROC=m
|
||||
CONFIG_PRU_REMOTEPROC=m
|
||||
# CONFIG_QCOM_SYSMON is not set
|
||||
CONFIG_ST_REMOTEPROC=m
|
||||
@ -8988,6 +9038,7 @@ CONFIG_QCOM_RMTFS_MEM=m
|
||||
CONFIG_QCOM_RPMPD=m
|
||||
# CONFIG_QCOM_SMEM is not set
|
||||
CONFIG_QCOM_SMD_RPM=m
|
||||
CONFIG_QCOM_SPM=m
|
||||
CONFIG_QCOM_WCNSS_CTRL=m
|
||||
# CONFIG_QCOM_APR is not set
|
||||
# end of Qualcomm SoC drivers
|
||||
@ -9104,9 +9155,15 @@ CONFIG_IIO_TRIGGERED_EVENT=m
|
||||
#
|
||||
# CONFIG_ADIS16201 is not set
|
||||
# CONFIG_ADIS16209 is not set
|
||||
CONFIG_ADXL313=m
|
||||
CONFIG_ADXL313_I2C=m
|
||||
CONFIG_ADXL313_SPI=m
|
||||
CONFIG_ADXL345=m
|
||||
CONFIG_ADXL345_I2C=m
|
||||
CONFIG_ADXL345_SPI=m
|
||||
CONFIG_ADXL355=m
|
||||
CONFIG_ADXL355_I2C=m
|
||||
CONFIG_ADXL355_SPI=m
|
||||
CONFIG_ADXL372=m
|
||||
CONFIG_ADXL372_SPI=m
|
||||
CONFIG_ADXL372_I2C=m
|
||||
@ -9186,6 +9243,7 @@ CONFIG_EXYNOS_ADC=m
|
||||
# CONFIG_HX711 is not set
|
||||
# CONFIG_INA2XX_ADC is not set
|
||||
CONFIG_IMX7D_ADC=m
|
||||
CONFIG_IMX8QXP_ADC=m
|
||||
CONFIG_LP8788_ADC=m
|
||||
# CONFIG_LTC2471 is not set
|
||||
# CONFIG_LTC2485 is not set
|
||||
@ -9274,11 +9332,13 @@ CONFIG_PMS7003=m
|
||||
CONFIG_SCD30_CORE=m
|
||||
CONFIG_SCD30_I2C=m
|
||||
# CONFIG_SCD30_SERIAL is not set
|
||||
CONFIG_SCD4X=m
|
||||
CONFIG_SENSIRION_SGP30=m
|
||||
CONFIG_SENSIRION_SGP40=m
|
||||
CONFIG_SPS30=m
|
||||
CONFIG_SPS30_I2C=m
|
||||
CONFIG_SPS30_SERIAL=m
|
||||
CONFIG_SENSEAIR_SUNRISE_CO2=m
|
||||
# CONFIG_VZ89X is not set
|
||||
# end of Chemical Sensors
|
||||
|
||||
@ -9372,6 +9432,7 @@ CONFIG_TI_DAC7612=m
|
||||
#
|
||||
# CONFIG_ADF4350 is not set
|
||||
# CONFIG_ADF4371 is not set
|
||||
CONFIG_ADRF6780=m
|
||||
# end of Phase-Locked Loop (PLL) frequency synthesizers
|
||||
# end of Frequency Synthesizers DDS/PLL
|
||||
|
||||
@ -9662,6 +9723,7 @@ CONFIG_TMP117=m
|
||||
# CONFIG_TSYS01 is not set
|
||||
# CONFIG_TSYS02D is not set
|
||||
CONFIG_MAX31856=m
|
||||
CONFIG_MAX31865=m
|
||||
# end of Temperature sensors
|
||||
|
||||
# CONFIG_NTB is not set
|
||||
@ -9763,7 +9825,13 @@ CONFIG_PHY_MESON_G12A_USB3_PCIE=m
|
||||
CONFIG_PHY_MESON_AXG_PCIE=y
|
||||
CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG=y
|
||||
CONFIG_PHY_MESON_AXG_MIPI_DPHY=m
|
||||
|
||||
#
|
||||
# PHY drivers for Broadcom platforms
|
||||
#
|
||||
# CONFIG_BCM_KONA_USB2_PHY is not set
|
||||
# end of PHY drivers for Broadcom platforms
|
||||
|
||||
CONFIG_PHY_CADENCE_TORRENT=m
|
||||
CONFIG_PHY_CADENCE_DPHY=m
|
||||
CONFIG_PHY_CADENCE_SIERRA=m
|
||||
@ -10196,6 +10264,11 @@ CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
|
||||
# CONFIG_PSTORE_PMSG is not set
|
||||
# CONFIG_PSTORE_FTRACE is not set
|
||||
CONFIG_PSTORE_RAM=m
|
||||
CONFIG_PSTORE_ZONE=m
|
||||
CONFIG_PSTORE_BLK=m
|
||||
CONFIG_PSTORE_BLK_BLKDEV="m"
|
||||
CONFIG_PSTORE_BLK_KMSG_SIZE=64
|
||||
CONFIG_PSTORE_BLK_MAX_REASON=2
|
||||
CONFIG_SYSV_FS=m
|
||||
CONFIG_UFS_FS=m
|
||||
# CONFIG_UFS_FS_WRITE is not set
|
||||
@ -10268,7 +10341,6 @@ CONFIG_CIFS_DFS_UPCALL=y
|
||||
# CONFIG_CIFS_SWN_UPCALL is not set
|
||||
CONFIG_CIFS_FSCACHE=y
|
||||
CONFIG_SMB_SERVER=m
|
||||
CONFIG_SMB_SERVER_SMBDIRECT=y
|
||||
CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y
|
||||
CONFIG_SMB_SERVER_KERBEROS5=y
|
||||
CONFIG_SMBFS_COMMON=m
|
||||
@ -10357,7 +10429,6 @@ CONFIG_SECURITY_PATH=y
|
||||
CONFIG_LSM_MMAP_MIN_ADDR=0
|
||||
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
|
||||
CONFIG_HARDENED_USERCOPY=y
|
||||
CONFIG_HARDENED_USERCOPY_FALLBACK=y
|
||||
CONFIG_FORTIFY_SOURCE=y
|
||||
# CONFIG_STATIC_USERMODEHELPER is not set
|
||||
CONFIG_SECURITY_SELINUX=y
|
||||
@ -10779,6 +10850,7 @@ CONFIG_XZ_DEC_IA64=y
|
||||
CONFIG_XZ_DEC_ARM=y
|
||||
CONFIG_XZ_DEC_ARMTHUMB=y
|
||||
CONFIG_XZ_DEC_SPARC=y
|
||||
# CONFIG_XZ_DEC_MICROLZMA is not set
|
||||
CONFIG_XZ_DEC_BCJ=y
|
||||
# CONFIG_XZ_DEC_TEST is not set
|
||||
CONFIG_DECOMPRESS_GZIP=y
|
||||
@ -11167,6 +11239,7 @@ CONFIG_CMDLINE_KUNIT_TEST=m
|
||||
CONFIG_BITS_TEST=m
|
||||
CONFIG_SLUB_KUNIT_TEST=m
|
||||
CONFIG_RATIONAL_KUNIT_TEST=m
|
||||
CONFIG_MEMCPY_KUNIT_TEST=m
|
||||
# CONFIG_TEST_UDELAY is not set
|
||||
# CONFIG_TEST_STATIC_KEYS is not set
|
||||
# CONFIG_TEST_KMOD is not set
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,6 +1,6 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# Linux/arm64 5.15.1 Kernel Configuration
|
||||
# Linux/arm64 5.16.8 Kernel Configuration
|
||||
#
|
||||
CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0"
|
||||
CONFIG_CC_IS_GCC=y
|
||||
@ -59,7 +59,6 @@ CONFIG_GENERIC_IRQ_IPI=y
|
||||
CONFIG_GENERIC_MSI_IRQ=y
|
||||
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_IRQ_MSI_IOMMU=y
|
||||
CONFIG_HANDLE_DOMAIN_IRQ=y
|
||||
CONFIG_IRQ_FORCED_THREADING=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
|
||||
@ -69,6 +68,8 @@ CONFIG_GENERIC_TIME_VSYSCALL=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS=y
|
||||
CONFIG_ARCH_HAS_TICK_BROADCAST=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
|
||||
CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
|
||||
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
|
||||
|
||||
#
|
||||
# Timers subsystem
|
||||
@ -97,6 +98,7 @@ CONFIG_BPF_JIT_DEFAULT_ON=y
|
||||
# CONFIG_BPF_PRELOAD is not set
|
||||
# end of BPF subsystem
|
||||
|
||||
CONFIG_PREEMPT_BUILD=y
|
||||
# CONFIG_PREEMPT_NONE is not set
|
||||
# CONFIG_PREEMPT_VOLUNTARY is not set
|
||||
CONFIG_PREEMPT=y
|
||||
@ -153,6 +155,7 @@ CONFIG_GENERIC_SCHED_CLOCK=y
|
||||
|
||||
CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
|
||||
CONFIG_CC_HAS_INT128=y
|
||||
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
|
||||
CONFIG_ARCH_SUPPORTS_INT128=y
|
||||
# CONFIG_NUMA_BALANCING is not set
|
||||
CONFIG_CGROUPS=y
|
||||
@ -361,6 +364,15 @@ CONFIG_ARM64_ERRATUM_1286807=y
|
||||
CONFIG_ARM64_ERRATUM_1463225=y
|
||||
CONFIG_ARM64_ERRATUM_1542419=y
|
||||
CONFIG_ARM64_ERRATUM_1508412=y
|
||||
CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE=y
|
||||
CONFIG_ARM64_ERRATUM_2119858=y
|
||||
CONFIG_ARM64_ERRATUM_2139208=y
|
||||
CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
|
||||
CONFIG_ARM64_ERRATUM_2054223=y
|
||||
CONFIG_ARM64_ERRATUM_2067961=y
|
||||
CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE=y
|
||||
CONFIG_ARM64_ERRATUM_2253138=y
|
||||
CONFIG_ARM64_ERRATUM_2224489=y
|
||||
CONFIG_CAVIUM_ERRATUM_22375=y
|
||||
CONFIG_CAVIUM_ERRATUM_23144=y
|
||||
CONFIG_CAVIUM_ERRATUM_23154=y
|
||||
@ -388,6 +400,7 @@ CONFIG_ARM64_PA_BITS=48
|
||||
# CONFIG_CPU_BIG_ENDIAN is not set
|
||||
CONFIG_CPU_LITTLE_ENDIAN=y
|
||||
CONFIG_SCHED_MC=y
|
||||
CONFIG_SCHED_CLUSTER=y
|
||||
# CONFIG_SCHED_SMT is not set
|
||||
CONFIG_NR_CPUS=64
|
||||
CONFIG_HOTPLUG_CPU=y
|
||||
@ -396,6 +409,7 @@ CONFIG_NODES_SHIFT=2
|
||||
CONFIG_USE_PERCPU_NUMA_NODE_ID=y
|
||||
CONFIG_HAVE_SETUP_PER_CPU_AREA=y
|
||||
CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
|
||||
CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
|
||||
# CONFIG_HZ_100 is not set
|
||||
CONFIG_HZ_250=y
|
||||
# CONFIG_HZ_300 is not set
|
||||
@ -617,8 +631,7 @@ CONFIG_ACPI_GTDT=y
|
||||
CONFIG_ACPI_PPTT=y
|
||||
# CONFIG_PMIC_OPREGION is not set
|
||||
CONFIG_IRQ_BYPASS_MANAGER=y
|
||||
CONFIG_VIRTUALIZATION=y
|
||||
CONFIG_KVM=y
|
||||
CONFIG_HAVE_KVM=y
|
||||
CONFIG_HAVE_KVM_IRQCHIP=y
|
||||
CONFIG_HAVE_KVM_IRQFD=y
|
||||
CONFIG_HAVE_KVM_IRQ_ROUTING=y
|
||||
@ -632,6 +645,8 @@ CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
|
||||
CONFIG_HAVE_KVM_IRQ_BYPASS=y
|
||||
CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE=y
|
||||
CONFIG_KVM_XFER_TO_GUEST_WORK=y
|
||||
CONFIG_VIRTUALIZATION=y
|
||||
CONFIG_KVM=y
|
||||
# CONFIG_NVHE_EL2_DEBUG is not set
|
||||
CONFIG_ARM64_CRYPTO=y
|
||||
CONFIG_CRYPTO_SHA256_ARM64=y
|
||||
@ -665,6 +680,7 @@ CONFIG_JUMP_LABEL=y
|
||||
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
|
||||
CONFIG_HAVE_KPROBES=y
|
||||
CONFIG_HAVE_KRETPROBES=y
|
||||
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
|
||||
CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
|
||||
CONFIG_HAVE_NMI=y
|
||||
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
|
||||
@ -722,6 +738,7 @@ CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
|
||||
CONFIG_ARCH_MMAP_RND_BITS=18
|
||||
CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
|
||||
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
|
||||
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
|
||||
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
|
||||
CONFIG_CLONE_BACKWARDS=y
|
||||
CONFIG_OLD_SIGSUSPEND3=y
|
||||
@ -741,7 +758,6 @@ CONFIG_ARCH_USE_MEMREMAP_PROT=y
|
||||
# CONFIG_LOCK_EVENT_COUNTS is not set
|
||||
CONFIG_ARCH_HAS_RELR=y
|
||||
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
|
||||
CONFIG_HAVE_ARCH_PFN_VALID=y
|
||||
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
|
||||
|
||||
#
|
||||
@ -753,7 +769,6 @@ CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
|
||||
|
||||
CONFIG_HAVE_GCC_PLUGINS=y
|
||||
CONFIG_GCC_PLUGINS=y
|
||||
# CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set
|
||||
# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
|
||||
# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set
|
||||
# end of General architecture-dependent options
|
||||
@ -1044,6 +1059,8 @@ CONFIG_BRIDGE_NETFILTER=m
|
||||
# Core Netfilter Configuration
|
||||
#
|
||||
CONFIG_NETFILTER_INGRESS=y
|
||||
CONFIG_NETFILTER_EGRESS=y
|
||||
CONFIG_NETFILTER_SKIP_EGRESS=y
|
||||
CONFIG_NETFILTER_NETLINK=m
|
||||
CONFIG_NETFILTER_FAMILY_BRIDGE=y
|
||||
CONFIG_NETFILTER_FAMILY_ARP=y
|
||||
@ -1464,10 +1481,11 @@ CONFIG_NET_DSA_TAG_DSA=m
|
||||
CONFIG_NET_DSA_TAG_EDSA=m
|
||||
CONFIG_NET_DSA_TAG_MTK=m
|
||||
CONFIG_NET_DSA_TAG_KSZ=m
|
||||
CONFIG_NET_DSA_TAG_RTL4_A=m
|
||||
CONFIG_NET_DSA_TAG_OCELOT=m
|
||||
CONFIG_NET_DSA_TAG_OCELOT_8021Q=m
|
||||
CONFIG_NET_DSA_TAG_QCA=m
|
||||
CONFIG_NET_DSA_TAG_RTL4_A=m
|
||||
CONFIG_NET_DSA_TAG_RTL8_4=m
|
||||
CONFIG_NET_DSA_TAG_LAN9303=m
|
||||
CONFIG_NET_DSA_TAG_SJA1105=m
|
||||
CONFIG_NET_DSA_TAG_TRAILER=m
|
||||
@ -1772,7 +1790,7 @@ CONFIG_AF_RXRPC=m
|
||||
# CONFIG_AF_RXRPC_DEBUG is not set
|
||||
# CONFIG_RXKAD is not set
|
||||
# CONFIG_AF_KCM is not set
|
||||
CONFIG_MCTP=m
|
||||
CONFIG_MCTP=y
|
||||
CONFIG_FIB_RULES=y
|
||||
CONFIG_WIRELESS=y
|
||||
CONFIG_WIRELESS_EXT=y
|
||||
@ -2228,7 +2246,6 @@ CONFIG_OF_KOBJ=y
|
||||
CONFIG_OF_DYNAMIC=y
|
||||
CONFIG_OF_ADDRESS=y
|
||||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_NET=y
|
||||
CONFIG_OF_RESERVED_MEM=y
|
||||
# CONFIG_OF_OVERLAY is not set
|
||||
CONFIG_OF_NUMA=y
|
||||
@ -2255,7 +2272,6 @@ CONFIG_ZRAM_WRITEBACK=y
|
||||
# CONFIG_ZRAM_MEMORY_TRACKING is not set
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
|
||||
CONFIG_BLK_DEV_CRYPTOLOOP=y
|
||||
CONFIG_BLK_DEV_DRBD=m
|
||||
# CONFIG_DRBD_FAULT_INJECTION is not set
|
||||
CONFIG_BLK_DEV_NBD=m
|
||||
@ -2414,6 +2430,7 @@ CONFIG_SCSI_MVUMI=m
|
||||
CONFIG_SCSI_MPI3MR=m
|
||||
# CONFIG_SCSI_SMARTPQI is not set
|
||||
# CONFIG_SCSI_UFSHCD is not set
|
||||
CONFIG_SCSI_UFS_HWMON=y
|
||||
# CONFIG_SCSI_HPTIOP is not set
|
||||
CONFIG_SCSI_MYRB=m
|
||||
CONFIG_SCSI_MYRS=m
|
||||
@ -2589,6 +2606,7 @@ CONFIG_DM_VERITY_FEC=y
|
||||
CONFIG_DM_SWITCH=m
|
||||
CONFIG_DM_LOG_WRITES=m
|
||||
CONFIG_DM_INTEGRITY=m
|
||||
CONFIG_DM_AUDIT=y
|
||||
CONFIG_TARGET_CORE=m
|
||||
CONFIG_TCM_IBLOCK=m
|
||||
CONFIG_TCM_FILEIO=m
|
||||
@ -2624,6 +2642,7 @@ CONFIG_VXLAN=m
|
||||
CONFIG_GENEVE=m
|
||||
CONFIG_BAREUDP=m
|
||||
# CONFIG_GTP is not set
|
||||
CONFIG_AMT=m
|
||||
# CONFIG_MACSEC is not set
|
||||
# CONFIG_NETCONSOLE is not set
|
||||
CONFIG_TUN=y
|
||||
@ -2699,6 +2718,9 @@ CONFIG_NET_VENDOR_AMD=y
|
||||
CONFIG_NET_VENDOR_AQUANTIA=y
|
||||
# CONFIG_AQTION is not set
|
||||
CONFIG_NET_VENDOR_ARC=y
|
||||
CONFIG_NET_VENDOR_ASIX=y
|
||||
CONFIG_SPI_AX88796C=m
|
||||
# CONFIG_SPI_AX88796C_COMPRESSION is not set
|
||||
CONFIG_NET_VENDOR_ATHEROS=y
|
||||
# CONFIG_ATL2 is not set
|
||||
# CONFIG_ATL1 is not set
|
||||
@ -2772,6 +2794,7 @@ CONFIG_IXGBEVF=y
|
||||
# CONFIG_I40E is not set
|
||||
# CONFIG_I40EVF is not set
|
||||
CONFIG_ICE=m
|
||||
CONFIG_ICE_SWITCHDEV=y
|
||||
# CONFIG_FM10K is not set
|
||||
# CONFIG_IGC is not set
|
||||
CONFIG_NET_VENDOR_MICROSOFT=y
|
||||
@ -3232,7 +3255,9 @@ CONFIG_MT7663_USB_SDIO_COMMON=m
|
||||
CONFIG_MT7663U=m
|
||||
CONFIG_MT7663S=m
|
||||
CONFIG_MT7915E=m
|
||||
CONFIG_MT7921_COMMON=m
|
||||
CONFIG_MT7921E=m
|
||||
CONFIG_MT7921S=m
|
||||
CONFIG_WLAN_VENDOR_MICROCHIP=y
|
||||
# CONFIG_WILC1000_SDIO is not set
|
||||
# CONFIG_WILC1000_SPI is not set
|
||||
@ -3299,6 +3324,7 @@ CONFIG_RTW88_8723DE=m
|
||||
CONFIG_RTW88_8821CE=m
|
||||
# CONFIG_RTW88_DEBUG is not set
|
||||
# CONFIG_RTW88_DEBUGFS is not set
|
||||
# CONFIG_RTW89 is not set
|
||||
CONFIG_WLAN_VENDOR_RSI=y
|
||||
CONFIG_RSI_91X=m
|
||||
# CONFIG_RSI_DEBUGFS is not set
|
||||
@ -3324,7 +3350,6 @@ CONFIG_WILINK_PLATFORM_DATA=y
|
||||
CONFIG_RTL8723DS=m
|
||||
CONFIG_RTL8822CS=m
|
||||
CONFIG_RTL8822BU=m
|
||||
CONFIG_RTL8188EU=m
|
||||
CONFIG_RTL8821CU=m
|
||||
CONFIG_88XXAU=m
|
||||
CONFIG_RTL8192EU=m
|
||||
@ -3415,6 +3440,7 @@ CONFIG_KEYBOARD_IQS62X=m
|
||||
# CONFIG_KEYBOARD_XTKBD is not set
|
||||
# CONFIG_KEYBOARD_CAP11XX is not set
|
||||
# CONFIG_KEYBOARD_BCM is not set
|
||||
CONFIG_KEYBOARD_CYPRESS_SF=m
|
||||
CONFIG_INPUT_MOUSE=y
|
||||
CONFIG_MOUSE_PS2=y
|
||||
CONFIG_MOUSE_PS2_ALPS=y
|
||||
@ -3572,6 +3598,7 @@ CONFIG_HVC_IRQ=y
|
||||
CONFIG_HVC_XEN=y
|
||||
CONFIG_HVC_XEN_FRONTEND=y
|
||||
# CONFIG_HVC_DCC is not set
|
||||
CONFIG_RPMSG_TTY=m
|
||||
# CONFIG_SERIAL_DEV_BUS is not set
|
||||
CONFIG_TTY_PRINTK=m
|
||||
CONFIG_TTY_PRINTK_LEVEL=6
|
||||
@ -3720,6 +3747,7 @@ CONFIG_SPI_ARMADA_3700=y
|
||||
# CONFIG_SPI_BITBANG is not set
|
||||
# CONFIG_SPI_CADENCE is not set
|
||||
CONFIG_SPI_CADENCE_QUADSPI=m
|
||||
CONFIG_SPI_CADENCE_XSPI=m
|
||||
# CONFIG_SPI_DESIGNWARE is not set
|
||||
CONFIG_SPI_HISI_KUNPENG=m
|
||||
# CONFIG_SPI_HISI_SFC_V3XX is not set
|
||||
@ -4030,6 +4058,7 @@ CONFIG_SENSORS_MAX1668=m
|
||||
CONFIG_SENSORS_MAX197=m
|
||||
CONFIG_SENSORS_MAX31722=m
|
||||
# CONFIG_SENSORS_MAX31730 is not set
|
||||
CONFIG_SENSORS_MAX6620=m
|
||||
# CONFIG_SENSORS_MAX6621 is not set
|
||||
CONFIG_SENSORS_MAX6639=m
|
||||
CONFIG_SENSORS_MAX6642=m
|
||||
@ -4291,7 +4320,6 @@ CONFIG_MFD_MP2629=m
|
||||
# CONFIG_HTC_I2CPLD is not set
|
||||
# CONFIG_LPC_ICH is not set
|
||||
CONFIG_LPC_SCH=m
|
||||
CONFIG_MFD_INTEL_PMT=m
|
||||
CONFIG_MFD_IQS62X=m
|
||||
# CONFIG_MFD_JANZ_CMODIO is not set
|
||||
# CONFIG_MFD_KEMPLD is not set
|
||||
@ -4347,7 +4375,6 @@ CONFIG_MFD_TI_LP87565=m
|
||||
# CONFIG_MFD_TPS65910 is not set
|
||||
# CONFIG_MFD_TPS65912_I2C is not set
|
||||
# CONFIG_MFD_TPS65912_SPI is not set
|
||||
# CONFIG_MFD_TPS80031 is not set
|
||||
# CONFIG_TWL4030_CORE is not set
|
||||
# CONFIG_TWL6040_CORE is not set
|
||||
# CONFIG_MFD_WL1273_CORE is not set
|
||||
@ -4461,7 +4488,13 @@ CONFIG_IR_XMP_DECODER=y
|
||||
CONFIG_IR_IMON_DECODER=m
|
||||
# CONFIG_IR_RCMM_DECODER is not set
|
||||
# CONFIG_RC_DEVICES is not set
|
||||
|
||||
#
|
||||
# CEC support
|
||||
#
|
||||
# CONFIG_MEDIA_CEC_SUPPORT is not set
|
||||
# end of CEC support
|
||||
|
||||
CONFIG_MEDIA_SUPPORT=m
|
||||
# CONFIG_MEDIA_SUPPORT_FILTER is not set
|
||||
CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
|
||||
@ -4777,6 +4810,7 @@ CONFIG_VIDEO_ST_MIPID02=m
|
||||
#
|
||||
CONFIG_VIDEO_CCS_PLL=m
|
||||
CONFIG_VIDEO_HI556=m
|
||||
CONFIG_VIDEO_HI846=m
|
||||
CONFIG_VIDEO_IMX208=m
|
||||
CONFIG_VIDEO_IMX214=m
|
||||
CONFIG_VIDEO_IMX219=m
|
||||
@ -4814,6 +4848,7 @@ CONFIG_VIDEO_OV9282=m
|
||||
# CONFIG_VIDEO_OV9650 is not set
|
||||
CONFIG_VIDEO_OV9734=m
|
||||
# CONFIG_VIDEO_OV13858 is not set
|
||||
CONFIG_VIDEO_OV13B10=m
|
||||
# CONFIG_VIDEO_VS6624 is not set
|
||||
# CONFIG_VIDEO_MT9M001 is not set
|
||||
# CONFIG_VIDEO_MT9M032 is not set
|
||||
@ -5091,6 +5126,7 @@ CONFIG_DVB_SP2=m
|
||||
CONFIG_VGA_ARB=y
|
||||
CONFIG_VGA_ARB_MAX_GPUS=16
|
||||
# CONFIG_DRM is not set
|
||||
# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
|
||||
|
||||
#
|
||||
# ARM devices
|
||||
@ -5312,6 +5348,7 @@ CONFIG_HID_VIVALDI=m
|
||||
# CONFIG_HID_UCLOGIC is not set
|
||||
# CONFIG_HID_WALTOP is not set
|
||||
# CONFIG_HID_VIEWSONIC is not set
|
||||
CONFIG_HID_XIAOMI=m
|
||||
# CONFIG_HID_GYRATION is not set
|
||||
# CONFIG_HID_ICADE is not set
|
||||
CONFIG_HID_ITE=m
|
||||
@ -5334,6 +5371,8 @@ CONFIG_HID_LOGITECH=y
|
||||
CONFIG_HID_MICROSOFT=y
|
||||
CONFIG_HID_MONTEREY=y
|
||||
# CONFIG_HID_MULTITOUCH is not set
|
||||
CONFIG_HID_NINTENDO=m
|
||||
# CONFIG_NINTENDO_FF is not set
|
||||
# CONFIG_HID_NTI is not set
|
||||
# CONFIG_HID_NTRIG is not set
|
||||
# CONFIG_HID_ORTEK is not set
|
||||
@ -5689,7 +5728,6 @@ CONFIG_TYPEC_STUSB160X=m
|
||||
#
|
||||
# USB Type-C Alternate Mode drivers
|
||||
#
|
||||
# CONFIG_TYPEC_DP_ALTMODE is not set
|
||||
# end of USB Type-C Alternate Mode drivers
|
||||
|
||||
CONFIG_USB_ROLE_SWITCH=m
|
||||
@ -6008,8 +6046,10 @@ CONFIG_VFIO_PLATFORM=y
|
||||
# CONFIG_VFIO_PLATFORM_AMDXGBE_RESET is not set
|
||||
# CONFIG_VFIO_MDEV is not set
|
||||
CONFIG_VIRT_DRIVERS=y
|
||||
CONFIG_NITRO_ENCLAVES=m
|
||||
CONFIG_VIRTIO=y
|
||||
CONFIG_VIRTIO_PCI_LIB=y
|
||||
CONFIG_VIRTIO_PCI_LIB_LEGACY=y
|
||||
CONFIG_VIRTIO_MENU=y
|
||||
CONFIG_VIRTIO_PCI=y
|
||||
CONFIG_VIRTIO_PCI_LEGACY=y
|
||||
@ -6047,6 +6087,8 @@ CONFIG_XEN_GNTDEV=m
|
||||
CONFIG_XEN_GRANT_DEV_ALLOC=m
|
||||
# CONFIG_XEN_GRANT_DMA_ALLOC is not set
|
||||
CONFIG_SWIOTLB_XEN=y
|
||||
CONFIG_XEN_PCI_STUB=y
|
||||
CONFIG_XEN_PCIDEV_STUB=m
|
||||
# CONFIG_XEN_PVCALLS_FRONTEND is not set
|
||||
# CONFIG_XEN_PVCALLS_BACKEND is not set
|
||||
CONFIG_XEN_SCSI_BACKEND=m
|
||||
@ -6164,7 +6206,7 @@ CONFIG_COMMON_CLK=y
|
||||
#
|
||||
# Clock driver for ARM Reference designs
|
||||
#
|
||||
# CONFIG_ICST is not set
|
||||
# CONFIG_CLK_ICST is not set
|
||||
# CONFIG_CLK_SP810 is not set
|
||||
# CONFIG_CLK_VEXPRESS_OSC is not set
|
||||
# end of Clock driver for ARM Reference designs
|
||||
@ -6344,9 +6386,15 @@ CONFIG_IIO_TRIGGERED_EVENT=m
|
||||
#
|
||||
CONFIG_ADIS16201=m
|
||||
CONFIG_ADIS16209=m
|
||||
CONFIG_ADXL313=m
|
||||
CONFIG_ADXL313_I2C=m
|
||||
CONFIG_ADXL313_SPI=m
|
||||
CONFIG_ADXL345=m
|
||||
CONFIG_ADXL345_I2C=m
|
||||
CONFIG_ADXL345_SPI=m
|
||||
CONFIG_ADXL355=m
|
||||
CONFIG_ADXL355_I2C=m
|
||||
CONFIG_ADXL355_SPI=m
|
||||
# CONFIG_ADXL372_SPI is not set
|
||||
# CONFIG_ADXL372_I2C is not set
|
||||
CONFIG_BMA180=m
|
||||
@ -6488,10 +6536,12 @@ CONFIG_CCS811=m
|
||||
CONFIG_IAQCORE=m
|
||||
CONFIG_SCD30_CORE=m
|
||||
CONFIG_SCD30_I2C=m
|
||||
CONFIG_SCD4X=m
|
||||
# CONFIG_SENSIRION_SGP30 is not set
|
||||
CONFIG_SENSIRION_SGP40=m
|
||||
CONFIG_SPS30=m
|
||||
CONFIG_SPS30_I2C=m
|
||||
CONFIG_SENSEAIR_SUNRISE_CO2=m
|
||||
CONFIG_VZ89X=m
|
||||
# end of Chemical Sensors
|
||||
|
||||
@ -6582,6 +6632,7 @@ CONFIG_AD9523=m
|
||||
#
|
||||
CONFIG_ADF4350=m
|
||||
# CONFIG_ADF4371 is not set
|
||||
CONFIG_ADRF6780=m
|
||||
# end of Phase-Locked Loop (PLL) frequency synthesizers
|
||||
# end of Frequency Synthesizers DDS/PLL
|
||||
|
||||
@ -6872,6 +6923,7 @@ CONFIG_TMP117=m
|
||||
CONFIG_TSYS01=m
|
||||
CONFIG_TSYS02D=m
|
||||
# CONFIG_MAX31856 is not set
|
||||
CONFIG_MAX31865=m
|
||||
# end of Temperature sensors
|
||||
|
||||
# CONFIG_NTB is not set
|
||||
@ -6916,7 +6968,13 @@ CONFIG_RESET_CONTROLLER=y
|
||||
CONFIG_GENERIC_PHY=y
|
||||
CONFIG_PHY_XGENE=y
|
||||
CONFIG_PHY_CAN_TRANSCEIVER=m
|
||||
|
||||
#
|
||||
# PHY drivers for Broadcom platforms
|
||||
#
|
||||
# CONFIG_BCM_KONA_USB2_PHY is not set
|
||||
# end of PHY drivers for Broadcom platforms
|
||||
|
||||
CONFIG_PHY_CADENCE_TORRENT=m
|
||||
# CONFIG_PHY_CADENCE_DPHY is not set
|
||||
# CONFIG_PHY_CADENCE_SIERRA is not set
|
||||
@ -7197,10 +7255,8 @@ CONFIG_PNFS_FLEXFILE_LAYOUT=m
|
||||
CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
|
||||
CONFIG_NFS_V4_1_MIGRATION=y
|
||||
CONFIG_NFS_V4_SECURITY_LABEL=y
|
||||
CONFIG_NFS_FSCACHE=y
|
||||
# CONFIG_NFS_USE_LEGACY_DNS is not set
|
||||
CONFIG_NFS_USE_KERNEL_DNS=y
|
||||
CONFIG_NFS_DEBUG=y
|
||||
CONFIG_NFS_DISABLE_UDP_SUPPORT=y
|
||||
# CONFIG_NFS_V4_2_READ_PLUS is not set
|
||||
CONFIG_NFSD=m
|
||||
@ -7214,13 +7270,16 @@ CONFIG_NFSD_SCSILAYOUT=y
|
||||
CONFIG_NFSD_FLEXFILELAYOUT=y
|
||||
# CONFIG_NFSD_V4_2_INTER_SSC is not set
|
||||
CONFIG_NFSD_V4_SECURITY_LABEL=y
|
||||
CONFIG_GRACE_PERIOD=y
|
||||
CONFIG_LOCKD=y
|
||||
CONFIG_GRACE_PERIOD=m
|
||||
CONFIG_LOCKD=m
|
||||
CONFIG_LOCKD_V4=y
|
||||
CONFIG_NFS_ACL_SUPPORT=m
|
||||
CONFIG_NFS_COMMON=y
|
||||
CONFIG_SUNRPC=y
|
||||
CONFIG_NFS_V4_2_SSC_HELPER=y
|
||||
CONFIG_SUNRPC=m
|
||||
CONFIG_SUNRPC_GSS=m
|
||||
CONFIG_SUNRPC_BACKCHANNEL=y
|
||||
CONFIG_SUNRPC_SWAP=y
|
||||
CONFIG_RPCSEC_GSS_KRB5=m
|
||||
# CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES is not set
|
||||
# CONFIG_SUNRPC_DEBUG is not set
|
||||
@ -7237,7 +7296,6 @@ CONFIG_CIFS_POSIX=y
|
||||
# CONFIG_CIFS_DFS_UPCALL is not set
|
||||
# CONFIG_CIFS_SWN_UPCALL is not set
|
||||
CONFIG_SMB_SERVER=m
|
||||
CONFIG_SMB_SERVER_SMBDIRECT=y
|
||||
CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y
|
||||
CONFIG_SMB_SERVER_KERBEROS5=y
|
||||
CONFIG_SMBFS_COMMON=m
|
||||
@ -7396,7 +7454,6 @@ CONFIG_CRYPTO_PCRYPT=m
|
||||
CONFIG_CRYPTO_CRYPTD=y
|
||||
CONFIG_CRYPTO_AUTHENC=m
|
||||
CONFIG_CRYPTO_TEST=m
|
||||
CONFIG_CRYPTO_SIMD=y
|
||||
CONFIG_CRYPTO_ENGINE=m
|
||||
|
||||
#
|
||||
@ -7640,6 +7697,7 @@ CONFIG_XZ_DEC_IA64=y
|
||||
CONFIG_XZ_DEC_ARM=y
|
||||
CONFIG_XZ_DEC_ARMTHUMB=y
|
||||
CONFIG_XZ_DEC_SPARC=y
|
||||
# CONFIG_XZ_DEC_MICROLZMA is not set
|
||||
CONFIG_XZ_DEC_BCJ=y
|
||||
# CONFIG_XZ_DEC_TEST is not set
|
||||
CONFIG_DECOMPRESS_GZIP=y
|
||||
@ -7922,6 +7980,7 @@ CONFIG_CORESIGHT_SOURCE_ETM4X=y
|
||||
# CONFIG_ETM4X_IMPDEF_FEATURE is not set
|
||||
# CONFIG_CORESIGHT_STM is not set
|
||||
CONFIG_CORESIGHT_CPU_DEBUG=m
|
||||
# CONFIG_CORESIGHT_CPU_DEBUG_DEFAULT_ON is not set
|
||||
# CONFIG_CORESIGHT_CTI is not set
|
||||
CONFIG_CORESIGHT_TRBE=m
|
||||
# end of arm64 Debugging
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# Linux/arm 5.15.8 Kernel Configuration
|
||||
# Linux/arm 5.16.8 Kernel Configuration
|
||||
#
|
||||
CONFIG_CC_VERSION_TEXT="arm-linux-gnueabihf-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0"
|
||||
CONFIG_CC_IS_GCC=y
|
||||
@ -18,6 +18,7 @@ CONFIG_CC_HAS_ASM_INLINE=y
|
||||
CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
|
||||
CONFIG_IRQ_WORK=y
|
||||
CONFIG_BUILDTIME_TABLE_SORT=y
|
||||
CONFIG_THREAD_INFO_IN_TASK=y
|
||||
|
||||
#
|
||||
# General setup
|
||||
@ -64,7 +65,6 @@ CONFIG_HARDIRQS_SW_RESEND=y
|
||||
CONFIG_IRQ_DOMAIN=y
|
||||
CONFIG_IRQ_DOMAIN_HIERARCHY=y
|
||||
CONFIG_GENERIC_IRQ_IPI=y
|
||||
CONFIG_HANDLE_DOMAIN_IRQ=y
|
||||
CONFIG_IRQ_FORCED_THREADING=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
|
||||
@ -99,6 +99,7 @@ CONFIG_BPF_SYSCALL=y
|
||||
# CONFIG_BPF_PRELOAD is not set
|
||||
# end of BPF subsystem
|
||||
|
||||
CONFIG_PREEMPT_BUILD=y
|
||||
# CONFIG_PREEMPT_NONE is not set
|
||||
# CONFIG_PREEMPT_VOLUNTARY is not set
|
||||
CONFIG_PREEMPT=y
|
||||
@ -154,6 +155,7 @@ CONFIG_GENERIC_SCHED_CLOCK=y
|
||||
# CONFIG_UCLAMP_TASK is not set
|
||||
# end of Scheduler features
|
||||
|
||||
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
|
||||
CONFIG_CGROUPS=y
|
||||
CONFIG_PAGE_COUNTER=y
|
||||
CONFIG_MEMCG=y
|
||||
@ -448,6 +450,7 @@ CONFIG_ARM_ERRATA_814220=y
|
||||
CONFIG_HAVE_SMP=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SMP_ON_UP=y
|
||||
CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
|
||||
CONFIG_ARM_CPU_TOPOLOGY=y
|
||||
# CONFIG_SCHED_MC is not set
|
||||
# CONFIG_SCHED_SMT is not set
|
||||
@ -679,6 +682,7 @@ CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
|
||||
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
|
||||
CONFIG_HAVE_EXIT_THREAD=y
|
||||
CONFIG_ARCH_MMAP_RND_BITS=8
|
||||
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
|
||||
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
|
||||
CONFIG_CLONE_BACKWARDS=y
|
||||
CONFIG_OLD_SIGSUSPEND3=y
|
||||
@ -980,6 +984,8 @@ CONFIG_BRIDGE_NETFILTER=m
|
||||
# Core Netfilter Configuration
|
||||
#
|
||||
CONFIG_NETFILTER_INGRESS=y
|
||||
CONFIG_NETFILTER_EGRESS=y
|
||||
CONFIG_NETFILTER_SKIP_EGRESS=y
|
||||
CONFIG_NETFILTER_NETLINK=m
|
||||
CONFIG_NETFILTER_FAMILY_BRIDGE=y
|
||||
CONFIG_NETFILTER_FAMILY_ARP=y
|
||||
@ -1581,8 +1587,6 @@ CONFIG_CAN_CALC_BITTIMING=y
|
||||
# CONFIG_CAN_CC770 is not set
|
||||
# CONFIG_CAN_IFI_CANFD is not set
|
||||
# CONFIG_CAN_M_CAN is not set
|
||||
# CONFIG_CAN_RCAR is not set
|
||||
# CONFIG_CAN_RCAR_CANFD is not set
|
||||
# CONFIG_CAN_SJA1000 is not set
|
||||
# CONFIG_CAN_SOFTING is not set
|
||||
|
||||
@ -1825,7 +1829,6 @@ CONFIG_OF_EARLY_FLATTREE=y
|
||||
CONFIG_OF_KOBJ=y
|
||||
CONFIG_OF_ADDRESS=y
|
||||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_NET=y
|
||||
CONFIG_OF_RESERVED_MEM=y
|
||||
# CONFIG_OF_OVERLAY is not set
|
||||
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
|
||||
@ -1848,7 +1851,6 @@ CONFIG_ZRAM_WRITEBACK=y
|
||||
# CONFIG_ZRAM_MEMORY_TRACKING is not set
|
||||
CONFIG_BLK_DEV_LOOP=m
|
||||
CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
|
||||
CONFIG_BLK_DEV_CRYPTOLOOP=m
|
||||
CONFIG_BLK_DEV_DRBD=m
|
||||
# CONFIG_DRBD_FAULT_INJECTION is not set
|
||||
CONFIG_BLK_DEV_NBD=m
|
||||
@ -1927,7 +1929,7 @@ CONFIG_UACCE=m
|
||||
#
|
||||
CONFIG_SCSI_MOD=m
|
||||
CONFIG_RAID_ATTRS=m
|
||||
CONFIG_SCSI_COMMON=y
|
||||
CONFIG_SCSI_COMMON=m
|
||||
CONFIG_SCSI=m
|
||||
CONFIG_SCSI_DMA=y
|
||||
CONFIG_SCSI_PROC_FS=y
|
||||
@ -1960,6 +1962,7 @@ CONFIG_SCSI_LOWLEVEL=y
|
||||
CONFIG_ISCSI_TCP=m
|
||||
CONFIG_ISCSI_BOOT_SYSFS=m
|
||||
# CONFIG_SCSI_UFSHCD is not set
|
||||
# CONFIG_SCSI_UFS_HWMON is not set
|
||||
# CONFIG_SCSI_DEBUG is not set
|
||||
CONFIG_SCSI_VIRTIO=m
|
||||
# CONFIG_SCSI_DH is not set
|
||||
@ -2016,6 +2019,7 @@ CONFIG_DM_SWITCH=m
|
||||
CONFIG_DM_LOG_WRITES=m
|
||||
CONFIG_DM_INTEGRITY=m
|
||||
CONFIG_DM_ZONED=m
|
||||
CONFIG_DM_AUDIT=y
|
||||
CONFIG_TARGET_CORE=m
|
||||
CONFIG_TCM_IBLOCK=m
|
||||
CONFIG_TCM_FILEIO=m
|
||||
@ -2046,6 +2050,7 @@ CONFIG_VXLAN=m
|
||||
# CONFIG_GENEVE is not set
|
||||
CONFIG_BAREUDP=m
|
||||
# CONFIG_GTP is not set
|
||||
CONFIG_AMT=m
|
||||
CONFIG_MACSEC=m
|
||||
CONFIG_NETCONSOLE=m
|
||||
CONFIG_NETCONSOLE_DYNAMIC=y
|
||||
@ -2068,6 +2073,9 @@ CONFIG_NET_VENDOR_ALACRITECH=y
|
||||
CONFIG_NET_VENDOR_AMAZON=y
|
||||
CONFIG_NET_VENDOR_AQUANTIA=y
|
||||
CONFIG_NET_VENDOR_ARC=y
|
||||
CONFIG_NET_VENDOR_ASIX=y
|
||||
CONFIG_SPI_AX88796C=m
|
||||
# CONFIG_SPI_AX88796C_COMPRESSION is not set
|
||||
CONFIG_NET_VENDOR_BROADCOM=y
|
||||
# CONFIG_B44 is not set
|
||||
# CONFIG_BCMGENET is not set
|
||||
@ -2365,6 +2373,7 @@ CONFIG_MT7601U=m
|
||||
CONFIG_MT76_CORE=m
|
||||
CONFIG_MT76_LEDS=y
|
||||
CONFIG_MT76_USB=m
|
||||
CONFIG_MT76_SDIO=m
|
||||
CONFIG_MT76x02_LIB=m
|
||||
CONFIG_MT76x02_USB=m
|
||||
CONFIG_MT76_CONNAC_LIB=m
|
||||
@ -2376,6 +2385,8 @@ CONFIG_MT7615_COMMON=m
|
||||
CONFIG_MT7663_USB_SDIO_COMMON=m
|
||||
CONFIG_MT7663U=m
|
||||
# CONFIG_MT7663S is not set
|
||||
CONFIG_MT7921_COMMON=m
|
||||
CONFIG_MT7921S=m
|
||||
CONFIG_WLAN_VENDOR_MICROCHIP=y
|
||||
# CONFIG_WILC1000_SDIO is not set
|
||||
# CONFIG_WILC1000_SPI is not set
|
||||
@ -2408,6 +2419,7 @@ CONFIG_RTL8192C_COMMON=m
|
||||
CONFIG_RTL8XXXU=m
|
||||
# CONFIG_RTL8XXXU_UNTESTED is not set
|
||||
CONFIG_RTW88=m
|
||||
CONFIG_RTW89=m
|
||||
CONFIG_WLAN_VENDOR_RSI=y
|
||||
# CONFIG_RSI_91X is not set
|
||||
CONFIG_WLAN_VENDOR_ST=y
|
||||
@ -2422,7 +2434,6 @@ CONFIG_RTL8723DU=m
|
||||
CONFIG_RTL8723DS=m
|
||||
CONFIG_RTL8822CS=m
|
||||
CONFIG_RTL8822BU=m
|
||||
CONFIG_RTL8188EU=m
|
||||
CONFIG_RTL8821CU=m
|
||||
CONFIG_88XXAU=m
|
||||
CONFIG_RTL8192EU=m
|
||||
@ -2526,6 +2537,7 @@ CONFIG_KEYBOARD_IQS62X=m
|
||||
CONFIG_KEYBOARD_CROS_EC=m
|
||||
# CONFIG_KEYBOARD_CAP11XX is not set
|
||||
# CONFIG_KEYBOARD_BCM is not set
|
||||
CONFIG_KEYBOARD_CYPRESS_SF=m
|
||||
CONFIG_INPUT_MOUSE=y
|
||||
# CONFIG_MOUSE_PS2 is not set
|
||||
# CONFIG_MOUSE_SERIAL is not set
|
||||
@ -2771,7 +2783,6 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4
|
||||
# CONFIG_SERIAL_8250_EXTENDED is not set
|
||||
# CONFIG_SERIAL_8250_ASPEED_VUART is not set
|
||||
# CONFIG_SERIAL_8250_DW is not set
|
||||
# CONFIG_SERIAL_8250_EM is not set
|
||||
# CONFIG_SERIAL_8250_RT288X is not set
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
|
||||
@ -3242,6 +3253,7 @@ CONFIG_SENSORS_MAX127=m
|
||||
# CONFIG_SENSORS_MAX197 is not set
|
||||
# CONFIG_SENSORS_MAX31722 is not set
|
||||
CONFIG_SENSORS_MAX31730=m
|
||||
CONFIG_SENSORS_MAX6620=m
|
||||
# CONFIG_SENSORS_MAX6621 is not set
|
||||
# CONFIG_SENSORS_MAX6639 is not set
|
||||
# CONFIG_SENSORS_MAX6642 is not set
|
||||
@ -3481,7 +3493,6 @@ CONFIG_MFD_TPS65090=y
|
||||
# CONFIG_MFD_TPS65910 is not set
|
||||
# CONFIG_MFD_TPS65912_I2C is not set
|
||||
# CONFIG_MFD_TPS65912_SPI is not set
|
||||
# CONFIG_MFD_TPS80031 is not set
|
||||
# CONFIG_TWL4030_CORE is not set
|
||||
# CONFIG_TWL6040_CORE is not set
|
||||
# CONFIG_MFD_WL1273_CORE is not set
|
||||
@ -3621,11 +3632,14 @@ CONFIG_IR_TTUSBIR=m
|
||||
# CONFIG_RC_LOOPBACK is not set
|
||||
CONFIG_IR_GPIO_CIR=y
|
||||
# CONFIG_IR_SERIAL is not set
|
||||
# CONFIG_IR_SIR is not set
|
||||
# CONFIG_RC_XBOX_DVD is not set
|
||||
CONFIG_IR_TOY=m
|
||||
CONFIG_CEC_CORE=y
|
||||
CONFIG_CEC_NOTIFIER=y
|
||||
|
||||
#
|
||||
# CEC support
|
||||
#
|
||||
# CONFIG_MEDIA_CEC_RC is not set
|
||||
CONFIG_MEDIA_CEC_SUPPORT=y
|
||||
CONFIG_CEC_CH7322=m
|
||||
@ -3634,6 +3648,8 @@ CONFIG_CEC_CROS_EC=m
|
||||
CONFIG_CEC_SAMSUNG_S5P=m
|
||||
# CONFIG_USB_PULSE8_CEC is not set
|
||||
# CONFIG_USB_RAINSHADOW_CEC is not set
|
||||
# end of CEC support
|
||||
|
||||
CONFIG_MEDIA_SUPPORT=y
|
||||
CONFIG_MEDIA_SUPPORT_FILTER=y
|
||||
CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
|
||||
@ -3924,6 +3940,7 @@ CONFIG_VIDEO_CX25840=m
|
||||
CONFIG_VIDEO_APTINA_PLL=m
|
||||
CONFIG_VIDEO_CCS_PLL=m
|
||||
CONFIG_VIDEO_HI556=m
|
||||
CONFIG_VIDEO_HI846=m
|
||||
CONFIG_VIDEO_IMX208=m
|
||||
CONFIG_VIDEO_IMX214=m
|
||||
CONFIG_VIDEO_IMX219=m
|
||||
@ -3959,6 +3976,7 @@ CONFIG_VIDEO_OV8865=m
|
||||
CONFIG_VIDEO_OV9640=m
|
||||
CONFIG_VIDEO_OV9650=m
|
||||
CONFIG_VIDEO_OV13858=m
|
||||
CONFIG_VIDEO_OV13B10=m
|
||||
CONFIG_VIDEO_VS6624=m
|
||||
CONFIG_VIDEO_MT9M001=m
|
||||
CONFIG_VIDEO_MT9M032=m
|
||||
@ -4191,7 +4209,7 @@ CONFIG_DVB_SP2=m
|
||||
CONFIG_DRM=y
|
||||
CONFIG_DRM_MIPI_DBI=m
|
||||
CONFIG_DRM_MIPI_DSI=y
|
||||
CONFIG_DRM_DP_AUX_BUS=y
|
||||
CONFIG_DRM_DP_AUX_BUS=m
|
||||
# CONFIG_DRM_DP_AUX_CHARDEV is not set
|
||||
# CONFIG_DRM_DEBUG_MM is not set
|
||||
CONFIG_DRM_KMS_HELPER=y
|
||||
@ -4272,6 +4290,7 @@ CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
|
||||
CONFIG_DRM_PANEL_DSI_CM=m
|
||||
# CONFIG_DRM_PANEL_LVDS is not set
|
||||
CONFIG_DRM_PANEL_SIMPLE=y
|
||||
CONFIG_DRM_PANEL_EDP=m
|
||||
CONFIG_DRM_PANEL_ELIDA_KD35T133=m
|
||||
CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m
|
||||
# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set
|
||||
@ -4304,6 +4323,7 @@ CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
|
||||
# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set
|
||||
# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set
|
||||
# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set
|
||||
CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m
|
||||
# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set
|
||||
CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=y
|
||||
# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
|
||||
@ -4314,6 +4334,7 @@ CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m
|
||||
# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set
|
||||
# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set
|
||||
# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set
|
||||
CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m
|
||||
# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set
|
||||
CONFIG_DRM_PANEL_SITRONIX_ST7703=m
|
||||
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
|
||||
@ -4634,6 +4655,8 @@ CONFIG_SND_SOC_CROS_EC_CODEC=m
|
||||
# CONFIG_SND_SOC_CS35L34 is not set
|
||||
# CONFIG_SND_SOC_CS35L35 is not set
|
||||
CONFIG_SND_SOC_CS35L36=m
|
||||
CONFIG_SND_SOC_CS35L41_SPI=m
|
||||
CONFIG_SND_SOC_CS35L41_I2C=m
|
||||
# CONFIG_SND_SOC_CS42L42 is not set
|
||||
# CONFIG_SND_SOC_CS42L51_I2C is not set
|
||||
# CONFIG_SND_SOC_CS42L52 is not set
|
||||
@ -4668,6 +4691,7 @@ CONFIG_SND_SOC_MAX98357A=m
|
||||
# CONFIG_SND_SOC_MAX98504 is not set
|
||||
CONFIG_SND_SOC_MAX9867=m
|
||||
# CONFIG_SND_SOC_MAX98927 is not set
|
||||
CONFIG_SND_SOC_MAX98520=m
|
||||
CONFIG_SND_SOC_MAX98373=m
|
||||
CONFIG_SND_SOC_MAX98373_I2C=m
|
||||
CONFIG_SND_SOC_MAX98390=m
|
||||
@ -4693,6 +4717,7 @@ CONFIG_SND_SOC_RL6231=m
|
||||
CONFIG_SND_SOC_RT5631=m
|
||||
CONFIG_SND_SOC_RT5640=m
|
||||
CONFIG_SND_SOC_RT5659=m
|
||||
CONFIG_SND_SOC_RT9120=m
|
||||
# CONFIG_SND_SOC_SGTL5000 is not set
|
||||
CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
|
||||
CONFIG_SND_SOC_SIMPLE_MUX=m
|
||||
@ -4761,6 +4786,7 @@ CONFIG_SND_SOC_MT6660=m
|
||||
CONFIG_SND_SOC_NAU8315=m
|
||||
# CONFIG_SND_SOC_NAU8540 is not set
|
||||
# CONFIG_SND_SOC_NAU8810 is not set
|
||||
CONFIG_SND_SOC_NAU8821=m
|
||||
CONFIG_SND_SOC_NAU8822=m
|
||||
# CONFIG_SND_SOC_NAU8824 is not set
|
||||
# CONFIG_SND_SOC_TPA6130A2 is not set
|
||||
@ -4773,6 +4799,9 @@ CONFIG_SND_SOC_LPASS_TX_MACRO=m
|
||||
CONFIG_SND_SIMPLE_CARD_UTILS=y
|
||||
CONFIG_SND_SIMPLE_CARD=y
|
||||
# CONFIG_SND_AUDIO_GRAPH_CARD is not set
|
||||
CONFIG_SND_AUDIO_GRAPH_CARD2=m
|
||||
CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=m
|
||||
CONFIG_SND_TEST_COMPONENT=m
|
||||
CONFIG_SND_VIRTIO=m
|
||||
|
||||
#
|
||||
@ -4829,6 +4858,7 @@ CONFIG_HID_KYE=m
|
||||
CONFIG_HID_UCLOGIC=m
|
||||
CONFIG_HID_WALTOP=m
|
||||
CONFIG_HID_VIEWSONIC=m
|
||||
CONFIG_HID_XIAOMI=m
|
||||
CONFIG_HID_GYRATION=m
|
||||
CONFIG_HID_ICADE=m
|
||||
CONFIG_HID_ITE=m
|
||||
@ -4852,6 +4882,8 @@ CONFIG_HID_REDRAGON=y
|
||||
CONFIG_HID_MICROSOFT=m
|
||||
CONFIG_HID_MONTEREY=m
|
||||
CONFIG_HID_MULTITOUCH=m
|
||||
CONFIG_HID_NINTENDO=m
|
||||
# CONFIG_NINTENDO_FF is not set
|
||||
CONFIG_HID_NTI=m
|
||||
CONFIG_HID_NTRIG=m
|
||||
CONFIG_HID_ORTEK=m
|
||||
@ -5455,7 +5487,6 @@ CONFIG_RTC_DRV_NTXEC=m
|
||||
#
|
||||
# on-CPU RTC drivers
|
||||
#
|
||||
CONFIG_HAVE_S3C_RTC=y
|
||||
CONFIG_RTC_DRV_S3C=y
|
||||
# CONFIG_RTC_DRV_PL030 is not set
|
||||
# CONFIG_RTC_DRV_PL031 is not set
|
||||
@ -5566,7 +5597,6 @@ CONFIG_RTLLIB_CRYPTO_WEP=m
|
||||
CONFIG_RTL8723BS=m
|
||||
CONFIG_R8712U=m
|
||||
CONFIG_R8188EU=m
|
||||
CONFIG_88EU_AP_MODE=y
|
||||
CONFIG_VT6656=m
|
||||
|
||||
#
|
||||
@ -5677,7 +5707,7 @@ CONFIG_COMMON_CLK=y
|
||||
#
|
||||
# Clock driver for ARM Reference designs
|
||||
#
|
||||
# CONFIG_ICST is not set
|
||||
# CONFIG_CLK_ICST is not set
|
||||
# CONFIG_CLK_SP810 is not set
|
||||
# end of Clock driver for ARM Reference designs
|
||||
|
||||
@ -5877,8 +5907,14 @@ CONFIG_IIO_TRIGGERED_EVENT=m
|
||||
#
|
||||
# CONFIG_ADIS16201 is not set
|
||||
# CONFIG_ADIS16209 is not set
|
||||
CONFIG_ADXL313=m
|
||||
CONFIG_ADXL313_I2C=m
|
||||
CONFIG_ADXL313_SPI=m
|
||||
# CONFIG_ADXL345_I2C is not set
|
||||
# CONFIG_ADXL345_SPI is not set
|
||||
CONFIG_ADXL355=m
|
||||
CONFIG_ADXL355_I2C=m
|
||||
CONFIG_ADXL355_SPI=m
|
||||
# CONFIG_ADXL372_SPI is not set
|
||||
# CONFIG_ADXL372_I2C is not set
|
||||
# CONFIG_BMA180 is not set
|
||||
@ -6014,10 +6050,12 @@ CONFIG_BME680_SPI=m
|
||||
# CONFIG_IAQCORE is not set
|
||||
CONFIG_SCD30_CORE=m
|
||||
CONFIG_SCD30_I2C=m
|
||||
CONFIG_SCD4X=m
|
||||
CONFIG_SENSIRION_SGP30=m
|
||||
# CONFIG_SENSIRION_SGP40 is not set
|
||||
CONFIG_SPS30=m
|
||||
CONFIG_SPS30_I2C=m
|
||||
CONFIG_SENSEAIR_SUNRISE_CO2=m
|
||||
# CONFIG_VZ89X is not set
|
||||
# end of Chemical Sensors
|
||||
|
||||
@ -6105,6 +6143,7 @@ CONFIG_AD5770R=m
|
||||
#
|
||||
# CONFIG_ADF4350 is not set
|
||||
# CONFIG_ADF4371 is not set
|
||||
CONFIG_ADRF6780=m
|
||||
# end of Phase-Locked Loop (PLL) frequency synthesizers
|
||||
# end of Frequency Synthesizers DDS/PLL
|
||||
|
||||
@ -6372,6 +6411,7 @@ CONFIG_TMP117=m
|
||||
# CONFIG_TSYS01 is not set
|
||||
# CONFIG_TSYS02D is not set
|
||||
# CONFIG_MAX31856 is not set
|
||||
CONFIG_MAX31865=m
|
||||
# end of Temperature sensors
|
||||
|
||||
CONFIG_PWM=y
|
||||
@ -6405,7 +6445,13 @@ CONFIG_EXYNOS_IRQ_COMBINER=y
|
||||
CONFIG_GENERIC_PHY=y
|
||||
CONFIG_GENERIC_PHY_MIPI_DPHY=y
|
||||
CONFIG_PHY_CAN_TRANSCEIVER=m
|
||||
|
||||
#
|
||||
# PHY drivers for Broadcom platforms
|
||||
#
|
||||
# CONFIG_BCM_KONA_USB2_PHY is not set
|
||||
# end of PHY drivers for Broadcom platforms
|
||||
|
||||
CONFIG_PHY_CADENCE_TORRENT=m
|
||||
# CONFIG_PHY_CADENCE_DPHY is not set
|
||||
CONFIG_PHY_CADENCE_SALVO=m
|
||||
@ -6685,7 +6731,6 @@ CONFIG_NFS_V4_SECURITY_LABEL=y
|
||||
CONFIG_NFS_FSCACHE=y
|
||||
# CONFIG_NFS_USE_LEGACY_DNS is not set
|
||||
CONFIG_NFS_USE_KERNEL_DNS=y
|
||||
CONFIG_NFS_DEBUG=y
|
||||
CONFIG_NFS_DISABLE_UDP_SUPPORT=y
|
||||
# CONFIG_NFS_V4_2_READ_PLUS is not set
|
||||
CONFIG_NFSD=m
|
||||
@ -6724,7 +6769,6 @@ CONFIG_CIFS_DFS_UPCALL=y
|
||||
# CONFIG_CIFS_SWN_UPCALL is not set
|
||||
CONFIG_CIFS_FSCACHE=y
|
||||
CONFIG_SMB_SERVER=y
|
||||
CONFIG_SMB_SERVER_SMBDIRECT=y
|
||||
CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y
|
||||
CONFIG_SMB_SERVER_KERBEROS5=y
|
||||
CONFIG_SMBFS_COMMON=m
|
||||
@ -7123,6 +7167,7 @@ CONFIG_XZ_DEC_IA64=y
|
||||
CONFIG_XZ_DEC_ARM=y
|
||||
CONFIG_XZ_DEC_ARMTHUMB=y
|
||||
CONFIG_XZ_DEC_SPARC=y
|
||||
# CONFIG_XZ_DEC_MICROLZMA is not set
|
||||
CONFIG_XZ_DEC_BCJ=y
|
||||
# CONFIG_XZ_DEC_TEST is not set
|
||||
CONFIG_DECOMPRESS_GZIP=y
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,6 +1,6 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# Linux/arm 5.15.13 Kernel Configuration
|
||||
# Linux/arm 5.16.5 Kernel Configuration
|
||||
#
|
||||
CONFIG_CC_VERSION_TEXT="arm-linux-gnueabihf-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0"
|
||||
CONFIG_CC_IS_GCC=y
|
||||
@ -18,6 +18,7 @@ CONFIG_CC_HAS_ASM_INLINE=y
|
||||
CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
|
||||
CONFIG_IRQ_WORK=y
|
||||
CONFIG_BUILDTIME_TABLE_SORT=y
|
||||
CONFIG_THREAD_INFO_IN_TASK=y
|
||||
|
||||
#
|
||||
# General setup
|
||||
@ -65,7 +66,6 @@ CONFIG_GENERIC_IRQ_CHIP=y
|
||||
CONFIG_IRQ_DOMAIN=y
|
||||
CONFIG_IRQ_DOMAIN_HIERARCHY=y
|
||||
CONFIG_GENERIC_IRQ_IPI=y
|
||||
CONFIG_HANDLE_DOMAIN_IRQ=y
|
||||
CONFIG_IRQ_FORCED_THREADING=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
|
||||
@ -99,6 +99,7 @@ CONFIG_HAVE_EBPF_JIT=y
|
||||
# CONFIG_BPF_JIT is not set
|
||||
# end of BPF subsystem
|
||||
|
||||
CONFIG_PREEMPT_BUILD=y
|
||||
# CONFIG_PREEMPT_NONE is not set
|
||||
# CONFIG_PREEMPT_VOLUNTARY is not set
|
||||
CONFIG_PREEMPT=y
|
||||
@ -149,6 +150,7 @@ CONFIG_GENERIC_SCHED_CLOCK=y
|
||||
# CONFIG_UCLAMP_TASK is not set
|
||||
# end of Scheduler features
|
||||
|
||||
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
|
||||
CONFIG_CGROUPS=y
|
||||
CONFIG_PAGE_COUNTER=y
|
||||
CONFIG_MEMCG=y
|
||||
@ -429,6 +431,7 @@ CONFIG_DEBUG_ALIGN_RODATA=y
|
||||
CONFIG_HAVE_SMP=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SMP_ON_UP=y
|
||||
CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
|
||||
CONFIG_ARM_CPU_TOPOLOGY=y
|
||||
# CONFIG_SCHED_MC is not set
|
||||
# CONFIG_SCHED_SMT is not set
|
||||
@ -614,6 +617,7 @@ CONFIG_ARCH_USE_BUILTIN_BSWAP=y
|
||||
CONFIG_HAVE_KPROBES=y
|
||||
CONFIG_HAVE_KRETPROBES=y
|
||||
CONFIG_HAVE_OPTPROBES=y
|
||||
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
|
||||
CONFIG_HAVE_NMI=y
|
||||
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
|
||||
CONFIG_HAVE_ARCH_TRACEHOOK=y
|
||||
@ -651,6 +655,7 @@ CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
|
||||
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
|
||||
CONFIG_HAVE_EXIT_THREAD=y
|
||||
CONFIG_ARCH_MMAP_RND_BITS=8
|
||||
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
|
||||
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
|
||||
CONFIG_CLONE_BACKWARDS=y
|
||||
CONFIG_OLD_SIGSUSPEND3=y
|
||||
@ -787,6 +792,7 @@ CONFIG_FLATMEM_MANUAL=y
|
||||
CONFIG_FLATMEM=y
|
||||
CONFIG_ARCH_KEEP_MEMBLOCK=y
|
||||
CONFIG_MEMORY_ISOLATION=y
|
||||
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
|
||||
CONFIG_SPLIT_PTLOCK_CPUS=4
|
||||
CONFIG_COMPACTION=y
|
||||
# CONFIG_PAGE_REPORTING is not set
|
||||
@ -969,6 +975,8 @@ CONFIG_BRIDGE_NETFILTER=m
|
||||
# Core Netfilter Configuration
|
||||
#
|
||||
CONFIG_NETFILTER_INGRESS=y
|
||||
CONFIG_NETFILTER_EGRESS=y
|
||||
CONFIG_NETFILTER_SKIP_EGRESS=y
|
||||
CONFIG_NETFILTER_NETLINK=m
|
||||
CONFIG_NETFILTER_FAMILY_BRIDGE=y
|
||||
CONFIG_NETFILTER_FAMILY_ARP=y
|
||||
@ -1380,10 +1388,11 @@ CONFIG_NET_DSA_TAG_DSA=m
|
||||
CONFIG_NET_DSA_TAG_EDSA=m
|
||||
CONFIG_NET_DSA_TAG_MTK=m
|
||||
CONFIG_NET_DSA_TAG_KSZ=m
|
||||
CONFIG_NET_DSA_TAG_RTL4_A=m
|
||||
# CONFIG_NET_DSA_TAG_OCELOT is not set
|
||||
# CONFIG_NET_DSA_TAG_OCELOT_8021Q is not set
|
||||
CONFIG_NET_DSA_TAG_QCA=m
|
||||
CONFIG_NET_DSA_TAG_RTL4_A=m
|
||||
CONFIG_NET_DSA_TAG_RTL8_4=m
|
||||
CONFIG_NET_DSA_TAG_LAN9303=m
|
||||
CONFIG_NET_DSA_TAG_SJA1105=m
|
||||
CONFIG_NET_DSA_TAG_TRAILER=m
|
||||
@ -1590,8 +1599,6 @@ CONFIG_CAN_IFI_CANFD=m
|
||||
CONFIG_CAN_M_CAN=m
|
||||
CONFIG_CAN_M_CAN_PLATFORM=m
|
||||
CONFIG_CAN_M_CAN_TCAN4X5X=m
|
||||
CONFIG_CAN_RCAR=m
|
||||
CONFIG_CAN_RCAR_CANFD=m
|
||||
CONFIG_CAN_SJA1000=m
|
||||
CONFIG_CAN_SJA1000_ISA=m
|
||||
CONFIG_CAN_SJA1000_PLATFORM=m
|
||||
@ -1838,7 +1845,6 @@ CONFIG_OF_KOBJ=y
|
||||
CONFIG_OF_DYNAMIC=y
|
||||
CONFIG_OF_ADDRESS=y
|
||||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_NET=y
|
||||
CONFIG_OF_RESERVED_MEM=y
|
||||
CONFIG_OF_RESOLVE=y
|
||||
CONFIG_OF_OVERLAY=y
|
||||
@ -1860,7 +1866,6 @@ CONFIG_ZRAM_WRITEBACK=y
|
||||
# CONFIG_ZRAM_MEMORY_TRACKING is not set
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
|
||||
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
|
||||
CONFIG_BLK_DEV_DRBD=m
|
||||
# CONFIG_DRBD_FAULT_INJECTION is not set
|
||||
# CONFIG_BLK_DEV_NBD is not set
|
||||
@ -1972,6 +1977,7 @@ CONFIG_SCSI_LOWLEVEL=y
|
||||
CONFIG_ISCSI_TCP=m
|
||||
# CONFIG_ISCSI_BOOT_SYSFS is not set
|
||||
# CONFIG_SCSI_UFSHCD is not set
|
||||
# CONFIG_SCSI_UFS_HWMON is not set
|
||||
# CONFIG_SCSI_DEBUG is not set
|
||||
CONFIG_SCSI_VIRTIO=m
|
||||
# CONFIG_SCSI_DH is not set
|
||||
@ -2020,6 +2026,7 @@ CONFIG_DM_VERITY=y
|
||||
# CONFIG_DM_SWITCH is not set
|
||||
# CONFIG_DM_LOG_WRITES is not set
|
||||
# CONFIG_DM_INTEGRITY is not set
|
||||
# CONFIG_DM_AUDIT is not set
|
||||
CONFIG_TARGET_CORE=m
|
||||
CONFIG_TCM_IBLOCK=m
|
||||
CONFIG_TCM_FILEIO=m
|
||||
@ -2045,6 +2052,7 @@ CONFIG_VXLAN=m
|
||||
CONFIG_GENEVE=m
|
||||
# CONFIG_BAREUDP is not set
|
||||
CONFIG_GTP=m
|
||||
# CONFIG_AMT is not set
|
||||
CONFIG_MACSEC=m
|
||||
# CONFIG_NETCONSOLE is not set
|
||||
CONFIG_TUN=y
|
||||
@ -2103,6 +2111,8 @@ CONFIG_ETHERNET=y
|
||||
CONFIG_NET_VENDOR_ARC=y
|
||||
CONFIG_ARC_EMAC_CORE=y
|
||||
CONFIG_EMAC_ROCKCHIP=y
|
||||
CONFIG_NET_VENDOR_ASIX=y
|
||||
# CONFIG_SPI_AX88796C is not set
|
||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
CONFIG_NET_VENDOR_CADENCE=y
|
||||
# CONFIG_MACB is not set
|
||||
@ -2386,6 +2396,7 @@ CONFIG_MT7615_COMMON=m
|
||||
CONFIG_MT7663_USB_SDIO_COMMON=m
|
||||
CONFIG_MT7663U=m
|
||||
# CONFIG_MT7663S is not set
|
||||
# CONFIG_MT7921S is not set
|
||||
# CONFIG_WLAN_VENDOR_MICROCHIP is not set
|
||||
CONFIG_WLAN_VENDOR_RALINK=y
|
||||
CONFIG_RT2X00=y
|
||||
@ -2417,8 +2428,9 @@ CONFIG_RTLWIFI_USB=m
|
||||
CONFIG_RTL8192C_COMMON=m
|
||||
CONFIG_RTL8XXXU=y
|
||||
# CONFIG_RTL8XXXU_UNTESTED is not set
|
||||
CONFIG_RTL8723CS=m
|
||||
CONFIG_RTW88=m
|
||||
CONFIG_RTL8723CS=m
|
||||
CONFIG_RTW89=m
|
||||
CONFIG_WLAN_VENDOR_RSI=y
|
||||
# CONFIG_RSI_91X is not set
|
||||
CONFIG_WLAN_VENDOR_ST=y
|
||||
@ -2509,6 +2521,7 @@ CONFIG_KEYBOARD_TM2_TOUCHKEY=m
|
||||
# CONFIG_KEYBOARD_XTKBD is not set
|
||||
# CONFIG_KEYBOARD_CAP11XX is not set
|
||||
# CONFIG_KEYBOARD_BCM is not set
|
||||
# CONFIG_KEYBOARD_CYPRESS_SF is not set
|
||||
CONFIG_INPUT_MOUSE=y
|
||||
# CONFIG_MOUSE_PS2 is not set
|
||||
# CONFIG_MOUSE_SERIAL is not set
|
||||
@ -2747,7 +2760,6 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4
|
||||
CONFIG_SERIAL_8250_DWLIB=y
|
||||
CONFIG_SERIAL_8250_FSL=y
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
# CONFIG_SERIAL_8250_EM is not set
|
||||
# CONFIG_SERIAL_8250_RT288X is not set
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
|
||||
@ -3220,6 +3232,7 @@ CONFIG_SENSORS_GPIO_FAN=y
|
||||
# CONFIG_SENSORS_MAX197 is not set
|
||||
# CONFIG_SENSORS_MAX31722 is not set
|
||||
# CONFIG_SENSORS_MAX31730 is not set
|
||||
# CONFIG_SENSORS_MAX6620 is not set
|
||||
# CONFIG_SENSORS_MAX6621 is not set
|
||||
# CONFIG_SENSORS_MAX6639 is not set
|
||||
# CONFIG_SENSORS_MAX6642 is not set
|
||||
@ -3455,7 +3468,6 @@ CONFIG_MFD_TPS6586X=y
|
||||
# CONFIG_MFD_TPS65910 is not set
|
||||
# CONFIG_MFD_TPS65912_I2C is not set
|
||||
# CONFIG_MFD_TPS65912_SPI is not set
|
||||
# CONFIG_MFD_TPS80031 is not set
|
||||
# CONFIG_TWL4030_CORE is not set
|
||||
# CONFIG_TWL6040_CORE is not set
|
||||
CONFIG_MFD_WL1273_CORE=m
|
||||
@ -3588,13 +3600,18 @@ CONFIG_IR_GPIO_CIR=m
|
||||
# CONFIG_IR_GPIO_TX is not set
|
||||
# CONFIG_IR_PWM_TX is not set
|
||||
# CONFIG_IR_SERIAL is not set
|
||||
# CONFIG_IR_SIR is not set
|
||||
# CONFIG_RC_XBOX_DVD is not set
|
||||
# CONFIG_IR_TOY is not set
|
||||
CONFIG_CEC_CORE=y
|
||||
CONFIG_CEC_NOTIFIER=y
|
||||
|
||||
#
|
||||
# CEC support
|
||||
#
|
||||
# CONFIG_MEDIA_CEC_RC is not set
|
||||
# CONFIG_MEDIA_CEC_SUPPORT is not set
|
||||
# end of CEC support
|
||||
|
||||
CONFIG_MEDIA_SUPPORT=y
|
||||
CONFIG_MEDIA_SUPPORT_FILTER=y
|
||||
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
|
||||
@ -3637,10 +3654,6 @@ CONFIG_VIDEOBUF_VMALLOC=m
|
||||
#
|
||||
CONFIG_MEDIA_CONTROLLER_DVB=y
|
||||
CONFIG_MEDIA_CONTROLLER_REQUEST_API=y
|
||||
|
||||
#
|
||||
# Please notice that the enabled Media controller Request API is EXPERIMENTAL
|
||||
#
|
||||
# end of Media controller options
|
||||
|
||||
#
|
||||
@ -3973,6 +3986,7 @@ CONFIG_VIDEO_CX25840=m
|
||||
# Camera sensor devices
|
||||
#
|
||||
# CONFIG_VIDEO_HI556 is not set
|
||||
# CONFIG_VIDEO_HI846 is not set
|
||||
# CONFIG_VIDEO_IMX208 is not set
|
||||
# CONFIG_VIDEO_IMX214 is not set
|
||||
# CONFIG_VIDEO_IMX219 is not set
|
||||
@ -4008,6 +4022,7 @@ CONFIG_VIDEO_CX25840=m
|
||||
# CONFIG_VIDEO_OV9640 is not set
|
||||
# CONFIG_VIDEO_OV9650 is not set
|
||||
# CONFIG_VIDEO_OV13858 is not set
|
||||
# CONFIG_VIDEO_OV13B10 is not set
|
||||
# CONFIG_VIDEO_VS6624 is not set
|
||||
# CONFIG_VIDEO_MT9M001 is not set
|
||||
# CONFIG_VIDEO_MT9M032 is not set
|
||||
@ -4277,12 +4292,12 @@ CONFIG_DVB_AF9033=m
|
||||
#
|
||||
# CONFIG_IMX_IPUV3_CORE is not set
|
||||
CONFIG_DRM=y
|
||||
CONFIG_DRM_DP_AUX_BUS=m
|
||||
# CONFIG_DRM_DP_AUX_CHARDEV is not set
|
||||
# CONFIG_DRM_DEBUG_MM is not set
|
||||
# CONFIG_DRM_DEBUG_SELFTEST is not set
|
||||
CONFIG_DRM_KMS_HELPER=y
|
||||
# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
|
||||
# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
|
||||
CONFIG_DRM_FBDEV_EMULATION=y
|
||||
CONFIG_DRM_FBDEV_OVERALLOC=100
|
||||
# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
|
||||
@ -4338,6 +4353,7 @@ CONFIG_DRM_PANEL=y
|
||||
# CONFIG_DRM_PANEL_ARM_VERSATILE is not set
|
||||
# CONFIG_DRM_PANEL_LVDS is not set
|
||||
CONFIG_DRM_PANEL_SIMPLE=m
|
||||
# CONFIG_DRM_PANEL_EDP is not set
|
||||
# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
|
||||
# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set
|
||||
# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
|
||||
@ -4348,6 +4364,7 @@ CONFIG_DRM_PANEL_SIMPLE=m
|
||||
# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
|
||||
# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set
|
||||
# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set
|
||||
# CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set
|
||||
# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
|
||||
# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set
|
||||
# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
|
||||
@ -4592,6 +4609,7 @@ CONFIG_SND_SOC_FSL_AUDMIX=m
|
||||
CONFIG_SND_SOC_MTK_BTCVSD=m
|
||||
CONFIG_SND_SOC_ROCKCHIP=m
|
||||
CONFIG_SND_SOC_ROCKCHIP_I2S=m
|
||||
CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m
|
||||
# CONFIG_SND_SOC_ROCKCHIP_PDM is not set
|
||||
CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
|
||||
CONFIG_SND_SOC_ROCKCHIP_MAX98090=m
|
||||
@ -4640,6 +4658,8 @@ CONFIG_SND_SOC_CPCAP=m
|
||||
# CONFIG_SND_SOC_CS35L34 is not set
|
||||
# CONFIG_SND_SOC_CS35L35 is not set
|
||||
CONFIG_SND_SOC_CS35L36=m
|
||||
# CONFIG_SND_SOC_CS35L41_SPI is not set
|
||||
# CONFIG_SND_SOC_CS35L41_I2C is not set
|
||||
# CONFIG_SND_SOC_CS42L42 is not set
|
||||
# CONFIG_SND_SOC_CS42L51_I2C is not set
|
||||
# CONFIG_SND_SOC_CS42L52 is not set
|
||||
@ -4674,6 +4694,7 @@ CONFIG_SND_SOC_MAX98090=m
|
||||
# CONFIG_SND_SOC_MAX98504 is not set
|
||||
CONFIG_SND_SOC_MAX9867=m
|
||||
# CONFIG_SND_SOC_MAX98927 is not set
|
||||
# CONFIG_SND_SOC_MAX98520 is not set
|
||||
# CONFIG_SND_SOC_MAX98373_I2C is not set
|
||||
# CONFIG_SND_SOC_MAX98390 is not set
|
||||
# CONFIG_SND_SOC_MAX9860 is not set
|
||||
@ -4701,6 +4722,7 @@ CONFIG_SND_SOC_RT5616=m
|
||||
# CONFIG_SND_SOC_RT5640 is not set
|
||||
CONFIG_SND_SOC_RT5645=m
|
||||
# CONFIG_SND_SOC_RT5659 is not set
|
||||
# CONFIG_SND_SOC_RT9120 is not set
|
||||
# CONFIG_SND_SOC_SGTL5000 is not set
|
||||
CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
|
||||
# CONFIG_SND_SOC_SIMPLE_MUX is not set
|
||||
@ -4767,6 +4789,7 @@ CONFIG_SND_SOC_MT6358=m
|
||||
# CONFIG_SND_SOC_NAU8315 is not set
|
||||
CONFIG_SND_SOC_NAU8540=m
|
||||
# CONFIG_SND_SOC_NAU8810 is not set
|
||||
# CONFIG_SND_SOC_NAU8821 is not set
|
||||
# CONFIG_SND_SOC_NAU8822 is not set
|
||||
# CONFIG_SND_SOC_NAU8824 is not set
|
||||
# CONFIG_SND_SOC_TPA6130A2 is not set
|
||||
@ -4779,6 +4802,8 @@ CONFIG_SND_SOC_NAU8540=m
|
||||
CONFIG_SND_SIMPLE_CARD_UTILS=m
|
||||
CONFIG_SND_SIMPLE_CARD=m
|
||||
# CONFIG_SND_AUDIO_GRAPH_CARD is not set
|
||||
# CONFIG_SND_AUDIO_GRAPH_CARD2 is not set
|
||||
# CONFIG_SND_TEST_COMPONENT is not set
|
||||
# CONFIG_SND_VIRTIO is not set
|
||||
|
||||
#
|
||||
@ -4834,6 +4859,7 @@ CONFIG_HID_KYE=m
|
||||
CONFIG_HID_UCLOGIC=m
|
||||
CONFIG_HID_WALTOP=m
|
||||
CONFIG_HID_VIEWSONIC=m
|
||||
# CONFIG_HID_XIAOMI is not set
|
||||
CONFIG_HID_GYRATION=m
|
||||
CONFIG_HID_ICADE=m
|
||||
# CONFIG_HID_ITE is not set
|
||||
@ -4857,6 +4883,7 @@ CONFIG_HID_MALTRON=m
|
||||
CONFIG_HID_MICROSOFT=m
|
||||
CONFIG_HID_MONTEREY=m
|
||||
CONFIG_HID_MULTITOUCH=m
|
||||
# CONFIG_HID_NINTENDO is not set
|
||||
CONFIG_HID_NTI=m
|
||||
CONFIG_HID_NTRIG=m
|
||||
CONFIG_HID_ORTEK=m
|
||||
@ -4870,8 +4897,6 @@ CONFIG_HID_PICOLCD_BACKLIGHT=y
|
||||
CONFIG_HID_PICOLCD_LEDS=y
|
||||
CONFIG_HID_PICOLCD_CIR=y
|
||||
CONFIG_HID_PLANTRONICS=m
|
||||
CONFIG_HID_PLAYSTATION=m
|
||||
CONFIG_PLAYSTATION_FF=y
|
||||
CONFIG_HID_PRIMAX=m
|
||||
# CONFIG_HID_RETRODE is not set
|
||||
CONFIG_HID_ROCCAT=m
|
||||
@ -5518,7 +5543,6 @@ CONFIG_STAGING=y
|
||||
CONFIG_RTL8723BS=m
|
||||
CONFIG_R8712U=m
|
||||
CONFIG_R8188EU=m
|
||||
CONFIG_88EU_AP_MODE=y
|
||||
# CONFIG_VT6656 is not set
|
||||
|
||||
#
|
||||
@ -5645,7 +5669,7 @@ CONFIG_COMMON_CLK=y
|
||||
#
|
||||
# Clock driver for ARM Reference designs
|
||||
#
|
||||
# CONFIG_ICST is not set
|
||||
# CONFIG_CLK_ICST is not set
|
||||
# CONFIG_CLK_SP810 is not set
|
||||
# end of Clock driver for ARM Reference designs
|
||||
|
||||
@ -5840,9 +5864,13 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
|
||||
#
|
||||
# CONFIG_ADIS16201 is not set
|
||||
# CONFIG_ADIS16209 is not set
|
||||
# CONFIG_ADXL313_I2C is not set
|
||||
# CONFIG_ADXL313_SPI is not set
|
||||
CONFIG_ADXL345=m
|
||||
CONFIG_ADXL345_I2C=m
|
||||
CONFIG_ADXL345_SPI=m
|
||||
# CONFIG_ADXL355_I2C is not set
|
||||
# CONFIG_ADXL355_SPI is not set
|
||||
# CONFIG_ADXL372_SPI is not set
|
||||
# CONFIG_ADXL372_I2C is not set
|
||||
# CONFIG_BMA180 is not set
|
||||
@ -5972,10 +6000,12 @@ CONFIG_BME680_SPI=m
|
||||
# CONFIG_IAQCORE is not set
|
||||
CONFIG_PMS7003=m
|
||||
# CONFIG_SCD30_CORE is not set
|
||||
# CONFIG_SCD4X is not set
|
||||
CONFIG_SENSIRION_SGP30=m
|
||||
# CONFIG_SENSIRION_SGP40 is not set
|
||||
# CONFIG_SPS30_I2C is not set
|
||||
# CONFIG_SPS30_SERIAL is not set
|
||||
# CONFIG_SENSEAIR_SUNRISE_CO2 is not set
|
||||
# CONFIG_VZ89X is not set
|
||||
# end of Chemical Sensors
|
||||
|
||||
@ -6058,6 +6088,7 @@ CONFIG_TI_DAC7612=m
|
||||
#
|
||||
# CONFIG_ADF4350 is not set
|
||||
# CONFIG_ADF4371 is not set
|
||||
# CONFIG_ADRF6780 is not set
|
||||
# end of Phase-Locked Loop (PLL) frequency synthesizers
|
||||
# end of Frequency Synthesizers DDS/PLL
|
||||
|
||||
@ -6315,6 +6346,7 @@ CONFIG_MLX90632=m
|
||||
# CONFIG_TSYS01 is not set
|
||||
# CONFIG_TSYS02D is not set
|
||||
CONFIG_MAX31856=m
|
||||
# CONFIG_MAX31865 is not set
|
||||
# end of Temperature sensors
|
||||
|
||||
CONFIG_PWM=y
|
||||
@ -6345,7 +6377,13 @@ CONFIG_RESET_CONTROLLER=y
|
||||
#
|
||||
CONFIG_GENERIC_PHY=y
|
||||
# CONFIG_PHY_CAN_TRANSCEIVER is not set
|
||||
|
||||
#
|
||||
# PHY drivers for Broadcom platforms
|
||||
#
|
||||
# CONFIG_BCM_KONA_USB2_PHY is not set
|
||||
# end of PHY drivers for Broadcom platforms
|
||||
|
||||
# CONFIG_PHY_CADENCE_TORRENT is not set
|
||||
# CONFIG_PHY_CADENCE_DPHY is not set
|
||||
# CONFIG_PHY_CADENCE_SIERRA is not set
|
||||
@ -7073,6 +7111,7 @@ CONFIG_XZ_DEC_IA64=y
|
||||
CONFIG_XZ_DEC_ARM=y
|
||||
CONFIG_XZ_DEC_ARMTHUMB=y
|
||||
CONFIG_XZ_DEC_SPARC=y
|
||||
CONFIG_XZ_DEC_MICROLZMA=y
|
||||
CONFIG_XZ_DEC_BCJ=y
|
||||
# CONFIG_XZ_DEC_TEST is not set
|
||||
CONFIG_DECOMPRESS_GZIP=y
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,6 +1,6 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# Linux/arm 5.15.1 Kernel Configuration
|
||||
# Linux/arm 5.16.5 Kernel Configuration
|
||||
#
|
||||
CONFIG_CC_VERSION_TEXT="arm-linux-gnueabihf-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0"
|
||||
CONFIG_CC_IS_GCC=y
|
||||
@ -18,6 +18,7 @@ CONFIG_CC_HAS_ASM_INLINE=y
|
||||
CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y
|
||||
CONFIG_IRQ_WORK=y
|
||||
CONFIG_BUILDTIME_TABLE_SORT=y
|
||||
CONFIG_THREAD_INFO_IN_TASK=y
|
||||
|
||||
#
|
||||
# General setup
|
||||
@ -65,7 +66,6 @@ CONFIG_GENERIC_IRQ_CHIP=y
|
||||
CONFIG_IRQ_DOMAIN=y
|
||||
CONFIG_IRQ_DOMAIN_HIERARCHY=y
|
||||
CONFIG_GENERIC_IRQ_IPI=y
|
||||
CONFIG_HANDLE_DOMAIN_IRQ=y
|
||||
CONFIG_IRQ_FORCED_THREADING=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
|
||||
@ -99,6 +99,7 @@ CONFIG_HAVE_EBPF_JIT=y
|
||||
# CONFIG_BPF_JIT is not set
|
||||
# end of BPF subsystem
|
||||
|
||||
CONFIG_PREEMPT_BUILD=y
|
||||
# CONFIG_PREEMPT_NONE is not set
|
||||
# CONFIG_PREEMPT_VOLUNTARY is not set
|
||||
CONFIG_PREEMPT=y
|
||||
@ -150,6 +151,7 @@ CONFIG_GENERIC_SCHED_CLOCK=y
|
||||
# CONFIG_UCLAMP_TASK is not set
|
||||
# end of Scheduler features
|
||||
|
||||
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
|
||||
CONFIG_CGROUPS=y
|
||||
CONFIG_PAGE_COUNTER=y
|
||||
CONFIG_MEMCG=y
|
||||
@ -430,6 +432,7 @@ CONFIG_ARM_ERRATA_825619=y
|
||||
CONFIG_HAVE_SMP=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SMP_ON_UP=y
|
||||
CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
|
||||
CONFIG_ARM_CPU_TOPOLOGY=y
|
||||
# CONFIG_SCHED_MC is not set
|
||||
# CONFIG_SCHED_SMT is not set
|
||||
@ -616,6 +619,7 @@ CONFIG_ARCH_USE_BUILTIN_BSWAP=y
|
||||
CONFIG_HAVE_KPROBES=y
|
||||
CONFIG_HAVE_KRETPROBES=y
|
||||
CONFIG_HAVE_OPTPROBES=y
|
||||
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
|
||||
CONFIG_HAVE_NMI=y
|
||||
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
|
||||
CONFIG_HAVE_ARCH_TRACEHOOK=y
|
||||
@ -653,6 +657,7 @@ CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
|
||||
CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
|
||||
CONFIG_HAVE_EXIT_THREAD=y
|
||||
CONFIG_ARCH_MMAP_RND_BITS=8
|
||||
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
|
||||
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
|
||||
CONFIG_CLONE_BACKWARDS=y
|
||||
CONFIG_OLD_SIGSUSPEND3=y
|
||||
@ -678,7 +683,6 @@ CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
|
||||
|
||||
CONFIG_HAVE_GCC_PLUGINS=y
|
||||
CONFIG_GCC_PLUGINS=y
|
||||
# CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set
|
||||
# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set
|
||||
# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set
|
||||
# end of General architecture-dependent options
|
||||
@ -791,6 +795,7 @@ CONFIG_FLATMEM_MANUAL=y
|
||||
CONFIG_FLATMEM=y
|
||||
CONFIG_ARCH_KEEP_MEMBLOCK=y
|
||||
CONFIG_MEMORY_ISOLATION=y
|
||||
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
|
||||
CONFIG_SPLIT_PTLOCK_CPUS=4
|
||||
CONFIG_COMPACTION=y
|
||||
# CONFIG_PAGE_REPORTING is not set
|
||||
@ -830,6 +835,7 @@ CONFIG_IDLE_PAGE_TRACKING=y
|
||||
# CONFIG_PERCPU_STATS is not set
|
||||
# CONFIG_GUP_TEST is not set
|
||||
CONFIG_KMAP_LOCAL=y
|
||||
CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
|
||||
|
||||
#
|
||||
# Data Access Monitoring
|
||||
@ -972,6 +978,8 @@ CONFIG_BRIDGE_NETFILTER=m
|
||||
# Core Netfilter Configuration
|
||||
#
|
||||
CONFIG_NETFILTER_INGRESS=y
|
||||
CONFIG_NETFILTER_EGRESS=y
|
||||
CONFIG_NETFILTER_SKIP_EGRESS=y
|
||||
CONFIG_NETFILTER_NETLINK=m
|
||||
CONFIG_NETFILTER_FAMILY_BRIDGE=y
|
||||
CONFIG_NETFILTER_FAMILY_ARP=y
|
||||
@ -1383,10 +1391,11 @@ CONFIG_NET_DSA_TAG_DSA=m
|
||||
CONFIG_NET_DSA_TAG_EDSA=m
|
||||
CONFIG_NET_DSA_TAG_MTK=m
|
||||
CONFIG_NET_DSA_TAG_KSZ=m
|
||||
CONFIG_NET_DSA_TAG_RTL4_A=m
|
||||
CONFIG_NET_DSA_TAG_OCELOT=m
|
||||
CONFIG_NET_DSA_TAG_OCELOT_8021Q=m
|
||||
CONFIG_NET_DSA_TAG_QCA=m
|
||||
CONFIG_NET_DSA_TAG_RTL4_A=m
|
||||
CONFIG_NET_DSA_TAG_RTL8_4=m
|
||||
CONFIG_NET_DSA_TAG_LAN9303=m
|
||||
CONFIG_NET_DSA_TAG_SJA1105=m
|
||||
CONFIG_NET_DSA_TAG_TRAILER=m
|
||||
@ -1593,8 +1602,6 @@ CONFIG_CAN_IFI_CANFD=m
|
||||
CONFIG_CAN_M_CAN=m
|
||||
CONFIG_CAN_M_CAN_PLATFORM=m
|
||||
CONFIG_CAN_M_CAN_TCAN4X5X=m
|
||||
CONFIG_CAN_RCAR=m
|
||||
CONFIG_CAN_RCAR_CANFD=m
|
||||
CONFIG_CAN_SJA1000=m
|
||||
CONFIG_CAN_SJA1000_ISA=m
|
||||
CONFIG_CAN_SJA1000_PLATFORM=m
|
||||
@ -1683,7 +1690,7 @@ CONFIG_BT_VIRTIO=m
|
||||
# CONFIG_AF_RXRPC is not set
|
||||
# CONFIG_AF_KCM is not set
|
||||
CONFIG_STREAM_PARSER=y
|
||||
CONFIG_MCTP=m
|
||||
# CONFIG_MCTP is not set
|
||||
CONFIG_FIB_RULES=y
|
||||
CONFIG_WIRELESS=y
|
||||
CONFIG_WIRELESS_EXT=y
|
||||
@ -1858,7 +1865,6 @@ CONFIG_OF_KOBJ=y
|
||||
CONFIG_OF_DYNAMIC=y
|
||||
CONFIG_OF_ADDRESS=y
|
||||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_NET=y
|
||||
CONFIG_OF_RESERVED_MEM=y
|
||||
CONFIG_OF_RESOLVE=y
|
||||
CONFIG_OF_OVERLAY=y
|
||||
@ -1879,7 +1885,6 @@ CONFIG_ZRAM_WRITEBACK=y
|
||||
# CONFIG_ZRAM_MEMORY_TRACKING is not set
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
|
||||
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
|
||||
CONFIG_BLK_DEV_DRBD=m
|
||||
# CONFIG_DRBD_FAULT_INJECTION is not set
|
||||
# CONFIG_BLK_DEV_NBD is not set
|
||||
@ -1991,6 +1996,7 @@ CONFIG_SCSI_LOWLEVEL=y
|
||||
CONFIG_ISCSI_TCP=m
|
||||
# CONFIG_ISCSI_BOOT_SYSFS is not set
|
||||
# CONFIG_SCSI_UFSHCD is not set
|
||||
# CONFIG_SCSI_UFS_HWMON is not set
|
||||
# CONFIG_SCSI_DEBUG is not set
|
||||
CONFIG_SCSI_VIRTIO=m
|
||||
# CONFIG_SCSI_DH is not set
|
||||
@ -2045,6 +2051,7 @@ CONFIG_DM_VERITY_FEC=y
|
||||
CONFIG_DM_SWITCH=m
|
||||
CONFIG_DM_LOG_WRITES=m
|
||||
CONFIG_DM_INTEGRITY=m
|
||||
CONFIG_DM_AUDIT=y
|
||||
CONFIG_TARGET_CORE=m
|
||||
CONFIG_TCM_IBLOCK=m
|
||||
CONFIG_TCM_FILEIO=m
|
||||
@ -2070,6 +2077,7 @@ CONFIG_VXLAN=m
|
||||
CONFIG_GENEVE=m
|
||||
# CONFIG_BAREUDP is not set
|
||||
CONFIG_GTP=m
|
||||
# CONFIG_AMT is not set
|
||||
CONFIG_MACSEC=m
|
||||
# CONFIG_NETCONSOLE is not set
|
||||
CONFIG_TUN=y
|
||||
@ -2129,6 +2137,8 @@ CONFIG_ETHERNET=y
|
||||
CONFIG_NET_VENDOR_ARC=y
|
||||
CONFIG_ARC_EMAC_CORE=y
|
||||
CONFIG_EMAC_ROCKCHIP=y
|
||||
CONFIG_NET_VENDOR_ASIX=y
|
||||
# CONFIG_SPI_AX88796C is not set
|
||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
CONFIG_NET_VENDOR_CADENCE=y
|
||||
# CONFIG_MACB is not set
|
||||
@ -2238,10 +2248,6 @@ CONFIG_DP83869_PHY=m
|
||||
CONFIG_VITESSE_PHY=m
|
||||
# CONFIG_XILINX_GMII2RGMII is not set
|
||||
# CONFIG_MICREL_KS8995MA is not set
|
||||
|
||||
#
|
||||
# MCTP Device Drivers
|
||||
#
|
||||
CONFIG_MDIO_DEVICE=y
|
||||
CONFIG_MDIO_BUS=y
|
||||
CONFIG_FWNODE_MDIO=y
|
||||
@ -2422,6 +2428,7 @@ CONFIG_MT7615_COMMON=m
|
||||
CONFIG_MT7663_USB_SDIO_COMMON=m
|
||||
# CONFIG_MT7663U is not set
|
||||
CONFIG_MT7663S=m
|
||||
# CONFIG_MT7921S is not set
|
||||
CONFIG_WLAN_VENDOR_MICROCHIP=y
|
||||
# CONFIG_WILC1000_SDIO is not set
|
||||
# CONFIG_WILC1000_SPI is not set
|
||||
@ -2456,6 +2463,7 @@ CONFIG_RTL8192C_COMMON=m
|
||||
CONFIG_RTL8XXXU=y
|
||||
# CONFIG_RTL8XXXU_UNTESTED is not set
|
||||
CONFIG_RTW88=m
|
||||
CONFIG_RTW89=m
|
||||
CONFIG_WLAN_VENDOR_RSI=y
|
||||
# CONFIG_RSI_91X is not set
|
||||
CONFIG_WLAN_VENDOR_ST=y
|
||||
@ -2548,6 +2556,7 @@ CONFIG_KEYBOARD_TM2_TOUCHKEY=m
|
||||
CONFIG_KEYBOARD_CROS_EC=y
|
||||
# CONFIG_KEYBOARD_CAP11XX is not set
|
||||
# CONFIG_KEYBOARD_BCM is not set
|
||||
# CONFIG_KEYBOARD_CYPRESS_SF is not set
|
||||
CONFIG_INPUT_MOUSE=y
|
||||
# CONFIG_MOUSE_PS2 is not set
|
||||
# CONFIG_MOUSE_SERIAL is not set
|
||||
@ -2787,7 +2796,6 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4
|
||||
CONFIG_SERIAL_8250_DWLIB=y
|
||||
CONFIG_SERIAL_8250_FSL=y
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
# CONFIG_SERIAL_8250_EM is not set
|
||||
# CONFIG_SERIAL_8250_RT288X is not set
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
|
||||
@ -2827,8 +2835,6 @@ CONFIG_HVC_DRIVER=y
|
||||
# CONFIG_HVC_DCC is not set
|
||||
CONFIG_SERIAL_DEV_BUS=y
|
||||
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
|
||||
CONFIG_RK_CHAR_DRIVERS=y
|
||||
CONFIG_RK3288_DEVGPIOMEM=m
|
||||
# CONFIG_TTY_PRINTK is not set
|
||||
CONFIG_VIRTIO_CONSOLE=m
|
||||
# CONFIG_IPMI_HANDLER is not set
|
||||
@ -3266,6 +3272,7 @@ CONFIG_SENSORS_MAX1668=m
|
||||
CONFIG_SENSORS_MAX197=m
|
||||
CONFIG_SENSORS_MAX31722=m
|
||||
# CONFIG_SENSORS_MAX31730 is not set
|
||||
# CONFIG_SENSORS_MAX6620 is not set
|
||||
# CONFIG_SENSORS_MAX6621 is not set
|
||||
CONFIG_SENSORS_MAX6639=m
|
||||
CONFIG_SENSORS_MAX6642=m
|
||||
@ -3507,7 +3514,6 @@ CONFIG_MFD_TPS6586X=y
|
||||
# CONFIG_MFD_TPS65910 is not set
|
||||
# CONFIG_MFD_TPS65912_I2C is not set
|
||||
# CONFIG_MFD_TPS65912_SPI is not set
|
||||
# CONFIG_MFD_TPS80031 is not set
|
||||
# CONFIG_TWL4030_CORE is not set
|
||||
# CONFIG_TWL6040_CORE is not set
|
||||
CONFIG_MFD_WL1273_CORE=m
|
||||
@ -3647,13 +3653,18 @@ CONFIG_IR_GPIO_CIR=m
|
||||
# CONFIG_IR_GPIO_TX is not set
|
||||
# CONFIG_IR_PWM_TX is not set
|
||||
# CONFIG_IR_SERIAL is not set
|
||||
# CONFIG_IR_SIR is not set
|
||||
# CONFIG_RC_XBOX_DVD is not set
|
||||
CONFIG_IR_TOY=m
|
||||
CONFIG_CEC_CORE=y
|
||||
CONFIG_CEC_NOTIFIER=y
|
||||
|
||||
#
|
||||
# CEC support
|
||||
#
|
||||
# CONFIG_MEDIA_CEC_RC is not set
|
||||
# CONFIG_MEDIA_CEC_SUPPORT is not set
|
||||
# end of CEC support
|
||||
|
||||
CONFIG_MEDIA_SUPPORT=y
|
||||
CONFIG_MEDIA_SUPPORT_FILTER=y
|
||||
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
|
||||
@ -3696,10 +3707,6 @@ CONFIG_VIDEOBUF_VMALLOC=m
|
||||
#
|
||||
CONFIG_MEDIA_CONTROLLER_DVB=y
|
||||
CONFIG_MEDIA_CONTROLLER_REQUEST_API=y
|
||||
|
||||
#
|
||||
# Please notice that the enabled Media controller Request API is EXPERIMENTAL
|
||||
#
|
||||
# end of Media controller options
|
||||
|
||||
#
|
||||
@ -3927,7 +3934,6 @@ CONFIG_VIDEO_XILINX_TPG=m
|
||||
CONFIG_VIDEO_XILINX_VTC=m
|
||||
CONFIG_V4L_MEM2MEM_DRIVERS=y
|
||||
# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set
|
||||
CONFIG_VIDEO_ROCKCHIP_IEP=m
|
||||
CONFIG_VIDEO_ROCKCHIP_RGA=m
|
||||
CONFIG_DVB_PLATFORM_DRIVERS=y
|
||||
CONFIG_DVB_C8SECTPFE=m
|
||||
@ -4058,6 +4064,7 @@ CONFIG_VIDEO_ST_MIPID02=m
|
||||
CONFIG_VIDEO_APTINA_PLL=m
|
||||
CONFIG_VIDEO_CCS_PLL=m
|
||||
CONFIG_VIDEO_HI556=m
|
||||
# CONFIG_VIDEO_HI846 is not set
|
||||
CONFIG_VIDEO_IMX208=m
|
||||
# CONFIG_VIDEO_IMX214 is not set
|
||||
# CONFIG_VIDEO_IMX219 is not set
|
||||
@ -4093,6 +4100,7 @@ CONFIG_VIDEO_OV9282=m
|
||||
CONFIG_VIDEO_OV9640=m
|
||||
CONFIG_VIDEO_OV9650=m
|
||||
CONFIG_VIDEO_OV13858=m
|
||||
# CONFIG_VIDEO_OV13B10 is not set
|
||||
CONFIG_VIDEO_VS6624=m
|
||||
CONFIG_VIDEO_MT9M001=m
|
||||
CONFIG_VIDEO_MT9M032=m
|
||||
@ -4366,12 +4374,13 @@ CONFIG_DVB_SP2=m
|
||||
CONFIG_DRM=y
|
||||
CONFIG_DRM_MIPI_DBI=m
|
||||
CONFIG_DRM_MIPI_DSI=y
|
||||
CONFIG_DRM_DP_AUX_BUS=y
|
||||
CONFIG_DRM_DP_AUX_BUS=m
|
||||
# CONFIG_DRM_DP_AUX_CHARDEV is not set
|
||||
# CONFIG_DRM_DEBUG_MM is not set
|
||||
# CONFIG_DRM_DEBUG_SELFTEST is not set
|
||||
CONFIG_DRM_KMS_HELPER=y
|
||||
# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
|
||||
# CONFIG_DRM_DEBUG_MODESET_LOCK is not set
|
||||
CONFIG_DRM_FBDEV_EMULATION=y
|
||||
CONFIG_DRM_FBDEV_OVERALLOC=100
|
||||
# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
|
||||
@ -4432,6 +4441,7 @@ CONFIG_DRM_PANEL_ARM_VERSATILE=m
|
||||
CONFIG_DRM_PANEL_DSI_CM=m
|
||||
# CONFIG_DRM_PANEL_LVDS is not set
|
||||
CONFIG_DRM_PANEL_SIMPLE=y
|
||||
# CONFIG_DRM_PANEL_EDP is not set
|
||||
# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set
|
||||
# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set
|
||||
# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set
|
||||
@ -4464,6 +4474,7 @@ CONFIG_DRM_PANEL_RAYDIUM_RM68200=m
|
||||
CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
|
||||
CONFIG_DRM_PANEL_SAMSUNG_DB7430=m
|
||||
# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set
|
||||
# CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set
|
||||
CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m
|
||||
CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
|
||||
# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
|
||||
@ -4474,6 +4485,7 @@ CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m
|
||||
CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
|
||||
CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
|
||||
CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m
|
||||
# CONFIG_DRM_PANEL_SHARP_LS060T1SX01 is not set
|
||||
CONFIG_DRM_PANEL_SITRONIX_ST7701=m
|
||||
CONFIG_DRM_PANEL_SITRONIX_ST7703=m
|
||||
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
|
||||
@ -4725,6 +4737,7 @@ CONFIG_SND_SOC_FSL_XCVR=m
|
||||
CONFIG_SND_SOC_MTK_BTCVSD=m
|
||||
CONFIG_SND_SOC_ROCKCHIP=m
|
||||
CONFIG_SND_SOC_ROCKCHIP_I2S=m
|
||||
CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m
|
||||
# CONFIG_SND_SOC_ROCKCHIP_PDM is not set
|
||||
CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
|
||||
CONFIG_SND_SOC_ROCKCHIP_MAX98090=m
|
||||
@ -4777,6 +4790,8 @@ CONFIG_SND_SOC_CROS_EC_CODEC=m
|
||||
# CONFIG_SND_SOC_CS35L34 is not set
|
||||
# CONFIG_SND_SOC_CS35L35 is not set
|
||||
CONFIG_SND_SOC_CS35L36=m
|
||||
# CONFIG_SND_SOC_CS35L41_SPI is not set
|
||||
# CONFIG_SND_SOC_CS35L41_I2C is not set
|
||||
# CONFIG_SND_SOC_CS42L42 is not set
|
||||
# CONFIG_SND_SOC_CS42L51_I2C is not set
|
||||
# CONFIG_SND_SOC_CS42L52 is not set
|
||||
@ -4811,6 +4826,7 @@ CONFIG_SND_SOC_MAX98090=m
|
||||
# CONFIG_SND_SOC_MAX98504 is not set
|
||||
CONFIG_SND_SOC_MAX9867=m
|
||||
# CONFIG_SND_SOC_MAX98927 is not set
|
||||
# CONFIG_SND_SOC_MAX98520 is not set
|
||||
CONFIG_SND_SOC_MAX98373=m
|
||||
CONFIG_SND_SOC_MAX98373_I2C=m
|
||||
# CONFIG_SND_SOC_MAX98390 is not set
|
||||
@ -4838,6 +4854,7 @@ CONFIG_SND_SOC_RT5616=m
|
||||
CONFIG_SND_SOC_RT5640=m
|
||||
CONFIG_SND_SOC_RT5645=m
|
||||
CONFIG_SND_SOC_RT5659=m
|
||||
# CONFIG_SND_SOC_RT9120 is not set
|
||||
# CONFIG_SND_SOC_SGTL5000 is not set
|
||||
CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
|
||||
CONFIG_SND_SOC_SIMPLE_MUX=m
|
||||
@ -4905,6 +4922,7 @@ CONFIG_SND_SOC_MT6358=m
|
||||
CONFIG_SND_SOC_NAU8315=m
|
||||
CONFIG_SND_SOC_NAU8540=m
|
||||
# CONFIG_SND_SOC_NAU8810 is not set
|
||||
# CONFIG_SND_SOC_NAU8821 is not set
|
||||
# CONFIG_SND_SOC_NAU8822 is not set
|
||||
# CONFIG_SND_SOC_NAU8824 is not set
|
||||
# CONFIG_SND_SOC_TPA6130A2 is not set
|
||||
@ -4917,6 +4935,8 @@ CONFIG_SND_SOC_LPASS_TX_MACRO=m
|
||||
CONFIG_SND_SIMPLE_CARD_UTILS=m
|
||||
CONFIG_SND_SIMPLE_CARD=m
|
||||
# CONFIG_SND_AUDIO_GRAPH_CARD is not set
|
||||
# CONFIG_SND_AUDIO_GRAPH_CARD2 is not set
|
||||
# CONFIG_SND_TEST_COMPONENT is not set
|
||||
CONFIG_SND_VIRTIO=m
|
||||
|
||||
#
|
||||
@ -4973,6 +4993,7 @@ CONFIG_HID_KYE=m
|
||||
CONFIG_HID_UCLOGIC=m
|
||||
CONFIG_HID_WALTOP=m
|
||||
CONFIG_HID_VIEWSONIC=m
|
||||
# CONFIG_HID_XIAOMI is not set
|
||||
CONFIG_HID_GYRATION=m
|
||||
CONFIG_HID_ICADE=m
|
||||
# CONFIG_HID_ITE is not set
|
||||
@ -4996,6 +5017,7 @@ CONFIG_HID_MALTRON=m
|
||||
CONFIG_HID_MICROSOFT=m
|
||||
CONFIG_HID_MONTEREY=m
|
||||
CONFIG_HID_MULTITOUCH=m
|
||||
# CONFIG_HID_NINTENDO is not set
|
||||
CONFIG_HID_NTI=m
|
||||
CONFIG_HID_NTRIG=m
|
||||
CONFIG_HID_ORTEK=m
|
||||
@ -5815,7 +5837,7 @@ CONFIG_COMMON_CLK=y
|
||||
#
|
||||
# Clock driver for ARM Reference designs
|
||||
#
|
||||
# CONFIG_ICST is not set
|
||||
# CONFIG_CLK_ICST is not set
|
||||
# CONFIG_CLK_SP810 is not set
|
||||
# end of Clock driver for ARM Reference designs
|
||||
|
||||
@ -6003,9 +6025,13 @@ CONFIG_IIO_TRIGGERED_EVENT=m
|
||||
#
|
||||
# CONFIG_ADIS16201 is not set
|
||||
# CONFIG_ADIS16209 is not set
|
||||
# CONFIG_ADXL313_I2C is not set
|
||||
# CONFIG_ADXL313_SPI is not set
|
||||
CONFIG_ADXL345=m
|
||||
CONFIG_ADXL345_I2C=m
|
||||
CONFIG_ADXL345_SPI=m
|
||||
# CONFIG_ADXL355_I2C is not set
|
||||
# CONFIG_ADXL355_SPI is not set
|
||||
# CONFIG_ADXL372_SPI is not set
|
||||
# CONFIG_ADXL372_I2C is not set
|
||||
# CONFIG_BMA180 is not set
|
||||
@ -6141,11 +6167,13 @@ CONFIG_PMS7003=m
|
||||
CONFIG_SCD30_CORE=m
|
||||
CONFIG_SCD30_I2C=m
|
||||
CONFIG_SCD30_SERIAL=m
|
||||
# CONFIG_SCD4X is not set
|
||||
CONFIG_SENSIRION_SGP30=m
|
||||
CONFIG_SENSIRION_SGP40=m
|
||||
CONFIG_SPS30=m
|
||||
CONFIG_SPS30_I2C=m
|
||||
CONFIG_SPS30_SERIAL=m
|
||||
# CONFIG_SENSEAIR_SUNRISE_CO2 is not set
|
||||
# CONFIG_VZ89X is not set
|
||||
# end of Chemical Sensors
|
||||
|
||||
@ -6235,6 +6263,7 @@ CONFIG_TI_DAC7612=m
|
||||
#
|
||||
# CONFIG_ADF4350 is not set
|
||||
# CONFIG_ADF4371 is not set
|
||||
# CONFIG_ADRF6780 is not set
|
||||
# end of Phase-Locked Loop (PLL) frequency synthesizers
|
||||
# end of Frequency Synthesizers DDS/PLL
|
||||
|
||||
@ -6499,6 +6528,7 @@ CONFIG_TMP117=m
|
||||
# CONFIG_TSYS01 is not set
|
||||
# CONFIG_TSYS02D is not set
|
||||
CONFIG_MAX31856=m
|
||||
# CONFIG_MAX31865 is not set
|
||||
# end of Temperature sensors
|
||||
|
||||
CONFIG_PWM=y
|
||||
@ -6533,7 +6563,13 @@ CONFIG_RESET_SCMI=m
|
||||
CONFIG_GENERIC_PHY=y
|
||||
CONFIG_GENERIC_PHY_MIPI_DPHY=y
|
||||
CONFIG_PHY_CAN_TRANSCEIVER=m
|
||||
|
||||
#
|
||||
# PHY drivers for Broadcom platforms
|
||||
#
|
||||
# CONFIG_BCM_KONA_USB2_PHY is not set
|
||||
# end of PHY drivers for Broadcom platforms
|
||||
|
||||
# CONFIG_PHY_CADENCE_TORRENT is not set
|
||||
CONFIG_PHY_CADENCE_DPHY=m
|
||||
# CONFIG_PHY_CADENCE_SIERRA is not set
|
||||
@ -6813,6 +6849,7 @@ CONFIG_PSTORE_CONSOLE=y
|
||||
# CONFIG_PSTORE_PMSG is not set
|
||||
# CONFIG_PSTORE_FTRACE is not set
|
||||
CONFIG_PSTORE_RAM=y
|
||||
# CONFIG_PSTORE_BLK is not set
|
||||
CONFIG_SYSV_FS=m
|
||||
CONFIG_UFS_FS=m
|
||||
# CONFIG_UFS_FS_WRITE is not set
|
||||
@ -6841,7 +6878,6 @@ CONFIG_NFS_V4_SECURITY_LABEL=y
|
||||
CONFIG_NFS_FSCACHE=y
|
||||
# CONFIG_NFS_USE_LEGACY_DNS is not set
|
||||
CONFIG_NFS_USE_KERNEL_DNS=y
|
||||
CONFIG_NFS_DEBUG=y
|
||||
CONFIG_NFS_DISABLE_UDP_SUPPORT=y
|
||||
# CONFIG_NFS_V4_2_READ_PLUS is not set
|
||||
CONFIG_NFSD=m
|
||||
@ -6855,14 +6891,14 @@ CONFIG_NFSD_SCSILAYOUT=y
|
||||
CONFIG_NFSD_FLEXFILELAYOUT=y
|
||||
# CONFIG_NFSD_V4_2_INTER_SSC is not set
|
||||
CONFIG_NFSD_V4_SECURITY_LABEL=y
|
||||
CONFIG_GRACE_PERIOD=y
|
||||
CONFIG_LOCKD=y
|
||||
CONFIG_GRACE_PERIOD=m
|
||||
CONFIG_LOCKD=m
|
||||
CONFIG_LOCKD_V4=y
|
||||
CONFIG_NFS_ACL_SUPPORT=y
|
||||
CONFIG_NFS_ACL_SUPPORT=m
|
||||
CONFIG_NFS_COMMON=y
|
||||
CONFIG_NFS_V4_2_SSC_HELPER=y
|
||||
CONFIG_SUNRPC=y
|
||||
CONFIG_SUNRPC_GSS=y
|
||||
CONFIG_SUNRPC=m
|
||||
CONFIG_SUNRPC_GSS=m
|
||||
CONFIG_SUNRPC_BACKCHANNEL=y
|
||||
CONFIG_SUNRPC_SWAP=y
|
||||
CONFIG_RPCSEC_GSS_KRB5=m
|
||||
@ -6883,7 +6919,6 @@ CONFIG_CIFS_POSIX=y
|
||||
# CONFIG_CIFS_SWN_UPCALL is not set
|
||||
CONFIG_CIFS_FSCACHE=y
|
||||
CONFIG_SMB_SERVER=m
|
||||
CONFIG_SMB_SERVER_SMBDIRECT=y
|
||||
CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y
|
||||
CONFIG_SMB_SERVER_KERBEROS5=y
|
||||
CONFIG_SMBFS_COMMON=m
|
||||
@ -7268,6 +7303,7 @@ CONFIG_XZ_DEC_IA64=y
|
||||
CONFIG_XZ_DEC_ARM=y
|
||||
CONFIG_XZ_DEC_ARMTHUMB=y
|
||||
CONFIG_XZ_DEC_SPARC=y
|
||||
CONFIG_XZ_DEC_MICROLZMA=y
|
||||
CONFIG_XZ_DEC_BCJ=y
|
||||
# CONFIG_XZ_DEC_TEST is not set
|
||||
CONFIG_DECOMPRESS_GZIP=y
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,6 +1,6 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# Linux/arm64 5.15.0 Kernel Configuration
|
||||
# Linux/arm64 5.16.8 Kernel Configuration
|
||||
#
|
||||
CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0"
|
||||
CONFIG_CC_IS_GCC=y
|
||||
@ -61,7 +61,6 @@ CONFIG_GENERIC_IRQ_IPI=y
|
||||
CONFIG_GENERIC_MSI_IRQ=y
|
||||
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_IRQ_MSI_IOMMU=y
|
||||
CONFIG_HANDLE_DOMAIN_IRQ=y
|
||||
CONFIG_IRQ_FORCED_THREADING=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
|
||||
@ -71,6 +70,8 @@ CONFIG_GENERIC_TIME_VSYSCALL=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS=y
|
||||
CONFIG_ARCH_HAS_TICK_BROADCAST=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
|
||||
CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y
|
||||
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
|
||||
|
||||
#
|
||||
# Timers subsystem
|
||||
@ -100,6 +101,7 @@ CONFIG_USERMODE_DRIVER=y
|
||||
# CONFIG_BPF_PRELOAD is not set
|
||||
# end of BPF subsystem
|
||||
|
||||
CONFIG_PREEMPT_NONE_BUILD=y
|
||||
CONFIG_PREEMPT_NONE=y
|
||||
# CONFIG_PREEMPT_VOLUNTARY is not set
|
||||
# CONFIG_PREEMPT is not set
|
||||
@ -153,6 +155,7 @@ CONFIG_GENERIC_SCHED_CLOCK=y
|
||||
|
||||
CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
|
||||
CONFIG_CC_HAS_INT128=y
|
||||
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
|
||||
CONFIG_ARCH_SUPPORTS_INT128=y
|
||||
# CONFIG_NUMA_BALANCING is not set
|
||||
CONFIG_CGROUPS=y
|
||||
@ -353,6 +356,9 @@ CONFIG_ARM64_ERRATUM_1286807=y
|
||||
CONFIG_ARM64_ERRATUM_1463225=y
|
||||
CONFIG_ARM64_ERRATUM_1542419=y
|
||||
CONFIG_ARM64_ERRATUM_1508412=y
|
||||
CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
|
||||
CONFIG_ARM64_ERRATUM_2054223=y
|
||||
CONFIG_ARM64_ERRATUM_2067961=y
|
||||
# CONFIG_CAVIUM_ERRATUM_22375 is not set
|
||||
CONFIG_CAVIUM_ERRATUM_23144=y
|
||||
# CONFIG_CAVIUM_ERRATUM_23154 is not set
|
||||
@ -380,6 +386,7 @@ CONFIG_ARM64_PA_BITS=48
|
||||
# CONFIG_CPU_BIG_ENDIAN is not set
|
||||
CONFIG_CPU_LITTLE_ENDIAN=y
|
||||
CONFIG_SCHED_MC=y
|
||||
CONFIG_SCHED_CLUSTER=y
|
||||
# CONFIG_SCHED_SMT is not set
|
||||
CONFIG_NR_CPUS=8
|
||||
CONFIG_HOTPLUG_CPU=y
|
||||
@ -388,6 +395,7 @@ CONFIG_NODES_SHIFT=2
|
||||
CONFIG_USE_PERCPU_NUMA_NODE_ID=y
|
||||
CONFIG_HAVE_SETUP_PER_CPU_AREA=y
|
||||
CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
|
||||
CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
|
||||
# CONFIG_HZ_100 is not set
|
||||
CONFIG_HZ_250=y
|
||||
# CONFIG_HZ_300 is not set
|
||||
@ -559,6 +567,7 @@ CONFIG_ARM_SCPI_CPUFREQ=m
|
||||
# end of CPU Frequency scaling
|
||||
# end of CPU Power Management
|
||||
|
||||
CONFIG_HAVE_KVM=y
|
||||
# CONFIG_VIRTUALIZATION is not set
|
||||
CONFIG_ARM64_CRYPTO=y
|
||||
CONFIG_CRYPTO_SHA256_ARM64=y
|
||||
@ -591,6 +600,7 @@ CONFIG_JUMP_LABEL=y
|
||||
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
|
||||
CONFIG_HAVE_KPROBES=y
|
||||
CONFIG_HAVE_KRETPROBES=y
|
||||
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
|
||||
CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y
|
||||
CONFIG_HAVE_NMI=y
|
||||
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
|
||||
@ -648,6 +658,7 @@ CONFIG_HAVE_ARCH_MMAP_RND_BITS=y
|
||||
CONFIG_ARCH_MMAP_RND_BITS=18
|
||||
CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
|
||||
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
|
||||
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
|
||||
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
|
||||
CONFIG_CLONE_BACKWARDS=y
|
||||
CONFIG_OLD_SIGSUSPEND3=y
|
||||
@ -666,7 +677,6 @@ CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
|
||||
# CONFIG_LOCK_EVENT_COUNTS is not set
|
||||
CONFIG_ARCH_HAS_RELR=y
|
||||
CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y
|
||||
CONFIG_HAVE_ARCH_PFN_VALID=y
|
||||
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
|
||||
|
||||
#
|
||||
@ -1039,6 +1049,8 @@ CONFIG_BRIDGE_NETFILTER=m
|
||||
# Core Netfilter Configuration
|
||||
#
|
||||
CONFIG_NETFILTER_INGRESS=y
|
||||
CONFIG_NETFILTER_EGRESS=y
|
||||
CONFIG_NETFILTER_SKIP_EGRESS=y
|
||||
CONFIG_NETFILTER_NETLINK=m
|
||||
CONFIG_NETFILTER_FAMILY_BRIDGE=y
|
||||
CONFIG_NETFILTER_FAMILY_ARP=y
|
||||
@ -1425,10 +1437,11 @@ CONFIG_NET_DSA_TAG_DSA=m
|
||||
CONFIG_NET_DSA_TAG_EDSA=m
|
||||
CONFIG_NET_DSA_TAG_MTK=m
|
||||
CONFIG_NET_DSA_TAG_KSZ=m
|
||||
CONFIG_NET_DSA_TAG_RTL4_A=m
|
||||
CONFIG_NET_DSA_TAG_OCELOT=m
|
||||
CONFIG_NET_DSA_TAG_OCELOT_8021Q=m
|
||||
CONFIG_NET_DSA_TAG_QCA=m
|
||||
CONFIG_NET_DSA_TAG_RTL4_A=m
|
||||
CONFIG_NET_DSA_TAG_RTL8_4=m
|
||||
CONFIG_NET_DSA_TAG_LAN9303=m
|
||||
CONFIG_NET_DSA_TAG_SJA1105=m
|
||||
CONFIG_NET_DSA_TAG_TRAILER=m
|
||||
@ -1746,7 +1759,7 @@ CONFIG_AF_RXRPC=m
|
||||
# CONFIG_RXKAD is not set
|
||||
# CONFIG_AF_KCM is not set
|
||||
CONFIG_STREAM_PARSER=y
|
||||
CONFIG_MCTP=m
|
||||
CONFIG_MCTP=y
|
||||
CONFIG_FIB_RULES=y
|
||||
CONFIG_WIRELESS=y
|
||||
CONFIG_WIRELESS_EXT=y
|
||||
@ -1762,6 +1775,10 @@ CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
|
||||
# CONFIG_CFG80211_DEBUGFS is not set
|
||||
CONFIG_CFG80211_CRDA_SUPPORT=y
|
||||
CONFIG_CFG80211_WEXT=y
|
||||
CONFIG_LIB80211=m
|
||||
CONFIG_LIB80211_CRYPT_WEP=m
|
||||
CONFIG_LIB80211_CRYPT_CCMP=m
|
||||
CONFIG_LIB80211_DEBUG=y
|
||||
CONFIG_MAC80211=m
|
||||
CONFIG_MAC80211_HAS_RC=y
|
||||
CONFIG_MAC80211_RC_MINSTREL=y
|
||||
@ -1973,6 +1990,7 @@ CONFIG_MTD_BLOCK=y
|
||||
# CONFIG_SSFDC is not set
|
||||
# CONFIG_SM_FTL is not set
|
||||
# CONFIG_MTD_OOPS is not set
|
||||
CONFIG_MTD_PSTORE=m
|
||||
# CONFIG_MTD_SWAP is not set
|
||||
# CONFIG_MTD_PARTITIONED_MASTER is not set
|
||||
|
||||
@ -2086,7 +2104,6 @@ CONFIG_OF_KOBJ=y
|
||||
CONFIG_OF_DYNAMIC=y
|
||||
CONFIG_OF_ADDRESS=y
|
||||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_NET=y
|
||||
CONFIG_OF_RESERVED_MEM=y
|
||||
CONFIG_OF_RESOLVE=y
|
||||
CONFIG_OF_OVERLAY=y
|
||||
@ -2108,7 +2125,6 @@ CONFIG_ZRAM_WRITEBACK=y
|
||||
# CONFIG_ZRAM_MEMORY_TRACKING is not set
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
|
||||
CONFIG_BLK_DEV_CRYPTOLOOP=m
|
||||
CONFIG_BLK_DEV_DRBD=m
|
||||
# CONFIG_DRBD_FAULT_INJECTION is not set
|
||||
# CONFIG_BLK_DEV_NBD is not set
|
||||
@ -2225,6 +2241,7 @@ CONFIG_SCSI_UFSHCD=m
|
||||
# CONFIG_SCSI_UFSHCD_PLATFORM is not set
|
||||
# CONFIG_SCSI_UFS_BSG is not set
|
||||
# CONFIG_SCSI_UFS_HPB is not set
|
||||
# CONFIG_SCSI_UFS_HWMON is not set
|
||||
# CONFIG_SCSI_DEBUG is not set
|
||||
# CONFIG_SCSI_VIRTIO is not set
|
||||
# CONFIG_SCSI_DH is not set
|
||||
@ -2293,6 +2310,7 @@ CONFIG_DM_DUST=m
|
||||
# CONFIG_DM_LOG_WRITES is not set
|
||||
CONFIG_DM_INTEGRITY=m
|
||||
# CONFIG_DM_ZONED is not set
|
||||
CONFIG_DM_AUDIT=y
|
||||
CONFIG_TARGET_CORE=m
|
||||
CONFIG_TCM_IBLOCK=m
|
||||
CONFIG_TCM_FILEIO=m
|
||||
@ -2323,6 +2341,7 @@ CONFIG_VXLAN=m
|
||||
CONFIG_GENEVE=m
|
||||
CONFIG_BAREUDP=m
|
||||
CONFIG_GTP=m
|
||||
CONFIG_AMT=m
|
||||
CONFIG_MACSEC=m
|
||||
CONFIG_NETCONSOLE=m
|
||||
# CONFIG_NETCONSOLE_DYNAMIC is not set
|
||||
@ -2381,6 +2400,9 @@ CONFIG_AMD_XGBE=m
|
||||
# CONFIG_AMD_XGBE_DCB is not set
|
||||
CONFIG_NET_VENDOR_AQUANTIA=y
|
||||
# CONFIG_NET_VENDOR_ARC is not set
|
||||
CONFIG_NET_VENDOR_ASIX=y
|
||||
CONFIG_SPI_AX88796C=m
|
||||
# CONFIG_SPI_AX88796C_COMPRESSION is not set
|
||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
CONFIG_NET_VENDOR_CADENCE=y
|
||||
# CONFIG_MACB is not set
|
||||
@ -2677,6 +2699,7 @@ CONFIG_MT7601U=m
|
||||
CONFIG_MT76_CORE=m
|
||||
CONFIG_MT76_LEDS=y
|
||||
CONFIG_MT76_USB=m
|
||||
CONFIG_MT76_SDIO=m
|
||||
CONFIG_MT76x02_LIB=m
|
||||
CONFIG_MT76x02_USB=m
|
||||
CONFIG_MT76_CONNAC_LIB=m
|
||||
@ -2688,6 +2711,8 @@ CONFIG_MT7615_COMMON=m
|
||||
CONFIG_MT7663_USB_SDIO_COMMON=m
|
||||
CONFIG_MT7663U=m
|
||||
# CONFIG_MT7663S is not set
|
||||
CONFIG_MT7921_COMMON=m
|
||||
CONFIG_MT7921S=m
|
||||
CONFIG_WLAN_VENDOR_MICROCHIP=y
|
||||
# CONFIG_WILC1000_SDIO is not set
|
||||
# CONFIG_WILC1000_SPI is not set
|
||||
@ -2720,8 +2745,8 @@ CONFIG_RTLWIFI_USB=m
|
||||
CONFIG_RTL8192C_COMMON=m
|
||||
CONFIG_RTL8XXXU=m
|
||||
CONFIG_RTL8XXXU_UNTESTED=y
|
||||
CONFIG_RTL8723CS=m
|
||||
CONFIG_RTW88=m
|
||||
# CONFIG_RTW89 is not set
|
||||
# CONFIG_WLAN_VENDOR_RSI is not set
|
||||
# CONFIG_WLAN_VENDOR_ST is not set
|
||||
# CONFIG_WLAN_VENDOR_TI is not set
|
||||
@ -2730,7 +2755,6 @@ CONFIG_RTL8723DU=m
|
||||
CONFIG_RTL8723DS=m
|
||||
CONFIG_RTL8822CS=m
|
||||
CONFIG_RTL8822BU=m
|
||||
CONFIG_RTL8188EU=m
|
||||
CONFIG_RTL8821CU=m
|
||||
# CONFIG_WLAN_VENDOR_XRADIO is not set
|
||||
CONFIG_88XXAU=m
|
||||
@ -2765,7 +2789,7 @@ CONFIG_INPUT=y
|
||||
CONFIG_INPUT_LEDS=y
|
||||
CONFIG_INPUT_FF_MEMLESS=m
|
||||
# CONFIG_INPUT_SPARSEKMAP is not set
|
||||
# CONFIG_INPUT_MATRIXKMAP is not set
|
||||
CONFIG_INPUT_MATRIXKMAP=m
|
||||
|
||||
#
|
||||
# Userland interfaces
|
||||
@ -2796,6 +2820,7 @@ CONFIG_KEYBOARD_GPIO=y
|
||||
# CONFIG_KEYBOARD_TCA6416 is not set
|
||||
# CONFIG_KEYBOARD_TCA8418 is not set
|
||||
# CONFIG_KEYBOARD_MATRIX is not set
|
||||
CONFIG_KEYBOARD_KB151=m
|
||||
# CONFIG_KEYBOARD_LM8323 is not set
|
||||
# CONFIG_KEYBOARD_LM8333 is not set
|
||||
# CONFIG_KEYBOARD_MAX7359 is not set
|
||||
@ -2813,6 +2838,7 @@ CONFIG_KEYBOARD_IQS62X=m
|
||||
# CONFIG_KEYBOARD_XTKBD is not set
|
||||
# CONFIG_KEYBOARD_CAP11XX is not set
|
||||
# CONFIG_KEYBOARD_BCM is not set
|
||||
CONFIG_KEYBOARD_CYPRESS_SF=m
|
||||
CONFIG_INPUT_MOUSE=y
|
||||
CONFIG_MOUSE_PS2=y
|
||||
CONFIG_MOUSE_PS2_ALPS=y
|
||||
@ -3228,6 +3254,7 @@ CONFIG_SPI_AXI_SPI_ENGINE=m
|
||||
CONFIG_SPI_BITBANG=m
|
||||
CONFIG_SPI_CADENCE=m
|
||||
# CONFIG_SPI_CADENCE_QUADSPI is not set
|
||||
CONFIG_SPI_CADENCE_XSPI=m
|
||||
CONFIG_SPI_DESIGNWARE=m
|
||||
CONFIG_SPI_DW_DMA=y
|
||||
CONFIG_SPI_DW_MMIO=m
|
||||
@ -3471,6 +3498,7 @@ CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_POWER_SUPPLY_HWMON=y
|
||||
# CONFIG_PDA_POWER is not set
|
||||
# CONFIG_GENERIC_ADC_BATTERY is not set
|
||||
CONFIG_IP5XXX_POWER=m
|
||||
# CONFIG_TEST_POWER is not set
|
||||
CONFIG_CHARGER_ADP5061=m
|
||||
CONFIG_BATTERY_CW2015=m
|
||||
@ -3588,6 +3616,7 @@ CONFIG_SENSORS_MAX1668=m
|
||||
CONFIG_SENSORS_MAX197=m
|
||||
CONFIG_SENSORS_MAX31722=m
|
||||
CONFIG_SENSORS_MAX31730=m
|
||||
CONFIG_SENSORS_MAX6620=m
|
||||
CONFIG_SENSORS_MAX6621=m
|
||||
CONFIG_SENSORS_MAX6639=m
|
||||
CONFIG_SENSORS_MAX6642=m
|
||||
@ -3880,7 +3909,6 @@ CONFIG_MFD_SYSCON=y
|
||||
# CONFIG_MFD_TPS65910 is not set
|
||||
# CONFIG_MFD_TPS65912_I2C is not set
|
||||
# CONFIG_MFD_TPS65912_SPI is not set
|
||||
# CONFIG_MFD_TPS80031 is not set
|
||||
# CONFIG_TWL4030_CORE is not set
|
||||
# CONFIG_TWL6040_CORE is not set
|
||||
CONFIG_MFD_WL1273_CORE=m
|
||||
@ -4025,14 +4053,19 @@ CONFIG_IR_GPIO_TX=m
|
||||
CONFIG_IR_PWM_TX=m
|
||||
CONFIG_IR_SUNXI=m
|
||||
# CONFIG_IR_SERIAL is not set
|
||||
# CONFIG_IR_SIR is not set
|
||||
CONFIG_RC_XBOX_DVD=m
|
||||
# CONFIG_IR_TOY is not set
|
||||
CONFIG_CEC_CORE=y
|
||||
CONFIG_CEC_NOTIFIER=y
|
||||
CONFIG_CEC_PIN=y
|
||||
|
||||
#
|
||||
# CEC support
|
||||
#
|
||||
# CONFIG_CEC_PIN_ERROR_INJ is not set
|
||||
# CONFIG_MEDIA_CEC_SUPPORT is not set
|
||||
# end of CEC support
|
||||
|
||||
CONFIG_MEDIA_SUPPORT=m
|
||||
CONFIG_MEDIA_SUPPORT_FILTER=y
|
||||
CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
|
||||
@ -4074,10 +4107,6 @@ CONFIG_VIDEOBUF_VMALLOC=m
|
||||
#
|
||||
CONFIG_MEDIA_CONTROLLER_DVB=y
|
||||
CONFIG_MEDIA_CONTROLLER_REQUEST_API=y
|
||||
|
||||
#
|
||||
# Please notice that the enabled Media controller Request API is EXPERIMENTAL
|
||||
#
|
||||
# end of Media controller options
|
||||
|
||||
#
|
||||
@ -4322,6 +4351,7 @@ CONFIG_VIDEO_CX25840=m
|
||||
CONFIG_VIDEO_APTINA_PLL=m
|
||||
CONFIG_VIDEO_CCS_PLL=m
|
||||
CONFIG_VIDEO_HI556=m
|
||||
CONFIG_VIDEO_HI846=m
|
||||
CONFIG_VIDEO_IMX208=m
|
||||
CONFIG_VIDEO_IMX214=m
|
||||
CONFIG_VIDEO_IMX219=m
|
||||
@ -4357,6 +4387,7 @@ CONFIG_VIDEO_OV9282=m
|
||||
CONFIG_VIDEO_OV9640=m
|
||||
CONFIG_VIDEO_OV9650=m
|
||||
CONFIG_VIDEO_OV13858=m
|
||||
CONFIG_VIDEO_OV13B10=m
|
||||
CONFIG_VIDEO_VS6624=m
|
||||
CONFIG_VIDEO_MT9M001=m
|
||||
CONFIG_VIDEO_MT9M032=m
|
||||
@ -4649,6 +4680,7 @@ CONFIG_DRM_PANEL_BOE_HIMAX8279D=m
|
||||
CONFIG_DRM_PANEL_DSI_CM=m
|
||||
CONFIG_DRM_PANEL_LVDS=m
|
||||
CONFIG_DRM_PANEL_SIMPLE=m
|
||||
CONFIG_DRM_PANEL_EDP=m
|
||||
# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set
|
||||
CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m
|
||||
CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m
|
||||
@ -4682,6 +4714,7 @@ CONFIG_DRM_PANEL_RONBO_RB070D30=m
|
||||
CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
|
||||
CONFIG_DRM_PANEL_SAMSUNG_DB7430=m
|
||||
CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m
|
||||
CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m
|
||||
CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m
|
||||
CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m
|
||||
# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
|
||||
@ -4692,6 +4725,7 @@ CONFIG_DRM_PANEL_SEIKO_43WVF1G=m
|
||||
CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
|
||||
CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
|
||||
CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m
|
||||
CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m
|
||||
CONFIG_DRM_PANEL_SITRONIX_ST7701=m
|
||||
# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set
|
||||
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
|
||||
@ -5011,6 +5045,8 @@ CONFIG_SND_SOC_BD28623=m
|
||||
# CONFIG_SND_SOC_CS35L34 is not set
|
||||
# CONFIG_SND_SOC_CS35L35 is not set
|
||||
CONFIG_SND_SOC_CS35L36=m
|
||||
CONFIG_SND_SOC_CS35L41_SPI=m
|
||||
CONFIG_SND_SOC_CS35L41_I2C=m
|
||||
# CONFIG_SND_SOC_CS42L42 is not set
|
||||
# CONFIG_SND_SOC_CS42L51_I2C is not set
|
||||
# CONFIG_SND_SOC_CS42L52 is not set
|
||||
@ -5044,6 +5080,7 @@ CONFIG_SND_SOC_MAX98088=m
|
||||
# CONFIG_SND_SOC_MAX98504 is not set
|
||||
CONFIG_SND_SOC_MAX9867=m
|
||||
# CONFIG_SND_SOC_MAX98927 is not set
|
||||
CONFIG_SND_SOC_MAX98520=m
|
||||
# CONFIG_SND_SOC_MAX98373_I2C is not set
|
||||
# CONFIG_SND_SOC_MAX98390 is not set
|
||||
# CONFIG_SND_SOC_MAX9860 is not set
|
||||
@ -5071,6 +5108,7 @@ CONFIG_SND_SOC_RL6231=m
|
||||
# CONFIG_SND_SOC_RT5631 is not set
|
||||
CONFIG_SND_SOC_RT5640=m
|
||||
CONFIG_SND_SOC_RT5659=m
|
||||
CONFIG_SND_SOC_RT9120=m
|
||||
# CONFIG_SND_SOC_SGTL5000 is not set
|
||||
CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
|
||||
CONFIG_SND_SOC_SIMPLE_MUX=m
|
||||
@ -5139,6 +5177,7 @@ CONFIG_SND_SOC_MT6660=m
|
||||
CONFIG_SND_SOC_NAU8315=m
|
||||
# CONFIG_SND_SOC_NAU8540 is not set
|
||||
# CONFIG_SND_SOC_NAU8810 is not set
|
||||
CONFIG_SND_SOC_NAU8821=m
|
||||
CONFIG_SND_SOC_NAU8822=m
|
||||
# CONFIG_SND_SOC_NAU8824 is not set
|
||||
# CONFIG_SND_SOC_TPA6130A2 is not set
|
||||
@ -5151,6 +5190,9 @@ CONFIG_SND_SOC_LPASS_TX_MACRO=m
|
||||
CONFIG_SND_SIMPLE_CARD_UTILS=m
|
||||
CONFIG_SND_SIMPLE_CARD=m
|
||||
# CONFIG_SND_AUDIO_GRAPH_CARD is not set
|
||||
CONFIG_SND_AUDIO_GRAPH_CARD2=m
|
||||
CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=m
|
||||
CONFIG_SND_TEST_COMPONENT=m
|
||||
CONFIG_SND_VIRTIO=m
|
||||
|
||||
#
|
||||
@ -5206,6 +5248,7 @@ CONFIG_HID_KYE=m
|
||||
CONFIG_HID_UCLOGIC=m
|
||||
CONFIG_HID_WALTOP=m
|
||||
CONFIG_HID_VIEWSONIC=m
|
||||
CONFIG_HID_XIAOMI=m
|
||||
CONFIG_HID_GYRATION=m
|
||||
CONFIG_HID_ICADE=m
|
||||
# CONFIG_HID_ITE is not set
|
||||
@ -5229,6 +5272,8 @@ CONFIG_HID_REDRAGON=m
|
||||
CONFIG_HID_MICROSOFT=m
|
||||
CONFIG_HID_MONTEREY=m
|
||||
CONFIG_HID_MULTITOUCH=m
|
||||
CONFIG_HID_NINTENDO=m
|
||||
# CONFIG_NINTENDO_FF is not set
|
||||
CONFIG_HID_NTI=m
|
||||
CONFIG_HID_NTRIG=m
|
||||
CONFIG_HID_ORTEK=m
|
||||
@ -5243,8 +5288,6 @@ CONFIG_HID_PICOLCD_LCD=y
|
||||
CONFIG_HID_PICOLCD_LEDS=y
|
||||
CONFIG_HID_PICOLCD_CIR=y
|
||||
CONFIG_HID_PLANTRONICS=m
|
||||
CONFIG_HID_PLAYSTATION=m
|
||||
# CONFIG_PLAYSTATION_FF is not set
|
||||
CONFIG_HID_PRIMAX=m
|
||||
# CONFIG_HID_RETRODE is not set
|
||||
CONFIG_HID_ROCCAT=m
|
||||
@ -5638,6 +5681,7 @@ CONFIG_TYPEC_TPS6598X=m
|
||||
# CONFIG_TYPEC_ANX7688 is not set
|
||||
CONFIG_TYPEC_HD3SS3220=m
|
||||
# CONFIG_TYPEC_STUSB160X is not set
|
||||
CONFIG_TYPEC_EXTCON=m
|
||||
|
||||
#
|
||||
# USB Type-C Multiplexer/DeMultiplexer Switch support
|
||||
@ -6101,6 +6145,7 @@ CONFIG_MOST_COMPONENTS=m
|
||||
CONFIG_XIL_AXIS_FIFO=m
|
||||
# CONFIG_FIELDBUS_DEV is not set
|
||||
CONFIG_WFX=m
|
||||
CONFIG_RTL8723CS=m
|
||||
# CONFIG_GOLDFISH is not set
|
||||
# CONFIG_CHROME_PLATFORMS is not set
|
||||
# CONFIG_MELLANOX_PLATFORM is not set
|
||||
@ -6111,7 +6156,7 @@ CONFIG_COMMON_CLK=y
|
||||
#
|
||||
# Clock driver for ARM Reference designs
|
||||
#
|
||||
# CONFIG_ICST is not set
|
||||
# CONFIG_CLK_ICST is not set
|
||||
# CONFIG_CLK_SP810 is not set
|
||||
# end of Clock driver for ARM Reference designs
|
||||
|
||||
@ -6146,7 +6191,6 @@ CONFIG_SUN50I_A100_R_CCU=y
|
||||
CONFIG_SUN50I_H6_CCU=y
|
||||
CONFIG_SUN50I_H616_CCU=y
|
||||
CONFIG_SUN50I_H6_R_CCU=y
|
||||
CONFIG_SUN8I_A83T_CCU=y
|
||||
CONFIG_SUN8I_H3_CCU=y
|
||||
CONFIG_SUN8I_DE2_CCU=y
|
||||
CONFIG_SUN8I_R_CCU=y
|
||||
@ -6319,9 +6363,15 @@ CONFIG_IIO_TRIGGERED_EVENT=m
|
||||
#
|
||||
CONFIG_ADIS16201=m
|
||||
CONFIG_ADIS16209=m
|
||||
CONFIG_ADXL313=m
|
||||
CONFIG_ADXL313_I2C=m
|
||||
CONFIG_ADXL313_SPI=m
|
||||
CONFIG_ADXL345=m
|
||||
CONFIG_ADXL345_I2C=m
|
||||
CONFIG_ADXL345_SPI=m
|
||||
CONFIG_ADXL355=m
|
||||
CONFIG_ADXL355_I2C=m
|
||||
CONFIG_ADXL355_SPI=m
|
||||
CONFIG_ADXL372=m
|
||||
CONFIG_ADXL372_SPI=m
|
||||
CONFIG_ADXL372_I2C=m
|
||||
@ -6470,11 +6520,13 @@ CONFIG_BME680_SPI=m
|
||||
# CONFIG_IAQCORE is not set
|
||||
CONFIG_PMS7003=m
|
||||
# CONFIG_SCD30_CORE is not set
|
||||
CONFIG_SCD4X=m
|
||||
CONFIG_SENSIRION_SGP30=m
|
||||
CONFIG_SENSIRION_SGP40=m
|
||||
CONFIG_SPS30=m
|
||||
CONFIG_SPS30_I2C=m
|
||||
CONFIG_SPS30_SERIAL=m
|
||||
CONFIG_SENSEAIR_SUNRISE_CO2=m
|
||||
# CONFIG_VZ89X is not set
|
||||
# end of Chemical Sensors
|
||||
|
||||
@ -6567,6 +6619,7 @@ CONFIG_IIO_SIMPLE_DUMMY=m
|
||||
#
|
||||
# CONFIG_ADF4350 is not set
|
||||
# CONFIG_ADF4371 is not set
|
||||
CONFIG_ADRF6780=m
|
||||
# end of Phase-Locked Loop (PLL) frequency synthesizers
|
||||
# end of Frequency Synthesizers DDS/PLL
|
||||
|
||||
@ -6848,6 +6901,7 @@ CONFIG_TMP117=m
|
||||
CONFIG_TSYS01=m
|
||||
CONFIG_TSYS02D=m
|
||||
CONFIG_MAX31856=m
|
||||
CONFIG_MAX31865=m
|
||||
# end of Temperature sensors
|
||||
|
||||
CONFIG_PWM=y
|
||||
@ -6891,7 +6945,13 @@ CONFIG_PHY_SUN4I_USB=y
|
||||
CONFIG_PHY_SUN6I_MIPI_DPHY=y
|
||||
CONFIG_PHY_SUN9I_USB=y
|
||||
CONFIG_PHY_SUN50I_USB3=y
|
||||
|
||||
#
|
||||
# PHY drivers for Broadcom platforms
|
||||
#
|
||||
# CONFIG_BCM_KONA_USB2_PHY is not set
|
||||
# end of PHY drivers for Broadcom platforms
|
||||
|
||||
CONFIG_PHY_CADENCE_TORRENT=m
|
||||
CONFIG_PHY_CADENCE_DPHY=m
|
||||
CONFIG_PHY_CADENCE_SIERRA=m
|
||||
@ -7197,6 +7257,11 @@ CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
|
||||
# CONFIG_PSTORE_CONSOLE is not set
|
||||
# CONFIG_PSTORE_PMSG is not set
|
||||
CONFIG_PSTORE_RAM=m
|
||||
CONFIG_PSTORE_ZONE=m
|
||||
CONFIG_PSTORE_BLK=m
|
||||
CONFIG_PSTORE_BLK_BLKDEV="m"
|
||||
CONFIG_PSTORE_BLK_KMSG_SIZE=64
|
||||
CONFIG_PSTORE_BLK_MAX_REASON=2
|
||||
CONFIG_SYSV_FS=m
|
||||
CONFIG_UFS_FS=m
|
||||
# CONFIG_UFS_FS_WRITE is not set
|
||||
@ -7239,14 +7304,14 @@ CONFIG_NFSD_SCSILAYOUT=y
|
||||
CONFIG_NFSD_FLEXFILELAYOUT=y
|
||||
# CONFIG_NFSD_V4_2_INTER_SSC is not set
|
||||
CONFIG_NFSD_V4_SECURITY_LABEL=y
|
||||
CONFIG_GRACE_PERIOD=y
|
||||
CONFIG_LOCKD=y
|
||||
CONFIG_GRACE_PERIOD=m
|
||||
CONFIG_LOCKD=m
|
||||
CONFIG_LOCKD_V4=y
|
||||
CONFIG_NFS_ACL_SUPPORT=y
|
||||
CONFIG_NFS_ACL_SUPPORT=m
|
||||
CONFIG_NFS_COMMON=y
|
||||
CONFIG_NFS_V4_2_SSC_HELPER=y
|
||||
CONFIG_SUNRPC=y
|
||||
CONFIG_SUNRPC_GSS=y
|
||||
CONFIG_SUNRPC=m
|
||||
CONFIG_SUNRPC_GSS=m
|
||||
CONFIG_SUNRPC_BACKCHANNEL=y
|
||||
CONFIG_SUNRPC_SWAP=y
|
||||
CONFIG_RPCSEC_GSS_KRB5=m
|
||||
@ -7269,7 +7334,6 @@ CONFIG_CIFS_DFS_UPCALL=y
|
||||
# CONFIG_CIFS_SWN_UPCALL is not set
|
||||
CONFIG_CIFS_FSCACHE=y
|
||||
CONFIG_SMB_SERVER=m
|
||||
CONFIG_SMB_SERVER_SMBDIRECT=y
|
||||
CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y
|
||||
CONFIG_SMB_SERVER_KERBEROS5=y
|
||||
CONFIG_SMBFS_COMMON=m
|
||||
@ -7358,7 +7422,6 @@ CONFIG_SECURITY_PATH=y
|
||||
CONFIG_LSM_MMAP_MIN_ADDR=0
|
||||
CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
|
||||
CONFIG_HARDENED_USERCOPY=y
|
||||
CONFIG_HARDENED_USERCOPY_FALLBACK=y
|
||||
CONFIG_FORTIFY_SOURCE=y
|
||||
# CONFIG_STATIC_USERMODEHELPER is not set
|
||||
CONFIG_SECURITY_SELINUX=y
|
||||
@ -7492,7 +7555,6 @@ CONFIG_CRYPTO_PCRYPT=m
|
||||
CONFIG_CRYPTO_CRYPTD=y
|
||||
CONFIG_CRYPTO_AUTHENC=m
|
||||
CONFIG_CRYPTO_TEST=m
|
||||
CONFIG_CRYPTO_SIMD=y
|
||||
CONFIG_CRYPTO_ENGINE=y
|
||||
|
||||
#
|
||||
@ -7750,6 +7812,7 @@ CONFIG_XZ_DEC_IA64=y
|
||||
CONFIG_XZ_DEC_ARM=y
|
||||
CONFIG_XZ_DEC_ARMTHUMB=y
|
||||
CONFIG_XZ_DEC_SPARC=y
|
||||
# CONFIG_XZ_DEC_MICROLZMA is not set
|
||||
CONFIG_XZ_DEC_BCJ=y
|
||||
CONFIG_XZ_DEC_TEST=m
|
||||
CONFIG_DECOMPRESS_GZIP=y
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -9,13 +9,13 @@ case $BRANCH in
|
||||
|
||||
current)
|
||||
|
||||
KERNELBRANCH='branch:linux-5.10.y'
|
||||
KERNELBRANCH='branch:linux-5.15.y'
|
||||
|
||||
;;
|
||||
|
||||
edge)
|
||||
|
||||
KERNELBRANCH='branch:linux-5.15.y'
|
||||
KERNELBRANCH='branch:linux-5.16.y'
|
||||
|
||||
;;
|
||||
|
||||
|
||||
@ -11,11 +11,11 @@ LINUXFAMILY=sunxi64
|
||||
|
||||
case $BRANCH in
|
||||
|
||||
legacy) KERNEL_VERSION_LEVEL="5.4" ;;
|
||||
legacy) KERNEL_VERSION_LEVEL="5.10" ;;
|
||||
|
||||
current) KERNEL_VERSION_LEVEL="5.10" ;;
|
||||
current) KERNEL_VERSION_LEVEL="5.15" ;;
|
||||
|
||||
edge) KERNEL_VERSION_LEVEL="5.15" ;;
|
||||
edge) KERNEL_VERSION_LEVEL="5.16" ;;
|
||||
esac
|
||||
|
||||
case "$KERNEL_VERSION_LEVEL" in
|
||||
|
||||
@ -12,9 +12,9 @@ GOVERNOR=ondemand
|
||||
|
||||
case $BRANCH in
|
||||
|
||||
legacy) KERNEL_VERSION_LEVEL="5.4" ;;
|
||||
current) KERNEL_VERSION_LEVEL="5.10" ;;
|
||||
edge) KERNEL_VERSION_LEVEL="5.15" ;;
|
||||
legacy) KERNEL_VERSION_LEVEL="5.10" ;;
|
||||
current) KERNEL_VERSION_LEVEL="5.15" ;;
|
||||
edge) KERNEL_VERSION_LEVEL="5.16" ;;
|
||||
|
||||
esac
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
enable_extension "marvell-tools"
|
||||
ARCH=arm64
|
||||
BOOTBRANCH='branch:v2021.01'
|
||||
BOOTBRANCH='branch:v2022.01'
|
||||
BOOTENV_FILE='mvebu64.txt'
|
||||
ATFSOURCE='https://github.com/MarvellEmbeddedProcessors/atf-marvell'
|
||||
ATFDIR='arm-trusted-firmware-espressobin'
|
||||
@ -36,12 +36,12 @@ case $BRANCH in
|
||||
|
||||
current)
|
||||
|
||||
KERNELBRANCH='branch:linux-5.10.y'
|
||||
KERNELBRANCH='branch:linux-5.15.y'
|
||||
|
||||
;;
|
||||
|
||||
edge)
|
||||
KERNELBRANCH='branch:linux-5.15.y'
|
||||
KERNELBRANCH='branch:linux-5.16.y'
|
||||
;;
|
||||
|
||||
esac
|
||||
|
||||
@ -23,7 +23,7 @@ case $BRANCH in
|
||||
;;
|
||||
|
||||
edge)
|
||||
KERNELBRANCH='branch:linux-5.15.y'
|
||||
KERNELBRANCH='branch:linux-5.16.y'
|
||||
;;
|
||||
|
||||
esac
|
||||
|
||||
@ -19,13 +19,13 @@ case $BRANCH in
|
||||
|
||||
current)
|
||||
|
||||
KERNELBRANCH='branch:linux-5.10.y'
|
||||
KERNELBRANCH='branch:linux-5.15.y'
|
||||
|
||||
;;
|
||||
|
||||
edge)
|
||||
|
||||
KERNELBRANCH='branch:linux-5.15.y'
|
||||
KERNELBRANCH='branch:linux-5.16.y'
|
||||
|
||||
;;
|
||||
|
||||
|
||||
@ -26,13 +26,13 @@ case $BRANCH in
|
||||
|
||||
current)
|
||||
|
||||
KERNELBRANCH='branch:linux-5.10.y'
|
||||
KERNELBRANCH='branch:linux-5.15.y'
|
||||
|
||||
;;
|
||||
|
||||
edge)
|
||||
|
||||
KERNELBRANCH='branch:linux-5.15.y'
|
||||
KERNELBRANCH='branch:linux-5.16.y'
|
||||
|
||||
;;
|
||||
|
||||
|
||||
@ -107,21 +107,20 @@ compilation_prepare()
|
||||
# Linux splash file
|
||||
#
|
||||
|
||||
if linux-version compare "${version}" ge 5.8.10 && [ $SKIP_BOOTSPLASH != yes ]; then
|
||||
if linux-version compare "${version}" ge 5.10 && [ $SKIP_BOOTSPLASH != yes ]; then
|
||||
|
||||
display_alert "Adding" "Kernel splash file" "info"
|
||||
|
||||
if linux-version compare "${version}" ge 5.13; then
|
||||
process_patch_file "${SRC}/patch/misc/bootsplash-5.10.y-0001-Revert-vgacon-drop-unused-vga_init_done.patch" "applying"
|
||||
fi
|
||||
process_patch_file "${SRC}/patch/misc/bootsplash-5.16.y-0001-Revert-fbcon-Add-option-to-enable-legacy-hardware-ac.patch" "applying"
|
||||
|
||||
process_patch_file "${SRC}/patch/misc/bootsplash-5.8.10-0001-Revert-vgacon-remove-software-scrollback-support.patch" "applying"
|
||||
process_patch_file "${SRC}/patch/misc/bootsplash-5.8.10-0002-Revert-fbcon-remove-now-unusued-softback_lines-curso.patch" "applying"
|
||||
if linux-version compare "${version}" ge 5.10; then
|
||||
process_patch_file "${SRC}/patch/misc/bootsplash-5.10.y-0003-Revert-fbcon-remove-soft-scrollback-code.patch" "applying"
|
||||
else
|
||||
process_patch_file "${SRC}/patch/misc/bootsplash-5.8.10-0003-Revert-fbcon-remove-soft-scrollback-code.patch" "applying"
|
||||
if linux-version compare "${version}" ge 5.15; then
|
||||
process_patch_file "${SRC}/patch/misc/bootsplash-5.16.y-0002-Revert-vgacon-drop-unused-vga_init_done.patch" "applying"
|
||||
fi
|
||||
process_patch_file "${SRC}/patch/misc/bootsplash-5.16.y-0003-Revert-vgacon-remove-software-scrollback-support.patch" "applying"
|
||||
process_patch_file "${SRC}/patch/misc/bootsplash-5.16.y-0004-Revert-drivers-video-fbcon-fix-NULL-dereference-in-f.patch" "applying"
|
||||
process_patch_file "${SRC}/patch/misc/bootsplash-5.16.y-0005-Revert-fbcon-remove-no-op-fbcon_set_origin.patch" "applying"
|
||||
process_patch_file "${SRC}/patch/misc/bootsplash-5.16.y-0006-Revert-fbcon-remove-now-unusued-softback_lines-curso.patch" "applying"
|
||||
process_patch_file "${SRC}/patch/misc/bootsplash-5.16.y-0007-Revert-fbcon-remove-soft-scrollback-code.patch" "applying"
|
||||
|
||||
process_patch_file "${SRC}/patch/misc/0001-bootsplash.patch" "applying"
|
||||
process_patch_file "${SRC}/patch/misc/0002-bootsplash.patch" "applying"
|
||||
@ -168,6 +167,7 @@ compilation_prepare()
|
||||
# manual overrides
|
||||
if linux-version compare "${version}" ge 5.4.3 && linux-version compare "${version}" le 5.5 ; then aufstag="5.4.3"; fi
|
||||
if linux-version compare "${version}" ge 5.10.82 && linux-version compare "${version}" le 5.11 ; then aufstag="5.10.82"; fi
|
||||
if linux-version compare "${version}" ge 5.15.5 && linux-version compare "${version}" le 5.16 ; then aufstag="5.15.5"; fi
|
||||
|
||||
# check if Mr. Okajima already made a branch for this version
|
||||
improved_git ls-remote --exit-code --heads $GITHUB_SOURCE/sfjro/aufs5-standalone "aufs${aufstag}" >/dev/null
|
||||
|
||||
@ -1,82 +0,0 @@
|
||||
From 87659cab302321c59b4cbe2d5e978892519122ca Mon Sep 17 00:00:00 2001
|
||||
From: Thierry Escande <thierry.escande@collabora.com>
|
||||
Date: Wed, 26 Oct 2016 10:52:05 +0200
|
||||
Subject: [PATCH 06/75] ODROID-XU4: videobuf2-dc: Move vb2_dc_get_base_sgt()
|
||||
above mmap callbacks
|
||||
|
||||
This patch moves vb2_dc_get_base_sgt() function above mmap buffers
|
||||
callbacks, particularly vb2_dc_alloc() and vb2_dc_mmap() from where it
|
||||
will be called for cacheable MMAP support introduced in the next patch.
|
||||
|
||||
Change-Id: Ia504fbc1f0b3741986e8fff1ad329215b6e2db2e
|
||||
Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
|
||||
Signed-off-by: memeka <mihailescu2m@gmail.com>
|
||||
---
|
||||
.../common/videobuf2/videobuf2-dma-contig.c | 44 +++++++++----------
|
||||
1 file changed, 22 insertions(+), 22 deletions(-)
|
||||
|
||||
diff --git a/drivers/media/common/videobuf2/videobuf2-dma-contig.c b/drivers/media/common/videobuf2/videobuf2-dma-contig.c
|
||||
index a7f61ba85440..6298b4f23a29 100644
|
||||
--- a/drivers/media/common/videobuf2/videobuf2-dma-contig.c
|
||||
+++ b/drivers/media/common/videobuf2/videobuf2-dma-contig.c
|
||||
@@ -62,6 +62,28 @@ static unsigned long vb2_dc_get_contiguous_size(struct sg_table *sgt)
|
||||
return size;
|
||||
}
|
||||
|
||||
+static struct sg_table *vb2_dc_get_base_sgt(struct vb2_dc_buf *buf)
|
||||
+{
|
||||
+ int ret;
|
||||
+ struct sg_table *sgt;
|
||||
+
|
||||
+ sgt = kmalloc(sizeof(*sgt), GFP_KERNEL);
|
||||
+ if (!sgt) {
|
||||
+ dev_err(buf->dev, "failed to alloc sg table\n");
|
||||
+ return NULL;
|
||||
+ }
|
||||
+
|
||||
+ ret = dma_get_sgtable_attrs(buf->dev, sgt, buf->cookie, buf->dma_addr,
|
||||
+ buf->size, buf->attrs);
|
||||
+ if (ret < 0) {
|
||||
+ dev_err(buf->dev, "failed to get scatterlist from DMA API\n");
|
||||
+ kfree(sgt);
|
||||
+ return NULL;
|
||||
+ }
|
||||
+
|
||||
+ return sgt;
|
||||
+}
|
||||
+
|
||||
/*********************************************/
|
||||
/* callbacks for all buffers */
|
||||
/*********************************************/
|
||||
@@ -375,28 +397,6 @@ static const struct dma_buf_ops vb2_dc_dmabuf_ops = {
|
||||
.release = vb2_dc_dmabuf_ops_release,
|
||||
};
|
||||
|
||||
-static struct sg_table *vb2_dc_get_base_sgt(struct vb2_dc_buf *buf)
|
||||
-{
|
||||
- int ret;
|
||||
- struct sg_table *sgt;
|
||||
-
|
||||
- sgt = kmalloc(sizeof(*sgt), GFP_KERNEL);
|
||||
- if (!sgt) {
|
||||
- dev_err(buf->dev, "failed to alloc sg table\n");
|
||||
- return NULL;
|
||||
- }
|
||||
-
|
||||
- ret = dma_get_sgtable_attrs(buf->dev, sgt, buf->cookie, buf->dma_addr,
|
||||
- buf->size, buf->attrs);
|
||||
- if (ret < 0) {
|
||||
- dev_err(buf->dev, "failed to get scatterlist from DMA API\n");
|
||||
- kfree(sgt);
|
||||
- return NULL;
|
||||
- }
|
||||
-
|
||||
- return sgt;
|
||||
-}
|
||||
-
|
||||
static struct dma_buf *vb2_dc_get_dmabuf(void *buf_priv, unsigned long flags)
|
||||
{
|
||||
struct vb2_dc_buf *buf = buf_priv;
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -50,9 +50,9 @@ index 7e0934180724..407142a5ed0b 100644
|
||||
--- a/arch/arm/boot/dts/Makefile
|
||||
+++ b/arch/arm/boot/dts/Makefile
|
||||
@@ -1498,3 +1498,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
|
||||
aspeed-bmc-portwell-neptune.dtb \
|
||||
aspeed-bmc-quanta-q71l.dtb \
|
||||
aspeed-bmc-supermicro-x11spi.dtb
|
||||
aspeed-bmc-supermicro-x11spi.dtb \
|
||||
aspeed-bmc-inventec-transformers.dtb \
|
||||
aspeed-bmc-tyan-s7106.dtb
|
||||
+
|
||||
+targets += $(dtb-y)
|
||||
+
|
||||
@ -318,9 +318,9 @@ index 54582673fc1a..e82ce99da50c 100644
|
||||
--- a/scripts/Makefile.lib
|
||||
+++ b/scripts/Makefile.lib
|
||||
@@ -311,6 +311,7 @@ DTC_FLAGS += -Wno-interrupt_provider
|
||||
# Disable noisy checks by default
|
||||
ifeq ($(findstring 1,$(KBUILD_EXTRA_WARN)),)
|
||||
DTC_FLAGS += -Wno-unit_address_vs_reg \
|
||||
-Wno-unit_address_format \
|
||||
+ -Wno-gpios_property \
|
||||
-Wno-avoid_unnecessary_addr_size \
|
||||
-Wno-alias_paths \
|
||||
|
||||
@ -0,0 +1,287 @@
|
||||
From 3ec70749ae3cb072f19d886981a217121f776415 Mon Sep 17 00:00:00 2001
|
||||
From: Igor Pecovnik <igor.pecovnik@gmail.com>
|
||||
Date: Sat, 6 Nov 2021 19:15:23 +0100
|
||||
Subject: [PATCH] Revert "net: Remove net/ipx.h and uapi/linux/ipx.h header
|
||||
files"
|
||||
|
||||
This reverts commit 6c9b40844751ea30c72f7a2f92f4d704bc6b2927.
|
||||
---
|
||||
include/net/ipx.h | 171 +++++++++++++++++++++++++++++++++++++++
|
||||
include/uapi/linux/ipx.h | 87 ++++++++++++++++++++
|
||||
2 files changed, 258 insertions(+)
|
||||
create mode 100644 include/net/ipx.h
|
||||
create mode 100644 include/uapi/linux/ipx.h
|
||||
|
||||
diff --git a/include/net/ipx.h b/include/net/ipx.h
|
||||
new file mode 100644
|
||||
index 000000000000..9d1342807b59
|
||||
--- /dev/null
|
||||
+++ b/include/net/ipx.h
|
||||
@@ -0,0 +1,171 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0 */
|
||||
+#ifndef _NET_INET_IPX_H_
|
||||
+#define _NET_INET_IPX_H_
|
||||
+/*
|
||||
+ * The following information is in its entirety obtained from:
|
||||
+ *
|
||||
+ * Novell 'IPX Router Specification' Version 1.10
|
||||
+ * Part No. 107-000029-001
|
||||
+ *
|
||||
+ * Which is available from ftp.novell.com
|
||||
+ */
|
||||
+
|
||||
+#include <linux/netdevice.h>
|
||||
+#include <net/datalink.h>
|
||||
+#include <linux/ipx.h>
|
||||
+#include <linux/list.h>
|
||||
+#include <linux/slab.h>
|
||||
+#include <linux/refcount.h>
|
||||
+
|
||||
+struct ipx_address {
|
||||
+ __be32 net;
|
||||
+ __u8 node[IPX_NODE_LEN];
|
||||
+ __be16 sock;
|
||||
+};
|
||||
+
|
||||
+#define ipx_broadcast_node "\377\377\377\377\377\377"
|
||||
+#define ipx_this_node "\0\0\0\0\0\0"
|
||||
+
|
||||
+#define IPX_MAX_PPROP_HOPS 8
|
||||
+
|
||||
+struct ipxhdr {
|
||||
+ __be16 ipx_checksum __packed;
|
||||
+#define IPX_NO_CHECKSUM cpu_to_be16(0xFFFF)
|
||||
+ __be16 ipx_pktsize __packed;
|
||||
+ __u8 ipx_tctrl;
|
||||
+ __u8 ipx_type;
|
||||
+#define IPX_TYPE_UNKNOWN 0x00
|
||||
+#define IPX_TYPE_RIP 0x01 /* may also be 0 */
|
||||
+#define IPX_TYPE_SAP 0x04 /* may also be 0 */
|
||||
+#define IPX_TYPE_SPX 0x05 /* SPX protocol */
|
||||
+#define IPX_TYPE_NCP 0x11 /* $lots for docs on this (SPIT) */
|
||||
+#define IPX_TYPE_PPROP 0x14 /* complicated flood fill brdcast */
|
||||
+ struct ipx_address ipx_dest __packed;
|
||||
+ struct ipx_address ipx_source __packed;
|
||||
+};
|
||||
+
|
||||
+/* From af_ipx.c */
|
||||
+extern int sysctl_ipx_pprop_broadcasting;
|
||||
+
|
||||
+struct ipx_interface {
|
||||
+ /* IPX address */
|
||||
+ __be32 if_netnum;
|
||||
+ unsigned char if_node[IPX_NODE_LEN];
|
||||
+ refcount_t refcnt;
|
||||
+
|
||||
+ /* physical device info */
|
||||
+ struct net_device *if_dev;
|
||||
+ struct datalink_proto *if_dlink;
|
||||
+ __be16 if_dlink_type;
|
||||
+
|
||||
+ /* socket support */
|
||||
+ unsigned short if_sknum;
|
||||
+ struct hlist_head if_sklist;
|
||||
+ spinlock_t if_sklist_lock;
|
||||
+
|
||||
+ /* administrative overhead */
|
||||
+ int if_ipx_offset;
|
||||
+ unsigned char if_internal;
|
||||
+ unsigned char if_primary;
|
||||
+
|
||||
+ struct list_head node; /* node in ipx_interfaces list */
|
||||
+};
|
||||
+
|
||||
+struct ipx_route {
|
||||
+ __be32 ir_net;
|
||||
+ struct ipx_interface *ir_intrfc;
|
||||
+ unsigned char ir_routed;
|
||||
+ unsigned char ir_router_node[IPX_NODE_LEN];
|
||||
+ struct list_head node; /* node in ipx_routes list */
|
||||
+ refcount_t refcnt;
|
||||
+};
|
||||
+
|
||||
+struct ipx_cb {
|
||||
+ u8 ipx_tctrl;
|
||||
+ __be32 ipx_dest_net;
|
||||
+ __be32 ipx_source_net;
|
||||
+ struct {
|
||||
+ __be32 netnum;
|
||||
+ int index;
|
||||
+ } last_hop;
|
||||
+};
|
||||
+
|
||||
+#include <net/sock.h>
|
||||
+
|
||||
+struct ipx_sock {
|
||||
+ /* struct sock has to be the first member of ipx_sock */
|
||||
+ struct sock sk;
|
||||
+ struct ipx_address dest_addr;
|
||||
+ struct ipx_interface *intrfc;
|
||||
+ __be16 port;
|
||||
+#ifdef CONFIG_IPX_INTERN
|
||||
+ unsigned char node[IPX_NODE_LEN];
|
||||
+#endif
|
||||
+ unsigned short type;
|
||||
+ /*
|
||||
+ * To handle special ncp connection-handling sockets for mars_nwe,
|
||||
+ * the connection number must be stored in the socket.
|
||||
+ */
|
||||
+ unsigned short ipx_ncp_conn;
|
||||
+};
|
||||
+
|
||||
+static inline struct ipx_sock *ipx_sk(struct sock *sk)
|
||||
+{
|
||||
+ return (struct ipx_sock *)sk;
|
||||
+}
|
||||
+
|
||||
+#define IPX_SKB_CB(__skb) ((struct ipx_cb *)&((__skb)->cb[0]))
|
||||
+
|
||||
+#define IPX_MIN_EPHEMERAL_SOCKET 0x4000
|
||||
+#define IPX_MAX_EPHEMERAL_SOCKET 0x7fff
|
||||
+
|
||||
+extern struct list_head ipx_routes;
|
||||
+extern rwlock_t ipx_routes_lock;
|
||||
+
|
||||
+extern struct list_head ipx_interfaces;
|
||||
+struct ipx_interface *ipx_interfaces_head(void);
|
||||
+extern spinlock_t ipx_interfaces_lock;
|
||||
+
|
||||
+extern struct ipx_interface *ipx_primary_net;
|
||||
+
|
||||
+int ipx_proc_init(void);
|
||||
+void ipx_proc_exit(void);
|
||||
+
|
||||
+const char *ipx_frame_name(__be16);
|
||||
+const char *ipx_device_name(struct ipx_interface *intrfc);
|
||||
+
|
||||
+static __inline__ void ipxitf_hold(struct ipx_interface *intrfc)
|
||||
+{
|
||||
+ refcount_inc(&intrfc->refcnt);
|
||||
+}
|
||||
+
|
||||
+void ipxitf_down(struct ipx_interface *intrfc);
|
||||
+struct ipx_interface *ipxitf_find_using_net(__be32 net);
|
||||
+int ipxitf_send(struct ipx_interface *intrfc, struct sk_buff *skb, char *node);
|
||||
+__be16 ipx_cksum(struct ipxhdr *packet, int length);
|
||||
+int ipxrtr_add_route(__be32 network, struct ipx_interface *intrfc,
|
||||
+ unsigned char *node);
|
||||
+void ipxrtr_del_routes(struct ipx_interface *intrfc);
|
||||
+int ipxrtr_route_packet(struct sock *sk, struct sockaddr_ipx *usipx,
|
||||
+ struct msghdr *msg, size_t len, int noblock);
|
||||
+int ipxrtr_route_skb(struct sk_buff *skb);
|
||||
+struct ipx_route *ipxrtr_lookup(__be32 net);
|
||||
+int ipxrtr_ioctl(unsigned int cmd, void __user *arg);
|
||||
+
|
||||
+static __inline__ void ipxitf_put(struct ipx_interface *intrfc)
|
||||
+{
|
||||
+ if (refcount_dec_and_test(&intrfc->refcnt))
|
||||
+ ipxitf_down(intrfc);
|
||||
+}
|
||||
+
|
||||
+static __inline__ void ipxrtr_hold(struct ipx_route *rt)
|
||||
+{
|
||||
+ refcount_inc(&rt->refcnt);
|
||||
+}
|
||||
+
|
||||
+static __inline__ void ipxrtr_put(struct ipx_route *rt)
|
||||
+{
|
||||
+ if (refcount_dec_and_test(&rt->refcnt))
|
||||
+ kfree(rt);
|
||||
+}
|
||||
+#endif /* _NET_INET_IPX_H_ */
|
||||
diff --git a/include/uapi/linux/ipx.h b/include/uapi/linux/ipx.h
|
||||
new file mode 100644
|
||||
index 000000000000..3168137adae8
|
||||
--- /dev/null
|
||||
+++ b/include/uapi/linux/ipx.h
|
||||
@@ -0,0 +1,87 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
|
||||
+#ifndef _IPX_H_
|
||||
+#define _IPX_H_
|
||||
+#include <linux/libc-compat.h> /* for compatibility with glibc netipx/ipx.h */
|
||||
+#include <linux/types.h>
|
||||
+#include <linux/sockios.h>
|
||||
+#include <linux/socket.h>
|
||||
+#define IPX_NODE_LEN 6
|
||||
+#define IPX_MTU 576
|
||||
+
|
||||
+#if __UAPI_DEF_SOCKADDR_IPX
|
||||
+struct sockaddr_ipx {
|
||||
+ __kernel_sa_family_t sipx_family;
|
||||
+ __be16 sipx_port;
|
||||
+ __be32 sipx_network;
|
||||
+ unsigned char sipx_node[IPX_NODE_LEN];
|
||||
+ __u8 sipx_type;
|
||||
+ unsigned char sipx_zero; /* 16 byte fill */
|
||||
+};
|
||||
+#endif /* __UAPI_DEF_SOCKADDR_IPX */
|
||||
+
|
||||
+/*
|
||||
+ * So we can fit the extra info for SIOCSIFADDR into the address nicely
|
||||
+ */
|
||||
+#define sipx_special sipx_port
|
||||
+#define sipx_action sipx_zero
|
||||
+#define IPX_DLTITF 0
|
||||
+#define IPX_CRTITF 1
|
||||
+
|
||||
+#if __UAPI_DEF_IPX_ROUTE_DEFINITION
|
||||
+struct ipx_route_definition {
|
||||
+ __be32 ipx_network;
|
||||
+ __be32 ipx_router_network;
|
||||
+ unsigned char ipx_router_node[IPX_NODE_LEN];
|
||||
+};
|
||||
+#endif /* __UAPI_DEF_IPX_ROUTE_DEFINITION */
|
||||
+
|
||||
+#if __UAPI_DEF_IPX_INTERFACE_DEFINITION
|
||||
+struct ipx_interface_definition {
|
||||
+ __be32 ipx_network;
|
||||
+ unsigned char ipx_device[16];
|
||||
+ unsigned char ipx_dlink_type;
|
||||
+#define IPX_FRAME_NONE 0
|
||||
+#define IPX_FRAME_SNAP 1
|
||||
+#define IPX_FRAME_8022 2
|
||||
+#define IPX_FRAME_ETHERII 3
|
||||
+#define IPX_FRAME_8023 4
|
||||
+#define IPX_FRAME_TR_8022 5 /* obsolete */
|
||||
+ unsigned char ipx_special;
|
||||
+#define IPX_SPECIAL_NONE 0
|
||||
+#define IPX_PRIMARY 1
|
||||
+#define IPX_INTERNAL 2
|
||||
+ unsigned char ipx_node[IPX_NODE_LEN];
|
||||
+};
|
||||
+#endif /* __UAPI_DEF_IPX_INTERFACE_DEFINITION */
|
||||
+
|
||||
+#if __UAPI_DEF_IPX_CONFIG_DATA
|
||||
+struct ipx_config_data {
|
||||
+ unsigned char ipxcfg_auto_select_primary;
|
||||
+ unsigned char ipxcfg_auto_create_interfaces;
|
||||
+};
|
||||
+#endif /* __UAPI_DEF_IPX_CONFIG_DATA */
|
||||
+
|
||||
+/*
|
||||
+ * OLD Route Definition for backward compatibility.
|
||||
+ */
|
||||
+
|
||||
+#if __UAPI_DEF_IPX_ROUTE_DEF
|
||||
+struct ipx_route_def {
|
||||
+ __be32 ipx_network;
|
||||
+ __be32 ipx_router_network;
|
||||
+#define IPX_ROUTE_NO_ROUTER 0
|
||||
+ unsigned char ipx_router_node[IPX_NODE_LEN];
|
||||
+ unsigned char ipx_device[16];
|
||||
+ unsigned short ipx_flags;
|
||||
+#define IPX_RT_SNAP 8
|
||||
+#define IPX_RT_8022 4
|
||||
+#define IPX_RT_BLUEBOOK 2
|
||||
+#define IPX_RT_ROUTED 1
|
||||
+};
|
||||
+#endif /* __UAPI_DEF_IPX_ROUTE_DEF */
|
||||
+
|
||||
+#define SIOCAIPXITFCRT (SIOCPROTOPRIVATE)
|
||||
+#define SIOCAIPXPRISLT (SIOCPROTOPRIVATE + 1)
|
||||
+#define SIOCIPXCFGDATA (SIOCPROTOPRIVATE + 2)
|
||||
+#define SIOCIPXNCPCONN (SIOCPROTOPRIVATE + 3)
|
||||
+#endif /* _IPX_H_ */
|
||||
--
|
||||
2.25.1
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,406 @@
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Sat, 10 Oct 2020 15:32:18 +0000
|
||||
Subject: [PATCH] phy/rockchip: inno-hdmi: use correct vco_div_5 macro on
|
||||
rk3328
|
||||
|
||||
inno_hdmi_phy_rk3328_clk_set_rate() is using the RK3228 macro
|
||||
when configuring vco_div_5 on RK3328.
|
||||
|
||||
Fix this by using correct vco_div_5 macro for RK3328.
|
||||
|
||||
Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy")
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
index 80acca4e9e14..15339338aae3 100644
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
@@ -790,8 +790,8 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw,
|
||||
RK3328_PRE_PLL_POWER_DOWN);
|
||||
|
||||
/* Configure pre-pll */
|
||||
- inno_update_bits(inno, 0xa0, RK3228_PCLK_VCO_DIV_5_MASK,
|
||||
- RK3228_PCLK_VCO_DIV_5(cfg->vco_div_5_en));
|
||||
+ inno_update_bits(inno, 0xa0, RK3328_PCLK_VCO_DIV_5_MASK,
|
||||
+ RK3328_PCLK_VCO_DIV_5(cfg->vco_div_5_en));
|
||||
inno_write(inno, 0xa1, RK3328_PRE_PLL_PRE_DIV(cfg->prediv));
|
||||
|
||||
val = RK3328_SPREAD_SPECTRUM_MOD_DISABLE;
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Zheng Yang <zhengyang@rock-chips.com>
|
||||
Date: Sat, 10 Oct 2020 15:32:18 +0000
|
||||
Subject: [PATCH] phy/rockchip: inno-hdmi: round fractal pixclock in rk3328
|
||||
recalc_rate
|
||||
|
||||
inno_hdmi_phy_rk3328_clk_recalc_rate() is returning a rate not found
|
||||
in the pre pll config table when the fractal divider is used.
|
||||
This can prevent proper power_on because a tmdsclock for the new rate
|
||||
is not found in the pre pll config table.
|
||||
|
||||
Fix this by saving and returning a rounded pixel rate that exist
|
||||
in the pre pll config table.
|
||||
|
||||
Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy")
|
||||
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 8 +++++---
|
||||
1 file changed, 5 insertions(+), 3 deletions(-)
|
||||
|
||||
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
index 15339338aae3..15a008a1ac7b 100644
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
@@ -745,10 +745,12 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw,
|
||||
do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2));
|
||||
}
|
||||
|
||||
- inno->pixclock = vco;
|
||||
- dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);
|
||||
+ inno->pixclock = DIV_ROUND_CLOSEST((unsigned long)vco, 1000) * 1000;
|
||||
|
||||
- return vco;
|
||||
+ dev_dbg(inno->dev, "%s rate %lu vco %llu\n",
|
||||
+ __func__, inno->pixclock, vco);
|
||||
+
|
||||
+ return inno->pixclock;
|
||||
}
|
||||
|
||||
static long inno_hdmi_phy_rk3328_clk_round_rate(struct clk_hw *hw,
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Sat, 10 Oct 2020 15:32:19 +0000
|
||||
Subject: [PATCH] phy/rockchip: inno-hdmi: remove unused no_c from rk3328
|
||||
recalc_rate
|
||||
|
||||
no_c is not used in any calculation, lets remove it.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 5 +----
|
||||
1 file changed, 1 insertion(+), 4 deletions(-)
|
||||
|
||||
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
index 15a008a1ac7b..4b936ca19920 100644
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
@@ -714,7 +714,7 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw,
|
||||
{
|
||||
struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
|
||||
unsigned long frac;
|
||||
- u8 nd, no_a, no_b, no_c, no_d;
|
||||
+ u8 nd, no_a, no_b, no_d;
|
||||
u64 vco;
|
||||
u16 nf;
|
||||
|
||||
@@ -737,9 +737,6 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw,
|
||||
no_b = inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_B_MASK;
|
||||
no_b >>= RK3328_PRE_PLL_PCLK_DIV_B_SHIFT;
|
||||
no_b += 2;
|
||||
- no_c = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_C_MASK;
|
||||
- no_c >>= RK3328_PRE_PLL_PCLK_DIV_C_SHIFT;
|
||||
- no_c = 1 << no_c;
|
||||
no_d = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_D_MASK;
|
||||
|
||||
do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2));
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Sat, 10 Oct 2020 15:32:19 +0000
|
||||
Subject: [PATCH] phy/rockchip: inno-hdmi: do not power on rk3328 post pll on
|
||||
reg write
|
||||
|
||||
inno_write is used to configure 0xaa reg, that also hold the
|
||||
POST_PLL_POWER_DOWN bit.
|
||||
When POST_PLL_REFCLK_SEL_TMDS is configured the power down bit is not
|
||||
taken into consideration.
|
||||
|
||||
Fix this by keeping the power down bit until configuration is complete.
|
||||
Also reorder the reg write order for consistency.
|
||||
|
||||
Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy")
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 6 ++++--
|
||||
1 file changed, 4 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
index 4b936ca19920..620961fcfc1d 100644
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
@@ -1020,9 +1020,10 @@ inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno,
|
||||
|
||||
inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv));
|
||||
if (cfg->postdiv == 1) {
|
||||
- inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS);
|
||||
inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) |
|
||||
RK3328_POST_PLL_PRE_DIV(cfg->prediv));
|
||||
+ inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS |
|
||||
+ RK3328_POST_PLL_POWER_DOWN);
|
||||
} else {
|
||||
v = (cfg->postdiv / 2) - 1;
|
||||
v &= RK3328_POST_PLL_POST_DIV_MASK;
|
||||
@@ -1030,7 +1031,8 @@ inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno,
|
||||
inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) |
|
||||
RK3328_POST_PLL_PRE_DIV(cfg->prediv));
|
||||
inno_write(inno, 0xaa, RK3328_POST_PLL_POST_DIV_ENABLE |
|
||||
- RK3328_POST_PLL_REFCLK_SEL_TMDS);
|
||||
+ RK3328_POST_PLL_REFCLK_SEL_TMDS |
|
||||
+ RK3328_POST_PLL_POWER_DOWN);
|
||||
}
|
||||
|
||||
for (v = 0; v < 14; v++)
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Huicong Xu <xhc@rock-chips.com>
|
||||
Date: Sat, 10 Oct 2020 15:32:20 +0000
|
||||
Subject: [PATCH] phy/rockchip: inno-hdmi: force set_rate on power_on
|
||||
|
||||
Regular 8-bit and Deep Color video formats mainly differ in TMDS rate and
|
||||
not in pixel clock rate.
|
||||
When the hdmiphy clock is configured with the same pixel clock rate using
|
||||
clk_set_rate() the clock framework do not signal the hdmi phy driver
|
||||
to set_rate when switching between 8-bit and Deep Color.
|
||||
This result in pre/post pll not being re-configured when switching between
|
||||
regular 8-bit and Deep Color video formats.
|
||||
|
||||
Fix this by calling set_rate in power_on to force pre pll re-configuration.
|
||||
|
||||
Signed-off-by: Huicong Xu <xhc@rock-chips.com>
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 13 +++++++++++++
|
||||
1 file changed, 13 insertions(+)
|
||||
|
||||
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
index 620961fcfc1d..2f01259823ea 100644
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
@@ -245,6 +245,7 @@ struct inno_hdmi_phy {
|
||||
struct clk_hw hw;
|
||||
struct clk *phyclk;
|
||||
unsigned long pixclock;
|
||||
+ unsigned long tmdsclock;
|
||||
};
|
||||
|
||||
struct pre_pll_config {
|
||||
@@ -485,6 +486,8 @@ static int inno_hdmi_phy_power_on(struct phy *phy)
|
||||
|
||||
dev_dbg(inno->dev, "Inno HDMI PHY Power On\n");
|
||||
|
||||
+ inno->plat_data->clk_ops->set_rate(&inno->hw, inno->pixclock, 24000000);
|
||||
+
|
||||
ret = clk_prepare_enable(inno->phyclk);
|
||||
if (ret)
|
||||
return ret;
|
||||
@@ -509,6 +512,8 @@ static int inno_hdmi_phy_power_off(struct phy *phy)
|
||||
|
||||
clk_disable_unprepare(inno->phyclk);
|
||||
|
||||
+ inno->tmdsclock = 0;
|
||||
+
|
||||
dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n");
|
||||
|
||||
return 0;
|
||||
@@ -628,6 +633,9 @@ static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw,
|
||||
dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",
|
||||
__func__, rate, tmdsclock);
|
||||
|
||||
+ if (inno->pixclock == rate && inno->tmdsclock == tmdsclock)
|
||||
+ return 0;
|
||||
+
|
||||
cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate);
|
||||
if (IS_ERR(cfg))
|
||||
return PTR_ERR(cfg);
|
||||
@@ -670,6 +678,7 @@ static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw,
|
||||
}
|
||||
|
||||
inno->pixclock = rate;
|
||||
+ inno->tmdsclock = tmdsclock;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -781,6 +790,9 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw,
|
||||
dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",
|
||||
__func__, rate, tmdsclock);
|
||||
|
||||
+ if (inno->pixclock == rate && inno->tmdsclock == tmdsclock)
|
||||
+ return 0;
|
||||
+
|
||||
cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate);
|
||||
if (IS_ERR(cfg))
|
||||
return PTR_ERR(cfg);
|
||||
@@ -820,6 +832,7 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw,
|
||||
}
|
||||
|
||||
inno->pixclock = rate;
|
||||
+ inno->tmdsclock = tmdsclock;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Sun, 17 Feb 2019 22:14:38 +0000
|
||||
Subject: [PATCH] mmc: core: set initial signal voltage on power off
|
||||
|
||||
Some boards have SD card connectors where the power rail cannot be switched
|
||||
off by the driver. If the card has not been power cycled, it may still be
|
||||
using 1.8V signaling after a warm re-boot. Bootroms expecting 3.3V signaling
|
||||
will fail to boot from a UHS card that continue to use 1.8V signaling.
|
||||
|
||||
Set initial signal voltage in mmc_power_off() to allow re-boot to function.
|
||||
|
||||
This fixes re-boot with UHS cards on Asus Tinker Board (Rockchip RK3288),
|
||||
same issue have been seen on some Rockchip RK3399 boards.
|
||||
|
||||
I am sending this as a RFC because I have no insights into SD/MMC subsystem,
|
||||
this change fix a re-boot issue on my boards and does not break emmc/sdio.
|
||||
Is this an acceptable workaround? Any advice is appreciated.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/mmc/core/core.c | 8 ++++++++
|
||||
1 file changed, 8 insertions(+)
|
||||
|
||||
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
|
||||
index 95fedcf56e4a..38e75b275bb6 100644
|
||||
--- a/drivers/mmc/core/core.c
|
||||
+++ b/drivers/mmc/core/core.c
|
||||
@@ -1355,6 +1355,14 @@ void mmc_power_off(struct mmc_host *host)
|
||||
if (host->ios.power_mode == MMC_POWER_OFF)
|
||||
return;
|
||||
|
||||
+ mmc_set_initial_signal_voltage(host);
|
||||
+
|
||||
+ /*
|
||||
+ * This delay should be sufficient to allow the power supply
|
||||
+ * to reach the minimum voltage.
|
||||
+ */
|
||||
+ mmc_delay(host->ios.power_delay_ms);
|
||||
+
|
||||
mmc_pwrseq_power_off(host);
|
||||
|
||||
host->ios.clock = 0;
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Wed, 23 Jun 2021 16:59:18 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add sdmmc_ext for RK3328
|
||||
|
||||
RK3328 SoC has a fourth mmc controller called SDMMC_EXT. Some
|
||||
boards have sdio wifi connected to it. In order to use it
|
||||
one would have to add the pinctrls from sdmmc0ext group which
|
||||
is done on board level.
|
||||
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 14 ++++++++++++++
|
||||
1 file changed, 14 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
index 5b2020590f53..df46edbec82c 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
@@ -975,6 +975,20 @@ usb_host0_ohci: usb@ff5d0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ sdmmc_ext: mmc@ff5f0000 {
|
||||
+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
+ reg = <0x0 0xff5f0000 0x0 0x4000>;
|
||||
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>,
|
||||
+ <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>;
|
||||
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
+ fifo-depth = <0x100>;
|
||||
+ max-frequency = <150000000>;
|
||||
+ resets = <&cru SRST_SDMMCEXT>;
|
||||
+ reset-names = "reset";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
usbdrd3: usb@ff600000 {
|
||||
compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
|
||||
reg = <0x0 0xff600000 0x0 0x100000>;
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Wed, 23 Jun 2021 17:02:08 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add sdmmc/sdio/emmc reset controls for
|
||||
RK3328
|
||||
|
||||
The DW MCI controller driver will use them to reset the IP block before
|
||||
initialisation.
|
||||
|
||||
Fixes: d717f7352ec6 ("arm64: dts: rockchip: add sdmmc/sdio/emmc nodes for RK3328 SoCs")
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 ++++++
|
||||
1 file changed, 6 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
index df46edbec82c..cfc57be009a6 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
@@ -853,6 +853,8 @@ sdmmc: mmc@ff500000 {
|
||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
fifo-depth = <0x100>;
|
||||
max-frequency = <150000000>;
|
||||
+ resets = <&cru SRST_MMC0>;
|
||||
+ reset-names = "reset";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -865,6 +867,8 @@ sdio: mmc@ff510000 {
|
||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
fifo-depth = <0x100>;
|
||||
max-frequency = <150000000>;
|
||||
+ resets = <&cru SRST_SDIO>;
|
||||
+ reset-names = "reset";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -877,6 +881,8 @@ emmc: mmc@ff520000 {
|
||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
fifo-depth = <0x100>;
|
||||
max-frequency = <150000000>;
|
||||
+ resets = <&cru SRST_EMMC>;
|
||||
+ reset-names = "reset";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Sat, 21 Aug 2021 19:13:31 +0200
|
||||
Subject: [PATCH] Commit a728c10dd62a ("arm64: dts: rockchip: remove
|
||||
interrupt-names from iommu nodes") intended to remove the interrupt-names
|
||||
property for the mmu nodes. It also removed them for the vpu node in
|
||||
rk3399.dtsi which currently results in a non-working driver. Fix this by
|
||||
re-adding them.
|
||||
|
||||
Fixes: a728c10dd62a ("arm64: dts: rockchip: remove interrupt-names from iommu nodes")
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
index 9db9484ca38f..44def886b391 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
@@ -1240,6 +1240,7 @@ vpu: video-codec@ff650000 {
|
||||
reg = <0x0 0xff650000 0x0 0x800>;
|
||||
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
+ interrupt-names = "vepu", "vdpu";
|
||||
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
|
||||
clock-names = "aclk", "hclk";
|
||||
iommus = <&vpu_mmu>;
|
||||
@ -0,0 +1,735 @@
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Mon, 6 Jul 2020 21:54:33 +0000
|
||||
Subject: [PATCH] media: rkvdec: h264: Fix reference frame_num wrap for second
|
||||
field
|
||||
|
||||
When decoding the second field in a complementary field pair the second
|
||||
field is sharing the same frame_num with the first field.
|
||||
|
||||
Currently the frame_num for the first field is wrapped when it matches the
|
||||
field being decoded, this cause issues to decode the second field in a
|
||||
complementary field pair.
|
||||
|
||||
Fix this by using inclusive comparison, less than or equal.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
|
||||
---
|
||||
drivers/staging/media/rkvdec/rkvdec-h264.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
index 76e97cbe2512..af44a16c0c4a 100644
|
||||
--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
@@ -752,7 +752,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
|
||||
continue;
|
||||
|
||||
if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM ||
|
||||
- dpb[i].frame_num < dec_params->frame_num) {
|
||||
+ dpb[i].frame_num <= dec_params->frame_num) {
|
||||
p[i] = dpb[i].frame_num;
|
||||
continue;
|
||||
}
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Mon, 6 Jul 2020 21:54:34 +0000
|
||||
Subject: [PATCH] media: rkvdec: Ensure decoded resolution fit coded resolution
|
||||
|
||||
Ensure decoded CAPTURE buffer resolution is larger or equal to the coded
|
||||
OPTUPT buffer resolution.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/staging/media/rkvdec/rkvdec.c | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
|
||||
index 7131156c1f2c..65a8334a188b 100644
|
||||
--- a/drivers/staging/media/rkvdec/rkvdec.c
|
||||
+++ b/drivers/staging/media/rkvdec/rkvdec.c
|
||||
@@ -233,6 +233,8 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv,
|
||||
pix_mp->pixelformat = coded_desc->decoded_fmts[0];
|
||||
|
||||
/* Always apply the frmsize constraint of the coded end. */
|
||||
+ pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width);
|
||||
+ pix_mp->height = max(pix_mp->height, ctx->coded_fmt.fmt.pix_mp.height);
|
||||
v4l2_apply_frmsize_constraints(&pix_mp->width,
|
||||
&pix_mp->height,
|
||||
&coded_desc->frmsize);
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Mon, 6 Jul 2020 21:54:34 +0000
|
||||
Subject: [PATCH] media: rkvdec: h264: Validate and use pic width and height in
|
||||
mbs
|
||||
|
||||
The width and height in mbs is currently configured based on OUTPUT buffer
|
||||
resolution, this works for frame pictures but can cause issues for field
|
||||
pictures.
|
||||
|
||||
When frame_mbs_only_flag is 0 the height in mbs should be height of
|
||||
the field instead of height of frame.
|
||||
|
||||
Validate pic_width_in_mbs_minus1 and pic_height_in_map_units_minus1
|
||||
against OUTPUT buffer resolution and use these values to configure HW.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/staging/media/rkvdec/rkvdec-h264.c | 4 ++--
|
||||
drivers/staging/media/rkvdec/rkvdec.c | 10 ++++++++++
|
||||
2 files changed, 12 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
index af44a16c0c4a..9852c3519f56 100644
|
||||
--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
@@ -671,8 +671,8 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx,
|
||||
LOG2_MAX_PIC_ORDER_CNT_LSB_MINUS4);
|
||||
WRITE_PPS(!!(sps->flags & V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO),
|
||||
DELTA_PIC_ORDER_ALWAYS_ZERO_FLAG);
|
||||
- WRITE_PPS(DIV_ROUND_UP(ctx->coded_fmt.fmt.pix_mp.width, 16), PIC_WIDTH_IN_MBS);
|
||||
- WRITE_PPS(DIV_ROUND_UP(ctx->coded_fmt.fmt.pix_mp.height, 16), PIC_HEIGHT_IN_MBS);
|
||||
+ WRITE_PPS(sps->pic_width_in_mbs_minus1 + 1, PIC_WIDTH_IN_MBS);
|
||||
+ WRITE_PPS(sps->pic_height_in_map_units_minus1 + 1, PIC_HEIGHT_IN_MBS);
|
||||
WRITE_PPS(!!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY),
|
||||
FRAME_MBS_ONLY_FLAG);
|
||||
WRITE_PPS(!!(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD),
|
||||
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
|
||||
index 65a8334a188b..f4c5ee4a1e26 100644
|
||||
--- a/drivers/staging/media/rkvdec/rkvdec.c
|
||||
+++ b/drivers/staging/media/rkvdec/rkvdec.c
|
||||
@@ -29,8 +29,11 @@
|
||||
|
||||
static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
|
||||
{
|
||||
+ struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
|
||||
+
|
||||
if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) {
|
||||
const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps;
|
||||
+ unsigned int width, height;
|
||||
/*
|
||||
* TODO: The hardware supports 10-bit and 4:2:2 profiles,
|
||||
* but it's currently broken in the driver.
|
||||
@@ -45,6 +48,13 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
|
||||
if (sps->bit_depth_luma_minus8 != 0)
|
||||
/* Only 8-bit is supported */
|
||||
return -EINVAL;
|
||||
+
|
||||
+ width = (sps->pic_width_in_mbs_minus1 + 1) * 16;
|
||||
+ height = (sps->pic_height_in_map_units_minus1 + 1) * 16;
|
||||
+
|
||||
+ if (width > ctx->coded_fmt.fmt.pix_mp.width ||
|
||||
+ height > ctx->coded_fmt.fmt.pix_mp.height)
|
||||
+ return -EINVAL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Mon, 6 Jul 2020 21:54:35 +0000
|
||||
Subject: [PATCH] media: rkvdec: h264: Fix bit depth wrap in pps packet
|
||||
|
||||
The luma and chroma bit depth fields in the pps packet is 3 bits wide.
|
||||
8 is wrongly added to the bit depth value written to these 3-bit fields.
|
||||
Because only the 3 LSB is written the hardware is configured correctly.
|
||||
|
||||
Correct this by not adding 8 to the luma and chroma bit depth value.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
|
||||
---
|
||||
drivers/staging/media/rkvdec/rkvdec-h264.c | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
index 9852c3519f56..f3ff3e709169 100644
|
||||
--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
@@ -661,8 +661,8 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx,
|
||||
WRITE_PPS(0xff, PROFILE_IDC);
|
||||
WRITE_PPS(1, CONSTRAINT_SET3_FLAG);
|
||||
WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC);
|
||||
- WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA);
|
||||
- WRITE_PPS(sps->bit_depth_chroma_minus8 + 8, BIT_DEPTH_CHROMA);
|
||||
+ WRITE_PPS(sps->bit_depth_luma_minus8, BIT_DEPTH_LUMA);
|
||||
+ WRITE_PPS(sps->bit_depth_chroma_minus8, BIT_DEPTH_CHROMA);
|
||||
WRITE_PPS(0, QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG);
|
||||
WRITE_PPS(sps->log2_max_frame_num_minus4, LOG2_MAX_FRAME_NUM_MINUS4);
|
||||
WRITE_PPS(sps->max_num_ref_frames, MAX_NUM_REF_FRAMES);
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Mon, 6 Jul 2020 21:54:35 +0000
|
||||
Subject: [PATCH] media: v4l2-common: Add helpers to calculate bytesperline and
|
||||
sizeimage
|
||||
|
||||
Add helper functions to calculate plane bytesperline and sizeimage, these
|
||||
new helpers consider block width and height when calculating plane
|
||||
bytesperline and sizeimage.
|
||||
|
||||
This prepare support for new pixel formats added in next patch that make
|
||||
use of block width and height.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/media/v4l2-core/v4l2-common.c | 77 +++++++++++++--------------
|
||||
1 file changed, 38 insertions(+), 39 deletions(-)
|
||||
|
||||
diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c
|
||||
index 04af03285a20..ae585828c388 100644
|
||||
--- a/drivers/media/v4l2-core/v4l2-common.c
|
||||
+++ b/drivers/media/v4l2-core/v4l2-common.c
|
||||
@@ -333,6 +333,33 @@ static inline unsigned int v4l2_format_block_height(const struct v4l2_format_inf
|
||||
return info->block_h[plane];
|
||||
}
|
||||
|
||||
+static inline unsigned int v4l2_format_plane_width(const struct v4l2_format_info *info, int plane,
|
||||
+ unsigned int width)
|
||||
+{
|
||||
+ unsigned int hdiv = plane ? info->hdiv : 1;
|
||||
+ unsigned int bytes = DIV_ROUND_UP(width * info->bpp[plane],
|
||||
+ v4l2_format_block_width(info, plane) *
|
||||
+ v4l2_format_block_height(info, plane));
|
||||
+
|
||||
+ return DIV_ROUND_UP(bytes, hdiv);
|
||||
+}
|
||||
+
|
||||
+static inline unsigned int v4l2_format_plane_height(const struct v4l2_format_info *info, int plane,
|
||||
+ unsigned int height)
|
||||
+{
|
||||
+ unsigned int vdiv = plane ? info->vdiv : 1;
|
||||
+ unsigned int lines = ALIGN(height, v4l2_format_block_height(info, plane));
|
||||
+
|
||||
+ return DIV_ROUND_UP(lines, vdiv);
|
||||
+}
|
||||
+
|
||||
+static inline unsigned int v4l2_format_plane_size(const struct v4l2_format_info *info, int plane,
|
||||
+ unsigned int width, unsigned int height)
|
||||
+{
|
||||
+ return v4l2_format_plane_width(info, plane, width) *
|
||||
+ v4l2_format_plane_height(info, plane, height);
|
||||
+}
|
||||
+
|
||||
void v4l2_apply_frmsize_constraints(u32 *width, u32 *height,
|
||||
const struct v4l2_frmsize_stepwise *frmsize)
|
||||
{
|
||||
@@ -368,37 +395,19 @@ int v4l2_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt,
|
||||
|
||||
if (info->mem_planes == 1) {
|
||||
plane = &pixfmt->plane_fmt[0];
|
||||
- plane->bytesperline = ALIGN(width, v4l2_format_block_width(info, 0)) * info->bpp[0];
|
||||
+ plane->bytesperline = v4l2_format_plane_width(info, 0, width);
|
||||
plane->sizeimage = 0;
|
||||
|
||||
- for (i = 0; i < info->comp_planes; i++) {
|
||||
- unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
|
||||
- unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
|
||||
- unsigned int aligned_width;
|
||||
- unsigned int aligned_height;
|
||||
-
|
||||
- aligned_width = ALIGN(width, v4l2_format_block_width(info, i));
|
||||
- aligned_height = ALIGN(height, v4l2_format_block_height(info, i));
|
||||
-
|
||||
- plane->sizeimage += info->bpp[i] *
|
||||
- DIV_ROUND_UP(aligned_width, hdiv) *
|
||||
- DIV_ROUND_UP(aligned_height, vdiv);
|
||||
- }
|
||||
+ for (i = 0; i < info->comp_planes; i++)
|
||||
+ plane->sizeimage +=
|
||||
+ v4l2_format_plane_size(info, i, width, height);
|
||||
} else {
|
||||
for (i = 0; i < info->comp_planes; i++) {
|
||||
- unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
|
||||
- unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
|
||||
- unsigned int aligned_width;
|
||||
- unsigned int aligned_height;
|
||||
-
|
||||
- aligned_width = ALIGN(width, v4l2_format_block_width(info, i));
|
||||
- aligned_height = ALIGN(height, v4l2_format_block_height(info, i));
|
||||
-
|
||||
plane = &pixfmt->plane_fmt[i];
|
||||
plane->bytesperline =
|
||||
- info->bpp[i] * DIV_ROUND_UP(aligned_width, hdiv);
|
||||
- plane->sizeimage =
|
||||
- plane->bytesperline * DIV_ROUND_UP(aligned_height, vdiv);
|
||||
+ v4l2_format_plane_width(info, i, width);
|
||||
+ plane->sizeimage = plane->bytesperline *
|
||||
+ v4l2_format_plane_height(info, i, height);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
@@ -422,22 +431,12 @@ int v4l2_fill_pixfmt(struct v4l2_pix_format *pixfmt, u32 pixelformat,
|
||||
pixfmt->width = width;
|
||||
pixfmt->height = height;
|
||||
pixfmt->pixelformat = pixelformat;
|
||||
- pixfmt->bytesperline = ALIGN(width, v4l2_format_block_width(info, 0)) * info->bpp[0];
|
||||
+ pixfmt->bytesperline = v4l2_format_plane_width(info, 0, width);
|
||||
pixfmt->sizeimage = 0;
|
||||
|
||||
- for (i = 0; i < info->comp_planes; i++) {
|
||||
- unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
|
||||
- unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
|
||||
- unsigned int aligned_width;
|
||||
- unsigned int aligned_height;
|
||||
-
|
||||
- aligned_width = ALIGN(width, v4l2_format_block_width(info, i));
|
||||
- aligned_height = ALIGN(height, v4l2_format_block_height(info, i));
|
||||
-
|
||||
- pixfmt->sizeimage += info->bpp[i] *
|
||||
- DIV_ROUND_UP(aligned_width, hdiv) *
|
||||
- DIV_ROUND_UP(aligned_height, vdiv);
|
||||
- }
|
||||
+ for (i = 0; i < info->comp_planes; i++)
|
||||
+ pixfmt->sizeimage +=
|
||||
+ v4l2_format_plane_size(info, i, width, height);
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(v4l2_fill_pixfmt);
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Mon, 6 Jul 2020 21:54:36 +0000
|
||||
Subject: [PATCH] media: v4l2: Add NV15 and NV20 pixel formats
|
||||
|
||||
Add NV15 and NV20 pixel formats used by the Rockchip Video Decoder for
|
||||
10-bit buffers.
|
||||
|
||||
NV15 and NV20 is a packed 10-bit 4:2:0/4:2:2 semi-planar Y/CbCr format
|
||||
similar to P010 and P210 but has no padding between components. Instead,
|
||||
luminance and chrominance samples are grouped into 4s so that each group is
|
||||
packed into an integer number of bytes:
|
||||
|
||||
YYYY = UVUV = 4 * 10 bits = 40 bits = 5 bytes
|
||||
|
||||
The '15' and '20' suffix refers to the optimum effective bits per pixel
|
||||
which is achieved when the total number of luminance samples is a multiple
|
||||
of 8 for NV15 and 4 for NV20.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/media/v4l2-core/v4l2-common.c | 3 +++
|
||||
drivers/media/v4l2-core/v4l2-ioctl.c | 2 ++
|
||||
include/uapi/linux/videodev2.h | 3 +++
|
||||
3 files changed, 8 insertions(+)
|
||||
|
||||
diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c
|
||||
index ae585828c388..5bafbdbe30b0 100644
|
||||
--- a/drivers/media/v4l2-core/v4l2-common.c
|
||||
+++ b/drivers/media/v4l2-core/v4l2-common.c
|
||||
@@ -267,6 +267,9 @@ const struct v4l2_format_info *v4l2_format_info(u32 format)
|
||||
{ .format = V4L2_PIX_FMT_NV24, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 1, .vdiv = 1 },
|
||||
{ .format = V4L2_PIX_FMT_NV42, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 1, .vdiv = 1 },
|
||||
|
||||
+ { .format = V4L2_PIX_FMT_NV15, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .hdiv = 2, .vdiv = 2, .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } },
|
||||
+ { .format = V4L2_PIX_FMT_NV20, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .hdiv = 2, .vdiv = 1, .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } },
|
||||
+
|
||||
{ .format = V4L2_PIX_FMT_YUV410, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 4 },
|
||||
{ .format = V4L2_PIX_FMT_YVU410, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 4 },
|
||||
{ .format = V4L2_PIX_FMT_YUV411P, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 1 },
|
||||
diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c
|
||||
index 9ac557b8e..0573d9a6a 100644
|
||||
--- a/drivers/media/v4l2-core/v4l2-ioctl.c
|
||||
+++ b/drivers/media/v4l2-core/v4l2-ioctl.c
|
||||
@@ -1299,6 +1299,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
|
||||
case V4L2_PIX_FMT_NV61: descr = "Y/CrCb 4:2:2"; break;
|
||||
case V4L2_PIX_FMT_NV24: descr = "Y/CbCr 4:4:4"; break;
|
||||
case V4L2_PIX_FMT_NV42: descr = "Y/CrCb 4:4:4"; break;
|
||||
+ case V4L2_PIX_FMT_NV15: descr = "10-bit Y/CbCr 4:2:0 (Packed)"; break;
|
||||
+ case V4L2_PIX_FMT_NV20: descr = "10-bit Y/CbCr 4:2:2 (Packed)"; break;
|
||||
case V4L2_PIX_FMT_NV12_4L4: descr = "Y/CbCr 4:2:0 (4x4 Linear)"; break;
|
||||
case V4L2_PIX_FMT_NV12_16L16: descr = "Y/CbCr 4:2:0 (16x16 Linear)"; break;
|
||||
case V4L2_PIX_FMT_NV12_32L32: descr = "Y/CbCr 4:2:0 (32x32 Linear)"; break;
|
||||
diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
|
||||
index 9260791b8438..169f8ad6fade 100644
|
||||
--- a/include/uapi/linux/videodev2.h
|
||||
+++ b/include/uapi/linux/videodev2.h
|
||||
@@ -603,6 +603,9 @@ struct v4l2_pix_format {
|
||||
#define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/CrCb 4:4:4 */
|
||||
#define V4L2_PIX_FMT_HM12 v4l2_fourcc('H', 'M', '1', '2') /* 8 YUV 4:2:0 16x16 macroblocks */
|
||||
|
||||
+#define V4L2_PIX_FMT_NV15 v4l2_fourcc('N', 'V', '1', '5') /* 15 Y/CbCr 4:2:0 10-bit packed */
|
||||
+#define V4L2_PIX_FMT_NV20 v4l2_fourcc('N', 'V', '2', '0') /* 20 Y/CbCr 4:2:2 10-bit packed */
|
||||
+
|
||||
/* two non contiguous planes - one Y, one Cr + Cb interleaved */
|
||||
#define V4L2_PIX_FMT_NV12M v4l2_fourcc('N', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 */
|
||||
#define V4L2_PIX_FMT_NV21M v4l2_fourcc('N', 'M', '2', '1') /* 21 Y/CrCb 4:2:0 */
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Mon, 6 Jul 2020 21:54:36 +0000
|
||||
Subject: [PATCH] media: rkvdec: h264: Use bytesperline and buffer height to
|
||||
calculate stride
|
||||
|
||||
Use bytesperline and buffer height to calculate the strides configured.
|
||||
|
||||
This does not really change anything other than ensuring the bytesperline
|
||||
that is signaled to userspace matches what is configured in HW.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/staging/media/rkvdec/rkvdec-h264.c | 10 +++++-----
|
||||
1 file changed, 5 insertions(+), 5 deletions(-)
|
||||
|
||||
diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
index 503ae683d0fd..88f5f4bb320b 100644
|
||||
--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
@@ -893,9 +893,9 @@ static void config_registers(struct rkvdec_ctx *ctx,
|
||||
dma_addr_t rlc_addr;
|
||||
dma_addr_t refer_addr;
|
||||
u32 rlc_len;
|
||||
- u32 hor_virstride = 0;
|
||||
- u32 ver_virstride = 0;
|
||||
- u32 y_virstride = 0;
|
||||
+ u32 hor_virstride;
|
||||
+ u32 ver_virstride;
|
||||
+ u32 y_virstride;
|
||||
u32 yuv_virstride = 0;
|
||||
u32 offset;
|
||||
dma_addr_t dst_addr;
|
||||
@@ -906,8 +906,8 @@ static void config_registers(struct rkvdec_ctx *ctx,
|
||||
|
||||
f = &ctx->decoded_fmt;
|
||||
dst_fmt = &f->fmt.pix_mp;
|
||||
- hor_virstride = (sps->bit_depth_luma_minus8 + 8) * dst_fmt->width / 8;
|
||||
- ver_virstride = round_up(dst_fmt->height, 16);
|
||||
+ hor_virstride = dst_fmt->plane_fmt[0].bytesperline;
|
||||
+ ver_virstride = dst_fmt->height;
|
||||
y_virstride = hor_virstride * ver_virstride;
|
||||
|
||||
if (sps->chroma_format_idc == 0)
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Mon, 6 Jul 2020 21:54:37 +0000
|
||||
Subject: [PATCH] media: rkvdec: Extract rkvdec_fill_decoded_pixfmt helper
|
||||
method
|
||||
|
||||
This extract setting decoded pixfmt into a helper method, current code is
|
||||
replaced with a call to the new helper method.
|
||||
|
||||
The helper method is also called from a new function in next patch.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/staging/media/rkvdec/rkvdec.c | 29 ++++++++++++++-------------
|
||||
1 file changed, 15 insertions(+), 14 deletions(-)
|
||||
|
||||
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
|
||||
index f4c5ee4a1e26..d8d0eab9e25d 100644
|
||||
--- a/drivers/staging/media/rkvdec/rkvdec.c
|
||||
+++ b/drivers/staging/media/rkvdec/rkvdec.c
|
||||
@@ -27,6 +27,17 @@
|
||||
#include "rkvdec.h"
|
||||
#include "rkvdec-regs.h"
|
||||
|
||||
+static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx,
|
||||
+ struct v4l2_pix_format_mplane *pix_mp)
|
||||
+{
|
||||
+ v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat,
|
||||
+ pix_mp->width, pix_mp->height);
|
||||
+ pix_mp->plane_fmt[0].sizeimage += 128 *
|
||||
+ DIV_ROUND_UP(pix_mp->width, 16) *
|
||||
+ DIV_ROUND_UP(pix_mp->height, 16);
|
||||
+ pix_mp->field = V4L2_FIELD_NONE;
|
||||
+}
|
||||
+
|
||||
static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
|
||||
{
|
||||
struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
|
||||
@@ -177,13 +188,9 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx)
|
||||
|
||||
rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]);
|
||||
f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
|
||||
- v4l2_fill_pixfmt_mp(&f->fmt.pix_mp,
|
||||
- ctx->coded_fmt_desc->decoded_fmts[0],
|
||||
- ctx->coded_fmt.fmt.pix_mp.width,
|
||||
- ctx->coded_fmt.fmt.pix_mp.height);
|
||||
- f->fmt.pix_mp.plane_fmt[0].sizeimage += 128 *
|
||||
- DIV_ROUND_UP(f->fmt.pix_mp.width, 16) *
|
||||
- DIV_ROUND_UP(f->fmt.pix_mp.height, 16);
|
||||
+ f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width;
|
||||
+ f->fmt.pix_mp.height = ctx->coded_fmt.fmt.pix_mp.height;
|
||||
+ rkvdec_fill_decoded_pixfmt(ctx, &f->fmt.pix_mp);
|
||||
}
|
||||
|
||||
static int rkvdec_enum_framesizes(struct file *file, void *priv,
|
||||
@@ -249,13 +256,7 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv,
|
||||
&pix_mp->height,
|
||||
&coded_desc->frmsize);
|
||||
|
||||
- v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat,
|
||||
- pix_mp->width, pix_mp->height);
|
||||
- pix_mp->plane_fmt[0].sizeimage +=
|
||||
- 128 *
|
||||
- DIV_ROUND_UP(pix_mp->width, 16) *
|
||||
- DIV_ROUND_UP(pix_mp->height, 16);
|
||||
- pix_mp->field = V4L2_FIELD_NONE;
|
||||
+ rkvdec_fill_decoded_pixfmt(ctx, pix_mp);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Mon, 6 Jul 2020 21:54:37 +0000
|
||||
Subject: [PATCH] media: rkvdec: Lock capture pixel format in s_ctrl and s_fmt
|
||||
|
||||
Add an optional valid_fmt operation that should return the valid
|
||||
pixelformat of CAPTURE buffers.
|
||||
|
||||
This is used in next patch to ensure correct pixelformat is used for 10-bit
|
||||
and 4:2:2 content.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/staging/media/rkvdec/rkvdec.c | 59 ++++++++++++++++++++++++---
|
||||
drivers/staging/media/rkvdec/rkvdec.h | 2 +
|
||||
2 files changed, 55 insertions(+), 6 deletions(-)
|
||||
|
||||
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
|
||||
index d8d0eab9e25d..d31344c4acaa 100644
|
||||
--- a/drivers/staging/media/rkvdec/rkvdec.c
|
||||
+++ b/drivers/staging/media/rkvdec/rkvdec.c
|
||||
@@ -38,6 +38,16 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx,
|
||||
pix_mp->field = V4L2_FIELD_NONE;
|
||||
}
|
||||
|
||||
+static u32 rkvdec_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
|
||||
+{
|
||||
+ const struct rkvdec_coded_fmt_desc *coded_desc = ctx->coded_fmt_desc;
|
||||
+
|
||||
+ if (coded_desc->ops->valid_fmt)
|
||||
+ return coded_desc->ops->valid_fmt(ctx, ctrl);
|
||||
+
|
||||
+ return ctx->valid_fmt;
|
||||
+}
|
||||
+
|
||||
static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
|
||||
{
|
||||
struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
|
||||
@@ -60,6 +70,10 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
|
||||
/* Only 8-bit is supported */
|
||||
return -EINVAL;
|
||||
|
||||
+ if (ctx->valid_fmt && ctx->valid_fmt != rkvdec_valid_fmt(ctx, ctrl))
|
||||
+ /* Only current valid format */
|
||||
+ return -EINVAL;
|
||||
+
|
||||
width = (sps->pic_width_in_mbs_minus1 + 1) * 16;
|
||||
height = (sps->pic_height_in_map_units_minus1 + 1) * 16;
|
||||
|
||||
@@ -70,8 +84,27 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl)
|
||||
+{
|
||||
+ struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
|
||||
+
|
||||
+ if (ctrl->id == V4L2_CID_STATELESS_H264_SPS && !ctx->valid_fmt) {
|
||||
+ ctx->valid_fmt = rkvdec_valid_fmt(ctx, ctrl);
|
||||
+ if (ctx->valid_fmt) {
|
||||
+ struct v4l2_pix_format_mplane *pix_mp;
|
||||
+
|
||||
+ pix_mp = &ctx->decoded_fmt.fmt.pix_mp;
|
||||
+ pix_mp->pixelformat = ctx->valid_fmt;
|
||||
+ rkvdec_fill_decoded_pixfmt(ctx, pix_mp);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static const struct v4l2_ctrl_ops rkvdec_ctrl_ops = {
|
||||
.try_ctrl = rkvdec_try_ctrl,
|
||||
+ .s_ctrl = rkvdec_s_ctrl,
|
||||
};
|
||||
|
||||
static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = {
|
||||
@@ -186,6 +219,7 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx)
|
||||
{
|
||||
struct v4l2_format *f = &ctx->decoded_fmt;
|
||||
|
||||
+ ctx->valid_fmt = 0;
|
||||
rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]);
|
||||
f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
|
||||
f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width;
|
||||
@@ -241,13 +275,17 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv,
|
||||
if (WARN_ON(!coded_desc))
|
||||
return -EINVAL;
|
||||
|
||||
- for (i = 0; i < coded_desc->num_decoded_fmts; i++) {
|
||||
- if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat)
|
||||
- break;
|
||||
- }
|
||||
+ if (ctx->valid_fmt) {
|
||||
+ pix_mp->pixelformat = ctx->valid_fmt;
|
||||
+ } else {
|
||||
+ for (i = 0; i < coded_desc->num_decoded_fmts; i++) {
|
||||
+ if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat)
|
||||
+ break;
|
||||
+ }
|
||||
|
||||
- if (i == coded_desc->num_decoded_fmts)
|
||||
- pix_mp->pixelformat = coded_desc->decoded_fmts[0];
|
||||
+ if (i == coded_desc->num_decoded_fmts)
|
||||
+ pix_mp->pixelformat = coded_desc->decoded_fmts[0];
|
||||
+ }
|
||||
|
||||
/* Always apply the frmsize constraint of the coded end. */
|
||||
pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width);
|
||||
@@ -322,6 +360,7 @@ static int rkvdec_s_capture_fmt(struct file *file, void *priv,
|
||||
return ret;
|
||||
|
||||
ctx->decoded_fmt = *f;
|
||||
+ ctx->valid_fmt = f->fmt.pix_mp.pixelformat;
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -411,6 +450,14 @@ static int rkvdec_enum_capture_fmt(struct file *file, void *priv,
|
||||
if (WARN_ON(!ctx->coded_fmt_desc))
|
||||
return -EINVAL;
|
||||
|
||||
+ if (ctx->valid_fmt) {
|
||||
+ if (f->index)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ f->pixelformat = ctx->valid_fmt;
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
if (f->index >= ctx->coded_fmt_desc->num_decoded_fmts)
|
||||
return -EINVAL;
|
||||
|
||||
diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
|
||||
index 52ac3874c5e5..7b6f44ee8a1a 100644
|
||||
--- a/drivers/staging/media/rkvdec/rkvdec.h
|
||||
+++ b/drivers/staging/media/rkvdec/rkvdec.h
|
||||
@@ -62,6 +62,7 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf)
|
||||
struct rkvdec_coded_fmt_ops {
|
||||
int (*adjust_fmt)(struct rkvdec_ctx *ctx,
|
||||
struct v4l2_format *f);
|
||||
+ u32 (*valid_fmt)(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl);
|
||||
int (*start)(struct rkvdec_ctx *ctx);
|
||||
void (*stop)(struct rkvdec_ctx *ctx);
|
||||
int (*run)(struct rkvdec_ctx *ctx);
|
||||
@@ -95,6 +96,7 @@ struct rkvdec_ctx {
|
||||
struct v4l2_fh fh;
|
||||
struct v4l2_format coded_fmt;
|
||||
struct v4l2_format decoded_fmt;
|
||||
+ u32 valid_fmt;
|
||||
const struct rkvdec_coded_fmt_desc *coded_fmt_desc;
|
||||
struct v4l2_ctrl_handler ctrl_hdl;
|
||||
struct rkvdec_dev *dev;
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Mon, 6 Jul 2020 21:54:37 +0000
|
||||
Subject: [PATCH] media: rkvdec: h264: Support High 10 and 4:2:2 profiles
|
||||
|
||||
Add support and enable decoding of H264 High 10 and 4:2:2 profiles.
|
||||
|
||||
Decoded CAPTURE buffer width is aligned to 64 pixels to accommodate HW
|
||||
requirement on 10-bit format buffers.
|
||||
|
||||
The new valid_fmt operation is implemented and return a valid pixelformat
|
||||
for the provided SPS control.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/staging/media/rkvdec/rkvdec-h264.c | 20 ++++++++++++++++++++
|
||||
drivers/staging/media/rkvdec/rkvdec.c | 19 +++++++++----------
|
||||
2 files changed, 29 insertions(+), 10 deletions(-)
|
||||
|
||||
diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
index 88f5f4bb320b..c9a551dbd9bc 100644
|
||||
--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
@@ -1021,6 +1021,25 @@ static int rkvdec_h264_adjust_fmt(struct rkvdec_ctx *ctx,
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static u32 rkvdec_h264_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
|
||||
+{
|
||||
+ const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps;
|
||||
+
|
||||
+ if (sps->bit_depth_luma_minus8 == 0) {
|
||||
+ if (sps->chroma_format_idc == 2)
|
||||
+ return V4L2_PIX_FMT_NV16;
|
||||
+ else
|
||||
+ return V4L2_PIX_FMT_NV12;
|
||||
+ } else if (sps->bit_depth_luma_minus8 == 2) {
|
||||
+ if (sps->chroma_format_idc == 2)
|
||||
+ return V4L2_PIX_FMT_NV20;
|
||||
+ else
|
||||
+ return V4L2_PIX_FMT_NV15;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int rkvdec_h264_start(struct rkvdec_ctx *ctx)
|
||||
{
|
||||
struct rkvdec_dev *rkvdec = ctx->dev;
|
||||
@@ -1124,6 +1143,7 @@ static int rkvdec_h264_run(struct rkvdec_ctx *ctx)
|
||||
|
||||
const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops = {
|
||||
.adjust_fmt = rkvdec_h264_adjust_fmt,
|
||||
+ .valid_fmt = rkvdec_h264_valid_fmt,
|
||||
.start = rkvdec_h264_start,
|
||||
.stop = rkvdec_h264_stop,
|
||||
.run = rkvdec_h264_run,
|
||||
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
|
||||
index d31344c4acaa..d068383aeea8 100644
|
||||
--- a/drivers/staging/media/rkvdec/rkvdec.c
|
||||
+++ b/drivers/staging/media/rkvdec/rkvdec.c
|
||||
@@ -31,7 +31,7 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx,
|
||||
struct v4l2_pix_format_mplane *pix_mp)
|
||||
{
|
||||
v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat,
|
||||
- pix_mp->width, pix_mp->height);
|
||||
+ ALIGN(pix_mp->width, 64), pix_mp->height);
|
||||
pix_mp->plane_fmt[0].sizeimage += 128 *
|
||||
DIV_ROUND_UP(pix_mp->width, 16) *
|
||||
DIV_ROUND_UP(pix_mp->height, 16);
|
||||
@@ -55,19 +55,15 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
|
||||
if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) {
|
||||
const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps;
|
||||
unsigned int width, height;
|
||||
- /*
|
||||
- * TODO: The hardware supports 10-bit and 4:2:2 profiles,
|
||||
- * but it's currently broken in the driver.
|
||||
- * Reject them for now, until it's fixed.
|
||||
- */
|
||||
- if (sps->chroma_format_idc > 1)
|
||||
- /* Only 4:0:0 and 4:2:0 are supported */
|
||||
+
|
||||
+ if (sps->chroma_format_idc > 2)
|
||||
+ /* Only 4:0:0, 4:2:0 and 4:2:2 are supported */
|
||||
return -EINVAL;
|
||||
if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
|
||||
/* Luma and chroma bit depth mismatch */
|
||||
return -EINVAL;
|
||||
- if (sps->bit_depth_luma_minus8 != 0)
|
||||
- /* Only 8-bit is supported */
|
||||
+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
|
||||
+ /* Only 8-bit and 10-bit is supported */
|
||||
return -EINVAL;
|
||||
|
||||
if (ctx->valid_fmt && ctx->valid_fmt != rkvdec_valid_fmt(ctx, ctrl))
|
||||
@@ -155,6 +151,9 @@ static const struct rkvdec_ctrls rkvdec_h264_ctrls = {
|
||||
|
||||
static const u32 rkvdec_h264_decoded_fmts[] = {
|
||||
V4L2_PIX_FMT_NV12,
|
||||
+ V4L2_PIX_FMT_NV15,
|
||||
+ V4L2_PIX_FMT_NV16,
|
||||
+ V4L2_PIX_FMT_NV20,
|
||||
};
|
||||
|
||||
static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
|
||||
|
||||
@ -0,0 +1,531 @@
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Mon, 6 Jul 2020 22:30:13 +0000
|
||||
Subject: [PATCH] drm: drm_fourcc: add NV20 and NV30 YUV formats
|
||||
|
||||
DRM_FORMAT_NV20 and DRM_FORMAT_NV30 formats is the 2x1 and non-subsampled
|
||||
variant of NV15, a 10-bit 2-plane YUV format that has no padding between
|
||||
components. Instead, luminance and chrominance samples are grouped into 4s
|
||||
so that each group is packed into an integer number of bytes:
|
||||
|
||||
YYYY = UVUV = 4 * 10 bits = 40 bits = 5 bytes
|
||||
|
||||
The '20' and '30' suffix refers to the optimum effective bits per pixel
|
||||
which is achieved when the total number of luminance samples is a multiple
|
||||
of 4.
|
||||
|
||||
V2: Added NV30 format
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
Reviewed-by: Sandy Huang <hjc@rock-chips.com>
|
||||
---
|
||||
drivers/gpu/drm/drm_fourcc.c | 8 ++++++++
|
||||
include/uapi/drm/drm_fourcc.h | 2 ++
|
||||
2 files changed, 10 insertions(+)
|
||||
|
||||
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
|
||||
index eda832f9200d..9498e9d466fb 100644
|
||||
--- a/drivers/gpu/drm/drm_fourcc.c
|
||||
+++ b/drivers/gpu/drm/drm_fourcc.c
|
||||
@@ -258,6 +258,14 @@ const struct drm_format_info *__drm_format_info(u32 format)
|
||||
.num_planes = 2, .char_per_block = { 5, 5, 0 },
|
||||
.block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 2,
|
||||
.vsub = 2, .is_yuv = true },
|
||||
+ { .format = DRM_FORMAT_NV20, .depth = 0,
|
||||
+ .num_planes = 2, .char_per_block = { 5, 5, 0 },
|
||||
+ .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 2,
|
||||
+ .vsub = 1, .is_yuv = true },
|
||||
+ { .format = DRM_FORMAT_NV30, .depth = 0,
|
||||
+ .num_planes = 2, .char_per_block = { 5, 5, 0 },
|
||||
+ .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 1,
|
||||
+ .vsub = 1, .is_yuv = true },
|
||||
{ .format = DRM_FORMAT_Q410, .depth = 0,
|
||||
.num_planes = 3, .char_per_block = { 2, 2, 2 },
|
||||
.block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, .hsub = 0,
|
||||
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
|
||||
index f7156322aba5..a30bb7ef7632 100644
|
||||
--- a/include/uapi/drm/drm_fourcc.h
|
||||
+++ b/include/uapi/drm/drm_fourcc.h
|
||||
@@ -279,6 +279,8 @@ extern "C" {
|
||||
* index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
|
||||
*/
|
||||
#define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
|
||||
+#define DRM_FORMAT_NV20 fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */
|
||||
+#define DRM_FORMAT_NV30 fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
|
||||
|
||||
/*
|
||||
* 2 plane YCbCr MSB aligned
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Mon, 6 Jul 2020 22:30:13 +0000
|
||||
Subject: [PATCH] drm: rockchip: add NV15, NV20 and NV30 support
|
||||
|
||||
Add support for displaying 10-bit 4:2:0 and 4:2:2 formats produced by the
|
||||
Rockchip Video Decoder on RK322X, RK3288, RK3328, RK3368 and RK3399.
|
||||
Also add support for 10-bit 4:4:4 format while at it.
|
||||
|
||||
V2: Added NV30 support
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
Reviewed-by: Sandy Huang <hjc@rock-chips.com>
|
||||
---
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 29 +++++++++++++++++--
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 +
|
||||
drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 32 +++++++++++++++++----
|
||||
3 files changed, 54 insertions(+), 8 deletions(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
|
||||
index f5b9028a16a3..9df4a271f3aa 100644
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
|
||||
@@ -262,6 +262,18 @@ static bool has_rb_swapped(uint32_t format)
|
||||
}
|
||||
}
|
||||
|
||||
+static bool is_fmt_10(uint32_t format)
|
||||
+{
|
||||
+ switch (format) {
|
||||
+ case DRM_FORMAT_NV15:
|
||||
+ case DRM_FORMAT_NV20:
|
||||
+ case DRM_FORMAT_NV30:
|
||||
+ return true;
|
||||
+ default:
|
||||
+ return false;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
static enum vop_data_format vop_convert_format(uint32_t format)
|
||||
{
|
||||
switch (format) {
|
||||
@@ -277,10 +289,13 @@ static enum vop_data_format vop_convert_format(uint32_t format)
|
||||
case DRM_FORMAT_BGR565:
|
||||
return VOP_FMT_RGB565;
|
||||
case DRM_FORMAT_NV12:
|
||||
+ case DRM_FORMAT_NV15:
|
||||
return VOP_FMT_YUV420SP;
|
||||
case DRM_FORMAT_NV16:
|
||||
+ case DRM_FORMAT_NV20:
|
||||
return VOP_FMT_YUV422SP;
|
||||
case DRM_FORMAT_NV24:
|
||||
+ case DRM_FORMAT_NV30:
|
||||
return VOP_FMT_YUV444SP;
|
||||
default:
|
||||
DRM_ERROR("unsupported format[%08x]\n", format);
|
||||
@@ -931,7 +946,12 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
|
||||
dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
|
||||
dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
|
||||
|
||||
- offset = (src->x1 >> 16) * fb->format->cpp[0];
|
||||
+ if (fb->format->block_w[0])
|
||||
+ offset = (src->x1 >> 16) * fb->format->char_per_block[0] /
|
||||
+ fb->format->block_w[0];
|
||||
+ else
|
||||
+ offset = (src->x1 >> 16) * fb->format->cpp[0];
|
||||
+
|
||||
offset += (src->y1 >> 16) * fb->pitches[0];
|
||||
dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
|
||||
|
||||
@@ -957,6 +977,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
|
||||
}
|
||||
|
||||
VOP_WIN_SET(vop, win, format, format);
|
||||
+ VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format));
|
||||
VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
|
||||
VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
|
||||
VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
|
||||
@@ -973,7 +994,11 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
|
||||
uv_obj = fb->obj[1];
|
||||
rk_uv_obj = to_rockchip_obj(uv_obj);
|
||||
|
||||
- offset = (src->x1 >> 16) * bpp / hsub;
|
||||
+ if (fb->format->block_w[1])
|
||||
+ offset = (src->x1 >> 16) * bpp /
|
||||
+ fb->format->block_w[1] / hsub;
|
||||
+ else
|
||||
+ offset = (src->x1 >> 16) * bpp / hsub;
|
||||
offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
|
||||
|
||||
dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
|
||||
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
|
||||
index 857d97cdc67c..b7169010622a 100644
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
|
||||
@@ -165,6 +165,7 @@ struct vop_win_phy {
|
||||
struct vop_reg enable;
|
||||
struct vop_reg gate;
|
||||
struct vop_reg format;
|
||||
+ struct vop_reg fmt_10;
|
||||
struct vop_reg rb_swap;
|
||||
struct vop_reg act_info;
|
||||
struct vop_reg dsp_info;
|
||||
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
|
||||
index ca7cc82125cb..fff9c3387b9d 100644
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
|
||||
@@ -50,6 +50,23 @@ static const uint32_t formats_win_full[] = {
|
||||
DRM_FORMAT_NV24,
|
||||
};
|
||||
|
||||
+static const uint32_t formats_win_full_10[] = {
|
||||
+ DRM_FORMAT_XRGB8888,
|
||||
+ DRM_FORMAT_ARGB8888,
|
||||
+ DRM_FORMAT_XBGR8888,
|
||||
+ DRM_FORMAT_ABGR8888,
|
||||
+ DRM_FORMAT_RGB888,
|
||||
+ DRM_FORMAT_BGR888,
|
||||
+ DRM_FORMAT_RGB565,
|
||||
+ DRM_FORMAT_BGR565,
|
||||
+ DRM_FORMAT_NV12,
|
||||
+ DRM_FORMAT_NV16,
|
||||
+ DRM_FORMAT_NV24,
|
||||
+ DRM_FORMAT_NV15,
|
||||
+ DRM_FORMAT_NV20,
|
||||
+ DRM_FORMAT_NV30,
|
||||
+};
|
||||
+
|
||||
static const uint64_t format_modifiers_win_full[] = {
|
||||
DRM_FORMAT_MOD_LINEAR,
|
||||
DRM_FORMAT_MOD_INVALID,
|
||||
@@ -613,11 +630,12 @@ static const struct vop_scl_regs rk3288_win_full_scl = {
|
||||
|
||||
static const struct vop_win_phy rk3288_win01_data = {
|
||||
.scl = &rk3288_win_full_scl,
|
||||
- .data_formats = formats_win_full,
|
||||
- .nformats = ARRAY_SIZE(formats_win_full),
|
||||
+ .data_formats = formats_win_full_10,
|
||||
+ .nformats = ARRAY_SIZE(formats_win_full_10),
|
||||
.format_modifiers = format_modifiers_win_full,
|
||||
.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
|
||||
.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
|
||||
+ .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
|
||||
.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
|
||||
.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
|
||||
.dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
|
||||
@@ -747,11 +765,12 @@ static const struct vop_intr rk3368_vop_intr = {
|
||||
|
||||
static const struct vop_win_phy rk3368_win01_data = {
|
||||
.scl = &rk3288_win_full_scl,
|
||||
- .data_formats = formats_win_full,
|
||||
- .nformats = ARRAY_SIZE(formats_win_full),
|
||||
+ .data_formats = formats_win_full_10,
|
||||
+ .nformats = ARRAY_SIZE(formats_win_full_10),
|
||||
.format_modifiers = format_modifiers_win_full,
|
||||
.enable = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 0),
|
||||
.format = VOP_REG(RK3368_WIN0_CTRL0, 0x7, 1),
|
||||
+ .fmt_10 = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 4),
|
||||
.rb_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 12),
|
||||
.x_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 21),
|
||||
.y_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 22),
|
||||
@@ -896,11 +915,12 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_big_win_yuv2yuv_data[] = {
|
||||
|
||||
static const struct vop_win_phy rk3399_win01_data = {
|
||||
.scl = &rk3288_win_full_scl,
|
||||
- .data_formats = formats_win_full,
|
||||
- .nformats = ARRAY_SIZE(formats_win_full),
|
||||
+ .data_formats = formats_win_full_10,
|
||||
+ .nformats = ARRAY_SIZE(formats_win_full_10),
|
||||
.format_modifiers = format_modifiers_win_full_afbc,
|
||||
.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
|
||||
.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
|
||||
+ .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
|
||||
.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
|
||||
.y_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 22),
|
||||
.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Qinglang Miao <miaoqinglang@huawei.com>
|
||||
Date: Tue, 1 Dec 2020 20:54:57 +0800
|
||||
Subject: [PATCH] drm/rockchip: cdn-dp: fix reference leak when
|
||||
pm_runtime_get_sync fails
|
||||
|
||||
The PM reference count is not expected to be incremented on
|
||||
return in cdn_dp_clk_enable.
|
||||
|
||||
However, pm_runtime_get_sync will increment the PM reference
|
||||
count even failed. Forgetting to putting operation will result
|
||||
in a reference leak here.
|
||||
|
||||
Replace it with pm_runtime_resume_and_get to keep usage
|
||||
counter balanced.
|
||||
|
||||
Fixes: efe0220fc2d2 ("drm/rockchip: cdn-dp: Fix error handling")
|
||||
Reported-by: Hulk Robot <hulkci@huawei.com>
|
||||
Signed-off-by: Qinglang Miao <miaoqinglang@huawei.com>
|
||||
---
|
||||
drivers/gpu/drm/rockchip/cdn-dp-core.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c
|
||||
index 8ab3247dbc4a..8429c6706ec5 100644
|
||||
--- a/drivers/gpu/drm/rockchip/cdn-dp-core.c
|
||||
+++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c
|
||||
@@ -100,7 +100,7 @@ static int cdn_dp_clk_enable(struct cdn_dp_device *dp)
|
||||
goto err_core_clk;
|
||||
}
|
||||
|
||||
- ret = pm_runtime_get_sync(dp->dev);
|
||||
+ ret = pm_runtime_resume_and_get(dp->dev);
|
||||
if (ret < 0) {
|
||||
DRM_DEV_ERROR(dp->dev, "cannot get pm runtime %d\n", ret);
|
||||
goto err_pm_runtime_get;
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Qinglang Miao <miaoqinglang@huawei.com>
|
||||
Date: Tue, 1 Dec 2020 20:54:58 +0800
|
||||
Subject: [PATCH] drm/rockchip: vop: fix reference leak when
|
||||
pm_runtime_get_sync fails
|
||||
|
||||
The PM reference count is not expected to be incremented on
|
||||
return in functions vop_enable and vop_enable.
|
||||
|
||||
However, pm_runtime_get_sync will increment the PM reference
|
||||
count even failed. Forgetting to putting operation will result
|
||||
in a reference leak here.
|
||||
|
||||
Replace it with pm_runtime_resume_and_get to keep usage
|
||||
counter balanced.
|
||||
|
||||
Fixes: 5e570373c015 ("drm/rockchip: vop: Enable pm domain before vop_initial")
|
||||
Reported-by: Hulk Robot <hulkci@huawei.com>
|
||||
Signed-off-by: Qinglang Miao <miaoqinglang@huawei.com>
|
||||
---
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
|
||||
index 9df4a271f3aa..c3c0de25b8e6 100644
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
|
||||
@@ -603,7 +603,7 @@ static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state)
|
||||
struct vop *vop = to_vop(crtc);
|
||||
int ret, i;
|
||||
|
||||
- ret = pm_runtime_get_sync(vop->dev);
|
||||
+ ret = pm_runtime_resume_and_get(vop->dev);
|
||||
if (ret < 0) {
|
||||
DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
|
||||
return ret;
|
||||
@@ -1956,7 +1956,7 @@ static int vop_initial(struct vop *vop)
|
||||
return PTR_ERR(vop->dclk);
|
||||
}
|
||||
|
||||
- ret = pm_runtime_get_sync(vop->dev);
|
||||
+ ret = pm_runtime_resume_and_get(vop->dev);
|
||||
if (ret < 0) {
|
||||
DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
|
||||
return ret;
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Qinglang Miao <miaoqinglang@huawei.com>
|
||||
Date: Tue, 1 Dec 2020 20:54:59 +0800
|
||||
Subject: [PATCH] drm/rockchip: lvds: fix reference leak when
|
||||
pm_runtime_get_sync fails
|
||||
|
||||
The PM reference count is not expected to be incremented on
|
||||
return in functions rk3288_lvds_poweron and px30_lvds_poweron.
|
||||
|
||||
However, pm_runtime_get_sync will increment the PM reference
|
||||
count even failed. Forgetting to putting operation will result
|
||||
in a reference leak here.
|
||||
|
||||
Replace it with pm_runtime_resume_and_get to keep usage
|
||||
counter balanced.
|
||||
|
||||
Fixes: cca1705c3d89 ("drm/rockchip: lvds: Add PX30 support")
|
||||
Reported-by: Hulk Robot <hulkci@huawei.com>
|
||||
Signed-off-by: Qinglang Miao <miaoqinglang@huawei.com>
|
||||
---
|
||||
drivers/gpu/drm/rockchip/rockchip_lvds.c | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c b/drivers/gpu/drm/rockchip/rockchip_lvds.c
|
||||
index 489d63c05c0d..aaf0b6bbcb85 100644
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_lvds.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c
|
||||
@@ -145,7 +145,7 @@ static int rk3288_lvds_poweron(struct rockchip_lvds *lvds)
|
||||
DRM_DEV_ERROR(lvds->dev, "failed to enable lvds pclk %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
- ret = pm_runtime_get_sync(lvds->dev);
|
||||
+ ret = pm_runtime_resume_and_get(lvds->dev);
|
||||
if (ret < 0) {
|
||||
DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret);
|
||||
clk_disable(lvds->pclk);
|
||||
@@ -329,7 +329,7 @@ static int px30_lvds_poweron(struct rockchip_lvds *lvds)
|
||||
{
|
||||
int ret;
|
||||
|
||||
- ret = pm_runtime_get_sync(lvds->dev);
|
||||
+ ret = pm_runtime_resume_and_get(lvds->dev);
|
||||
if (ret < 0) {
|
||||
DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret);
|
||||
return ret;
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Thomas Zimmermann <tzimmermann@suse.de>
|
||||
Date: Thu, 24 Jun 2021 11:55:02 +0200
|
||||
Subject: [PATCH] drm/rockchip: Implement mmap as GEM object function
|
||||
|
||||
Moving the driver-specific mmap code into a GEM object function allows
|
||||
for using DRM helpers for various mmap callbacks.
|
||||
|
||||
The respective rockchip functions are being removed. The file_operations
|
||||
structure fops is now being created by the helper macro
|
||||
DEFINE_DRM_GEM_FOPS().
|
||||
|
||||
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
|
||||
Tested-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 13 +-----
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c | 3 +-
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 44 +++++--------------
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_gem.h | 7 ---
|
||||
4 files changed, 15 insertions(+), 52 deletions(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
|
||||
index b730b8d5d949..2e3ab573a817 100644
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
|
||||
@@ -208,16 +208,7 @@ static void rockchip_drm_unbind(struct device *dev)
|
||||
drm_dev_put(drm_dev);
|
||||
}
|
||||
|
||||
-static const struct file_operations rockchip_drm_driver_fops = {
|
||||
- .owner = THIS_MODULE,
|
||||
- .open = drm_open,
|
||||
- .mmap = rockchip_gem_mmap,
|
||||
- .poll = drm_poll,
|
||||
- .read = drm_read,
|
||||
- .unlocked_ioctl = drm_ioctl,
|
||||
- .compat_ioctl = drm_compat_ioctl,
|
||||
- .release = drm_release,
|
||||
-};
|
||||
+DEFINE_DRM_GEM_FOPS(rockchip_drm_driver_fops);
|
||||
|
||||
static const struct drm_driver rockchip_drm_driver = {
|
||||
.driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
|
||||
@@ -226,7 +217,7 @@ static const struct drm_driver rockchip_drm_driver = {
|
||||
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
|
||||
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
|
||||
.gem_prime_import_sg_table = rockchip_gem_prime_import_sg_table,
|
||||
- .gem_prime_mmap = rockchip_gem_mmap_buf,
|
||||
+ .gem_prime_mmap = drm_gem_prime_mmap,
|
||||
.fops = &rockchip_drm_driver_fops,
|
||||
.name = DRIVER_NAME,
|
||||
.desc = DRIVER_DESC,
|
||||
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c
|
||||
index 2fdc455c4ad7..d8418dd39d0e 100644
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c
|
||||
@@ -7,6 +7,7 @@
|
||||
#include <drm/drm.h>
|
||||
#include <drm/drm_fb_helper.h>
|
||||
#include <drm/drm_fourcc.h>
|
||||
+#include <drm/drm_prime.h>
|
||||
#include <drm/drm_probe_helper.h>
|
||||
|
||||
#include "rockchip_drm_drv.h"
|
||||
@@ -24,7 +25,7 @@ static int rockchip_fbdev_mmap(struct fb_info *info,
|
||||
struct drm_fb_helper *helper = info->par;
|
||||
struct rockchip_drm_private *private = to_drm_private(helper);
|
||||
|
||||
- return rockchip_gem_mmap_buf(private->fbdev_bo, vma);
|
||||
+ return drm_gem_prime_mmap(private->fbdev_bo, vma);
|
||||
}
|
||||
|
||||
static const struct fb_ops rockchip_drm_fbdev_ops = {
|
||||
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
|
||||
index 7971f57436dd..63eb73b624aa 100644
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
|
||||
@@ -240,12 +240,22 @@ static int rockchip_drm_gem_object_mmap(struct drm_gem_object *obj,
|
||||
int ret;
|
||||
struct rockchip_gem_object *rk_obj = to_rockchip_obj(obj);
|
||||
|
||||
+ /*
|
||||
+ * Set vm_pgoff (used as a fake buffer offset by DRM) to 0 and map the
|
||||
+ * whole buffer from the start.
|
||||
+ */
|
||||
+ vma->vm_pgoff = 0;
|
||||
+
|
||||
/*
|
||||
* We allocated a struct page table for rk_obj, so clear
|
||||
* VM_PFNMAP flag that was set by drm_gem_mmap_obj()/drm_gem_mmap().
|
||||
*/
|
||||
+ vma->vm_flags |= VM_IO | VM_DONTEXPAND | VM_DONTDUMP;
|
||||
vma->vm_flags &= ~VM_PFNMAP;
|
||||
|
||||
+ vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
|
||||
+ vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot);
|
||||
+
|
||||
if (rk_obj->pages)
|
||||
ret = rockchip_drm_gem_object_mmap_iommu(obj, vma);
|
||||
else
|
||||
@@ -257,39 +267,6 @@ static int rockchip_drm_gem_object_mmap(struct drm_gem_object *obj,
|
||||
return ret;
|
||||
}
|
||||
|
||||
-int rockchip_gem_mmap_buf(struct drm_gem_object *obj,
|
||||
- struct vm_area_struct *vma)
|
||||
-{
|
||||
- int ret;
|
||||
-
|
||||
- ret = drm_gem_mmap_obj(obj, obj->size, vma);
|
||||
- if (ret)
|
||||
- return ret;
|
||||
-
|
||||
- return rockchip_drm_gem_object_mmap(obj, vma);
|
||||
-}
|
||||
-
|
||||
-/* drm driver mmap file operations */
|
||||
-int rockchip_gem_mmap(struct file *filp, struct vm_area_struct *vma)
|
||||
-{
|
||||
- struct drm_gem_object *obj;
|
||||
- int ret;
|
||||
-
|
||||
- ret = drm_gem_mmap(filp, vma);
|
||||
- if (ret)
|
||||
- return ret;
|
||||
-
|
||||
- /*
|
||||
- * Set vm_pgoff (used as a fake buffer offset by DRM) to 0 and map the
|
||||
- * whole buffer from the start.
|
||||
- */
|
||||
- vma->vm_pgoff = 0;
|
||||
-
|
||||
- obj = vma->vm_private_data;
|
||||
-
|
||||
- return rockchip_drm_gem_object_mmap(obj, vma);
|
||||
-}
|
||||
-
|
||||
static void rockchip_gem_release_object(struct rockchip_gem_object *rk_obj)
|
||||
{
|
||||
drm_gem_object_release(&rk_obj->base);
|
||||
@@ -301,6 +278,7 @@ static const struct drm_gem_object_funcs rockchip_gem_object_funcs = {
|
||||
.get_sg_table = rockchip_gem_prime_get_sg_table,
|
||||
.vmap = rockchip_gem_prime_vmap,
|
||||
.vunmap = rockchip_gem_prime_vunmap,
|
||||
+ .mmap = rockchip_drm_gem_object_mmap,
|
||||
.vm_ops = &drm_gem_cma_vm_ops,
|
||||
};
|
||||
|
||||
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.h b/drivers/gpu/drm/rockchip/rockchip_drm_gem.h
|
||||
index 5a70a56cd406..47c1861eece0 100644
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.h
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.h
|
||||
@@ -34,13 +34,6 @@ rockchip_gem_prime_import_sg_table(struct drm_device *dev,
|
||||
int rockchip_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map);
|
||||
void rockchip_gem_prime_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map);
|
||||
|
||||
-/* drm driver mmap file operations */
|
||||
-int rockchip_gem_mmap(struct file *filp, struct vm_area_struct *vma);
|
||||
-
|
||||
-/* mmap a gem object to userspace. */
|
||||
-int rockchip_gem_mmap_buf(struct drm_gem_object *obj,
|
||||
- struct vm_area_struct *vma);
|
||||
-
|
||||
struct rockchip_gem_object *
|
||||
rockchip_gem_create_object(struct drm_device *drm, unsigned int size,
|
||||
bool alloc_kmap);
|
||||
|
||||
3505
patch/kernel/archive/rk322x-5.16/01-linux-1000-drm-rockchip.patch
Normal file
3505
patch/kernel/archive/rk322x-5.16/01-linux-1000-drm-rockchip.patch
Normal file
File diff suppressed because it is too large
Load Diff
1023
patch/kernel/archive/rk322x-5.16/01-linux-1001-v4l2-rockchip.patch
Normal file
1023
patch/kernel/archive/rk322x-5.16/01-linux-1001-v4l2-rockchip.patch
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,647 @@
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Wed, 2 Sep 2020 19:52:02 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: add gpu powerdomain, gpu opp-table and
|
||||
cooling cell for RK3328
|
||||
|
||||
Note: since the regulator that supplies the GPU usually also supplies
|
||||
other SoC components, we have to make sure voltage is never lower then
|
||||
1075 mV.
|
||||
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 34 ++++++++++++++++++++++++
|
||||
1 file changed, 34 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
index 23021373e15b..ca03c8ed9708 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
@@ -300,6 +300,11 @@ power: power-controller {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
+ power-domain@RK3328_PD_GPU {
|
||||
+ reg = <RK3328_PD_GPU>;
|
||||
+ clocks = <&cru ACLK_GPU>;
|
||||
+ #power-domain-cells = <0>;
|
||||
+ };
|
||||
power-domain@RK3328_PD_HEVC {
|
||||
reg = <RK3328_PD_HEVC>;
|
||||
#power-domain-cells = <0>;
|
||||
@@ -539,6 +544,11 @@ map0 {
|
||||
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
contribution = <4096>;
|
||||
};
|
||||
+ map1 {
|
||||
+ trip = <&target>;
|
||||
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
+ contribution = <4096>;
|
||||
+ };
|
||||
};
|
||||
};
|
||||
|
||||
@@ -620,7 +630,31 @@ gpu: gpu@ff300000 {
|
||||
"ppmmu1";
|
||||
clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
|
||||
clock-names = "bus", "core";
|
||||
+ operating-points-v2 = <&gpu_opp_table>;
|
||||
+ power-domains = <&power RK3328_PD_GPU>;
|
||||
resets = <&cru SRST_GPU_A>;
|
||||
+ #cooling-cells = <2>;
|
||||
+ };
|
||||
+
|
||||
+ gpu_opp_table: gpu-opp-table {
|
||||
+ compatible = "operating-points-v2";
|
||||
+
|
||||
+ opp-200000000 {
|
||||
+ opp-hz = /bits/ 64 <200000000>;
|
||||
+ opp-microvolt = <1075000>;
|
||||
+ };
|
||||
+ opp-300000000 {
|
||||
+ opp-hz = /bits/ 64 <300000000>;
|
||||
+ opp-microvolt = <1075000>;
|
||||
+ };
|
||||
+ opp-400000000 {
|
||||
+ opp-hz = /bits/ 64 <400000000>;
|
||||
+ opp-microvolt = <1075000>;
|
||||
+ };
|
||||
+ opp-500000000 {
|
||||
+ opp-hz = /bits/ 64 <500000000>;
|
||||
+ opp-microvolt = <1150000>;
|
||||
+ };
|
||||
};
|
||||
|
||||
h265e_mmu: iommu@ff330200 {
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Tue, 2 Feb 2021 17:22:21 +0200
|
||||
Subject: [PATCH] ARM: dts: RK3288 miqi add hdmi sound nodes
|
||||
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
---
|
||||
arch/arm/boot/dts/rk3288-miqi.dts | 20 ++++++++++++++++++++
|
||||
1 file changed, 20 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
|
||||
index 713f55e143c6..8d30c49f406e 100644
|
||||
--- a/arch/arm/boot/dts/rk3288-miqi.dts
|
||||
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
|
||||
@@ -78,6 +78,21 @@ vcc_sys: vsys-regulator {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
+
|
||||
+ sound {
|
||||
+ compatible = "simple-audio-card";
|
||||
+ simple-audio-card,format = "i2s";
|
||||
+ simple-audio-card,name = "HDMI";
|
||||
+ simple-audio-card,mclk-fs = <512>;
|
||||
+
|
||||
+ simple-audio-card,codec {
|
||||
+ sound-dai = <&hdmi>;
|
||||
+ };
|
||||
+
|
||||
+ simple-audio-card,cpu {
|
||||
+ sound-dai = <&i2s>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
@@ -284,6 +299,11 @@ &i2c5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&i2s {
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&io_domains {
|
||||
status = "okay";
|
||||
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Fri, 2 Apr 2021 17:54:22 +0200
|
||||
Subject: [PATCH] ARM/arm64: dts: rockchip: align sound card names
|
||||
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
---
|
||||
arch/arm/boot/dts/rk3288-tinker.dtsi | 2 +-
|
||||
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +-
|
||||
2 files changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi
|
||||
index 9c1e38c54eae..ee332fc9cf1f 100644
|
||||
--- a/arch/arm/boot/dts/rk3288-tinker.dtsi
|
||||
+++ b/arch/arm/boot/dts/rk3288-tinker.dtsi
|
||||
@@ -75,7 +75,7 @@ sdio_pwrseq: sdio-pwrseq {
|
||||
sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,format = "i2s";
|
||||
- simple-audio-card,name = "rockchip,tinker-codec";
|
||||
+ simple-audio-card,name = "HDMI";
|
||||
simple-audio-card,mclk-fs = <512>;
|
||||
|
||||
simple-audio-card,codec {
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
index ec3561d147d5..b2ed593a229c 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
@@ -1807,7 +1807,7 @@ hdmi_sound: hdmi-sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,mclk-fs = <256>;
|
||||
- simple-audio-card,name = "hdmi-sound";
|
||||
+ simple-audio-card,name = "HDMI";
|
||||
status = "disabled";
|
||||
|
||||
simple-audio-card,cpu {
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Wed, 10 Feb 2021 18:44:56 +0200
|
||||
Subject: [PATCH] HACK: drm/gem: suppress warning about missing vm_flags
|
||||
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
---
|
||||
drivers/gpu/drm/drm_gem.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
|
||||
index d62fb1a3c916..e46165bed006 100644
|
||||
--- a/drivers/gpu/drm/drm_gem.c
|
||||
+++ b/drivers/gpu/drm/drm_gem.c
|
||||
@@ -1073,7 +1073,7 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size,
|
||||
ret = obj->funcs->mmap(obj, vma);
|
||||
if (ret)
|
||||
goto err_drm_gem_object_put;
|
||||
- WARN_ON(!(vma->vm_flags & VM_DONTEXPAND));
|
||||
+ //WARN_ON(!(vma->vm_flags & VM_DONTEXPAND));
|
||||
} else {
|
||||
if (!vma->vm_ops) {
|
||||
ret = -EINVAL;
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Sun, 25 Mar 2018 22:17:06 +0200
|
||||
Subject: [PATCH] ASoC: hdmi-codec: fix channel allocation
|
||||
|
||||
---
|
||||
sound/soc/codecs/hdmi-codec.c | 113 ++++++++++++++++------------------
|
||||
1 file changed, 52 insertions(+), 61 deletions(-)
|
||||
|
||||
diff --git a/sound/soc/codecs/hdmi-codec.c b/sound/soc/codecs/hdmi-codec.c
|
||||
index b61f980cabdc..3ad50ae8c93d 100644
|
||||
--- a/sound/soc/codecs/hdmi-codec.c
|
||||
+++ b/sound/soc/codecs/hdmi-codec.c
|
||||
@@ -194,78 +194,69 @@ static const struct snd_pcm_chmap_elem hdmi_codec_8ch_chmaps[] = {
|
||||
*/
|
||||
static const struct hdmi_codec_cea_spk_alloc hdmi_codec_channel_alloc[] = {
|
||||
{ .ca_id = 0x00, .n_ch = 2,
|
||||
- .mask = FL | FR},
|
||||
- /* 2.1 */
|
||||
- { .ca_id = 0x01, .n_ch = 4,
|
||||
- .mask = FL | FR | LFE},
|
||||
- /* Dolby Surround */
|
||||
+ .mask = FL | FR },
|
||||
+ { .ca_id = 0x03, .n_ch = 4,
|
||||
+ .mask = FL | FR | LFE | FC },
|
||||
{ .ca_id = 0x02, .n_ch = 4,
|
||||
.mask = FL | FR | FC },
|
||||
- /* surround51 */
|
||||
+ { .ca_id = 0x01, .n_ch = 4,
|
||||
+ .mask = FL | FR | LFE },
|
||||
{ .ca_id = 0x0b, .n_ch = 6,
|
||||
- .mask = FL | FR | LFE | FC | RL | RR},
|
||||
- /* surround40 */
|
||||
- { .ca_id = 0x08, .n_ch = 6,
|
||||
- .mask = FL | FR | RL | RR },
|
||||
- /* surround41 */
|
||||
- { .ca_id = 0x09, .n_ch = 6,
|
||||
- .mask = FL | FR | LFE | RL | RR },
|
||||
- /* surround50 */
|
||||
+ .mask = FL | FR | LFE | FC | RL | RR },
|
||||
{ .ca_id = 0x0a, .n_ch = 6,
|
||||
.mask = FL | FR | FC | RL | RR },
|
||||
- /* 6.1 */
|
||||
- { .ca_id = 0x0f, .n_ch = 8,
|
||||
- .mask = FL | FR | LFE | FC | RL | RR | RC },
|
||||
- /* surround71 */
|
||||
+ { .ca_id = 0x09, .n_ch = 6,
|
||||
+ .mask = FL | FR | LFE | RL | RR },
|
||||
+ { .ca_id = 0x08, .n_ch = 6,
|
||||
+ .mask = FL | FR | RL | RR },
|
||||
+ { .ca_id = 0x07, .n_ch = 6,
|
||||
+ .mask = FL | FR | LFE | FC | RC },
|
||||
+ { .ca_id = 0x06, .n_ch = 6,
|
||||
+ .mask = FL | FR | FC | RC },
|
||||
+ { .ca_id = 0x05, .n_ch = 6,
|
||||
+ .mask = FL | FR | LFE | RC },
|
||||
+ { .ca_id = 0x04, .n_ch = 6,
|
||||
+ .mask = FL | FR | RC },
|
||||
{ .ca_id = 0x13, .n_ch = 8,
|
||||
.mask = FL | FR | LFE | FC | RL | RR | RLC | RRC },
|
||||
- /* others */
|
||||
- { .ca_id = 0x03, .n_ch = 8,
|
||||
- .mask = FL | FR | LFE | FC },
|
||||
- { .ca_id = 0x04, .n_ch = 8,
|
||||
- .mask = FL | FR | RC},
|
||||
- { .ca_id = 0x05, .n_ch = 8,
|
||||
- .mask = FL | FR | LFE | RC },
|
||||
- { .ca_id = 0x06, .n_ch = 8,
|
||||
- .mask = FL | FR | FC | RC },
|
||||
- { .ca_id = 0x07, .n_ch = 8,
|
||||
- .mask = FL | FR | LFE | FC | RC },
|
||||
- { .ca_id = 0x0c, .n_ch = 8,
|
||||
- .mask = FL | FR | RC | RL | RR },
|
||||
- { .ca_id = 0x0d, .n_ch = 8,
|
||||
- .mask = FL | FR | LFE | RL | RR | RC },
|
||||
- { .ca_id = 0x0e, .n_ch = 8,
|
||||
- .mask = FL | FR | FC | RL | RR | RC },
|
||||
- { .ca_id = 0x10, .n_ch = 8,
|
||||
- .mask = FL | FR | RL | RR | RLC | RRC },
|
||||
- { .ca_id = 0x11, .n_ch = 8,
|
||||
- .mask = FL | FR | LFE | RL | RR | RLC | RRC },
|
||||
+ { .ca_id = 0x1f, .n_ch = 8,
|
||||
+ .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC },
|
||||
{ .ca_id = 0x12, .n_ch = 8,
|
||||
.mask = FL | FR | FC | RL | RR | RLC | RRC },
|
||||
- { .ca_id = 0x14, .n_ch = 8,
|
||||
- .mask = FL | FR | FLC | FRC },
|
||||
- { .ca_id = 0x15, .n_ch = 8,
|
||||
- .mask = FL | FR | LFE | FLC | FRC },
|
||||
- { .ca_id = 0x16, .n_ch = 8,
|
||||
- .mask = FL | FR | FC | FLC | FRC },
|
||||
- { .ca_id = 0x17, .n_ch = 8,
|
||||
- .mask = FL | FR | LFE | FC | FLC | FRC },
|
||||
- { .ca_id = 0x18, .n_ch = 8,
|
||||
- .mask = FL | FR | RC | FLC | FRC },
|
||||
- { .ca_id = 0x19, .n_ch = 8,
|
||||
- .mask = FL | FR | LFE | RC | FLC | FRC },
|
||||
- { .ca_id = 0x1a, .n_ch = 8,
|
||||
- .mask = FL | FR | RC | FC | FLC | FRC },
|
||||
- { .ca_id = 0x1b, .n_ch = 8,
|
||||
- .mask = FL | FR | LFE | RC | FC | FLC | FRC },
|
||||
- { .ca_id = 0x1c, .n_ch = 8,
|
||||
- .mask = FL | FR | RL | RR | FLC | FRC },
|
||||
- { .ca_id = 0x1d, .n_ch = 8,
|
||||
- .mask = FL | FR | LFE | RL | RR | FLC | FRC },
|
||||
{ .ca_id = 0x1e, .n_ch = 8,
|
||||
.mask = FL | FR | FC | RL | RR | FLC | FRC },
|
||||
- { .ca_id = 0x1f, .n_ch = 8,
|
||||
- .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC },
|
||||
+ { .ca_id = 0x11, .n_ch = 8,
|
||||
+ .mask = FL | FR | LFE | RL | RR | RLC | RRC },
|
||||
+ { .ca_id = 0x1d, .n_ch = 8,
|
||||
+ .mask = FL | FR | LFE | RL | RR | FLC | FRC },
|
||||
+ { .ca_id = 0x10, .n_ch = 8,
|
||||
+ .mask = FL | FR | RL | RR | RLC | RRC },
|
||||
+ { .ca_id = 0x1c, .n_ch = 8,
|
||||
+ .mask = FL | FR | RL | RR | FLC | FRC },
|
||||
+ { .ca_id = 0x0f, .n_ch = 8,
|
||||
+ .mask = FL | FR | LFE | FC | RL | RR | RC },
|
||||
+ { .ca_id = 0x1b, .n_ch = 8,
|
||||
+ .mask = FL | FR | LFE | RC | FC | FLC | FRC },
|
||||
+ { .ca_id = 0x0e, .n_ch = 8,
|
||||
+ .mask = FL | FR | FC | RL | RR | RC },
|
||||
+ { .ca_id = 0x1a, .n_ch = 8,
|
||||
+ .mask = FL | FR | RC | FC | FLC | FRC },
|
||||
+ { .ca_id = 0x0d, .n_ch = 8,
|
||||
+ .mask = FL | FR | LFE | RL | RR | RC },
|
||||
+ { .ca_id = 0x19, .n_ch = 8,
|
||||
+ .mask = FL | FR | LFE | RC | FLC | FRC },
|
||||
+ { .ca_id = 0x0c, .n_ch = 8,
|
||||
+ .mask = FL | FR | RC | RL | RR },
|
||||
+ { .ca_id = 0x18, .n_ch = 8,
|
||||
+ .mask = FL | FR | RC | FLC | FRC },
|
||||
+ { .ca_id = 0x17, .n_ch = 8,
|
||||
+ .mask = FL | FR | LFE | FC | FLC | FRC },
|
||||
+ { .ca_id = 0x16, .n_ch = 8,
|
||||
+ .mask = FL | FR | FC | FLC | FRC },
|
||||
+ { .ca_id = 0x15, .n_ch = 8,
|
||||
+ .mask = FL | FR | LFE | FLC | FRC },
|
||||
+ { .ca_id = 0x14, .n_ch = 8,
|
||||
+ .mask = FL | FR | FLC | FRC },
|
||||
};
|
||||
|
||||
struct hdmi_codec_priv {
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Sun, 2 May 2021 20:44:21 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: Fix gmac delays for rockpro64 board
|
||||
|
||||
Values are measured by RK's delayline tool in vendor kernel
|
||||
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
|
||||
index 83db4ca67334..06d2a1e3e340 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
|
||||
@@ -289,8 +289,8 @@ &gmac {
|
||||
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 10000 50000>;
|
||||
- tx_delay = <0x28>;
|
||||
- rx_delay = <0x11>;
|
||||
+ tx_delay = <0x23>;
|
||||
+ rx_delay = <0x1e>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Sat, 27 Feb 2021 17:52:02 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: add SPDIF nodes for RK3328 A1 board
|
||||
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 23 ++++++++++++++++++++++
|
||||
1 file changed, 23 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
|
||||
index de2d3e88e27f..68b74ed080f3 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
|
||||
@@ -57,6 +57,24 @@ ir-receiver {
|
||||
gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
|
||||
linux,rc-map-name = "rc-beelink-gs1";
|
||||
};
|
||||
+
|
||||
+ spdif_sound: spdif-sound {
|
||||
+ compatible = "simple-audio-card";
|
||||
+ simple-audio-card,name = "SPDIF";
|
||||
+
|
||||
+ simple-audio-card,cpu {
|
||||
+ sound-dai = <&spdif>;
|
||||
+ };
|
||||
+
|
||||
+ simple-audio-card,codec {
|
||||
+ sound-dai = <&spdif_dit>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ spdif_dit: spdif-dit {
|
||||
+ compatible = "linux,spdif-dit";
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ };
|
||||
};
|
||||
|
||||
&analog_sound {
|
||||
@@ -324,6 +342,11 @@ &sdmmc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&spdif {
|
||||
+ pinctrl-0 = <&spdifm0_tx>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <0>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Sat, 27 Feb 2021 18:01:13 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add ir-receiver node for RK3328 ROC CC
|
||||
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 14 ++++++++++++++
|
||||
1 file changed, 14 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
|
||||
index aa22a0c22265..a78fbddd21df 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
|
||||
@@ -88,6 +88,13 @@ vcc_phy: vcc-phy-regulator {
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
+ ir-receiver {
|
||||
+ compatible = "gpio-ir-receiver";
|
||||
+ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
|
||||
+ pinctrl-0 = <&ir_int>;
|
||||
+ pinctrl-names = "default";
|
||||
+ };
|
||||
+
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
@@ -308,6 +315,13 @@ &io_domains {
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
+
|
||||
+ ir {
|
||||
+ ir_int: ir-int {
|
||||
+ rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
pmic {
|
||||
pmic_int_l: pmic-int-l {
|
||||
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Mon, 1 Mar 2021 21:24:15 +0100
|
||||
Subject: [PATCH] ARM: dts: add cec pinctrl for RK3288 miqi board
|
||||
|
||||
---
|
||||
arch/arm/boot/dts/rk3288-miqi.dts | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
|
||||
index 8d30c49f406e..6d90db5a3b75 100644
|
||||
--- a/arch/arm/boot/dts/rk3288-miqi.dts
|
||||
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
|
||||
@@ -145,6 +145,8 @@ &gpu {
|
||||
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&i2c5>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&hdmi_cec_c0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Mon, 1 Mar 2021 19:22:15 +0100
|
||||
Subject: [PATCH] HACK: arm64: dts: enable FE phy for Beelink A1 also
|
||||
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 8 ++++++++
|
||||
1 file changed, 8 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
|
||||
index 68b74ed080f3..6736b5dc53e4 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
|
||||
@@ -147,6 +147,14 @@ rtl8211f: ethernet-phy@0 {
|
||||
};
|
||||
};
|
||||
|
||||
+&gmac2phy {
|
||||
+ clock_in_out = "output";
|
||||
+ assigned-clock-rate = <50000000>;
|
||||
+ assigned-clocks = <&cru SCLK_MAC2PHY>;
|
||||
+ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&gpu {
|
||||
mali-supply = <&vdd_logic>;
|
||||
};
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Tue, 26 Feb 2019 20:45:14 +0000
|
||||
Subject: [PATCH] WIP: dw-hdmi-cec: sleep 100ms on error
|
||||
|
||||
---
|
||||
drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c | 18 ++++++++++++++++--
|
||||
1 file changed, 16 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c
|
||||
index 70ab4fbdc23e..bf54bc70624f 100644
|
||||
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c
|
||||
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c
|
||||
@@ -4,6 +4,7 @@
|
||||
*
|
||||
* Copyright (C) 2015-2017 Russell King.
|
||||
*/
|
||||
+#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
@@ -129,8 +130,15 @@ static irqreturn_t dw_hdmi_cec_hardirq(int irq, void *data)
|
||||
|
||||
dw_hdmi_write(cec, stat, HDMI_IH_CEC_STAT0);
|
||||
|
||||
- if (stat & CEC_STAT_ERROR_INIT) {
|
||||
- cec->tx_status = CEC_TX_STATUS_ERROR;
|
||||
+ /* Status with both done and error_initiator bits have been seen
|
||||
+ * on Rockchip RK3328 devices, transmit attempt seems to have failed
|
||||
+ * when this happens, report as low drive and block cec-framework
|
||||
+ * 100ms before core retransmits the failed message, this seems to
|
||||
+ * mitigate the issue with failed transmit attempts.
|
||||
+ */
|
||||
+ if ((stat & (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) == (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) {
|
||||
+ pr_debug("dw_hdmi_cec_hardirq: stat=%02x LOW_DRIVE\n", stat);
|
||||
+ cec->tx_status = CEC_TX_STATUS_LOW_DRIVE;
|
||||
cec->tx_done = true;
|
||||
ret = IRQ_WAKE_THREAD;
|
||||
} else if (stat & CEC_STAT_DONE) {
|
||||
@@ -141,6 +149,10 @@ static irqreturn_t dw_hdmi_cec_hardirq(int irq, void *data)
|
||||
cec->tx_status = CEC_TX_STATUS_NACK;
|
||||
cec->tx_done = true;
|
||||
ret = IRQ_WAKE_THREAD;
|
||||
+ } else if (stat & CEC_STAT_ERROR_INIT) {
|
||||
+ cec->tx_status = CEC_TX_STATUS_ERROR;
|
||||
+ cec->tx_done = true;
|
||||
+ ret = IRQ_WAKE_THREAD;
|
||||
}
|
||||
|
||||
if (stat & CEC_STAT_EOM) {
|
||||
@@ -173,6 +185,8 @@ static irqreturn_t dw_hdmi_cec_thread(int irq, void *data)
|
||||
|
||||
if (cec->tx_done) {
|
||||
cec->tx_done = false;
|
||||
+ if (cec->tx_status == CEC_TX_STATUS_LOW_DRIVE)
|
||||
+ msleep(100);
|
||||
cec_transmit_attempt_done(adap, cec->tx_status);
|
||||
}
|
||||
if (cec->rx_done) {
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Wed, 5 May 2021 19:11:12 +0200
|
||||
Subject: [PATCH] arm64: boot: dts: Increase ACLK_PERILP0 clock rate for RK3399
|
||||
|
||||
As per vendor kernel. Leaving this clock at the lower rate will
|
||||
result in poor DMA controller performance
|
||||
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
index b2ed593a229c..27938ff0d208 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
@@ -1393,7 +1393,7 @@ cru: clock-controller@ff760000 {
|
||||
<1000000000>,
|
||||
<150000000>, <75000000>,
|
||||
<37500000>,
|
||||
- <100000000>, <100000000>,
|
||||
+ <300000000>, <100000000>,
|
||||
<50000000>, <600000000>,
|
||||
<100000000>, <50000000>,
|
||||
<400000000>, <400000000>,
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Sat, 21 Aug 2021 17:04:46 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: Enable USB3 for rk3328 Beelink A1
|
||||
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 5 +++++
|
||||
1 file changed, 5 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
|
||||
index 6736b5dc53e4..9000fae2a5ee 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
|
||||
@@ -388,6 +388,11 @@ &usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&usbdrd3 {
|
||||
+ dr_mode = "host";
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&vop {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Sat, 21 Aug 2021 14:03:25 +0200
|
||||
Subject: [PATCH] HACK: media: hantro: rockchip: disable H264 for RK3328
|
||||
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
---
|
||||
drivers/staging/media/hantro/rockchip_vpu_hw.c | 3 +--
|
||||
1 file changed, 1 insertion(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c
|
||||
index 3d98e2251ea5..b201700ccc8a 100644
|
||||
--- a/drivers/staging/media/hantro/rockchip_vpu_hw.c
|
||||
+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c
|
||||
@@ -530,8 +530,7 @@ const struct hantro_variant rk3328_vpu_variant = {
|
||||
.dec_offset = 0x400,
|
||||
.dec_fmts = rk3399_vpu_dec_fmts,
|
||||
.num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
|
||||
- .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
|
||||
- HANTRO_H264_DECODER,
|
||||
+ .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER,
|
||||
.codec_ops = rk3399_vpu_codec_ops,
|
||||
.irqs = rockchip_vdpu2_irqs,
|
||||
.num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs),
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,558 @@
|
||||
From d2d4783003509c554653cfceeb5ff946fe223bc2 Mon Sep 17 00:00:00 2001
|
||||
From: Paolo Sabatino <paolo.sabatino@gmail.com>
|
||||
Date: Thu, 9 Sep 2021 16:35:34 +0000
|
||||
Subject: [PATCH 1/4] 01-linux-0002-rockchip-from-list
|
||||
|
||||
---
|
||||
drivers/clk/rockchip/clk-pll.c | 236 ++++++++++++++++++++++++++++--
|
||||
drivers/clk/rockchip/clk-rk3228.c | 18 ++-
|
||||
drivers/clk/rockchip/clk.c | 39 ++++-
|
||||
drivers/clk/rockchip/clk.h | 27 +++-
|
||||
include/linux/clk-provider.h | 2 +
|
||||
5 files changed, 292 insertions(+), 30 deletions(-)
|
||||
|
||||
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
|
||||
index f7827b3b7..8409e9eed 100644
|
||||
--- a/drivers/clk/rockchip/clk-pll.c
|
||||
+++ b/drivers/clk/rockchip/clk-pll.c
|
||||
@@ -15,6 +15,7 @@
|
||||
#include <linux/iopoll.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/clk.h>
|
||||
+#include <linux/gcd.h>
|
||||
#include "clk.h"
|
||||
|
||||
#define PLL_MODE_MASK 0x3
|
||||
@@ -47,6 +48,198 @@ struct rockchip_clk_pll {
|
||||
#define to_rockchip_clk_pll_nb(nb) \
|
||||
container_of(nb, struct rockchip_clk_pll, clk_nb)
|
||||
|
||||
+#define MHZ (1000UL * 1000UL)
|
||||
+#define KHZ (1000UL)
|
||||
+
|
||||
+/* CLK_PLL_TYPE_RK3066_AUTO type ops */
|
||||
+#define PLL_FREF_MIN (269 * KHZ)
|
||||
+#define PLL_FREF_MAX (2200 * MHZ)
|
||||
+
|
||||
+#define PLL_FVCO_MIN (440 * MHZ)
|
||||
+#define PLL_FVCO_MAX (2200 * MHZ)
|
||||
+
|
||||
+#define PLL_FOUT_MIN (27500 * KHZ)
|
||||
+#define PLL_FOUT_MAX (2200 * MHZ)
|
||||
+
|
||||
+#define PLL_NF_MAX (4096)
|
||||
+#define PLL_NR_MAX (64)
|
||||
+#define PLL_NO_MAX (16)
|
||||
+
|
||||
+/* CLK_PLL_TYPE_RK3036/3366/3399_AUTO type ops */
|
||||
+#define MIN_FOUTVCO_FREQ (800 * MHZ)
|
||||
+#define MAX_FOUTVCO_FREQ (2000 * MHZ)
|
||||
+
|
||||
+static struct rockchip_pll_rate_table auto_table;
|
||||
+
|
||||
+static struct rockchip_pll_rate_table *rk_pll_rate_table_get(void)
|
||||
+{
|
||||
+ return &auto_table;
|
||||
+}
|
||||
+
|
||||
+static int rockchip_pll_clk_set_postdiv(unsigned long fout_hz,
|
||||
+ u32 *postdiv1,
|
||||
+ u32 *postdiv2,
|
||||
+ u32 *foutvco)
|
||||
+{
|
||||
+ unsigned long freq;
|
||||
+
|
||||
+ if (fout_hz < MIN_FOUTVCO_FREQ) {
|
||||
+ for (*postdiv1 = 1; *postdiv1 <= 7; (*postdiv1)++) {
|
||||
+ for (*postdiv2 = 1; *postdiv2 <= 7; (*postdiv2)++) {
|
||||
+ freq = fout_hz * (*postdiv1) * (*postdiv2);
|
||||
+ if (freq >= MIN_FOUTVCO_FREQ &&
|
||||
+ freq <= MAX_FOUTVCO_FREQ) {
|
||||
+ *foutvco = freq;
|
||||
+ return 0;
|
||||
+ }
|
||||
+ }
|
||||
+ }
|
||||
+ pr_err("CANNOT FIND postdiv1/2 to make fout in range from 800M to 2000M,fout = %lu\n",
|
||||
+ fout_hz);
|
||||
+ } else {
|
||||
+ *postdiv1 = 1;
|
||||
+ *postdiv2 = 1;
|
||||
+ }
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct rockchip_pll_rate_table *
|
||||
+rockchip_pll_clk_set_by_auto(struct rockchip_clk_pll *pll,
|
||||
+ unsigned long fin_hz,
|
||||
+ unsigned long fout_hz)
|
||||
+{
|
||||
+ struct rockchip_pll_rate_table *rate_table = rk_pll_rate_table_get();
|
||||
+ /* FIXME set postdiv1/2 always 1*/
|
||||
+ u32 foutvco = fout_hz;
|
||||
+ u64 fin_64, frac_64;
|
||||
+ u32 f_frac, postdiv1, postdiv2;
|
||||
+ unsigned long clk_gcd = 0;
|
||||
+
|
||||
+ if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz)
|
||||
+ return NULL;
|
||||
+
|
||||
+ rockchip_pll_clk_set_postdiv(fout_hz, &postdiv1, &postdiv2, &foutvco);
|
||||
+ rate_table->postdiv1 = postdiv1;
|
||||
+ rate_table->postdiv2 = postdiv2;
|
||||
+ rate_table->dsmpd = 1;
|
||||
+
|
||||
+ if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) {
|
||||
+ fin_hz /= MHZ;
|
||||
+ foutvco /= MHZ;
|
||||
+ clk_gcd = gcd(fin_hz, foutvco);
|
||||
+ rate_table->refdiv = fin_hz / clk_gcd;
|
||||
+ rate_table->fbdiv = foutvco / clk_gcd;
|
||||
+
|
||||
+ rate_table->frac = 0;
|
||||
+
|
||||
+ pr_debug("fin = %lu, fout = %lu, clk_gcd = %lu, refdiv = %u, fbdiv = %u, postdiv1 = %u, postdiv2 = %u, frac = %u\n",
|
||||
+ fin_hz, fout_hz, clk_gcd, rate_table->refdiv,
|
||||
+ rate_table->fbdiv, rate_table->postdiv1,
|
||||
+ rate_table->postdiv2, rate_table->frac);
|
||||
+ } else {
|
||||
+ pr_debug("frac div running, fin_hz = %lu, fout_hz = %lu, fin_INT_mhz = %lu, fout_INT_mhz = %lu\n",
|
||||
+ fin_hz, fout_hz,
|
||||
+ fin_hz / MHZ * MHZ,
|
||||
+ fout_hz / MHZ * MHZ);
|
||||
+ pr_debug("frac get postdiv1 = %u, postdiv2 = %u, foutvco = %u\n",
|
||||
+ rate_table->postdiv1, rate_table->postdiv2, foutvco);
|
||||
+ clk_gcd = gcd(fin_hz / MHZ, foutvco / MHZ);
|
||||
+ rate_table->refdiv = fin_hz / MHZ / clk_gcd;
|
||||
+ rate_table->fbdiv = foutvco / MHZ / clk_gcd;
|
||||
+ pr_debug("frac get refdiv = %u, fbdiv = %u\n",
|
||||
+ rate_table->refdiv, rate_table->fbdiv);
|
||||
+
|
||||
+ rate_table->frac = 0;
|
||||
+
|
||||
+ f_frac = (foutvco % MHZ);
|
||||
+ fin_64 = fin_hz;
|
||||
+ do_div(fin_64, (u64)rate_table->refdiv);
|
||||
+ frac_64 = (u64)f_frac << 24;
|
||||
+ do_div(frac_64, fin_64);
|
||||
+ rate_table->frac = (u32)frac_64;
|
||||
+ if (rate_table->frac > 0)
|
||||
+ rate_table->dsmpd = 0;
|
||||
+ pr_debug("frac = %x\n", rate_table->frac);
|
||||
+ }
|
||||
+ return rate_table;
|
||||
+}
|
||||
+
|
||||
+static struct rockchip_pll_rate_table *
|
||||
+rockchip_rk3066_pll_clk_set_by_auto(struct rockchip_clk_pll *pll,
|
||||
+ unsigned long fin_hz,
|
||||
+ unsigned long fout_hz)
|
||||
+{
|
||||
+ struct rockchip_pll_rate_table *rate_table = rk_pll_rate_table_get();
|
||||
+ u32 nr, nf, no, nonr;
|
||||
+ u32 nr_out, nf_out, no_out;
|
||||
+ u32 n;
|
||||
+ u32 numerator, denominator;
|
||||
+ u64 fref, fvco, fout;
|
||||
+ unsigned long clk_gcd = 0;
|
||||
+
|
||||
+ nr_out = PLL_NR_MAX + 1;
|
||||
+ no_out = 0;
|
||||
+ nf_out = 0;
|
||||
+
|
||||
+ if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz)
|
||||
+ return NULL;
|
||||
+
|
||||
+ clk_gcd = gcd(fin_hz, fout_hz);
|
||||
+
|
||||
+ numerator = fout_hz / clk_gcd;
|
||||
+ denominator = fin_hz / clk_gcd;
|
||||
+
|
||||
+ for (n = 1;; n++) {
|
||||
+ nf = numerator * n;
|
||||
+ nonr = denominator * n;
|
||||
+ if (nf > PLL_NF_MAX || nonr > (PLL_NO_MAX * PLL_NR_MAX))
|
||||
+ break;
|
||||
+
|
||||
+ for (no = 1; no <= PLL_NO_MAX; no++) {
|
||||
+ if (!(no == 1 || !(no % 2)))
|
||||
+ continue;
|
||||
+
|
||||
+ if (nonr % no)
|
||||
+ continue;
|
||||
+ nr = nonr / no;
|
||||
+
|
||||
+ if (nr > PLL_NR_MAX)
|
||||
+ continue;
|
||||
+
|
||||
+ fref = fin_hz / nr;
|
||||
+ if (fref < PLL_FREF_MIN || fref > PLL_FREF_MAX)
|
||||
+ continue;
|
||||
+
|
||||
+ fvco = fref * nf;
|
||||
+ if (fvco < PLL_FVCO_MIN || fvco > PLL_FVCO_MAX)
|
||||
+ continue;
|
||||
+
|
||||
+ fout = fvco / no;
|
||||
+ if (fout < PLL_FOUT_MIN || fout > PLL_FOUT_MAX)
|
||||
+ continue;
|
||||
+
|
||||
+ /* select the best from all available PLL settings */
|
||||
+ if ((no > no_out) ||
|
||||
+ ((no == no_out) && (nr < nr_out))) {
|
||||
+ nr_out = nr;
|
||||
+ nf_out = nf;
|
||||
+ no_out = no;
|
||||
+ }
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ /* output the best PLL setting */
|
||||
+ if ((nr_out <= PLL_NR_MAX) && (no_out > 0)) {
|
||||
+ rate_table->nr = nr_out;
|
||||
+ rate_table->nf = nf_out;
|
||||
+ rate_table->no = no_out;
|
||||
+ } else {
|
||||
+ return NULL;
|
||||
+ }
|
||||
+
|
||||
+ return rate_table;
|
||||
+}
|
||||
+
|
||||
static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(
|
||||
struct rockchip_clk_pll *pll, unsigned long rate)
|
||||
{
|
||||
@@ -58,24 +251,16 @@ static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(
|
||||
return &rate_table[i];
|
||||
}
|
||||
|
||||
- return NULL;
|
||||
+ if (pll->type == pll_rk3066)
|
||||
+ return rockchip_rk3066_pll_clk_set_by_auto(pll, 24 * MHZ, rate);
|
||||
+ else
|
||||
+ return rockchip_pll_clk_set_by_auto(pll, 24 * MHZ, rate);
|
||||
}
|
||||
|
||||
static long rockchip_pll_round_rate(struct clk_hw *hw,
|
||||
unsigned long drate, unsigned long *prate)
|
||||
{
|
||||
- struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
|
||||
- const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
|
||||
- int i;
|
||||
-
|
||||
- /* Assumming rate_table is in descending order */
|
||||
- for (i = 0; i < pll->rate_count; i++) {
|
||||
- if (drate >= rate_table[i].rate)
|
||||
- return rate_table[i].rate;
|
||||
- }
|
||||
-
|
||||
- /* return minimum supported value */
|
||||
- return rate_table[i - 1].rate;
|
||||
+ return drate;
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -165,7 +350,7 @@ static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw,
|
||||
{
|
||||
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
|
||||
struct rockchip_pll_rate_table cur;
|
||||
- u64 rate64 = prate;
|
||||
+ u64 rate64 = prate, frac_rate64 = prate;
|
||||
|
||||
rockchip_rk3036_pll_get_params(pll, &cur);
|
||||
|
||||
@@ -174,7 +359,7 @@ static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw,
|
||||
|
||||
if (cur.dsmpd == 0) {
|
||||
/* fractional mode */
|
||||
- u64 frac_rate64 = prate * cur.frac;
|
||||
+ frac_rate64 *= cur.frac;
|
||||
|
||||
do_div(frac_rate64, cur.refdiv);
|
||||
rate64 += frac_rate64 >> 24;
|
||||
@@ -210,6 +395,11 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
|
||||
rate_change_remuxed = 1;
|
||||
}
|
||||
|
||||
+ /* set pll power down */
|
||||
+ writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN,
|
||||
+ RK3036_PLLCON1_PWRDOWN, 0),
|
||||
+ pll->reg_base + RK3036_PLLCON(1));
|
||||
+
|
||||
/* update pll values */
|
||||
writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK,
|
||||
RK3036_PLLCON0_FBDIV_SHIFT) |
|
||||
@@ -231,6 +421,11 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
|
||||
pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT;
|
||||
writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));
|
||||
|
||||
+ /* set pll power up */
|
||||
+ writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),
|
||||
+ pll->reg_base + RK3036_PLLCON(1));
|
||||
+ udelay(1);
|
||||
+
|
||||
/* wait for the pll to lock */
|
||||
ret = rockchip_rk3036_pll_wait_lock(pll);
|
||||
if (ret) {
|
||||
@@ -692,6 +887,11 @@ static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll,
|
||||
rate_change_remuxed = 1;
|
||||
}
|
||||
|
||||
+ /* set pll power down */
|
||||
+ writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN,
|
||||
+ RK3399_PLLCON3_PWRDOWN, 0),
|
||||
+ pll->reg_base + RK3399_PLLCON(3));
|
||||
+
|
||||
/* update pll values */
|
||||
writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK,
|
||||
RK3399_PLLCON0_FBDIV_SHIFT),
|
||||
@@ -715,6 +915,12 @@ static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll,
|
||||
RK3399_PLLCON3_DSMPD_SHIFT),
|
||||
pll->reg_base + RK3399_PLLCON(3));
|
||||
|
||||
+ /* set pll power up */
|
||||
+ writel(HIWORD_UPDATE(0,
|
||||
+ RK3399_PLLCON3_PWRDOWN, 0),
|
||||
+ pll->reg_base + RK3399_PLLCON(3));
|
||||
+ udelay(1);
|
||||
+
|
||||
/* wait for the pll to lock */
|
||||
ret = rockchip_rk3399_pll_wait_lock(pll);
|
||||
if (ret) {
|
||||
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
|
||||
index 7343d2d76..aca1a483a 100644
|
||||
--- a/drivers/clk/rockchip/clk-rk3228.c
|
||||
+++ b/drivers/clk/rockchip/clk-rk3228.c
|
||||
@@ -15,6 +15,10 @@
|
||||
|
||||
#define RK3228_GRF_SOC_STATUS0 0x480
|
||||
|
||||
+#define RK3228_UART_FRAC_MAX_PRATE 600000000
|
||||
+#define RK3228_SPDIF_FRAC_MAX_PRATE 600000000
|
||||
+#define RK3228_I2S_FRAC_MAX_PRATE 600000000
|
||||
+
|
||||
enum rk3228_plls {
|
||||
apll, dpll, cpll, gpll,
|
||||
};
|
||||
@@ -420,7 +424,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
||||
COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(8), 0,
|
||||
RK2928_CLKGATE_CON(0), 4, GFLAGS,
|
||||
- &rk3228_i2s0_fracmux),
|
||||
+ &rk3228_i2s0_fracmux, RK3228_I2S_FRAC_MAX_PRATE),
|
||||
GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKGATE_CON(0), 5, GFLAGS),
|
||||
|
||||
@@ -430,7 +434,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
||||
COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(7), 0,
|
||||
RK2928_CLKGATE_CON(0), 11, GFLAGS,
|
||||
- &rk3228_i2s1_fracmux),
|
||||
+ &rk3228_i2s1_fracmux, RK3228_I2S_FRAC_MAX_PRATE),
|
||||
GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKGATE_CON(0), 14, GFLAGS),
|
||||
COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0,
|
||||
@@ -443,7 +447,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
||||
COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(30), 0,
|
||||
RK2928_CLKGATE_CON(0), 8, GFLAGS,
|
||||
- &rk3228_i2s2_fracmux),
|
||||
+ &rk3228_i2s2_fracmux, RK3228_I2S_FRAC_MAX_PRATE),
|
||||
GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKGATE_CON(0), 9, GFLAGS),
|
||||
|
||||
@@ -453,7 +457,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
||||
COMPOSITE_FRACMUX(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(20), 0,
|
||||
RK2928_CLKGATE_CON(2), 12, GFLAGS,
|
||||
- &rk3228_spdif_fracmux),
|
||||
+ &rk3228_spdif_fracmux, RK3228_SPDIF_FRAC_MAX_PRATE),
|
||||
|
||||
GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(1), 3, GFLAGS),
|
||||
@@ -488,15 +492,15 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
||||
COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(17), 0,
|
||||
RK2928_CLKGATE_CON(1), 9, GFLAGS,
|
||||
- &rk3228_uart0_fracmux),
|
||||
+ &rk3228_uart0_fracmux, RK3228_UART_FRAC_MAX_PRATE),
|
||||
COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(18), 0,
|
||||
RK2928_CLKGATE_CON(1), 11, GFLAGS,
|
||||
- &rk3228_uart1_fracmux),
|
||||
+ &rk3228_uart1_fracmux, RK3228_UART_FRAC_MAX_PRATE),
|
||||
COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(19), 0,
|
||||
RK2928_CLKGATE_CON(1), 13, GFLAGS,
|
||||
- &rk3228_uart2_fracmux),
|
||||
+ &rk3228_uart2_fracmux, RK3228_UART_FRAC_MAX_PRATE),
|
||||
|
||||
COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0,
|
||||
RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, 8, 5, DFLAGS,
|
||||
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
|
||||
index 049e5e0b6..d8e744c22 100644
|
||||
--- a/drivers/clk/rockchip/clk.c
|
||||
+++ b/drivers/clk/rockchip/clk.c
|
||||
@@ -210,7 +229,7 @@ static struct clk *rockchip_clk_register_frac_branch(
|
||||
void __iomem *base, int muxdiv_offset, u8 div_flags,
|
||||
int gate_offset, u8 gate_shift, u8 gate_flags,
|
||||
unsigned long flags, struct rockchip_clk_branch *child,
|
||||
- spinlock_t *lock)
|
||||
+ unsigned long max_prate, spinlock_t *lock)
|
||||
{
|
||||
struct clk_hw *hw;
|
||||
struct rockchip_clk_frac *frac;
|
||||
@@ -251,6 +270,7 @@ static struct clk *rockchip_clk_register_frac_branch(
|
||||
div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
|
||||
div->lock = lock;
|
||||
div->approximation = rockchip_fractional_approximation;
|
||||
+ div->max_prate = max_prate;
|
||||
div_ops = &clk_fractional_divider_ops;
|
||||
|
||||
hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
|
||||
@@ -387,6 +407,8 @@ struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
|
||||
|
||||
ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
|
||||
"rockchip,grf");
|
||||
+ ctx->pmugrf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
|
||||
+ "rockchip,pmugrf");
|
||||
|
||||
return ctx;
|
||||
|
||||
@@ -465,6 +487,13 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
|
||||
list->mux_shift, list->mux_width,
|
||||
list->mux_flags);
|
||||
break;
|
||||
+ case branch_muxpmugrf:
|
||||
+ clk = rockchip_clk_register_muxgrf(list->name,
|
||||
+ list->parent_names, list->num_parents,
|
||||
+ flags, ctx->pmugrf, list->muxdiv_offset,
|
||||
+ list->mux_shift, list->mux_width,
|
||||
+ list->mux_flags);
|
||||
+ break;
|
||||
case branch_divider:
|
||||
if (list->div_table)
|
||||
clk = clk_register_divider_table(NULL,
|
||||
@@ -488,7 +517,7 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
|
||||
list->div_flags,
|
||||
list->gate_offset, list->gate_shift,
|
||||
list->gate_flags, flags, list->child,
|
||||
- &ctx->lock);
|
||||
+ list->max_prate, &ctx->lock);
|
||||
break;
|
||||
case branch_half_divider:
|
||||
clk = rockchip_clk_register_halfdiv(list->name,
|
||||
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
|
||||
index 7aa45cc70..6becf40a8 100644
|
||||
--- a/drivers/clk/rockchip/clk.h
|
||||
+++ b/drivers/clk/rockchip/clk.h
|
||||
@@ -266,6 +266,7 @@ struct rockchip_clk_provider {
|
||||
struct clk_onecell_data clk_data;
|
||||
struct device_node *cru_node;
|
||||
struct regmap *grf;
|
||||
+ struct regmap *pmugrf;
|
||||
spinlock_t lock;
|
||||
};
|
||||
|
||||
@@ -427,6 +428,7 @@ enum rockchip_clk_branch_type {
|
||||
branch_composite,
|
||||
branch_mux,
|
||||
branch_muxgrf,
|
||||
+ branch_muxpmugrf,
|
||||
branch_divider,
|
||||
branch_fraction_divider,
|
||||
branch_gate,
|
||||
@@ -457,6 +459,7 @@ struct rockchip_clk_branch {
|
||||
u8 gate_shift;
|
||||
u8 gate_flags;
|
||||
struct rockchip_clk_branch *child;
|
||||
+ unsigned long max_prate;
|
||||
};
|
||||
|
||||
#define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
|
||||
@@ -596,7 +599,7 @@ struct rockchip_clk_branch {
|
||||
.gate_offset = -1, \
|
||||
}
|
||||
|
||||
-#define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
|
||||
+#define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf, prate)\
|
||||
{ \
|
||||
.id = _id, \
|
||||
.branch_type = branch_fraction_divider, \
|
||||
@@ -611,9 +614,10 @@ struct rockchip_clk_branch {
|
||||
.gate_offset = go, \
|
||||
.gate_shift = gs, \
|
||||
.gate_flags = gf, \
|
||||
+ .max_prate = prate, \
|
||||
}
|
||||
|
||||
-#define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \
|
||||
+#define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch, prate) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.branch_type = branch_fraction_divider, \
|
||||
@@ -629,9 +633,10 @@ struct rockchip_clk_branch {
|
||||
.gate_shift = gs, \
|
||||
.gate_flags = gf, \
|
||||
.child = ch, \
|
||||
+ .max_prate = prate, \
|
||||
}
|
||||
|
||||
-#define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \
|
||||
+#define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch, prate) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.branch_type = branch_fraction_divider, \
|
||||
@@ -645,6 +650,7 @@ struct rockchip_clk_branch {
|
||||
.div_flags = df, \
|
||||
.gate_offset = -1, \
|
||||
.child = ch, \
|
||||
+ .max_prate = prate, \
|
||||
}
|
||||
|
||||
#define COMPOSITE_DDRCLK(_id, cname, pnames, f, mo, ms, mw, \
|
||||
@@ -695,6 +701,21 @@ struct rockchip_clk_branch {
|
||||
.gate_offset = -1, \
|
||||
}
|
||||
|
||||
+#define MUXPMUGRF(_id, cname, pnames, f, o, s, w, mf) \
|
||||
+ { \
|
||||
+ .id = _id, \
|
||||
+ .branch_type = branch_muxpmugrf, \
|
||||
+ .name = cname, \
|
||||
+ .parent_names = pnames, \
|
||||
+ .num_parents = ARRAY_SIZE(pnames), \
|
||||
+ .flags = f, \
|
||||
+ .muxdiv_offset = o, \
|
||||
+ .mux_shift = s, \
|
||||
+ .mux_width = w, \
|
||||
+ .mux_flags = mf, \
|
||||
+ .gate_offset = -1, \
|
||||
+ }
|
||||
+
|
||||
#define DIV(_id, cname, pname, f, o, s, w, df) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
|
||||
index d83b82930..d54624046 100644
|
||||
--- a/include/linux/clk-provider.h
|
||||
+++ b/include/linux/clk-provider.h
|
||||
@@ -989,6 +989,7 @@ struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
|
||||
* @mwidth: width of the numerator bit field
|
||||
* @nshift: shift to the denominator bit field
|
||||
* @nwidth: width of the denominator bit field
|
||||
+ * @max_parent: the maximum frequency of fractional divider parent clock
|
||||
* @lock: register lock
|
||||
*
|
||||
* Clock with adjustable fractional divider affecting its output frequency.
|
||||
@@ -1012,6 +1013,7 @@ struct clk_fractional_divider {
|
||||
u8 nwidth;
|
||||
u32 nmask;
|
||||
u8 flags;
|
||||
+ unsigned long max_prate;
|
||||
void (*approximation)(struct clk_hw *hw,
|
||||
unsigned long rate, unsigned long *parent_rate,
|
||||
unsigned long *m, unsigned long *n);
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,24 @@
|
||||
From 6408e6688b18e5c712c711110d196a4e95f3f870 Mon Sep 17 00:00:00 2001
|
||||
From: Paolo Sabatino <paolo.sabatino@gmail.com>
|
||||
Date: Thu, 9 Sep 2021 16:37:28 +0000
|
||||
Subject: [PATCH 2/4] 01-linux-1000-export-mm_trace_rss_stat
|
||||
|
||||
---
|
||||
mm/memory.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/mm/memory.c b/mm/memory.c
|
||||
index 25fc46e87..7ef0adaa5 100644
|
||||
--- a/mm/memory.c
|
||||
+++ b/mm/memory.c
|
||||
@@ -171,6 +171,7 @@ void mm_trace_rss_stat(struct mm_struct *mm, int member, long count)
|
||||
{
|
||||
trace_rss_stat(mm, member, count);
|
||||
}
|
||||
+EXPORT_SYMBOL(mm_trace_rss_stat);
|
||||
|
||||
#if defined(SPLIT_RSS_COUNTING)
|
||||
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,782 @@
|
||||
From 92a42b2df843c0f6c2937dc6bdbfe72332c9e557 Mon Sep 17 00:00:00 2001
|
||||
From: Paolo Sabatino <paolo.sabatino@gmail.com>
|
||||
Date: Thu, 9 Sep 2021 16:46:33 +0000
|
||||
Subject: [PATCH 3/4] 01-linux-1000-rockchip-wip
|
||||
|
||||
---
|
||||
arch/arm/boot/dts/rk322x.dtsi | 101 +++++++++++++++++-
|
||||
arch/arm/boot/dts/rk3xxx.dtsi | 2 +
|
||||
drivers/clk/rockchip/clk-rk3228.c | 61 ++++-------
|
||||
drivers/net/ethernet/arc/emac.h | 14 +++
|
||||
drivers/net/ethernet/arc/emac_main.c | 81 ++++++++++++--
|
||||
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 38 ++++++-
|
||||
drivers/soc/rockchip/pm_domains.c | 23 ++++
|
||||
drivers/usb/dwc2/core.c | 2 +-
|
||||
8 files changed, 266 insertions(+), 56 deletions(-)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
|
||||
index 75af99c76..c50b2ccd7 100644
|
||||
--- a/arch/arm/boot/dts/rk322x.dtsi
|
||||
+++ b/arch/arm/boot/dts/rk322x.dtsi
|
||||
@@ -15,6 +15,7 @@ / {
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
+ ethernet0 = &gmac;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
@@ -105,6 +106,22 @@ arm-pmu {
|
||||
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
|
||||
};
|
||||
|
||||
+ hdmi_sound: hdmi-sound {
|
||||
+ compatible = "simple-audio-card";
|
||||
+ simple-audio-card,name = "hdmi-sound";
|
||||
+ simple-audio-card,format = "i2s";
|
||||
+ simple-audio-card,mclk-fs = <256>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ simple-audio-card,cpu {
|
||||
+ sound-dai = <&i2s0>;
|
||||
+ };
|
||||
+
|
||||
+ simple-audio-card,codec {
|
||||
+ sound-dai = <&hdmi>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
psci {
|
||||
compatible = "arm,psci-1.0", "arm,psci-0.2";
|
||||
method = "smc";
|
||||
@@ -132,6 +149,17 @@ display_subsystem: display-subsystem {
|
||||
ports = <&vop_out>;
|
||||
};
|
||||
|
||||
+ crypto: cypto-controller@100a0000 {
|
||||
+ compatible = "rockchip,rk3288-crypto";
|
||||
+ reg = <0x100a0000 0x4000>;
|
||||
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru HCLK_M_CRYPTO>, <&cru HCLK_S_CRYPTO>,
|
||||
+ <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC>;
|
||||
+ clock-names = "aclk", "hclk", "sclk", "apb_pclk";
|
||||
+ resets = <&cru SRST_CRYPTO>;
|
||||
+ reset-names = "crypto-rst";
|
||||
+ };
|
||||
+
|
||||
i2s1: i2s1@100b0000 {
|
||||
compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
|
||||
reg = <0x100b0000 0x4000>;
|
||||
@@ -142,6 +170,7 @@ i2s1: i2s1@100b0000 {
|
||||
dma-names = "tx", "rx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s1_bus>;
|
||||
+ #sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -153,6 +182,7 @@ i2s0: i2s0@100c0000 {
|
||||
clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
|
||||
dmas = <&pdma 11>, <&pdma 12>;
|
||||
dma-names = "tx", "rx";
|
||||
+ #sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -166,6 +196,7 @@ spdif: spdif@100d0000 {
|
||||
dma-names = "tx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spdif_tx>;
|
||||
+ #sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -337,7 +368,7 @@ uart2: serial@11030000 {
|
||||
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
pinctrl-names = "default";
|
||||
- pinctrl-0 = <&uart2_xfer>;
|
||||
+ pinctrl-0 = <&uart21_xfer>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
@@ -358,6 +389,10 @@ efuse_id: id@7 {
|
||||
cpu_leakage: cpu_leakage@17 {
|
||||
reg = <0x17 0x1>;
|
||||
};
|
||||
+ hdmi_phy_flag: hdmi-phy-flag@1d {
|
||||
+ reg = <0x1d 0x1>;
|
||||
+ bits = <1 1>;
|
||||
+ };
|
||||
};
|
||||
|
||||
i2c0: i2c@11050000 {
|
||||
@@ -554,6 +589,11 @@ map1 {
|
||||
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
+ map2 {
|
||||
+ trip = <&cpu_alert1>;
|
||||
+ cooling-device =
|
||||
+ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
+ };
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -584,6 +624,8 @@ hdmi_phy: hdmi-phy@12030000 {
|
||||
clock-names = "sysclk", "refoclk", "refpclk";
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "hdmiphy_phy";
|
||||
+ nvmem-cells = <&hdmi_phy_flag>;
|
||||
+ nvmem-cell-names = "hdmi-phy-flag";
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -607,7 +649,27 @@ gpu: gpu@20000000 {
|
||||
clock-names = "bus", "core";
|
||||
power-domains = <&power RK3228_PD_GPU>;
|
||||
resets = <&cru SRST_GPU_A>;
|
||||
- status = "disabled";
|
||||
+ operating-points-v2 = <&gpu_opp_table>;
|
||||
+ #cooling-cells = <2>; /* min followed by max */
|
||||
+ };
|
||||
+
|
||||
+ gpu_opp_table: opp-table2 {
|
||||
+ compatible = "operating-points-v2";
|
||||
+
|
||||
+ opp-200000000 {
|
||||
+ opp-hz = /bits/ 64 <200000000>;
|
||||
+ opp-microvolt = <1050000>;
|
||||
+ };
|
||||
+
|
||||
+ opp-300000000 {
|
||||
+ opp-hz = /bits/ 64 <300000000>;
|
||||
+ opp-microvolt = <1050000>;
|
||||
+ };
|
||||
+
|
||||
+ opp-500000000 {
|
||||
+ opp-hz = /bits/ 64 <500000000>;
|
||||
+ opp-microvolt = <1150000>;
|
||||
+ };
|
||||
};
|
||||
|
||||
vpu: video-codec@20020000 {
|
||||
@@ -727,6 +789,7 @@ hdmi: hdmi@200a0000 {
|
||||
phys = <&hdmi_phy>;
|
||||
phy-names = "hdmi";
|
||||
rockchip,grf = <&grf>;
|
||||
+ #sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
@@ -748,9 +811,13 @@ sdmmc: mmc@30000000 {
|
||||
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
|
||||
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
|
||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
+ bus-width = <4>;
|
||||
fifo-depth = <0x100>;
|
||||
+ max-frequency = <150000000>;
|
||||
pinctrl-names = "default";
|
||||
- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
|
||||
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4 &sdmmc_pwr>;
|
||||
+ resets = <&cru SRST_SDMMC>;
|
||||
+ reset-names = "reset";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -760,10 +827,14 @@ sdio: mmc@30010000 {
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
|
||||
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
|
||||
+ bus-width = <4>;
|
||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
fifo-depth = <0x100>;
|
||||
+ max-frequency = <150000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
|
||||
+ resets = <&cru SRST_SDIO>;
|
||||
+ reset-names = "reset";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -771,14 +842,13 @@ emmc: mmc@30020000 {
|
||||
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
reg = <0x30020000 0x4000>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- clock-frequency = <37500000>;
|
||||
- max-frequency = <37500000>;
|
||||
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
|
||||
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
|
||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
bus-width = <8>;
|
||||
rockchip,default-sample-phase = <158>;
|
||||
fifo-depth = <0x100>;
|
||||
+ max-frequency = <150000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
|
||||
resets = <&cru SRST_EMMC>;
|
||||
@@ -1029,6 +1099,10 @@ sdmmc_bus4: sdmmc-bus4 {
|
||||
<1 RK_PC4 1 &pcfg_pull_none_drv_12ma>,
|
||||
<1 RK_PC5 1 &pcfg_pull_none_drv_12ma>;
|
||||
};
|
||||
+
|
||||
+ sdmmc_pwr: sdmmc-pwr {
|
||||
+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
};
|
||||
|
||||
sdio {
|
||||
@@ -1261,13 +1335,30 @@ uart1_xfer: uart1-xfer {
|
||||
<1 RK_PB2 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
+ uart11_xfer: uart11-xfer {
|
||||
+ rockchip,pins = <3 RK_PB6 1 &pcfg_pull_up>,
|
||||
+ <3 RK_PB5 1 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
uart1_cts: uart1-cts {
|
||||
rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
+ uart11_cts: uart11-cts {
|
||||
+ rockchip,pins = <3 RK_PA7 1 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
uart1_rts: uart1-rts {
|
||||
rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
|
||||
};
|
||||
+
|
||||
+ uart11_rts: uart11-rts {
|
||||
+ rockchip,pins = <3 RK_PA6 1 &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ uart11_rts_gpio: uart11-rts-gpio {
|
||||
+ rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
};
|
||||
|
||||
uart2 {
|
||||
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
|
||||
index 616a828e0..f233b7a77 100644
|
||||
--- a/arch/arm/boot/dts/rk3xxx.dtsi
|
||||
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
|
||||
@@ -64,6 +64,8 @@ L2: cache-controller@10138000 {
|
||||
reg = <0x10138000 0x1000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
+ prefetch-data = <1>;
|
||||
+ prefetch-instr = <1>;
|
||||
};
|
||||
|
||||
scu@1013c000 {
|
||||
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
|
||||
index aca1a483a..7250adc64 100644
|
||||
--- a/drivers/clk/rockchip/clk-rk3228.c
|
||||
+++ b/drivers/clk/rockchip/clk-rk3228.c
|
||||
@@ -135,24 +135,22 @@ static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = {
|
||||
|
||||
PNAME(mux_pll_p) = { "clk_24m", "xin24m" };
|
||||
|
||||
-PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" };
|
||||
+PNAME(mux_ddrphy_p) = { "dpll", "gpll", "apll" };
|
||||
PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" };
|
||||
PNAME(mux_usb480m_phy_p) = { "usb480m_phy0", "usb480m_phy1" };
|
||||
PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" };
|
||||
PNAME(mux_hdmiphy_p) = { "hdmiphy_phy", "xin24m" };
|
||||
-PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" };
|
||||
|
||||
PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy", "usb480m" };
|
||||
PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "hdmiphy" };
|
||||
PNAME(mux_pll_src_2plls_p) = { "cpll", "gpll" };
|
||||
PNAME(mux_sclk_hdmi_cec_p) = { "cpll", "gpll", "xin24m" };
|
||||
-PNAME(mux_aclk_peri_src_p) = { "cpll_peri", "gpll_peri", "hdmiphy_peri" };
|
||||
PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "usb480m" };
|
||||
PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" };
|
||||
|
||||
PNAME(mux_sclk_rga_p) = { "gpll", "cpll", "sclk_rga_src" };
|
||||
|
||||
-PNAME(mux_sclk_vop_src_p) = { "gpll_vop", "cpll_vop" };
|
||||
+PNAME(mux_sclk_vop_src_p) = { "gpll", "cpll" };
|
||||
PNAME(mux_dclk_vop_p) = { "hdmiphy", "sclk_vop_pre" };
|
||||
|
||||
PNAME(mux_i2s0_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
|
||||
@@ -221,27 +219,23 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
||||
RK2928_CLKSEL_CON(4), 8, 5, DFLAGS),
|
||||
|
||||
/* PD_DDR */
|
||||
- GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED,
|
||||
+ COMPOSITE(0, "clk_ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
|
||||
+ RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
|
||||
RK2928_CLKGATE_CON(0), 2, GFLAGS),
|
||||
- GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
|
||||
- RK2928_CLKGATE_CON(0), 2, GFLAGS),
|
||||
- GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
|
||||
- RK2928_CLKGATE_CON(0), 2, GFLAGS),
|
||||
- COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
|
||||
- RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
|
||||
+ GATE(0, "ddrphy4x", "clk_ddrphy_src", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(7), 1, GFLAGS),
|
||||
- GATE(0, "ddrc", "ddrphy_pre", CLK_IGNORE_UNUSED,
|
||||
+ FACTOR_GATE(0, "ddrc", "clk_ddrphy_src", CLK_IGNORE_UNUSED, 1, 4,
|
||||
RK2928_CLKGATE_CON(8), 5, GFLAGS),
|
||||
- FACTOR_GATE(0, "ddrphy", "ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
|
||||
+ FACTOR_GATE(0, "ddrphy", "clk_ddrphy_src", CLK_IGNORE_UNUSED, 1, 4,
|
||||
RK2928_CLKGATE_CON(7), 0, GFLAGS),
|
||||
|
||||
/* PD_CORE */
|
||||
- GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
|
||||
- RK2928_CLKGATE_CON(0), 6, GFLAGS),
|
||||
GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(0), 6, GFLAGS),
|
||||
GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(0), 6, GFLAGS),
|
||||
+ GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
|
||||
+ RK2928_CLKGATE_CON(0), 6, GFLAGS),
|
||||
COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
|
||||
RK2928_CLKGATE_CON(4), 1, GFLAGS),
|
||||
@@ -258,14 +252,9 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
||||
RK2928_MISC_CON, 15, 1, MFLAGS),
|
||||
|
||||
/* PD_BUS */
|
||||
- GATE(0, "hdmiphy_aclk_cpu", "hdmiphy", CLK_IGNORE_UNUSED,
|
||||
+ COMPOSITE(0, "aclk_cpu_src", mux_pll_src_3plls_p, 0,
|
||||
+ RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(0), 1, GFLAGS),
|
||||
- GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,
|
||||
- RK2928_CLKGATE_CON(0), 1, GFLAGS),
|
||||
- GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,
|
||||
- RK2928_CLKGATE_CON(0), 1, GFLAGS),
|
||||
- COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
|
||||
- RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS),
|
||||
GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", 0,
|
||||
RK2928_CLKGATE_CON(6), 0, GFLAGS),
|
||||
COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", 0,
|
||||
@@ -338,14 +327,9 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
||||
RK2928_CLKGATE_CON(3), 8, GFLAGS),
|
||||
|
||||
/* PD_PERI */
|
||||
- GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED,
|
||||
- RK2928_CLKGATE_CON(2), 0, GFLAGS),
|
||||
- GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED,
|
||||
+ COMPOSITE(0, "aclk_peri_src", mux_pll_src_3plls_p, 0,
|
||||
+ RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 0, GFLAGS),
|
||||
- GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED,
|
||||
- RK2928_CLKGATE_CON(2), 0, GFLAGS),
|
||||
- COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0,
|
||||
- RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS),
|
||||
COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
|
||||
RK2928_CLKSEL_CON(10), 12, 3, DFLAGS,
|
||||
RK2928_CLKGATE_CON(5), 2, GFLAGS),
|
||||
@@ -380,7 +364,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
||||
RK2928_CLKGATE_CON(10), 12, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0,
|
||||
- RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS,
|
||||
+ RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK2928_CLKGATE_CON(2), 15, GFLAGS),
|
||||
|
||||
COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
|
||||
@@ -403,12 +387,9 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
||||
* Clock-Architecture Diagram 2
|
||||
*/
|
||||
|
||||
- GATE(0, "gpll_vop", "gpll", 0,
|
||||
- RK2928_CLKGATE_CON(3), 1, GFLAGS),
|
||||
- GATE(0, "cpll_vop", "cpll", 0,
|
||||
+ COMPOSITE_NODIV(0, "sclk_vop_src", mux_sclk_vop_src_p, 0,
|
||||
+ RK2928_CLKSEL_CON(27), 0, 1, MFLAGS,
|
||||
RK2928_CLKGATE_CON(3), 1, GFLAGS),
|
||||
- MUX(0, "sclk_vop_src", mux_sclk_vop_src_p, 0,
|
||||
- RK2928_CLKSEL_CON(27), 0, 1, MFLAGS),
|
||||
DIV(DCLK_HDMI_PHY, "dclk_hdmiphy", "sclk_vop_src", 0,
|
||||
RK2928_CLKSEL_CON(29), 0, 3, DFLAGS),
|
||||
DIV(0, "sclk_vop_pre", "sclk_vop_src", 0,
|
||||
@@ -640,13 +621,13 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
||||
|
||||
/* PD_MMC */
|
||||
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3228_SDMMC_CON0, 1),
|
||||
- MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 0),
|
||||
+ MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 1),
|
||||
|
||||
MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3228_SDIO_CON0, 1),
|
||||
- MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 0),
|
||||
+ MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 1),
|
||||
|
||||
MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3228_EMMC_CON0, 1),
|
||||
- MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 0),
|
||||
+ MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 1),
|
||||
};
|
||||
|
||||
static const char *const rk3228_critical_clocks[] __initconst = {
|
||||
@@ -661,6 +642,7 @@ static const char *const rk3228_critical_clocks[] __initconst = {
|
||||
"aclk_vop_noc",
|
||||
"aclk_hdcp_noc",
|
||||
"hclk_vio_ahb_arbi",
|
||||
+ "hclk_vio_h2p",
|
||||
"hclk_vio_noc",
|
||||
"hclk_vop_noc",
|
||||
"hclk_host0_arb",
|
||||
@@ -678,10 +660,13 @@ static const char *const rk3228_critical_clocks[] __initconst = {
|
||||
"pclk_ddrphy",
|
||||
"pclk_acodecphy",
|
||||
"pclk_phy_noc",
|
||||
+ "pclk_vio_h2p",
|
||||
"aclk_vpu_noc",
|
||||
"aclk_rkvdec_noc",
|
||||
+ "aclk_rkvdec",
|
||||
"hclk_vpu_noc",
|
||||
"hclk_rkvdec_noc",
|
||||
+ "hclk_rkvdec",
|
||||
};
|
||||
|
||||
static void __init rk3228_clk_init(struct device_node *np)
|
||||
diff --git a/drivers/net/ethernet/arc/emac.h b/drivers/net/ethernet/arc/emac.h
|
||||
index d820ae03a..0ac87288b 100644
|
||||
--- a/drivers/net/ethernet/arc/emac.h
|
||||
+++ b/drivers/net/ethernet/arc/emac.h
|
||||
@@ -91,6 +91,20 @@ struct arc_emac_bd {
|
||||
#define RX_RING_SZ (RX_BD_NUM * sizeof(struct arc_emac_bd))
|
||||
#define TX_RING_SZ (TX_BD_NUM * sizeof(struct arc_emac_bd))
|
||||
|
||||
+/* PHY fixups */
|
||||
+#define RTL_8201F_PHY_ID 0x001cc816
|
||||
+
|
||||
+#define RTL_8201F_PG_SELECT_REG 0x1f
|
||||
+#define RTL_8201F_PG4_EEE_REG 0x10
|
||||
+#define RTL_8201F_PG4_EEE_RX_QUIET_EN BIT(8)
|
||||
+#define RTL_8201F_PG4_EEE_TX_QUIET_EN BIT(9)
|
||||
+#define RTL_8201F_PG4_EEE_NWAY_EN BIT(12)
|
||||
+#define RTL_8201F_PG4_EEE_10M_CAP BIT(13)
|
||||
+#define RTL_8201F_PG7_RMSR_REG 0x10
|
||||
+#define RTL_8201F_PG7_RMSR_CLK_DIR_IN BIT(12)
|
||||
+#define RTL_8201F_PG0_PSMR_REG 0x18
|
||||
+#define RTL_8201F_PG0_PSMR_PWRSVE_EN BIT(15)
|
||||
+
|
||||
/**
|
||||
* struct buffer_state - Stores Rx/Tx buffer state.
|
||||
* @sk_buff: Pointer to socket buffer.
|
||||
diff --git a/drivers/net/ethernet/arc/emac_main.c b/drivers/net/ethernet/arc/emac_main.c
|
||||
index 67b8113a2..40332a976 100644
|
||||
--- a/drivers/net/ethernet/arc/emac_main.c
|
||||
+++ b/drivers/net/ethernet/arc/emac_main.c
|
||||
@@ -140,7 +140,7 @@ static void arc_emac_tx_clean(struct net_device *ndev)
|
||||
stats->tx_bytes += skb->len;
|
||||
}
|
||||
|
||||
- dma_unmap_single(&ndev->dev, dma_unmap_addr(tx_buff, addr),
|
||||
+ dma_unmap_single(ndev->dev.parent, dma_unmap_addr(tx_buff, addr),
|
||||
dma_unmap_len(tx_buff, len), DMA_TO_DEVICE);
|
||||
|
||||
/* return the sk_buff to system */
|
||||
@@ -223,9 +223,9 @@ static int arc_emac_rx(struct net_device *ndev, int budget)
|
||||
continue;
|
||||
}
|
||||
|
||||
- addr = dma_map_single(&ndev->dev, (void *)skb->data,
|
||||
+ addr = dma_map_single(ndev->dev.parent, (void *)skb->data,
|
||||
EMAC_BUFFER_SIZE, DMA_FROM_DEVICE);
|
||||
- if (dma_mapping_error(&ndev->dev, addr)) {
|
||||
+ if (dma_mapping_error(ndev->dev.parent, addr)) {
|
||||
if (net_ratelimit())
|
||||
netdev_err(ndev, "cannot map dma buffer\n");
|
||||
dev_kfree_skb(skb);
|
||||
@@ -237,7 +237,7 @@ static int arc_emac_rx(struct net_device *ndev, int budget)
|
||||
}
|
||||
|
||||
/* unmap previosly mapped skb */
|
||||
- dma_unmap_single(&ndev->dev, dma_unmap_addr(rx_buff, addr),
|
||||
+ dma_unmap_single(ndev->dev.parent, dma_unmap_addr(rx_buff, addr),
|
||||
dma_unmap_len(rx_buff, len), DMA_FROM_DEVICE);
|
||||
|
||||
pktlen = info & LEN_MASK;
|
||||
@@ -445,9 +445,9 @@ static int arc_emac_open(struct net_device *ndev)
|
||||
if (unlikely(!rx_buff->skb))
|
||||
return -ENOMEM;
|
||||
|
||||
- addr = dma_map_single(&ndev->dev, (void *)rx_buff->skb->data,
|
||||
+ addr = dma_map_single(ndev->dev.parent, (void *)rx_buff->skb->data,
|
||||
EMAC_BUFFER_SIZE, DMA_FROM_DEVICE);
|
||||
- if (dma_mapping_error(&ndev->dev, addr)) {
|
||||
+ if (dma_mapping_error(ndev->dev.parent, addr)) {
|
||||
netdev_err(ndev, "cannot dma map\n");
|
||||
dev_kfree_skb(rx_buff->skb);
|
||||
return -ENOMEM;
|
||||
@@ -555,7 +555,7 @@ static void arc_free_tx_queue(struct net_device *ndev)
|
||||
struct buffer_state *tx_buff = &priv->tx_buff[i];
|
||||
|
||||
if (tx_buff->skb) {
|
||||
- dma_unmap_single(&ndev->dev,
|
||||
+ dma_unmap_single(ndev->dev.parent,
|
||||
dma_unmap_addr(tx_buff, addr),
|
||||
dma_unmap_len(tx_buff, len),
|
||||
DMA_TO_DEVICE);
|
||||
@@ -586,7 +586,7 @@ static void arc_free_rx_queue(struct net_device *ndev)
|
||||
struct buffer_state *rx_buff = &priv->rx_buff[i];
|
||||
|
||||
if (rx_buff->skb) {
|
||||
- dma_unmap_single(&ndev->dev,
|
||||
+ dma_unmap_single(ndev->dev.parent,
|
||||
dma_unmap_addr(rx_buff, addr),
|
||||
dma_unmap_len(rx_buff, len),
|
||||
DMA_FROM_DEVICE);
|
||||
@@ -692,10 +692,10 @@ static netdev_tx_t arc_emac_tx(struct sk_buff *skb, struct net_device *ndev)
|
||||
return NETDEV_TX_BUSY;
|
||||
}
|
||||
|
||||
- addr = dma_map_single(&ndev->dev, (void *)skb->data, len,
|
||||
+ addr = dma_map_single(ndev->dev.parent, (void *)skb->data, len,
|
||||
DMA_TO_DEVICE);
|
||||
|
||||
- if (unlikely(dma_mapping_error(&ndev->dev, addr))) {
|
||||
+ if (unlikely(dma_mapping_error(ndev->dev.parent, addr))) {
|
||||
stats->tx_dropped++;
|
||||
stats->tx_errors++;
|
||||
dev_kfree_skb_any(skb);
|
||||
@@ -850,6 +850,62 @@ static const struct net_device_ops arc_emac_netdev_ops = {
|
||||
#endif
|
||||
};
|
||||
|
||||
+/**
|
||||
+ * arc_emac_rtl8201f_phy_fixup
|
||||
+ * @phydev: Pointer to phy_device structure.
|
||||
+ *
|
||||
+ * This function registers a fixup in case RTL8201F's phy
|
||||
+ * clockout is used as reference for the mac interface
|
||||
+ * and disable EEE, since emac can't handle it
|
||||
+ */
|
||||
+static int arc_emac_rtl8201f_phy_fixup(struct phy_device *phydev)
|
||||
+{
|
||||
+ unsigned int reg, curr_pg;
|
||||
+ int err = 0;
|
||||
+
|
||||
+ curr_pg = phy_read(phydev, RTL_8201F_PG_SELECT_REG);
|
||||
+ err = phy_write(phydev, RTL_8201F_PG_SELECT_REG, 4);
|
||||
+ if (err)
|
||||
+ goto out_err;
|
||||
+ mdelay(10);
|
||||
+
|
||||
+ /* disable EEE */
|
||||
+ reg = phy_read(phydev, RTL_8201F_PG4_EEE_REG);
|
||||
+ reg &= ~RTL_8201F_PG4_EEE_RX_QUIET_EN &
|
||||
+ ~RTL_8201F_PG4_EEE_TX_QUIET_EN &
|
||||
+ ~RTL_8201F_PG4_EEE_NWAY_EN &
|
||||
+ ~RTL_8201F_PG4_EEE_10M_CAP;
|
||||
+ err = phy_write(phydev, RTL_8201F_PG4_EEE_REG, reg);
|
||||
+ if (err)
|
||||
+ goto out_err;
|
||||
+
|
||||
+ if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
|
||||
+ err = phy_write(phydev, RTL_8201F_PG_SELECT_REG, 7);
|
||||
+ if (err)
|
||||
+ goto out_err;
|
||||
+ mdelay(10);
|
||||
+
|
||||
+ reg = phy_read(phydev, RTL_8201F_PG7_RMSR_REG);
|
||||
+ err = phy_write(phydev, RTL_8201F_PG_SELECT_REG, 0);
|
||||
+ if (err)
|
||||
+ goto out_err;
|
||||
+ mdelay(10);
|
||||
+
|
||||
+ if (!(reg & RTL_8201F_PG7_RMSR_CLK_DIR_IN)) {
|
||||
+ /* disable powersave if phy's clock output is used */
|
||||
+ reg = phy_read(phydev, RTL_8201F_PG0_PSMR_REG);
|
||||
+ reg &= ~RTL_8201F_PG0_PSMR_PWRSVE_EN & 0xffff;
|
||||
+ err = phy_write(phydev, RTL_8201F_PG0_PSMR_REG, reg);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+out_err:
|
||||
+ phy_write(phydev, RTL_8201F_PG_SELECT_REG, curr_pg);
|
||||
+ mdelay(10);
|
||||
+
|
||||
+ return err;
|
||||
+};
|
||||
+
|
||||
int arc_emac_probe(struct net_device *ndev, int interface)
|
||||
{
|
||||
struct device *dev = ndev->dev.parent;
|
||||
@@ -970,6 +1026,11 @@ int arc_emac_probe(struct net_device *ndev, int interface)
|
||||
goto out_clken;
|
||||
}
|
||||
|
||||
+ err = phy_register_fixup_for_uid(RTL_8201F_PHY_ID, 0xfffff0,
|
||||
+ arc_emac_rtl8201f_phy_fixup);
|
||||
+ if (err)
|
||||
+ dev_warn(dev, "Cannot register PHY board fixup.\n");
|
||||
+
|
||||
phydev = of_phy_connect(ndev, phy_node, arc_emac_adjust_link, 0,
|
||||
interface);
|
||||
if (!phydev) {
|
||||
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
index 1889e78e1..6209f51b3 100644
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
@@ -237,6 +237,9 @@ struct inno_hdmi_phy {
|
||||
struct clk *refoclk;
|
||||
struct clk *refpclk;
|
||||
|
||||
+ /* phy_flag flag */
|
||||
+ bool phy_flag;
|
||||
+
|
||||
/* platform data */
|
||||
const struct inno_hdmi_phy_drv_data *plat_data;
|
||||
int chip_version;
|
||||
@@ -471,6 +474,7 @@ static const struct pre_pll_config pre_pll_cfg_table[] = {
|
||||
static const struct post_pll_config post_pll_cfg_table[] = {
|
||||
{33750000, 1, 40, 8, 1},
|
||||
{33750000, 1, 80, 8, 2},
|
||||
+ {33750000, 1, 10, 2, 4},
|
||||
{74250000, 1, 40, 8, 1},
|
||||
{74250000, 18, 80, 8, 2},
|
||||
{148500000, 2, 40, 4, 3},
|
||||
@@ -621,8 +625,11 @@ static int inno_hdmi_phy_power_on(struct phy *phy)
|
||||
return -EINVAL;
|
||||
|
||||
for (; cfg->tmdsclock != 0; cfg++)
|
||||
- if (tmdsclock <= cfg->tmdsclock &&
|
||||
- cfg->version & inno->chip_version)
|
||||
+ if (((!inno->phy_flag || tmdsclock > 33750000)
|
||||
+ && tmdsclock <= cfg->tmdsclock
|
||||
+ && cfg->version & inno->chip_version) ||
|
||||
+ (inno->phy_flag && tmdsclock <= 33750000
|
||||
+ && cfg->version & 4))
|
||||
break;
|
||||
|
||||
for (; phy_cfg->tmdsclock != 0; phy_cfg++)
|
||||
@@ -1033,6 +1040,10 @@ static int inno_hdmi_phy_clk_register(struct inno_hdmi_phy *inno)
|
||||
|
||||
static int inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno)
|
||||
{
|
||||
+ struct nvmem_cell *cell;
|
||||
+ unsigned char *efuse_buf;
|
||||
+ size_t len;
|
||||
+
|
||||
/*
|
||||
* Use phy internal register control
|
||||
* rxsense/poweron/pllpd/pdataen signal.
|
||||
@@ -1047,7 +1058,28 @@ static int inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno)
|
||||
inno_update_bits(inno, 0xaa, RK3228_POST_PLL_CTRL_MANUAL,
|
||||
RK3228_POST_PLL_CTRL_MANUAL);
|
||||
|
||||
+
|
||||
inno->chip_version = 1;
|
||||
+ inno->phy_flag = false;
|
||||
+
|
||||
+ cell = nvmem_cell_get(inno->dev, "hdmi-phy-flag");
|
||||
+ if (IS_ERR(cell)) {
|
||||
+ if (PTR_ERR(cell) == -EPROBE_DEFER)
|
||||
+ return -EPROBE_DEFER;
|
||||
+
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
+ efuse_buf = nvmem_cell_read(cell, &len);
|
||||
+ nvmem_cell_put(cell);
|
||||
+
|
||||
+ if (IS_ERR(efuse_buf))
|
||||
+ return 0;
|
||||
+ if (len == 1)
|
||||
+ inno->phy_flag = (efuse_buf[0] & BIT(1)) ? true : false;
|
||||
+ kfree(efuse_buf);
|
||||
+
|
||||
+ dev_info(inno->dev, "phy_flag is: %d\n", inno->phy_flag);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -1147,6 +1179,8 @@ static int inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy *inno)
|
||||
|
||||
/* try to read the chip-version */
|
||||
inno->chip_version = 1;
|
||||
+ inno->phy_flag = false;
|
||||
+
|
||||
cell = nvmem_cell_get(inno->dev, "cpu-version");
|
||||
if (IS_ERR(cell)) {
|
||||
if (PTR_ERR(cell) == -EPROBE_DEFER)
|
||||
diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c
|
||||
index fddb4022c..9583c76b4 100644
|
||||
--- a/drivers/soc/rockchip/pm_domains.c
|
||||
+++ b/drivers/soc/rockchip/pm_domains.c
|
||||
@@ -73,6 +73,7 @@ struct rockchip_pm_domain {
|
||||
struct regmap **qos_regmap;
|
||||
u32 *qos_save_regs[MAX_QOS_REGS_NUM];
|
||||
int num_clks;
|
||||
+ bool is_ignore_pwr;
|
||||
struct clk_bulk_data *clks;
|
||||
};
|
||||
|
||||
@@ -361,6 +362,9 @@ static int rockchip_pd_power_on(struct generic_pm_domain *domain)
|
||||
{
|
||||
struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
|
||||
|
||||
+ if (pd->is_ignore_pwr)
|
||||
+ return 0;
|
||||
+
|
||||
return rockchip_pd_power(pd, true);
|
||||
}
|
||||
|
||||
@@ -368,6 +372,9 @@ static int rockchip_pd_power_off(struct generic_pm_domain *domain)
|
||||
{
|
||||
struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
|
||||
|
||||
+ if (pd->is_ignore_pwr)
|
||||
+ return 0;
|
||||
+
|
||||
return rockchip_pd_power(pd, false);
|
||||
}
|
||||
|
||||
@@ -447,6 +454,9 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
|
||||
pd->info = pd_info;
|
||||
pd->pmu = pmu;
|
||||
|
||||
+ if (!pd_info->pwr_mask)
|
||||
+ pd->is_ignore_pwr = true;
|
||||
+
|
||||
pd->num_clks = of_clk_get_parent_count(node);
|
||||
if (pd->num_clks > 0) {
|
||||
pd->clks = devm_kcalloc(pmu->dev, pd->num_clks,
|
||||
@@ -600,6 +610,7 @@ static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
|
||||
{
|
||||
struct device_node *np;
|
||||
struct generic_pm_domain *child_domain, *parent_domain;
|
||||
+ struct rockchip_pm_domain *child_pd, *parent_pd;
|
||||
int error;
|
||||
|
||||
for_each_child_of_node(parent, np) {
|
||||
@@ -640,6 +651,18 @@ static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
|
||||
parent_domain->name, child_domain->name);
|
||||
}
|
||||
|
||||
+ /*
|
||||
+ * If child_pd doesn't do idle request or power on/off,
|
||||
+ * parent_pd may fail to do power on/off, so if parent_pd
|
||||
+ * need to power on/off, child_pd can't ignore to do idle
|
||||
+ * request and power on/off.
|
||||
+ */
|
||||
+ child_pd = to_rockchip_pd(child_domain);
|
||||
+ parent_pd = to_rockchip_pd(parent_domain);
|
||||
+ if (!parent_pd->is_ignore_pwr)
|
||||
+ child_pd->is_ignore_pwr = false;
|
||||
+
|
||||
+
|
||||
rockchip_pm_add_subdomain(pmu, np);
|
||||
}
|
||||
|
||||
diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
|
||||
index 272ae5722..cec178404 100644
|
||||
--- a/drivers/usb/dwc2/core.c
|
||||
+++ b/drivers/usb/dwc2/core.c
|
||||
@@ -607,7 +607,7 @@ void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
|
||||
* platforms on their host-only dwc2.
|
||||
*/
|
||||
if (!dwc2_hw_is_otg(hsotg))
|
||||
- msleep(50);
|
||||
+ msleep(200);
|
||||
|
||||
break;
|
||||
case USB_DR_MODE_PERIPHERAL:
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,291 @@
|
||||
diff --git a/arch/arm/boot/dts/rk322x-box.dtsi b/arch/arm/boot/dts/rk322x-box.dtsi
|
||||
new file mode 100644
|
||||
index 000000000..ef5fa28d8
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/rk322x-box.dtsi
|
||||
@@ -0,0 +1,282 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include <dt-bindings/clock/rk3228-cru.h>
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include <dt-bindings/input/input.h>
|
||||
+#include <dt-bindings/pinctrl/rockchip.h>
|
||||
+#include "rk322x.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Rockchip RK322x Box";
|
||||
+ compatible = "rockchip,rk3229";
|
||||
+
|
||||
+ chosen {
|
||||
+ bootargs = "earlyprintk=uart8250,mmio32,0x11030000";
|
||||
+ };
|
||||
+
|
||||
+ gpio_keys {
|
||||
+ compatible = "gpio-keys";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ autorepeat;
|
||||
+
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pwr_key>;
|
||||
+
|
||||
+ power_key: power-key {
|
||||
+ label = "GPIO Key Power";
|
||||
+ gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>;
|
||||
+ linux,code = <KEY_POWER>;
|
||||
+ debounce-interval = <100>;
|
||||
+ wakeup-source;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ ir_receiver: ir-receiver {
|
||||
+ compatible = "gpio-ir-receiver";
|
||||
+ gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_LOW>;
|
||||
+ pinctrl-0 = <&ir_int>;
|
||||
+ pinctrl-names = "default";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ memory@60000000 {
|
||||
+ device_type = "memory";
|
||||
+ reg = <0x60000000 0x40000000>;
|
||||
+ };
|
||||
+
|
||||
+ sdio_pwrseq: sdio-pwrseq {
|
||||
+ compatible = "mmc-pwrseq-simple";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&wifi_enable_h>;
|
||||
+ reset-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+
|
||||
+ timer {
|
||||
+ /delete-property/ arm,cpu-registers-not-fw-configured;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cpu_alert1 {
|
||||
+ temperature = <105000>;
|
||||
+};
|
||||
+
|
||||
+&cpu_crit {
|
||||
+ temperature = <115000>;
|
||||
+};
|
||||
+
|
||||
+&cpu_thermal {
|
||||
+ cooling-maps {
|
||||
+ /delete-node/ map0;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cru {
|
||||
+ assigned-clocks = <&cru PLL_GPLL>, <&cru ARMCLK>,
|
||||
+ <&cru PLL_CPLL>, <&cru ACLK_PERI>,
|
||||
+ <&cru HCLK_PERI>, <&cru PCLK_PERI>,
|
||||
+ <&cru ACLK_CPU>, <&cru HCLK_CPU>,
|
||||
+ <&cru PCLK_CPU>, <&cru ACLK_VOP>;
|
||||
+
|
||||
+ assigned-clock-rates = <1200000000>, <816000000>,
|
||||
+ <500000000>, <150000000>,
|
||||
+ <150000000>, <75000000>,
|
||||
+ <150000000>, <150000000>,
|
||||
+ <75000000>, <400000000>;
|
||||
+};
|
||||
+
|
||||
+&emmc {
|
||||
+ cap-mmc-highspeed;
|
||||
+ keep-power-in-suspend;
|
||||
+ non-removable;
|
||||
+};
|
||||
+
|
||||
+&gmac {
|
||||
+ assigned-clocks = <&cru SCLK_MAC_SRC>;
|
||||
+ assigned-clock-rates = <50000000>;
|
||||
+ clock_in_out = "output";
|
||||
+ phy-handle = <&phy>;
|
||||
+ phy-mode = "rmii";
|
||||
+ status = "okay";
|
||||
+
|
||||
+ mdio {
|
||||
+ compatible = "snps,dwmac-mdio";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ phy: phy@0 {
|
||||
+ compatible = "ethernet-phy-id1234.d400",
|
||||
+ "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <0>;
|
||||
+ clocks = <&cru SCLK_MAC_PHY>;
|
||||
+ phy-is-integrated;
|
||||
+ resets = <&cru SRST_MACPHY>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&gpu {
|
||||
+ assigned-clocks = <&cru ACLK_GPU>;
|
||||
+ assigned-clock-rates = <300000000>;
|
||||
+};
|
||||
+
|
||||
+&hdmi {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&hdmi_sound {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&hdmi_phy {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2s0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+
|
||||
+ ir {
|
||||
+ ir_int: ir-int {
|
||||
+ rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ keys {
|
||||
+ pwr_key: pwr-key {
|
||||
+ rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pwm1 {
|
||||
+ pwm1_pin_pull_down: pwm1-pin-pull-down {
|
||||
+ rockchip,pins = <0 RK_PD6 2 &pcfg_pull_down>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pwm2 {
|
||||
+ pwm2_pin_pull_up: pwm2-pin-pull-up {
|
||||
+ rockchip,pins = <1 RK_PB4 2 &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ sdio-pwrseq {
|
||||
+ wifi_enable_h: wifi-enable-h {
|
||||
+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb {
|
||||
+ host_vbus_drv: host-vbus-drv {
|
||||
+ rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ otg_vbus_drv: otg-vbus-drv {
|
||||
+ rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+};
|
||||
+
|
||||
+&sdio {
|
||||
+ mmc-pwrseq = <&sdio_pwrseq>;
|
||||
+ cap-sd-highspeed;
|
||||
+ cap-sdio-irq;
|
||||
+ keep-power-in-suspend;
|
||||
+ non-removable;
|
||||
+ no-sd;
|
||||
+};
|
||||
+
|
||||
+&sdmmc {
|
||||
+ cap-sd-highspeed;
|
||||
+ keep-power-in-suspend;
|
||||
+ no-sdio;
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ rockchip,grf = <&grf>;
|
||||
+ rockchip,hw-tshut-mode = <0>;
|
||||
+ rockchip,hw-tshut-polarity = <1>;
|
||||
+ rockchip,hw-tshut-temp = <120000>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy0_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy0_host {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy1_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy1_host {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart1 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&uart11_xfer &uart11_rts &uart11_cts>;
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host2_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host2_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vop {
|
||||
+ assigned-clocks = <&cru DCLK_VOP>;
|
||||
+ assigned-clock-parents = <&cru SCLK_HDMI_PHY>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vop_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&wdt {
|
||||
+ status = "okay";
|
||||
+};
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,14 @@
|
||||
diff --git a/arch/arm/boot/dts/rk322x-box.dtsi b/arch/arm/boot/dts/rk322x-box.dtsi
|
||||
index 6da7f7666..f9a8dcc2a 100644
|
||||
--- a/arch/arm/boot/dts/rk322x-box.dtsi
|
||||
+++ b/arch/arm/boot/dts/rk322x-box.dtsi
|
||||
@@ -66,9 +66,6 @@
|
||||
reset-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
- timer {
|
||||
- /delete-property/ arm,cpu-registers-not-fw-configured;
|
||||
- };
|
||||
};
|
||||
|
||||
&cpu_alert1 {
|
||||
@ -0,0 +1,12 @@
|
||||
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
|
||||
index 08011dc8c..4bee5c4cd 100644
|
||||
--- a/arch/arm/boot/dts/Makefile
|
||||
+++ b/arch/arm/boot/dts/Makefile
|
||||
@@ -923,6 +923,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
|
||||
rk3228-evb.dtb \
|
||||
rk3229-evb.dtb \
|
||||
rk3229-xms6.dtb \
|
||||
+ rk322x-box.dtb \
|
||||
rk3288-evb-act8846.dtb \
|
||||
rk3288-evb-rk808.dtb \
|
||||
rk3288-firefly-beta.dtb \
|
||||
@ -0,0 +1,15 @@
|
||||
diff --git a/arch/arm/boot/dts/rk322x-box.dtsi b/arch/arm/boot/dts/rk322x-box.dtsi
|
||||
index 44fb2f4ea..15d07a736 100644
|
||||
--- a/arch/arm/boot/dts/rk322x-box.dtsi
|
||||
+++ b/arch/arm/boot/dts/rk322x-box.dtsi
|
||||
@@ -89,6 +89,10 @@
|
||||
cap-mmc-highspeed;
|
||||
keep-power-in-suspend;
|
||||
non-removable;
|
||||
+ /delete-property/ pinctrl-names;
|
||||
+ /delete-property/ pinctrl-0;
|
||||
+ /delete-property/ default-sample-phase;
|
||||
+ rockchip,default-sample-phase = <180>;
|
||||
};
|
||||
|
||||
&gmac {
|
||||
@ -0,0 +1,93 @@
|
||||
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
|
||||
index 48e6e8d44..1dfd27f9f 100644
|
||||
--- a/arch/arm/boot/dts/rk322x.dtsi
|
||||
+++ b/arch/arm/boot/dts/rk322x.dtsi
|
||||
@@ -712,6 +712,22 @@ emmc: mmc@30020000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ nfc: nand-controller@30030000 {
|
||||
+ compatible = "rockchip,rk3228-nfc", "rockchip,rk2928-nfc";
|
||||
+ reg = <0x30030000 0x4000>;
|
||||
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>;
|
||||
+ clock-names = "nfc", "ahb";
|
||||
+ assigned-clocks = <&cru SCLK_NANDC>;
|
||||
+ assigned-clock-rates = <150000000>;
|
||||
+
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&flash_cs0 &flash_rdy &flash_ale &flash_cle
|
||||
+ &flash_wrn &flash_rdn &flash_bus8>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ };
|
||||
+
|
||||
usb_otg: usb@30040000 {
|
||||
compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
|
||||
"snps,dwc2";
|
||||
@@ -950,6 +966,65 @@ emmc_bus8: emmc-bus8 {
|
||||
};
|
||||
};
|
||||
|
||||
+ flash {
|
||||
+
|
||||
+ flash_cs0: flash-cs0 {
|
||||
+ rockchip,pins = <2 RK_PA6 1 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ flash_cs1: flash-cs1 {
|
||||
+ rockchip,pins = <0 RK_PC7 1 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ flash_cs2: flash-cs2 {
|
||||
+ rockchip,pins = <1 RK_PC6 1 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ flash_cs3: flash-cs3 {
|
||||
+ rockchip,pins = <1 RK_PC7 1 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ flash_rdy: flash-rdy {
|
||||
+ rockchip,pins = <2 RK_PA4 1 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ flash_ale: flash-ale {
|
||||
+ rockchip,pins = <2 RK_PA0 1 &pcfg_pull_down>;
|
||||
+ };
|
||||
+
|
||||
+ flash_cle: flash-cle {
|
||||
+ rockchip,pins = <2 RK_PA1 1 &pcfg_pull_down>;
|
||||
+ };
|
||||
+
|
||||
+ flash_wrn: flash-wrn {
|
||||
+ rockchip,pins = <2 RK_PA2 1 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ flash_rdn: flash-rdn {
|
||||
+ rockchip,pins = <2 RK_PA3 1 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ flash_bus8: flash-bus8 {
|
||||
+ rockchip,pins = <1 RK_PD0 1 &pcfg_pull_up>,
|
||||
+ <1 RK_PD1 1 &pcfg_pull_up>,
|
||||
+ <1 RK_PD2 1 &pcfg_pull_up>,
|
||||
+ <1 RK_PD3 1 &pcfg_pull_up>,
|
||||
+ <1 RK_PD4 1 &pcfg_pull_up>,
|
||||
+ <1 RK_PD5 1 &pcfg_pull_up>,
|
||||
+ <1 RK_PD6 1 &pcfg_pull_up>,
|
||||
+ <1 RK_PD7 1 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ flash_dqs: flash-dqs {
|
||||
+ rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ flash_wp: flash-wp {
|
||||
+ rockchip,pins = <2 RK_PA5 1 &pcfg_pull_down>;
|
||||
+ };
|
||||
+
|
||||
+ };
|
||||
+
|
||||
gmac {
|
||||
rgmii_pins: rgmii-pins {
|
||||
rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
|
||||
@ -0,0 +1,66 @@
|
||||
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
|
||||
index 73d24c6bbf05..d4ac6e161ef2 100644
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
|
||||
@@ -614,6 +614,44 @@ static const struct vop_common rk3288_common = {
|
||||
.dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0),
|
||||
};
|
||||
|
||||
+static const struct vop_win_phy rk3228_win0_data = {
|
||||
+ .scl = &rk3288_win_full_scl,
|
||||
+ .data_formats = formats_win_full,
|
||||
+ .nformats = ARRAY_SIZE(formats_win_full),
|
||||
+ .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
|
||||
+ .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
|
||||
+ .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
|
||||
+ .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
|
||||
+ .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
|
||||
+ .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
|
||||
+ .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
|
||||
+ .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
|
||||
+ .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
|
||||
+ .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
|
||||
+ .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
|
||||
+ .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
|
||||
+ .channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
|
||||
+};
|
||||
+
|
||||
+static const struct vop_win_phy rk3228_win1_data = {
|
||||
+ .scl = &rk3288_win_full_scl,
|
||||
+ .data_formats = formats_win_lite,
|
||||
+ .nformats = ARRAY_SIZE(formats_win_lite),
|
||||
+ .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
|
||||
+ .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
|
||||
+ .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
|
||||
+ .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
|
||||
+ .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
|
||||
+ .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
|
||||
+ .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
|
||||
+ .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
|
||||
+ .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
|
||||
+ .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
|
||||
+ .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
|
||||
+ .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
|
||||
+ .channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
|
||||
+};
|
||||
+
|
||||
/*
|
||||
* Note: rk3288 has a dedicated 'cursor' window, however, that window requires
|
||||
* special support to get alpha blending working. For now, just use overlay
|
||||
@@ -864,10 +902,10 @@ static const struct vop_data rk3399_vop_lit = {
|
||||
};
|
||||
|
||||
static const struct vop_win_data rk3228_vop_win_data[] = {
|
||||
- { .base = 0x00, .phy = &rk3288_win01_data,
|
||||
+ { .base = 0x00, .phy = &rk3228_win0_data,
|
||||
.type = DRM_PLANE_TYPE_PRIMARY },
|
||||
- { .base = 0x40, .phy = &rk3288_win01_data,
|
||||
- .type = DRM_PLANE_TYPE_CURSOR },
|
||||
+ { .base = 0x40, .phy = &rk3228_win1_data,
|
||||
+ .type = DRM_PLANE_TYPE_OVERLAY },
|
||||
};
|
||||
|
||||
static const struct vop_data rk3228_vop = {
|
||||
--
|
||||
2.17.1
|
||||
|
||||
@ -0,0 +1,34 @@
|
||||
From adecdd57a0155e0d96af2c84cc4fa52309fbb535 Mon Sep 17 00:00:00 2001
|
||||
From: Paolo Sabatino <paolo.sabatino@gmail.com>
|
||||
Date: Thu, 9 Sep 2021 19:14:08 +0000
|
||||
Subject: [PATCH] add iep node for rk322x
|
||||
|
||||
---
|
||||
arch/arm/boot/dts/rk322x.dtsi | 11 +++++++++++
|
||||
1 file changed, 11 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
|
||||
index 0ae753c1d..271e7835f 100644
|
||||
--- a/arch/arm/boot/dts/rk322x.dtsi
|
||||
+++ b/arch/arm/boot/dts/rk322x.dtsi
|
||||
@@ -834,6 +834,17 @@ rga: rga@20060000 {
|
||||
reset-names = "core", "axi", "ahb";
|
||||
};
|
||||
|
||||
+ iep: iep@20070000 {
|
||||
+ compatible = "rockchip,rk3228-iep";
|
||||
+ reg = <0x20070000 0x800>;
|
||||
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
|
||||
+ clock-names = "axi", "ahb";
|
||||
+ iommus = <&iep_mmu>;
|
||||
+ power-domains = <&power RK3228_PD_VIO>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
iep_mmu: iommu@20070800 {
|
||||
compatible = "rockchip,iommu";
|
||||
reg = <0x20070800 0x100>;
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,44 @@
|
||||
From 2d42546642fa4299d88fa4ae414fa1ab205dad70 Mon Sep 17 00:00:00 2001
|
||||
From: Paolo Sabatino <paolo.sabatino@gmail.com>
|
||||
Date: Sat, 11 Sep 2021 17:38:48 +0000
|
||||
Subject: [PATCH] rk322x: enable YUV modes for win1, 10-bit for win0/win1
|
||||
|
||||
---
|
||||
drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 10 ++++++----
|
||||
1 file changed, 6 insertions(+), 4 deletions(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
|
||||
index 70930b410..3fd00b323 100644
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
|
||||
@@ -719,10 +719,11 @@ static const struct vop_common rk3288_common = {
|
||||
|
||||
static const struct vop_win_phy rk3228_win0_data = {
|
||||
.scl = &rk3288_win_full_scl,
|
||||
- .data_formats = formats_win_full,
|
||||
- .nformats = ARRAY_SIZE(formats_win_full),
|
||||
+ .data_formats = formats_win_full_10,
|
||||
+ .nformats = ARRAY_SIZE(formats_win_full_10),
|
||||
.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
|
||||
.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
|
||||
+ .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
|
||||
.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
|
||||
.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
|
||||
.dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
|
||||
@@ -738,10 +739,11 @@ static const struct vop_win_phy rk3228_win0_data = {
|
||||
|
||||
static const struct vop_win_phy rk3228_win1_data = {
|
||||
.scl = &rk3288_win_full_scl,
|
||||
- .data_formats = formats_win_lite,
|
||||
- .nformats = ARRAY_SIZE(formats_win_lite),
|
||||
+ .data_formats = formats_win_full_10,
|
||||
+ .nformats = ARRAY_SIZE(formats_win_full_10),
|
||||
.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
|
||||
.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
|
||||
+ .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
|
||||
.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
|
||||
.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
|
||||
.dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,913 @@
|
||||
From b4f40590a4f946d8ee704faf8579930e53ef4650 Mon Sep 17 00:00:00 2001
|
||||
From: Paolo Sabatino <paolo.sabatino@gmail.com>
|
||||
Date: Sun, 12 Sep 2021 10:15:56 +0000
|
||||
Subject: [PATCH] rk322x: analog audio codec
|
||||
|
||||
---
|
||||
.../bindings/sound/rockchip,rk3228-codec.txt | 22 +
|
||||
arch/arm/boot/dts/rk322x.dtsi | 9 +
|
||||
drivers/clk/rockchip/clk-rk3228.c | 2 +-
|
||||
include/dt-bindings/clock/rk3228-cru.h | 1 +
|
||||
sound/soc/codecs/Kconfig | 5 +
|
||||
sound/soc/codecs/Makefile | 2 +
|
||||
sound/soc/codecs/rk3228_codec.c | 545 ++++++++++++++++++
|
||||
sound/soc/codecs/rk3228_codec.h | 218 +++++++
|
||||
8 files changed, 803 insertions(+), 1 deletion(-)
|
||||
create mode 100644 Documentation/devicetree/bindings/sound/rockchip,rk3228-codec.txt
|
||||
create mode 100644 sound/soc/codecs/rk3228_codec.c
|
||||
create mode 100644 sound/soc/codecs/rk3228_codec.h
|
||||
|
||||
diff --git a/Documentation/devicetree/bindings/sound/rockchip,rk3228-codec.txt b/Documentation/devicetree/bindings/sound/rockchip,rk3228-codec.txt
|
||||
new file mode 100644
|
||||
index 000000000..9191a8593
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/bindings/sound/rockchip,rk3228-codec.txt
|
||||
@@ -0,0 +1,22 @@
|
||||
+* Rockchip Rk3228 internal codec
|
||||
+
|
||||
+Required properties:
|
||||
+
|
||||
+- compatible: "rockchip,rk3228-codec"
|
||||
+- reg: physical base address of the controller and length of memory mapped
|
||||
+ region.
|
||||
+- clocks: a list of phandle + clock-specifer pairs, one for each entry in clock-names.
|
||||
+- clock-names: a list of clock names, one for each entry in clocks.
|
||||
+- spk-en-gpio: speaker enable gpio.
|
||||
+- spk-depop-time-ms: speaker depop time msec.
|
||||
+
|
||||
+Example for rk3228 internal codec:
|
||||
+
|
||||
+codec: codec@12010000 {
|
||||
+ compatible = "rockchip,rk3228-codec";
|
||||
+ reg = <0x12010000 0x1000>;
|
||||
+ clocks = <&cru SCLK_I2S_OUT>, <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
|
||||
+ clock-names = "mclk", "pclk", "sclk";
|
||||
+ spk-en-gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
+ status = "disabled";
|
||||
+};
|
||||
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
|
||||
index 75af99c76..c2670d498 100644
|
||||
--- a/arch/arm/boot/dts/rk322x.dtsi
|
||||
+++ b/arch/arm/boot/dts/rk322x.dtsi
|
||||
@@ -145,6 +145,15 @@ i2s1: i2s1@100b0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ codec: codec@12010000 {
|
||||
+ compatible = "rockchip,rk3228-codec";
|
||||
+ reg = <0x12010000 0x1000>;
|
||||
+ clocks = <&cru SCLK_I2S_OUT>, <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
|
||||
+ clock-names = "mclk", "pclk", "sclk";
|
||||
+ spk-en-gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
i2s0: i2s0@100c0000 {
|
||||
compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
|
||||
reg = <0x100c0000 0x4000>;
|
||||
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
|
||||
index a24a35553..69f8c792f 100644
|
||||
--- a/drivers/clk/rockchip/clk-rk3228.c
|
||||
+++ b/drivers/clk/rockchip/clk-rk3228.c
|
||||
@@ -620,7 +620,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
||||
GATE(0, "pclk_sim", "pclk_cpu", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
|
||||
|
||||
GATE(0, "pclk_ddrphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),
|
||||
- GATE(0, "pclk_acodecphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 5, GFLAGS),
|
||||
+ GATE(PCLK_ACODECPHY, "pclk_acodecphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 5, GFLAGS),
|
||||
GATE(PCLK_HDMI_PHY, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS),
|
||||
GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
|
||||
GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),
|
||||
diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
|
||||
index de550ea56..30d44ce90 100644
|
||||
--- a/include/dt-bindings/clock/rk3228-cru.h
|
||||
+++ b/include/dt-bindings/clock/rk3228-cru.h
|
||||
@@ -115,6 +115,7 @@
|
||||
#define PCLK_HDMI_CTRL 364
|
||||
#define PCLK_HDMI_PHY 365
|
||||
#define PCLK_GMAC 367
|
||||
+#define PCLK_ACODECPHY 368
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_I2S0_8CH 442
|
||||
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
|
||||
index db1607120..5f7f01102 100644
|
||||
--- a/sound/soc/codecs/Kconfig
|
||||
+++ b/sound/soc/codecs/Kconfig
|
||||
@@ -154,6 +154,7 @@ config SND_SOC_ALL_CODECS
|
||||
imply SND_SOC_PCM5102A
|
||||
imply SND_SOC_PCM512x_I2C
|
||||
imply SND_SOC_PCM512x_SPI
|
||||
+ imply SND_SOC_RK3228
|
||||
imply SND_SOC_RK3328
|
||||
imply SND_SOC_RK817
|
||||
imply SND_SOC_RT274
|
||||
@@ -1063,6 +1064,10 @@ config SND_SOC_PCM512x_SPI
|
||||
select SND_SOC_PCM512x
|
||||
select REGMAP_SPI
|
||||
|
||||
+config SND_SOC_RK3228
|
||||
+ select REGMAP_MMIO
|
||||
+ tristate "Rockchip RK3228 CODEC"
|
||||
+
|
||||
config SND_SOC_RK3328
|
||||
tristate "Rockchip RK3328 audio CODEC"
|
||||
select REGMAP_MMIO
|
||||
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
|
||||
index 7bb38c370..232b5c43e 100644
|
||||
--- a/sound/soc/codecs/Makefile
|
||||
+++ b/sound/soc/codecs/Makefile
|
||||
@@ -165,6 +165,7 @@ snd-soc-pcm5102a-objs := pcm5102a.o
|
||||
snd-soc-pcm512x-objs := pcm512x.o
|
||||
snd-soc-pcm512x-i2c-objs := pcm512x-i2c.o
|
||||
snd-soc-pcm512x-spi-objs := pcm512x-spi.o
|
||||
+snd-soc-rk3228-objs := rk3228_codec.o
|
||||
snd-soc-rk3328-objs := rk3328_codec.o
|
||||
snd-soc-rk817-objs := rk817_codec.o
|
||||
snd-soc-rl6231-objs := rl6231.o
|
||||
@@ -491,6 +492,7 @@ obj-$(CONFIG_SND_SOC_PCM5102A) += snd-soc-pcm5102a.o
|
||||
obj-$(CONFIG_SND_SOC_PCM512x) += snd-soc-pcm512x.o
|
||||
obj-$(CONFIG_SND_SOC_PCM512x_I2C) += snd-soc-pcm512x-i2c.o
|
||||
obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o
|
||||
+obj-$(CONFIG_SND_SOC_RK3228) += snd-soc-rk3228.o
|
||||
obj-$(CONFIG_SND_SOC_RK3328) += snd-soc-rk3328.o
|
||||
obj-$(CONFIG_SND_SOC_RK817) += snd-soc-rk817.o
|
||||
obj-$(CONFIG_SND_SOC_RL6231) += snd-soc-rl6231.o
|
||||
diff --git a/sound/soc/codecs/rk3228_codec.c b/sound/soc/codecs/rk3228_codec.c
|
||||
new file mode 100644
|
||||
index 000000000..b65307435
|
||||
--- /dev/null
|
||||
+++ b/sound/soc/codecs/rk3228_codec.c
|
||||
@@ -0,0 +1,545 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0
|
||||
+//
|
||||
+// rk3228_codec.c -- rk3228 ALSA Soc Audio driver
|
||||
+//
|
||||
+// Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd All rights reserved.
|
||||
+
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/device.h>
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/of_gpio.h>
|
||||
+#include <linux/clk.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/pm_runtime.h>
|
||||
+#include <linux/regmap.h>
|
||||
+#include <sound/pcm_params.h>
|
||||
+#include <sound/dmaengine_pcm.h>
|
||||
+#include "rk3228_codec.h"
|
||||
+
|
||||
+/*
|
||||
+ * volume setting
|
||||
+ * 0: -39dB
|
||||
+ * 26: 0dB
|
||||
+ * 31: 6dB
|
||||
+ * Step: 1.5dB
|
||||
+ */
|
||||
+#define OUT_VOLUME (0x18)
|
||||
+#define INITIAL_FREQ (11289600)
|
||||
+
|
||||
+struct rk3228_codec_priv {
|
||||
+ struct regmap *regmap;
|
||||
+ struct clk *mclk;
|
||||
+ struct clk *pclk;
|
||||
+ struct clk *sclk;
|
||||
+ struct gpio_desc *spk_en_gpio;
|
||||
+ int spk_depop_time; /* msec */
|
||||
+};
|
||||
+
|
||||
+static const struct reg_default rk3228_codec_reg_defaults[] = {
|
||||
+ { CODEC_RESET, 0x03 },
|
||||
+ { DAC_INIT_CTRL1, 0x00 },
|
||||
+ { DAC_INIT_CTRL2, 0x50 },
|
||||
+ { DAC_INIT_CTRL3, 0x0e },
|
||||
+ { DAC_PRECHARGE_CTRL, 0x01 },
|
||||
+ { DAC_PWR_CTRL, 0x00 },
|
||||
+ { DAC_CLK_CTRL, 0x00 },
|
||||
+ { HPMIX_CTRL, 0x00 },
|
||||
+ { HPOUT_CTRL, 0x00 },
|
||||
+ { HPOUTL_GAIN_CTRL, 0x00 },
|
||||
+ { HPOUTR_GAIN_CTRL, 0x00 },
|
||||
+ { HPOUT_POP_CTRL, 0x11 },
|
||||
+};
|
||||
+
|
||||
+static int rk3228_codec_reset(struct snd_soc_component *component)
|
||||
+{
|
||||
+ struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
|
||||
+
|
||||
+ regmap_write(rk3228->regmap, CODEC_RESET, 0);
|
||||
+ mdelay(10);
|
||||
+ regmap_write(rk3228->regmap, CODEC_RESET, 0x03);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3228_set_dai_fmt(struct snd_soc_dai *dai,
|
||||
+ unsigned int fmt)
|
||||
+{
|
||||
+ struct snd_soc_component *component = dai->component;
|
||||
+ struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
|
||||
+ unsigned int val = 0;
|
||||
+
|
||||
+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
|
||||
+ case SND_SOC_DAIFMT_CBS_CFS:
|
||||
+ val |= PIN_DIRECTION_IN | DAC_I2S_MODE_SLAVE;
|
||||
+ break;
|
||||
+ case SND_SOC_DAIFMT_CBM_CFM:
|
||||
+ val |= PIN_DIRECTION_OUT | DAC_I2S_MODE_MASTER;
|
||||
+ break;
|
||||
+ default:
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ regmap_update_bits(rk3228->regmap, DAC_INIT_CTRL1,
|
||||
+ PIN_DIRECTION_MASK | DAC_I2S_MODE_MASK, val);
|
||||
+
|
||||
+ val = 0;
|
||||
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
|
||||
+ case SND_SOC_DAIFMT_DSP_A:
|
||||
+ case SND_SOC_DAIFMT_DSP_B:
|
||||
+ val |= DAC_MODE_PCM;
|
||||
+ break;
|
||||
+ case SND_SOC_DAIFMT_I2S:
|
||||
+ val |= DAC_MODE_I2S;
|
||||
+ break;
|
||||
+ case SND_SOC_DAIFMT_RIGHT_J:
|
||||
+ val |= DAC_MODE_RJM;
|
||||
+ break;
|
||||
+ case SND_SOC_DAIFMT_LEFT_J:
|
||||
+ val |= DAC_MODE_LJM;
|
||||
+ break;
|
||||
+ default:
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ regmap_update_bits(rk3228->regmap, DAC_INIT_CTRL2,
|
||||
+ DAC_MODE_MASK, val);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void rk3228_analog_output(struct rk3228_codec_priv *rk3228, int mute)
|
||||
+{
|
||||
+ if (rk3228->spk_en_gpio)
|
||||
+ gpiod_set_value(rk3228->spk_en_gpio, mute);
|
||||
+}
|
||||
+
|
||||
+static int rk3228_mute_stream(struct snd_soc_dai *dai, int mute, int direction)
|
||||
+{
|
||||
+ struct snd_soc_component *component = dai->component;
|
||||
+ struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
|
||||
+ unsigned int val = 0;
|
||||
+
|
||||
+ if (direction != SNDRV_PCM_STREAM_PLAYBACK)
|
||||
+ return 0;
|
||||
+
|
||||
+ if (mute)
|
||||
+ val = HPOUTL_MUTE | HPOUTR_MUTE;
|
||||
+ else
|
||||
+ val = HPOUTL_UNMUTE | HPOUTR_UNMUTE;
|
||||
+
|
||||
+ regmap_update_bits(rk3228->regmap, HPOUT_CTRL,
|
||||
+ HPOUTL_MUTE_MASK | HPOUTR_MUTE_MASK, val);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3228_codec_power_on(struct snd_soc_component *component, int wait_ms)
|
||||
+{
|
||||
+ struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
|
||||
+
|
||||
+ regmap_update_bits(rk3228->regmap, DAC_PRECHARGE_CTRL,
|
||||
+ DAC_CHARGE_XCHARGE_MASK, DAC_CHARGE_PRECHARGE);
|
||||
+ mdelay(10);
|
||||
+ regmap_update_bits(rk3228->regmap, DAC_PRECHARGE_CTRL,
|
||||
+ DAC_CHARGE_CURRENT_ALL_MASK,
|
||||
+ DAC_CHARGE_CURRENT_ALL_ON);
|
||||
+
|
||||
+ mdelay(wait_ms);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3228_codec_power_off(struct snd_soc_component *component, int wait_ms)
|
||||
+{
|
||||
+ struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
|
||||
+
|
||||
+ regmap_update_bits(rk3228->regmap, DAC_PRECHARGE_CTRL,
|
||||
+ DAC_CHARGE_XCHARGE_MASK, DAC_CHARGE_DISCHARGE);
|
||||
+ mdelay(10);
|
||||
+ regmap_update_bits(rk3228->regmap, DAC_PRECHARGE_CTRL,
|
||||
+ DAC_CHARGE_CURRENT_ALL_MASK,
|
||||
+ DAC_CHARGE_CURRENT_ALL_ON);
|
||||
+
|
||||
+ mdelay(wait_ms);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct rk3228_reg_msk_val playback_open_list[] = {
|
||||
+ { DAC_PWR_CTRL, DAC_PWR_MASK, DAC_PWR_ON },
|
||||
+ { DAC_PWR_CTRL, DACL_PATH_REFV_MASK | DACR_PATH_REFV_MASK,
|
||||
+ DACL_PATH_REFV_ON | DACR_PATH_REFV_ON },
|
||||
+ { DAC_PWR_CTRL, HPOUTL_ZERO_CROSSING_ON | HPOUTR_ZERO_CROSSING_ON,
|
||||
+ HPOUTL_ZERO_CROSSING_ON | HPOUTR_ZERO_CROSSING_ON },
|
||||
+ { HPOUT_POP_CTRL, HPOUTR_POP_MASK | HPOUTL_POP_MASK,
|
||||
+ HPOUTR_POP_WORK | HPOUTL_POP_WORK },
|
||||
+ { HPMIX_CTRL, HPMIXL_MASK | HPMIXR_MASK, HPMIXL_EN | HPMIXR_EN },
|
||||
+ { HPMIX_CTRL, HPMIXL_INIT_MASK | HPMIXR_INIT_MASK,
|
||||
+ HPMIXL_INIT_EN | HPMIXR_INIT_EN },
|
||||
+ { HPOUT_CTRL, HPOUTL_MASK | HPOUTR_MASK, HPOUTL_EN | HPOUTR_EN },
|
||||
+ { HPOUT_CTRL, HPOUTL_INIT_MASK | HPOUTR_INIT_MASK,
|
||||
+ HPOUTL_INIT_EN | HPOUTR_INIT_EN },
|
||||
+ { DAC_CLK_CTRL, DACL_REFV_MASK | DACR_REFV_MASK,
|
||||
+ DACL_REFV_ON | DACR_REFV_ON },
|
||||
+ { DAC_CLK_CTRL, DACL_CLK_MASK | DACR_CLK_MASK,
|
||||
+ DACL_CLK_ON | DACR_CLK_ON },
|
||||
+ { DAC_CLK_CTRL, DACL_MASK | DACR_MASK, DACL_ON | DACR_ON },
|
||||
+ { DAC_CLK_CTRL, DACL_INIT_MASK | DACR_INIT_MASK,
|
||||
+ DACL_INIT_ON | DACR_INIT_ON },
|
||||
+ { DAC_SELECT, DACL_SELECT_MASK | DACR_SELECT_MASK,
|
||||
+ DACL_SELECT | DACR_SELECT },
|
||||
+ { HPMIX_CTRL, HPMIXL_INIT2_MASK | HPMIXR_INIT2_MASK,
|
||||
+ HPMIXL_INIT2_EN | HPMIXR_INIT2_EN },
|
||||
+ { HPOUT_CTRL, HPOUTL_MUTE_MASK | HPOUTR_MUTE_MASK,
|
||||
+ HPOUTL_UNMUTE | HPOUTR_UNMUTE },
|
||||
+};
|
||||
+
|
||||
+#define PLAYBACK_OPEN_LIST_LEN ARRAY_SIZE(playback_open_list)
|
||||
+
|
||||
+static int rk3228_codec_open_playback(struct snd_soc_component *component)
|
||||
+{
|
||||
+ struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
|
||||
+ int i = 0;
|
||||
+
|
||||
+ regmap_update_bits(rk3228->regmap, DAC_PRECHARGE_CTRL,
|
||||
+ DAC_CHARGE_CURRENT_ALL_MASK,
|
||||
+ DAC_CHARGE_CURRENT_I);
|
||||
+
|
||||
+ for (i = 0; i < PLAYBACK_OPEN_LIST_LEN; i++) {
|
||||
+ regmap_update_bits(rk3228->regmap,
|
||||
+ playback_open_list[i].reg,
|
||||
+ playback_open_list[i].msk,
|
||||
+ playback_open_list[i].val);
|
||||
+ mdelay(1);
|
||||
+ }
|
||||
+
|
||||
+ msleep(rk3228->spk_depop_time);
|
||||
+ rk3228_analog_output(rk3228, 1);
|
||||
+
|
||||
+ regmap_update_bits(rk3228->regmap, HPOUTL_GAIN_CTRL,
|
||||
+ HPOUTL_GAIN_MASK, OUT_VOLUME);
|
||||
+ regmap_update_bits(rk3228->regmap, HPOUTR_GAIN_CTRL,
|
||||
+ HPOUTR_GAIN_MASK, OUT_VOLUME);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct rk3228_reg_msk_val playback_close_list[] = {
|
||||
+ { HPMIX_CTRL, HPMIXL_INIT2_MASK | HPMIXR_INIT2_MASK,
|
||||
+ HPMIXL_INIT2_DIS | HPMIXR_INIT2_DIS },
|
||||
+ { DAC_SELECT, DACL_SELECT_MASK | DACR_SELECT_MASK,
|
||||
+ DACL_DESELECT | DACR_DESELECT },
|
||||
+ { HPOUT_CTRL, HPOUTL_MUTE_MASK | HPOUTR_MUTE_MASK,
|
||||
+ HPOUTL_MUTE | HPOUTR_MUTE },
|
||||
+ { HPOUT_CTRL, HPOUTL_INIT_MASK | HPOUTR_INIT_MASK,
|
||||
+ HPOUTL_INIT_DIS | HPOUTR_INIT_DIS },
|
||||
+ { HPOUT_CTRL, HPOUTL_MASK | HPOUTR_MASK, HPOUTL_DIS | HPOUTR_DIS },
|
||||
+ { HPMIX_CTRL, HPMIXL_MASK | HPMIXR_MASK, HPMIXL_DIS | HPMIXR_DIS },
|
||||
+ { DAC_CLK_CTRL, DACL_MASK | DACR_MASK, DACL_OFF | DACR_OFF },
|
||||
+ { DAC_CLK_CTRL, DACL_CLK_MASK | DACR_CLK_MASK,
|
||||
+ DACL_CLK_OFF | DACR_CLK_OFF },
|
||||
+ { DAC_CLK_CTRL, DACL_REFV_MASK | DACR_REFV_MASK,
|
||||
+ DACL_REFV_OFF | DACR_REFV_OFF },
|
||||
+ { HPOUT_POP_CTRL, HPOUTR_POP_MASK | HPOUTL_POP_MASK,
|
||||
+ HPOUTR_POP_XCHARGE | HPOUTL_POP_XCHARGE },
|
||||
+ { DAC_PWR_CTRL, DACL_PATH_REFV_MASK | DACR_PATH_REFV_MASK,
|
||||
+ DACL_PATH_REFV_OFF | DACR_PATH_REFV_OFF },
|
||||
+ { DAC_PWR_CTRL, DAC_PWR_MASK, DAC_PWR_OFF },
|
||||
+ { HPMIX_CTRL, HPMIXL_INIT_MASK | HPMIXR_INIT_MASK,
|
||||
+ HPMIXL_INIT_DIS | HPMIXR_INIT_DIS },
|
||||
+ { DAC_CLK_CTRL, DACL_INIT_MASK | DACR_INIT_MASK,
|
||||
+ DACL_INIT_OFF | DACR_INIT_OFF },
|
||||
+};
|
||||
+
|
||||
+#define PLAYBACK_CLOSE_LIST_LEN ARRAY_SIZE(playback_close_list)
|
||||
+
|
||||
+static int rk3228_codec_close_playback(struct snd_soc_component *component)
|
||||
+{
|
||||
+ struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
|
||||
+ int i = 0;
|
||||
+
|
||||
+ rk3228_analog_output(rk3228, 0);
|
||||
+
|
||||
+ regmap_update_bits(rk3228->regmap, HPOUTL_GAIN_CTRL,
|
||||
+ HPOUTL_GAIN_MASK, 0);
|
||||
+ regmap_update_bits(rk3228->regmap, HPOUTR_GAIN_CTRL,
|
||||
+ HPOUTR_GAIN_MASK, 0);
|
||||
+
|
||||
+ for (i = 0; i < PLAYBACK_CLOSE_LIST_LEN; i++) {
|
||||
+ regmap_update_bits(rk3228->regmap,
|
||||
+ playback_close_list[i].reg,
|
||||
+ playback_close_list[i].msk,
|
||||
+ playback_close_list[i].val);
|
||||
+ mdelay(1);
|
||||
+ }
|
||||
+
|
||||
+ regmap_update_bits(rk3228->regmap, DAC_PRECHARGE_CTRL,
|
||||
+ DAC_CHARGE_CURRENT_ALL_MASK,
|
||||
+ DAC_CHARGE_CURRENT_I);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3228_hw_params(struct snd_pcm_substream *substream,
|
||||
+ struct snd_pcm_hw_params *params,
|
||||
+ struct snd_soc_dai *dai)
|
||||
+{
|
||||
+ struct snd_soc_component *component = dai->component;
|
||||
+ struct rk3228_codec_priv *rk3228 = snd_soc_component_get_drvdata(component);
|
||||
+ unsigned int val = 0;
|
||||
+
|
||||
+ switch (params_format(params)) {
|
||||
+ case SNDRV_PCM_FORMAT_S16_LE:
|
||||
+ val |= DAC_VDL_16BITS;
|
||||
+ break;
|
||||
+ case SNDRV_PCM_FORMAT_S20_3LE:
|
||||
+ val |= DAC_VDL_20BITS;
|
||||
+ break;
|
||||
+ case SNDRV_PCM_FORMAT_S24_LE:
|
||||
+ val |= DAC_VDL_24BITS;
|
||||
+ break;
|
||||
+ case SNDRV_PCM_FORMAT_S32_LE:
|
||||
+ val |= DAC_VDL_32BITS;
|
||||
+ break;
|
||||
+ default:
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ regmap_update_bits(rk3228->regmap, DAC_INIT_CTRL2, DAC_VDL_MASK, val);
|
||||
+ val = DAC_WL_32BITS | DAC_RST_DIS;
|
||||
+ regmap_update_bits(rk3228->regmap, DAC_INIT_CTRL3,
|
||||
+ DAC_WL_MASK | DAC_RST_MASK, val);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3228_pcm_startup(struct snd_pcm_substream *substream,
|
||||
+ struct snd_soc_dai *dai)
|
||||
+{
|
||||
+ struct snd_soc_component *component = dai->component;
|
||||
+
|
||||
+ return rk3228_codec_open_playback(component);
|
||||
+}
|
||||
+
|
||||
+static void rk3228_pcm_shutdown(struct snd_pcm_substream *substream,
|
||||
+ struct snd_soc_dai *dai)
|
||||
+{
|
||||
+ struct snd_soc_component *component = dai->component;
|
||||
+
|
||||
+ rk3228_codec_close_playback(component);
|
||||
+}
|
||||
+
|
||||
+static struct snd_soc_dai_ops rk3228_dai_ops = {
|
||||
+ .hw_params = rk3228_hw_params,
|
||||
+ .set_fmt = rk3228_set_dai_fmt,
|
||||
+ .mute_stream = rk3228_mute_stream,
|
||||
+ .startup = rk3228_pcm_startup,
|
||||
+ .shutdown = rk3228_pcm_shutdown,
|
||||
+};
|
||||
+
|
||||
+static struct snd_soc_dai_driver rk3228_dai[] = {
|
||||
+ {
|
||||
+ .name = "rk3228-hifi",
|
||||
+ .id = RK3228_HIFI,
|
||||
+ .playback = {
|
||||
+ .stream_name = "HIFI Playback",
|
||||
+ .channels_min = 1,
|
||||
+ .channels_max = 2,
|
||||
+ .rates = SNDRV_PCM_RATE_8000_96000,
|
||||
+ .formats = (SNDRV_PCM_FMTBIT_S16_LE |
|
||||
+ SNDRV_PCM_FMTBIT_S20_3LE |
|
||||
+ SNDRV_PCM_FMTBIT_S24_LE |
|
||||
+ SNDRV_PCM_FMTBIT_S32_LE),
|
||||
+ },
|
||||
+ /*.capture = {
|
||||
+ .stream_name = "HIFI Capture",
|
||||
+ .channels_min = 2,
|
||||
+ .channels_max = 8,
|
||||
+ .rates = SNDRV_PCM_RATE_8000_96000,
|
||||
+ .formats = (SNDRV_PCM_FMTBIT_S16_LE |
|
||||
+ SNDRV_PCM_FMTBIT_S20_3LE |
|
||||
+ SNDRV_PCM_FMTBIT_S24_LE |
|
||||
+ SNDRV_PCM_FMTBIT_S32_LE),
|
||||
+ },*/
|
||||
+ .ops = &rk3228_dai_ops,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static int rk3228_codec_probe(struct snd_soc_component *component)
|
||||
+{
|
||||
+ rk3228_codec_reset(component);
|
||||
+ rk3228_codec_power_on(component, 0);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void rk3228_codec_remove(struct snd_soc_component *component)
|
||||
+{
|
||||
+ rk3228_codec_close_playback(component);
|
||||
+ rk3228_codec_power_off(component, 0);
|
||||
+}
|
||||
+
|
||||
+static struct snd_soc_component_driver soc_codec_dev_rk3228 = {
|
||||
+ .probe = rk3228_codec_probe,
|
||||
+ .remove = rk3228_codec_remove,
|
||||
+};
|
||||
+
|
||||
+static bool rk3228_codec_write_read_reg(struct device *dev, unsigned int reg)
|
||||
+{
|
||||
+ switch (reg) {
|
||||
+ case CODEC_RESET:
|
||||
+ case DAC_INIT_CTRL1:
|
||||
+ case DAC_INIT_CTRL2:
|
||||
+ case DAC_INIT_CTRL3:
|
||||
+ case DAC_PRECHARGE_CTRL:
|
||||
+ case DAC_PWR_CTRL:
|
||||
+ case DAC_CLK_CTRL:
|
||||
+ case HPMIX_CTRL:
|
||||
+ case DAC_SELECT:
|
||||
+ case HPOUT_CTRL:
|
||||
+ case HPOUTL_GAIN_CTRL:
|
||||
+ case HPOUTR_GAIN_CTRL:
|
||||
+ case HPOUT_POP_CTRL:
|
||||
+ return true;
|
||||
+ default:
|
||||
+ return false;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static bool rk3228_codec_volatile_reg(struct device *dev, unsigned int reg)
|
||||
+{
|
||||
+ switch (reg) {
|
||||
+ case CODEC_RESET:
|
||||
+ return true;
|
||||
+ default:
|
||||
+ return false;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static const struct regmap_config rk3228_codec_regmap_config = {
|
||||
+ .reg_bits = 32,
|
||||
+ .reg_stride = 4,
|
||||
+ .val_bits = 32,
|
||||
+ .max_register = HPOUT_POP_CTRL,
|
||||
+ .writeable_reg = rk3228_codec_write_read_reg,
|
||||
+ .readable_reg = rk3228_codec_write_read_reg,
|
||||
+ .volatile_reg = rk3228_codec_volatile_reg,
|
||||
+ .reg_defaults = rk3228_codec_reg_defaults,
|
||||
+ .num_reg_defaults = ARRAY_SIZE(rk3228_codec_reg_defaults),
|
||||
+ .cache_type = REGCACHE_FLAT,
|
||||
+};
|
||||
+
|
||||
+#ifdef CONFIG_OF
|
||||
+static const struct of_device_id rk3228codec_of_match[] = {
|
||||
+ { .compatible = "rockchip,rk3228-codec", },
|
||||
+ {},
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, rk3228codec_of_match);
|
||||
+#endif
|
||||
+
|
||||
+static int rk3228_platform_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct device_node *rk3228_np = pdev->dev.of_node;
|
||||
+ struct rk3228_codec_priv *rk3228;
|
||||
+ struct resource *res;
|
||||
+ void __iomem *base;
|
||||
+ int ret = 0;
|
||||
+
|
||||
+ rk3228 = devm_kzalloc(&pdev->dev, sizeof(*rk3228), GFP_KERNEL);
|
||||
+ if (!rk3228)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ rk3228->mclk = devm_clk_get(&pdev->dev, "mclk");
|
||||
+ if (PTR_ERR(rk3228->mclk) == -EPROBE_DEFER)
|
||||
+ return -EPROBE_DEFER;
|
||||
+
|
||||
+ rk3228->pclk = devm_clk_get(&pdev->dev, "pclk");
|
||||
+ if (IS_ERR(rk3228->pclk))
|
||||
+ return PTR_ERR(rk3228->pclk);
|
||||
+
|
||||
+ rk3228->sclk = devm_clk_get(&pdev->dev, "sclk");
|
||||
+ if (IS_ERR(rk3228->sclk))
|
||||
+ return PTR_ERR(rk3228->sclk);
|
||||
+
|
||||
+ rk3228->spk_en_gpio = devm_gpiod_get_optional(&pdev->dev,
|
||||
+ "spk-en",
|
||||
+ GPIOD_OUT_LOW);
|
||||
+ if (IS_ERR(rk3228->spk_en_gpio))
|
||||
+ return PTR_ERR(rk3228->spk_en_gpio);
|
||||
+
|
||||
+ ret = of_property_read_u32(rk3228_np, "spk-depop-time-ms",
|
||||
+ &rk3228->spk_depop_time);
|
||||
+ if (ret < 0) {
|
||||
+ dev_info(&pdev->dev, "spk_depop_time use default value.\n");
|
||||
+ rk3228->spk_depop_time = 100;
|
||||
+ }
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ base = devm_ioremap_resource(&pdev->dev, res);
|
||||
+ if (IS_ERR(base))
|
||||
+ return PTR_ERR(base);
|
||||
+
|
||||
+ ret = clk_prepare_enable(rk3228->mclk);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = clk_prepare_enable(rk3228->pclk);
|
||||
+ if (ret < 0)
|
||||
+ goto err_pclk;
|
||||
+
|
||||
+ ret = clk_prepare_enable(rk3228->sclk);
|
||||
+ if (ret)
|
||||
+ goto err_sclk;
|
||||
+
|
||||
+ clk_set_rate(rk3228->sclk, INITIAL_FREQ);
|
||||
+
|
||||
+ rk3228->regmap = devm_regmap_init_mmio(&pdev->dev, base,
|
||||
+ &rk3228_codec_regmap_config);
|
||||
+ if (IS_ERR(rk3228->regmap)) {
|
||||
+ ret = PTR_ERR(rk3228->regmap);
|
||||
+ goto err_clk;
|
||||
+ }
|
||||
+
|
||||
+ platform_set_drvdata(pdev, rk3228);
|
||||
+
|
||||
+ ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_rk3228,
|
||||
+ rk3228_dai, ARRAY_SIZE(rk3228_dai));
|
||||
+ if (!ret)
|
||||
+ return 0;
|
||||
+
|
||||
+err_clk:
|
||||
+ clk_disable_unprepare(rk3228->sclk);
|
||||
+err_sclk:
|
||||
+ clk_disable_unprepare(rk3228->pclk);
|
||||
+err_pclk:
|
||||
+ clk_disable_unprepare(rk3228->mclk);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int rk3228_platform_remove(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct rk3228_codec_priv *rk3228 = platform_get_drvdata(pdev);
|
||||
+
|
||||
+ if (!IS_ERR(rk3228->mclk))
|
||||
+ clk_disable_unprepare(rk3228->mclk);
|
||||
+
|
||||
+ if (!IS_ERR(rk3228->pclk))
|
||||
+ clk_disable_unprepare(rk3228->pclk);
|
||||
+
|
||||
+ if (!IS_ERR(rk3228->sclk))
|
||||
+ clk_disable_unprepare(rk3228->sclk);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver rk3228_codec_driver = {
|
||||
+ .driver = {
|
||||
+ .name = "rk3228-codec",
|
||||
+ .of_match_table = of_match_ptr(rk3228codec_of_match),
|
||||
+ },
|
||||
+ .probe = rk3228_platform_probe,
|
||||
+ .remove = rk3228_platform_remove,
|
||||
+};
|
||||
+module_platform_driver(rk3228_codec_driver);
|
||||
+
|
||||
+MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>");
|
||||
+MODULE_DESCRIPTION("ASoC rk3228 codec driver");
|
||||
+MODULE_LICENSE("GPL v2");
|
||||
diff --git a/sound/soc/codecs/rk3228_codec.h b/sound/soc/codecs/rk3228_codec.h
|
||||
new file mode 100644
|
||||
index 000000000..7283d0ba8
|
||||
--- /dev/null
|
||||
+++ b/sound/soc/codecs/rk3228_codec.h
|
||||
@@ -0,0 +1,218 @@
|
||||
+/*
|
||||
+ * rk3228_codec.h -- rk3228 ALSA Soc Audio driver
|
||||
+ *
|
||||
+ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd All rights reserved.
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify it
|
||||
+ * under the terms and conditions of the GNU General Public License,
|
||||
+ * version 2, as published by the Free Software Foundation.
|
||||
+ *
|
||||
+ * This program is distributed in the hope it will be useful, but WITHOUT
|
||||
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
+ * more details.
|
||||
+ *
|
||||
+ * You should have received a copy of the GNU General Public License
|
||||
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
+ *
|
||||
+ */
|
||||
+
|
||||
+#ifndef _RK3228_CODEC_H
|
||||
+#define _RK3228_CODEC_H
|
||||
+
|
||||
+/* codec register */
|
||||
+#define CODEC_RESET (0x00 << 2)
|
||||
+#define DAC_INIT_CTRL1 (0x03 << 2)
|
||||
+#define DAC_INIT_CTRL2 (0x04 << 2)
|
||||
+#define DAC_INIT_CTRL3 (0x05 << 2)
|
||||
+#define DAC_PRECHARGE_CTRL (0x22 << 2)
|
||||
+#define DAC_PWR_CTRL (0x23 << 2)
|
||||
+#define DAC_CLK_CTRL (0x24 << 2)
|
||||
+#define HPMIX_CTRL (0x25 << 2)
|
||||
+#define DAC_SELECT (0x26 << 2)
|
||||
+#define HPOUT_CTRL (0x27 << 2)
|
||||
+#define HPOUTL_GAIN_CTRL (0x28 << 2)
|
||||
+#define HPOUTR_GAIN_CTRL (0x29 << 2)
|
||||
+#define HPOUT_POP_CTRL (0x2a << 2)
|
||||
+
|
||||
+/* REG00: CODEC_RESET */
|
||||
+#define PWR_RST_BYPASS_DIS BIT(6)
|
||||
+#define PWR_RST_BYPASS_EN BIT(6)
|
||||
+#define DIG_CORE_RST (0 << 1)
|
||||
+#define DIG_CORE_WORK BIT(1)
|
||||
+#define SYS_RST (0)
|
||||
+#define SYS_WORK BIT(0)
|
||||
+
|
||||
+/* REG03: DAC_INIT_CTRL1 */
|
||||
+#define PIN_DIRECTION_MASK BIT(5)
|
||||
+#define PIN_DIRECTION_IN (0 << 5)
|
||||
+#define PIN_DIRECTION_OUT BIT(5)
|
||||
+#define DAC_I2S_MODE_MASK BIT(4)
|
||||
+#define DAC_I2S_MODE_SLAVE (0 << 4)
|
||||
+#define DAC_I2S_MODE_MASTER BIT(4)
|
||||
+
|
||||
+/* REG04: DAC_INIT_CTRL2 */
|
||||
+#define DAC_I2S_LRP_MASK BIT(7)
|
||||
+#define DAC_I2S_LRP_NORMAL (0 << 7)
|
||||
+#define DAC_I2S_LRP_REVERSAL BIT(7)
|
||||
+#define DAC_VDL_MASK (3 << 5)
|
||||
+#define DAC_VDL_16BITS (0 << 5)
|
||||
+#define DAC_VDL_20BITS BIT(5)
|
||||
+#define DAC_VDL_24BITS (2 << 5)
|
||||
+#define DAC_VDL_32BITS (3 << 5)
|
||||
+#define DAC_MODE_MASK (3 << 3)
|
||||
+#define DAC_MODE_RJM (0 << 3)
|
||||
+#define DAC_MODE_LJM BIT(3)
|
||||
+#define DAC_MODE_I2S (2 << 3)
|
||||
+#define DAC_MODE_PCM (3 << 3)
|
||||
+#define DAC_LR_SWAP_MASK BIT(2)
|
||||
+#define DAC_LR_SWAP_DIS (0 << 2)
|
||||
+#define DAC_LR_SWAP_EN BIT(2)
|
||||
+
|
||||
+/* REG05: DAC_INIT_CTRL3 */
|
||||
+#define DAC_WL_MASK (3 << 2)
|
||||
+#define DAC_WL_16BITS (0 << 2)
|
||||
+#define DAC_WL_20BITS BIT(2)
|
||||
+#define DAC_WL_24BITS (2 << 2)
|
||||
+#define DAC_WL_32BITS (3 << 2)
|
||||
+#define DAC_RST_MASK BIT(1)
|
||||
+#define DAC_RST_EN (0 << 1)
|
||||
+#define DAC_RST_DIS BIT(1)
|
||||
+#define DAC_BCP_MASK BIT(0)
|
||||
+#define DAC_BCP_NORMAL (0 << 0)
|
||||
+#define DAC_BCP_REVERSAL BIT(0)
|
||||
+
|
||||
+/* REG22: DAC_PRECHARGE_CTRL */
|
||||
+#define DAC_CHARGE_PRECHARGE BIT(7)
|
||||
+#define DAC_CHARGE_DISCHARGE (0 << 7)
|
||||
+#define DAC_CHARGE_XCHARGE_MASK BIT(7)
|
||||
+#define DAC_CHARGE_CURRENT_64I BIT(6)
|
||||
+#define DAC_CHARGE_CURRENT_64I_MASK BIT(6)
|
||||
+#define DAC_CHARGE_CURRENT_32I BIT(5)
|
||||
+#define DAC_CHARGE_CURRENT_32I_MASK BIT(5)
|
||||
+#define DAC_CHARGE_CURRENT_16I BIT(4)
|
||||
+#define DAC_CHARGE_CURRENT_16I_MASK BIT(4)
|
||||
+#define DAC_CHARGE_CURRENT_08I BIT(3)
|
||||
+#define DAC_CHARGE_CURRENT_08I_MASK BIT(3)
|
||||
+#define DAC_CHARGE_CURRENT_04I BIT(2)
|
||||
+#define DAC_CHARGE_CURRENT_04I_MASK BIT(2)
|
||||
+#define DAC_CHARGE_CURRENT_02I BIT(1)
|
||||
+#define DAC_CHARGE_CURRENT_02I_MASK BIT(1)
|
||||
+#define DAC_CHARGE_CURRENT_I BIT(0)
|
||||
+#define DAC_CHARGE_CURRENT_I_MASK BIT(0)
|
||||
+#define DAC_CHARGE_CURRENT_ALL_MASK (0x7f)
|
||||
+#define DAC_CHARGE_CURRENT_ALL_OFF (0x0)
|
||||
+#define DAC_CHARGE_CURRENT_ALL_ON (0x7f)
|
||||
+
|
||||
+/* REG23: DAC_PWR_CTRL */
|
||||
+#define DAC_PWR_OFF (0 << 6)
|
||||
+#define DAC_PWR_ON BIT(6)
|
||||
+#define DAC_PWR_MASK BIT(6)
|
||||
+#define DACL_PATH_REFV_OFF (0 << 5)
|
||||
+#define DACL_PATH_REFV_ON BIT(5)
|
||||
+#define DACL_PATH_REFV_MASK BIT(5)
|
||||
+#define HPOUTL_ZERO_CROSSING_OFF (0 << 4)
|
||||
+#define HPOUTL_ZERO_CROSSING_ON BIT(4)
|
||||
+#define DACR_PATH_REFV_OFF (0 << 1)
|
||||
+#define DACR_PATH_REFV_ON BIT(1)
|
||||
+#define DACR_PATH_REFV_MASK BIT(1)
|
||||
+#define HPOUTR_ZERO_CROSSING_OFF (0 << 0)
|
||||
+#define HPOUTR_ZERO_CROSSING_ON BIT(0)
|
||||
+
|
||||
+/* REG24: DAC_CLK_CTRL */
|
||||
+#define DACL_REFV_OFF (0 << 7)
|
||||
+#define DACL_REFV_ON BIT(7)
|
||||
+#define DACL_REFV_MASK BIT(7)
|
||||
+#define DACL_CLK_OFF (0 << 6)
|
||||
+#define DACL_CLK_ON BIT(6)
|
||||
+#define DACL_CLK_MASK BIT(6)
|
||||
+#define DACL_OFF (0 << 5)
|
||||
+#define DACL_ON BIT(5)
|
||||
+#define DACL_MASK BIT(5)
|
||||
+#define DACL_INIT_OFF (0 << 4)
|
||||
+#define DACL_INIT_ON BIT(4)
|
||||
+#define DACL_INIT_MASK BIT(4)
|
||||
+#define DACR_REFV_OFF (0 << 3)
|
||||
+#define DACR_REFV_ON BIT(3)
|
||||
+#define DACR_REFV_MASK BIT(3)
|
||||
+#define DACR_CLK_OFF (0 << 2)
|
||||
+#define DACR_CLK_ON BIT(2)
|
||||
+#define DACR_CLK_MASK BIT(2)
|
||||
+#define DACR_OFF (0 << 1)
|
||||
+#define DACR_ON BIT(1)
|
||||
+#define DACR_MASK BIT(1)
|
||||
+#define DACR_INIT_OFF (0 << 0)
|
||||
+#define DACR_INIT_ON BIT(0)
|
||||
+#define DACR_INIT_MASK BIT(0)
|
||||
+
|
||||
+/* REG25: HPMIX_CTRL*/
|
||||
+#define HPMIXL_DIS (0 << 6)
|
||||
+#define HPMIXL_EN BIT(6)
|
||||
+#define HPMIXL_MASK BIT(6)
|
||||
+#define HPMIXL_INIT_DIS (0 << 5)
|
||||
+#define HPMIXL_INIT_EN BIT(5)
|
||||
+#define HPMIXL_INIT_MASK BIT(5)
|
||||
+#define HPMIXL_INIT2_DIS (0 << 4)
|
||||
+#define HPMIXL_INIT2_EN BIT(4)
|
||||
+#define HPMIXL_INIT2_MASK BIT(4)
|
||||
+#define HPMIXR_DIS (0 << 2)
|
||||
+#define HPMIXR_EN BIT(2)
|
||||
+#define HPMIXR_MASK BIT(2)
|
||||
+#define HPMIXR_INIT_DIS (0 << 1)
|
||||
+#define HPMIXR_INIT_EN BIT(1)
|
||||
+#define HPMIXR_INIT_MASK BIT(1)
|
||||
+#define HPMIXR_INIT2_DIS (0 << 0)
|
||||
+#define HPMIXR_INIT2_EN BIT(0)
|
||||
+#define HPMIXR_INIT2_MASK BIT(0)
|
||||
+
|
||||
+/* REG26: DAC_SELECT */
|
||||
+#define DACL_SELECT BIT(4)
|
||||
+#define DACL_SELECT_MASK BIT(4)
|
||||
+#define DACL_DESELECT (0 << 4)
|
||||
+#define DACR_SELECT BIT(0)
|
||||
+#define DACR_SELECT_MASK BIT(0)
|
||||
+#define DACR_DESELECT (0 << 0)
|
||||
+
|
||||
+/* REG27: HPOUT_CTRL */
|
||||
+#define HPOUTL_DIS (0 << 7)
|
||||
+#define HPOUTL_EN BIT(7)
|
||||
+#define HPOUTL_MASK BIT(7)
|
||||
+#define HPOUTL_INIT_DIS (0 << 6)
|
||||
+#define HPOUTL_INIT_EN BIT(6)
|
||||
+#define HPOUTL_INIT_MASK BIT(6)
|
||||
+#define HPOUTL_MUTE (0 << 5)
|
||||
+#define HPOUTL_UNMUTE BIT(5)
|
||||
+#define HPOUTL_MUTE_MASK BIT(5)
|
||||
+#define HPOUTR_DIS (0 << 4)
|
||||
+#define HPOUTR_EN BIT(4)
|
||||
+#define HPOUTR_MASK BIT(4)
|
||||
+#define HPOUTR_INIT_DIS (0 << 3)
|
||||
+#define HPOUTR_INIT_EN BIT(3)
|
||||
+#define HPOUTR_INIT_MASK BIT(3)
|
||||
+#define HPOUTR_MUTE (0 << 2)
|
||||
+#define HPOUTR_UNMUTE BIT(2)
|
||||
+#define HPOUTR_MUTE_MASK BIT(2)
|
||||
+
|
||||
+/* REG28: HPOUTL_GAIN_CTRL */
|
||||
+#define HPOUTL_GAIN_MASK (0X1f << 0)
|
||||
+
|
||||
+/* REG29: HPOUTR_GAIN_CTRL */
|
||||
+#define HPOUTR_GAIN_MASK (0X1f << 0)
|
||||
+
|
||||
+/* REG2a: HPOUT_POP_CTRL */
|
||||
+#define HPOUTR_POP_XCHARGE BIT(4)
|
||||
+#define HPOUTR_POP_WORK (2 << 4)
|
||||
+#define HPOUTR_POP_MASK (3 << 4)
|
||||
+#define HPOUTL_POP_XCHARGE BIT(0)
|
||||
+#define HPOUTL_POP_WORK (2 << 0)
|
||||
+#define HPOUTL_POP_MASK (3 << 0)
|
||||
+
|
||||
+#define RK3228_HIFI (0)
|
||||
+
|
||||
+struct rk3228_reg_msk_val {
|
||||
+ unsigned int reg;
|
||||
+ unsigned int msk;
|
||||
+ unsigned int val;
|
||||
+};
|
||||
+
|
||||
+#endif
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,234 @@
|
||||
From e039790fb29227f646e91e6d7ec7c3e89c584243 Mon Sep 17 00:00:00 2001
|
||||
From: Paolo Sabatino <paolo.sabatino@gmail.com>
|
||||
Date: Tue, 6 Jul 2021 14:21:52 +0000
|
||||
Subject: [PATCH 1/5] rk3228/rk3328: fix ddr clock gate, add SIP v2 calls
|
||||
|
||||
---
|
||||
drivers/clk/rockchip/clk-ddr.c | 130 ++++++++++++++++++++++++++++++
|
||||
drivers/clk/rockchip/clk-rk3228.c | 14 ++--
|
||||
drivers/clk/rockchip/clk-rk3328.c | 7 +-
|
||||
drivers/clk/rockchip/clk.h | 3 +-
|
||||
4 files changed, 143 insertions(+), 11 deletions(-)
|
||||
|
||||
diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c
|
||||
index 86718c54e..b16b3795f 100644
|
||||
--- a/drivers/clk/rockchip/clk-ddr.c
|
||||
+++ b/drivers/clk/rockchip/clk-ddr.c
|
||||
@@ -87,6 +87,133 @@ static const struct clk_ops rockchip_ddrclk_sip_ops = {
|
||||
.get_parent = rockchip_ddrclk_get_parent,
|
||||
};
|
||||
|
||||
+/* See v4.4/include/dt-bindings/display/rk_fb.h */
|
||||
+#define SCREEN_NULL 0
|
||||
+#define SCREEN_HDMI 6
|
||||
+
|
||||
+static inline int rk_drm_get_lcdc_type(void)
|
||||
+{
|
||||
+ return SCREEN_NULL;
|
||||
+}
|
||||
+
|
||||
+struct share_params {
|
||||
+ u32 hz;
|
||||
+ u32 lcdc_type;
|
||||
+ u32 vop;
|
||||
+ u32 vop_dclk_mode;
|
||||
+ u32 sr_idle_en;
|
||||
+ u32 addr_mcu_el3;
|
||||
+ /*
|
||||
+ * 1: need to wait flag1
|
||||
+ * 0: never wait flag1
|
||||
+ */
|
||||
+ u32 wait_flag1;
|
||||
+ /*
|
||||
+ * 1: need to wait flag1
|
||||
+ * 0: never wait flag1
|
||||
+ */
|
||||
+ u32 wait_flag0;
|
||||
+ u32 complt_hwirq;
|
||||
+ /* if need, add parameter after */
|
||||
+};
|
||||
+
|
||||
+struct rockchip_ddrclk_data {
|
||||
+ u32 inited_flag;
|
||||
+ void __iomem *share_memory;
|
||||
+};
|
||||
+
|
||||
+static struct rockchip_ddrclk_data ddr_data;
|
||||
+
|
||||
+static void rockchip_ddrclk_data_init(void)
|
||||
+{
|
||||
+ struct arm_smccc_res res;
|
||||
+
|
||||
+ arm_smccc_smc(ROCKCHIP_SIP_SHARE_MEM,
|
||||
+ 1, SHARE_PAGE_TYPE_DDR, 0,
|
||||
+ 0, 0, 0, 0, &res);
|
||||
+
|
||||
+ if (!res.a0) {
|
||||
+ ddr_data.share_memory = (void __iomem *)ioremap(res.a1, 1<<12);
|
||||
+ ddr_data.inited_flag = 1;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static int rockchip_ddrclk_sip_set_rate_v2(struct clk_hw *hw,
|
||||
+ unsigned long drate,
|
||||
+ unsigned long prate)
|
||||
+{
|
||||
+ struct share_params *p;
|
||||
+ struct arm_smccc_res res;
|
||||
+
|
||||
+ if (!ddr_data.inited_flag)
|
||||
+ rockchip_ddrclk_data_init();
|
||||
+
|
||||
+ p = (struct share_params *)ddr_data.share_memory;
|
||||
+
|
||||
+ p->hz = drate;
|
||||
+ p->lcdc_type = rk_drm_get_lcdc_type();
|
||||
+ p->wait_flag1 = 1;
|
||||
+ p->wait_flag0 = 1;
|
||||
+
|
||||
+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
|
||||
+ SHARE_PAGE_TYPE_DDR, 0,
|
||||
+ ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE,
|
||||
+ 0, 0, 0, 0, &res);
|
||||
+
|
||||
+ if ((int)res.a1 == -6) {
|
||||
+ pr_err("%s: timeout, drate = %lumhz\n", __func__, drate/1000000);
|
||||
+ /* TODO: rockchip_dmcfreq_wait_complete(); */
|
||||
+ }
|
||||
+
|
||||
+ return res.a0;
|
||||
+}
|
||||
+
|
||||
+static unsigned long rockchip_ddrclk_sip_recalc_rate_v2
|
||||
+ (struct clk_hw *hw, unsigned long parent_rate)
|
||||
+{
|
||||
+ struct arm_smccc_res res;
|
||||
+
|
||||
+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
|
||||
+ SHARE_PAGE_TYPE_DDR, 0,
|
||||
+ ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE,
|
||||
+ 0, 0, 0, 0, &res);
|
||||
+ if (!res.a0)
|
||||
+ return res.a1;
|
||||
+ else
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static long rockchip_ddrclk_sip_round_rate_v2(struct clk_hw *hw,
|
||||
+ unsigned long rate,
|
||||
+ unsigned long *prate)
|
||||
+{
|
||||
+ struct share_params *p;
|
||||
+ struct arm_smccc_res res;
|
||||
+
|
||||
+ if (!ddr_data.inited_flag)
|
||||
+ rockchip_ddrclk_data_init();
|
||||
+
|
||||
+ p = (struct share_params *)ddr_data.share_memory;
|
||||
+
|
||||
+ p->hz = rate;
|
||||
+
|
||||
+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
|
||||
+ SHARE_PAGE_TYPE_DDR, 0,
|
||||
+ ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE,
|
||||
+ 0, 0, 0, 0, &res);
|
||||
+ if (!res.a0)
|
||||
+ return res.a1;
|
||||
+ else
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct clk_ops rockchip_ddrclk_sip_ops_v2 = {
|
||||
+ .recalc_rate = rockchip_ddrclk_sip_recalc_rate_v2,
|
||||
+ .set_rate = rockchip_ddrclk_sip_set_rate_v2,
|
||||
+ .round_rate = rockchip_ddrclk_sip_round_rate_v2,
|
||||
+ .get_parent = rockchip_ddrclk_get_parent,
|
||||
+};
|
||||
+
|
||||
struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
|
||||
const char *const *parent_names,
|
||||
u8 num_parents, int mux_offset,
|
||||
@@ -114,6 +241,9 @@ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
|
||||
case ROCKCHIP_DDRCLK_SIP:
|
||||
init.ops = &rockchip_ddrclk_sip_ops;
|
||||
break;
|
||||
+ case ROCKCHIP_DDRCLK_SIP_V2:
|
||||
+ init.ops = &rockchip_ddrclk_sip_ops_v2;
|
||||
+ break;
|
||||
default:
|
||||
pr_err("%s: unsupported ddrclk type %d\n", __func__, ddr_flag);
|
||||
kfree(ddrclk);
|
||||
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
|
||||
index 1f9176a5c..96393aa16 100644
|
||||
--- a/drivers/clk/rockchip/clk-rk3228.c
|
||||
+++ b/drivers/clk/rockchip/clk-rk3228.c
|
||||
@@ -218,9 +218,9 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
||||
RK2928_CLKSEL_CON(4), 8, 5, DFLAGS),
|
||||
|
||||
/* PD_DDR */
|
||||
- COMPOSITE(0, "clk_ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
|
||||
- RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
|
||||
- RK2928_CLKGATE_CON(0), 2, GFLAGS),
|
||||
+ COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
|
||||
+ RK2928_CLKSEL_CON(26), 8, 2, 0, 2,
|
||||
+ ROCKCHIP_DDRCLK_SIP_V2),
|
||||
GATE(0, "ddrphy4x", "clk_ddrphy_src", CLK_IGNORE_UNUSED,
|
||||
RK2928_CLKGATE_CON(7), 1, GFLAGS),
|
||||
FACTOR_GATE(0, "ddrc", "clk_ddrphy_src", CLK_IGNORE_UNUSED, 1, 4,
|
||||
@@ -576,8 +576,8 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
|
||||
GATE(HCLK_M_CRYPTO, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
|
||||
GATE(HCLK_S_CRYPTO, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
|
||||
|
||||
- GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
|
||||
- GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
|
||||
+ GATE(0, "pclk_ddr_upctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
|
||||
+ GATE(0, "pclk_ddr_mon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
|
||||
GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(10), 2, GFLAGS),
|
||||
|
||||
GATE(PCLK_EFUSE_1024, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
|
||||
@@ -652,8 +652,8 @@ static const char *const rk3228_critical_clocks[] __initconst = {
|
||||
"sclk_initmem_mbist",
|
||||
"aclk_initmem",
|
||||
"hclk_rom",
|
||||
- "pclk_ddrupctl",
|
||||
- "pclk_ddrmon",
|
||||
+ "pclk_ddr_upctl",
|
||||
+ "pclk_ddr_mon",
|
||||
"pclk_msch_noc",
|
||||
"pclk_stimer",
|
||||
"pclk_ddrphy",
|
||||
diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
|
||||
index cc18dbc18..5fdd611bb 100644
|
||||
--- a/drivers/clk/rockchip/clk-rk3328.c
|
||||
+++ b/drivers/clk/rockchip/clk-rk3328.c
|
||||
@@ -317,9 +317,10 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
|
||||
RK3328_CLKGATE_CON(14), 1, GFLAGS),
|
||||
|
||||
/* PD_DDR */
|
||||
- COMPOSITE(0, "clk_ddr", mux_ddrphy_p, CLK_IGNORE_UNUSED,
|
||||
- RK3328_CLKSEL_CON(3), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
|
||||
- RK3328_CLKGATE_CON(0), 4, GFLAGS),
|
||||
+ COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
|
||||
+ RK3328_CLKSEL_CON(3), 8, 2, 0, 3,
|
||||
+ ROCKCHIP_DDRCLK_SIP_V2),
|
||||
+
|
||||
GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(18), 6, GFLAGS),
|
||||
GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
|
||||
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
|
||||
index ae059b774..fdaa81ebb 100644
|
||||
--- a/drivers/clk/rockchip/clk.h
|
||||
+++ b/drivers/clk/rockchip/clk.h
|
||||
@@ -363,7 +363,8 @@ struct clk *rockchip_clk_register_mmc(const char *name,
|
||||
* DDRCLK flags, including method of setting the rate
|
||||
* ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
|
||||
*/
|
||||
-#define ROCKCHIP_DDRCLK_SIP BIT(0)
|
||||
+#define ROCKCHIP_DDRCLK_SIP 0x01
|
||||
+#define ROCKCHIP_DDRCLK_SIP_V2 0x03
|
||||
|
||||
struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
|
||||
const char *const *parent_names,
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,67 @@
|
||||
From 95358ea4a4434ad4af5545b3f762508e4f015fc3 Mon Sep 17 00:00:00 2001
|
||||
From: Paolo Sabatino <paolo.sabatino@gmail.com>
|
||||
Date: Tue, 6 Jul 2021 14:23:36 +0000
|
||||
Subject: [PATCH 2/5] rk3228/rk3328: add ddr clock and SIP related constants
|
||||
and defines
|
||||
|
||||
---
|
||||
include/dt-bindings/clock/rk3228-cru.h | 1 +
|
||||
include/soc/rockchip/rockchip_sip.h | 24 ++++++++++++++++++++++++
|
||||
2 files changed, 25 insertions(+)
|
||||
|
||||
diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
|
||||
index de550ea56..911824731 100644
|
||||
--- a/include/dt-bindings/clock/rk3228-cru.h
|
||||
+++ b/include/dt-bindings/clock/rk3228-cru.h
|
||||
@@ -15,6 +15,7 @@
|
||||
#define ARMCLK 5
|
||||
|
||||
/* sclk gates (special clocks) */
|
||||
+#define SCLK_DDRCLK 64
|
||||
#define SCLK_SPI0 65
|
||||
#define SCLK_NANDC 67
|
||||
#define SCLK_SDMMC 68
|
||||
diff --git a/include/soc/rockchip/rockchip_sip.h b/include/soc/rockchip/rockchip_sip.h
|
||||
index c46a9ae2a..34e653751 100644
|
||||
--- a/include/soc/rockchip/rockchip_sip.h
|
||||
+++ b/include/soc/rockchip/rockchip_sip.h
|
||||
@@ -6,6 +6,7 @@
|
||||
#ifndef __SOC_ROCKCHIP_SIP_H
|
||||
#define __SOC_ROCKCHIP_SIP_H
|
||||
|
||||
+#define ROCKCHIP_SIP_ATF_VERSION 0x82000001
|
||||
#define ROCKCHIP_SIP_DRAM_FREQ 0x82000008
|
||||
#define ROCKCHIP_SIP_CONFIG_DRAM_INIT 0x00
|
||||
#define ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE 0x01
|
||||
@@ -16,5 +17,28 @@
|
||||
#define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ 0x06
|
||||
#define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM 0x07
|
||||
#define ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD 0x08
|
||||
+#define ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION 0x08
|
||||
+#define ROCKCHIP_SIP_CONFIG_DRAM_POST_SET_RATE 0x09
|
||||
+#define ROCKCHIP_SIP_CONFIG_DRAM_SET_MSCH_RL 0x0a
|
||||
+#define ROCKCHIP_SIP_CONFIG_DRAM_DEBUG 0x0b
|
||||
+
|
||||
+#define ROCKCHIP_SIP_SHARE_MEM 0x82000009
|
||||
+#define ROCKCHIP_SIP_SIP_VERSION 0x8200000a
|
||||
+
|
||||
+/* Rockchip Sip version */
|
||||
+#define ROCKCHIP_SIP_IMPLEMENT_V1 (1)
|
||||
+#define ROCKCHIP_SIP_IMPLEMENT_V2 (2)
|
||||
+
|
||||
+/* SIP_ACCESS_REG: read or write */
|
||||
+#define SECURE_REG_RD 0x0
|
||||
+#define SECURE_REG_WR 0x1
|
||||
+
|
||||
+/* Share mem page types */
|
||||
+typedef enum {
|
||||
+ SHARE_PAGE_TYPE_INVALID = 0,
|
||||
+ SHARE_PAGE_TYPE_UARTDBG,
|
||||
+ SHARE_PAGE_TYPE_DDR,
|
||||
+ SHARE_PAGE_TYPE_MAX,
|
||||
+} share_page_type_t;
|
||||
|
||||
#endif
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,745 @@
|
||||
From 415ed43c9b64ca38bc433bd5dc0359292dd80380 Mon Sep 17 00:00:00 2001
|
||||
From: Paolo Sabatino <paolo.sabatino@gmail.com>
|
||||
Date: Tue, 6 Jul 2021 14:25:41 +0000
|
||||
Subject: [PATCH 3/5] rk3228/rk3328: extend rockchip dfi driver
|
||||
|
||||
---
|
||||
arch/arm/boot/dts/rk322x.dtsi | 7 +
|
||||
drivers/devfreq/event/rockchip-dfi.c | 598 ++++++++++++++++++++++++---
|
||||
2 files changed, 557 insertions(+), 48 deletions(-)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
|
||||
index ad98fcf37..7e06acc31 100644
|
||||
--- a/arch/arm/boot/dts/rk322x.dtsi
|
||||
+++ b/arch/arm/boot/dts/rk322x.dtsi
|
||||
@@ -97,6 +97,13 @@ opp-1200000000 {
|
||||
};
|
||||
};
|
||||
|
||||
+ dfi: dfi@11210000 {
|
||||
+ reg = <0x11210000 0x400>;
|
||||
+ compatible = "rockchip,rk3228-dfi";
|
||||
+ rockchip,grf = <&grf>;
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
arm-pmu {
|
||||
compatible = "arm,cortex-a7-pmu";
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
|
||||
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
|
||||
index 9a88faaf8..01fb84b99 100644
|
||||
--- a/drivers/devfreq/event/rockchip-dfi.c
|
||||
+++ b/drivers/devfreq/event/rockchip-dfi.c
|
||||
@@ -18,25 +18,68 @@
|
||||
#include <linux/list.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
-#include <soc/rockchip/rk3399_grf.h>
|
||||
-
|
||||
-#define RK3399_DMC_NUM_CH 2
|
||||
-
|
||||
+#define PX30_PMUGRF_OS_REG2 0x208
|
||||
+
|
||||
+#define RK3128_GRF_SOC_CON0 0x140
|
||||
+#define RK3128_GRF_OS_REG1 0x1cc
|
||||
+#define RK3128_GRF_DFI_WRNUM 0x220
|
||||
+#define RK3128_GRF_DFI_RDNUM 0x224
|
||||
+#define RK3128_GRF_DFI_TIMERVAL 0x22c
|
||||
+#define RK3128_DDR_MONITOR_EN ((1 << (16 + 6)) + (1 << 6))
|
||||
+#define RK3128_DDR_MONITOR_DISB ((1 << (16 + 6)) + (0 << 6))
|
||||
+
|
||||
+#define RK3228_GRF_OS_REG2 0x5d0
|
||||
+
|
||||
+#define RK3288_PMU_SYS_REG2 0x9c
|
||||
+#define RK3288_GRF_SOC_CON4 0x254
|
||||
+#define RK3288_GRF_SOC_STATUS(n) (0x280 + (n) * 4)
|
||||
+#define RK3288_DFI_EN (0x30003 << 14)
|
||||
+#define RK3288_DFI_DIS (0x30000 << 14)
|
||||
+#define RK3288_LPDDR_SEL (0x10001 << 13)
|
||||
+#define RK3288_DDR3_SEL (0x10000 << 13)
|
||||
+
|
||||
+#define RK3328_GRF_OS_REG2 0x5d0
|
||||
+
|
||||
+#define RK3368_GRF_DDRC0_CON0 0x600
|
||||
+#define RK3368_GRF_SOC_STATUS5 0x494
|
||||
+#define RK3368_GRF_SOC_STATUS6 0x498
|
||||
+#define RK3368_GRF_SOC_STATUS8 0x4a0
|
||||
+#define RK3368_GRF_SOC_STATUS9 0x4a4
|
||||
+#define RK3368_GRF_SOC_STATUS10 0x4a8
|
||||
+#define RK3368_DFI_EN (0x30003 << 5)
|
||||
+#define RK3368_DFI_DIS (0x30000 << 5)
|
||||
+
|
||||
+#define MAX_DMC_NUM_CH 2
|
||||
+#define READ_DRAMTYPE_INFO(n) (((n) >> 13) & 0x7)
|
||||
+#define READ_CH_INFO(n) (((n) >> 28) & 0x3)
|
||||
/* DDRMON_CTRL */
|
||||
-#define DDRMON_CTRL 0x04
|
||||
-#define CLR_DDRMON_CTRL (0x1f0000 << 0)
|
||||
-#define LPDDR4_EN (0x10001 << 4)
|
||||
-#define HARDWARE_EN (0x10001 << 3)
|
||||
-#define LPDDR3_EN (0x10001 << 2)
|
||||
-#define SOFTWARE_EN (0x10001 << 1)
|
||||
-#define SOFTWARE_DIS (0x10000 << 1)
|
||||
-#define TIME_CNT_EN (0x10001 << 0)
|
||||
+#define DDRMON_CTRL 0x04
|
||||
+#define CLR_DDRMON_CTRL (0x3f0000 << 0)
|
||||
+#define DDR4_EN (0x10001 << 5)
|
||||
+#define LPDDR4_EN (0x10001 << 4)
|
||||
+#define HARDWARE_EN (0x10001 << 3)
|
||||
+#define LPDDR2_3_EN (0x10001 << 2)
|
||||
+#define SOFTWARE_EN (0x10001 << 1)
|
||||
+#define SOFTWARE_DIS (0x10000 << 1)
|
||||
+#define TIME_CNT_EN (0x10001 << 0)
|
||||
|
||||
#define DDRMON_CH0_COUNT_NUM 0x28
|
||||
#define DDRMON_CH0_DFI_ACCESS_NUM 0x2c
|
||||
#define DDRMON_CH1_COUNT_NUM 0x3c
|
||||
#define DDRMON_CH1_DFI_ACCESS_NUM 0x40
|
||||
|
||||
+/* pmu grf */
|
||||
+#define PMUGRF_OS_REG2 0x308
|
||||
+
|
||||
+enum {
|
||||
+ DDR4 = 0,
|
||||
+ DDR3 = 3,
|
||||
+ LPDDR2 = 5,
|
||||
+ LPDDR3 = 6,
|
||||
+ LPDDR4 = 7,
|
||||
+ UNUSED = 0xFF
|
||||
+};
|
||||
+
|
||||
struct dmc_usage {
|
||||
u32 access;
|
||||
u32 total;
|
||||
@@ -50,33 +93,261 @@ struct dmc_usage {
|
||||
struct rockchip_dfi {
|
||||
struct devfreq_event_dev *edev;
|
||||
struct devfreq_event_desc *desc;
|
||||
- struct dmc_usage ch_usage[RK3399_DMC_NUM_CH];
|
||||
+ struct dmc_usage ch_usage[MAX_DMC_NUM_CH];
|
||||
struct device *dev;
|
||||
void __iomem *regs;
|
||||
struct regmap *regmap_pmu;
|
||||
+ struct regmap *regmap_grf;
|
||||
+ struct regmap *regmap_pmugrf;
|
||||
struct clk *clk;
|
||||
+ u32 dram_type;
|
||||
+ /*
|
||||
+ * available mask, 1: available, 0: not available
|
||||
+ * each bit represent a channel
|
||||
+ */
|
||||
+ u32 ch_msk;
|
||||
+};
|
||||
+
|
||||
+static void rk3128_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+
|
||||
+ regmap_write(info->regmap_grf,
|
||||
+ RK3128_GRF_SOC_CON0,
|
||||
+ RK3128_DDR_MONITOR_EN);
|
||||
+}
|
||||
+
|
||||
+static void rk3128_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+
|
||||
+ regmap_write(info->regmap_grf,
|
||||
+ RK3128_GRF_SOC_CON0,
|
||||
+ RK3128_DDR_MONITOR_DISB);
|
||||
+}
|
||||
+
|
||||
+static int rk3128_dfi_disable(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ rk3128_dfi_stop_hardware_counter(edev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3128_dfi_enable(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ rk3128_dfi_start_hardware_counter(edev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3128_dfi_set_event(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3128_dfi_get_event(struct devfreq_event_dev *edev,
|
||||
+ struct devfreq_event_data *edata)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+ unsigned long flags;
|
||||
+ u32 dfi_wr, dfi_rd, dfi_timer;
|
||||
+
|
||||
+ local_irq_save(flags);
|
||||
+
|
||||
+ rk3128_dfi_stop_hardware_counter(edev);
|
||||
+
|
||||
+ regmap_read(info->regmap_grf, RK3128_GRF_DFI_WRNUM, &dfi_wr);
|
||||
+ regmap_read(info->regmap_grf, RK3128_GRF_DFI_RDNUM, &dfi_rd);
|
||||
+ regmap_read(info->regmap_grf, RK3128_GRF_DFI_TIMERVAL, &dfi_timer);
|
||||
+
|
||||
+ edata->load_count = (dfi_wr + dfi_rd) * 4;
|
||||
+ edata->total_count = dfi_timer;
|
||||
+
|
||||
+ rk3128_dfi_start_hardware_counter(edev);
|
||||
+
|
||||
+ local_irq_restore(flags);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct devfreq_event_ops rk3128_dfi_ops = {
|
||||
+ .disable = rk3128_dfi_disable,
|
||||
+ .enable = rk3128_dfi_enable,
|
||||
+ .get_event = rk3128_dfi_get_event,
|
||||
+ .set_event = rk3128_dfi_set_event,
|
||||
+};
|
||||
+
|
||||
+static void rk3288_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+
|
||||
+ regmap_write(info->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_EN);
|
||||
+}
|
||||
+
|
||||
+static void rk3288_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+
|
||||
+ regmap_write(info->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_DIS);
|
||||
+}
|
||||
+
|
||||
+static int rk3288_dfi_disable(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ rk3288_dfi_stop_hardware_counter(edev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3288_dfi_enable(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ rk3288_dfi_start_hardware_counter(edev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3288_dfi_set_event(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3288_dfi_get_busier_ch(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+ u32 tmp, max = 0;
|
||||
+ u32 i, busier_ch = 0;
|
||||
+ u32 rd_count, wr_count, total_count;
|
||||
+
|
||||
+ rk3288_dfi_stop_hardware_counter(edev);
|
||||
+
|
||||
+ /* Find out which channel is busier */
|
||||
+ for (i = 0; i < MAX_DMC_NUM_CH; i++) {
|
||||
+ if (!(info->ch_msk & BIT(i)))
|
||||
+ continue;
|
||||
+ regmap_read(info->regmap_grf,
|
||||
+ RK3288_GRF_SOC_STATUS(11 + i * 4), &wr_count);
|
||||
+ regmap_read(info->regmap_grf,
|
||||
+ RK3288_GRF_SOC_STATUS(12 + i * 4), &rd_count);
|
||||
+ regmap_read(info->regmap_grf,
|
||||
+ RK3288_GRF_SOC_STATUS(14 + i * 4), &total_count);
|
||||
+ info->ch_usage[i].access = (wr_count + rd_count) * 4;
|
||||
+ info->ch_usage[i].total = total_count;
|
||||
+ tmp = info->ch_usage[i].access;
|
||||
+ if (tmp > max) {
|
||||
+ busier_ch = i;
|
||||
+ max = tmp;
|
||||
+ }
|
||||
+ }
|
||||
+ rk3288_dfi_start_hardware_counter(edev);
|
||||
+
|
||||
+ return busier_ch;
|
||||
+}
|
||||
+
|
||||
+static int rk3288_dfi_get_event(struct devfreq_event_dev *edev,
|
||||
+ struct devfreq_event_data *edata)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+ int busier_ch;
|
||||
+ unsigned long flags;
|
||||
+
|
||||
+ local_irq_save(flags);
|
||||
+ busier_ch = rk3288_dfi_get_busier_ch(edev);
|
||||
+ local_irq_restore(flags);
|
||||
+
|
||||
+ edata->load_count = info->ch_usage[busier_ch].access;
|
||||
+ edata->total_count = info->ch_usage[busier_ch].total;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct devfreq_event_ops rk3288_dfi_ops = {
|
||||
+ .disable = rk3288_dfi_disable,
|
||||
+ .enable = rk3288_dfi_enable,
|
||||
+ .get_event = rk3288_dfi_get_event,
|
||||
+ .set_event = rk3288_dfi_set_event,
|
||||
+};
|
||||
+
|
||||
+static void rk3368_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+
|
||||
+ regmap_write(info->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_EN);
|
||||
+}
|
||||
+
|
||||
+static void rk3368_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+
|
||||
+ regmap_write(info->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_DIS);
|
||||
+}
|
||||
+
|
||||
+static int rk3368_dfi_disable(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ rk3368_dfi_stop_hardware_counter(edev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3368_dfi_enable(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ rk3368_dfi_start_hardware_counter(edev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3368_dfi_set_event(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3368_dfi_get_event(struct devfreq_event_dev *edev,
|
||||
+ struct devfreq_event_data *edata)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+ unsigned long flags;
|
||||
+ u32 dfi0_wr, dfi0_rd, dfi1_wr, dfi1_rd, dfi_timer;
|
||||
+
|
||||
+ local_irq_save(flags);
|
||||
+
|
||||
+ rk3368_dfi_stop_hardware_counter(edev);
|
||||
+
|
||||
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS5, &dfi0_wr);
|
||||
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS6, &dfi0_rd);
|
||||
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS9, &dfi1_wr);
|
||||
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS10, &dfi1_rd);
|
||||
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS8, &dfi_timer);
|
||||
+
|
||||
+ edata->load_count = (dfi0_wr + dfi0_rd + dfi1_wr + dfi1_rd) * 2;
|
||||
+ edata->total_count = dfi_timer;
|
||||
+
|
||||
+ rk3368_dfi_start_hardware_counter(edev);
|
||||
+
|
||||
+ local_irq_restore(flags);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct devfreq_event_ops rk3368_dfi_ops = {
|
||||
+ .disable = rk3368_dfi_disable,
|
||||
+ .enable = rk3368_dfi_enable,
|
||||
+ .get_event = rk3368_dfi_get_event,
|
||||
+ .set_event = rk3368_dfi_set_event,
|
||||
};
|
||||
|
||||
static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
|
||||
{
|
||||
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
void __iomem *dfi_regs = info->regs;
|
||||
- u32 val;
|
||||
- u32 ddr_type;
|
||||
-
|
||||
- /* get ddr type */
|
||||
- regmap_read(info->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
|
||||
- ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
|
||||
- RK3399_PMUGRF_DDRTYPE_MASK;
|
||||
|
||||
/* clear DDRMON_CTRL setting */
|
||||
writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
|
||||
|
||||
/* set ddr type to dfi */
|
||||
- if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3)
|
||||
- writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
|
||||
- else if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4)
|
||||
+ if (info->dram_type == LPDDR3 || info->dram_type == LPDDR2)
|
||||
+ writel_relaxed(LPDDR2_3_EN, dfi_regs + DDRMON_CTRL);
|
||||
+ else if (info->dram_type == LPDDR4)
|
||||
writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
|
||||
+ else if (info->dram_type == DDR4)
|
||||
+ writel_relaxed(DDR4_EN, dfi_regs + DDRMON_CTRL);
|
||||
|
||||
/* enable count, use software mode */
|
||||
writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);
|
||||
@@ -100,12 +371,22 @@ static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev)
|
||||
rockchip_dfi_stop_hardware_counter(edev);
|
||||
|
||||
/* Find out which channel is busier */
|
||||
- for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
|
||||
- info->ch_usage[i].access = readl_relaxed(dfi_regs +
|
||||
- DDRMON_CH0_DFI_ACCESS_NUM + i * 20) * 4;
|
||||
+ for (i = 0; i < MAX_DMC_NUM_CH; i++) {
|
||||
+ if (!(info->ch_msk & BIT(i)))
|
||||
+ continue;
|
||||
+
|
||||
info->ch_usage[i].total = readl_relaxed(dfi_regs +
|
||||
DDRMON_CH0_COUNT_NUM + i * 20);
|
||||
- tmp = info->ch_usage[i].access;
|
||||
+
|
||||
+ /* LPDDR4 BL = 16,other DDR type BL = 8 */
|
||||
+ tmp = readl_relaxed(dfi_regs +
|
||||
+ DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
|
||||
+ if (info->dram_type == LPDDR4)
|
||||
+ tmp *= 8;
|
||||
+ else
|
||||
+ tmp *= 4;
|
||||
+ info->ch_usage[i].access = tmp;
|
||||
+
|
||||
if (tmp > max) {
|
||||
busier_ch = i;
|
||||
max = tmp;
|
||||
@@ -118,10 +399,14 @@ static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev)
|
||||
|
||||
static int rockchip_dfi_disable(struct devfreq_event_dev *edev)
|
||||
{
|
||||
+ struct device *dev = &edev->dev;
|
||||
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
|
||||
rockchip_dfi_stop_hardware_counter(edev);
|
||||
- clk_disable_unprepare(info->clk);
|
||||
+ if (info->clk)
|
||||
+ clk_disable_unprepare(info->clk);
|
||||
+
|
||||
+ dev_notice(dev,"Rockchip DFI interface disabled\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -129,20 +414,28 @@ static int rockchip_dfi_disable(struct devfreq_event_dev *edev)
|
||||
static int rockchip_dfi_enable(struct devfreq_event_dev *edev)
|
||||
{
|
||||
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+ struct device *dev = &edev->dev;
|
||||
int ret;
|
||||
|
||||
- ret = clk_prepare_enable(info->clk);
|
||||
- if (ret) {
|
||||
- dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ret);
|
||||
- return ret;
|
||||
+ if (info->clk) {
|
||||
+ ret = clk_prepare_enable(info->clk);
|
||||
+ if (ret) {
|
||||
+ dev_err(&edev->dev, "failed to enable dfi clk: %d\n",
|
||||
+ ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
}
|
||||
|
||||
rockchip_dfi_start_hardware_counter(edev);
|
||||
+
|
||||
+ dev_notice(dev,"Rockchip DFI interface enabled\n");
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_dfi_set_event(struct devfreq_event_dev *edev)
|
||||
{
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -151,8 +444,11 @@ static int rockchip_dfi_get_event(struct devfreq_event_dev *edev,
|
||||
{
|
||||
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
int busier_ch;
|
||||
+ unsigned long flags;
|
||||
|
||||
+ local_irq_save(flags);
|
||||
busier_ch = rockchip_dfi_get_busier_ch(edev);
|
||||
+ local_irq_restore(flags);
|
||||
|
||||
edata->load_count = info->ch_usage[busier_ch].access;
|
||||
edata->total_count = info->ch_usage[busier_ch].total;
|
||||
@@ -167,22 +463,151 @@ static const struct devfreq_event_ops rockchip_dfi_ops = {
|
||||
.set_event = rockchip_dfi_set_event,
|
||||
};
|
||||
|
||||
-static const struct of_device_id rockchip_dfi_id_match[] = {
|
||||
- { .compatible = "rockchip,rk3399-dfi" },
|
||||
- { },
|
||||
-};
|
||||
-MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);
|
||||
+static __init int px30_dfi_init(struct platform_device *pdev,
|
||||
+ struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc)
|
||||
+{
|
||||
+ struct device_node *np = pdev->dev.of_node, *node;
|
||||
+ struct resource *res;
|
||||
+ u32 val;
|
||||
|
||||
-static int rockchip_dfi_probe(struct platform_device *pdev)
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ data->regs = devm_ioremap_resource(&pdev->dev, res);
|
||||
+ if (IS_ERR(data->regs))
|
||||
+ return PTR_ERR(data->regs);
|
||||
+
|
||||
+ node = of_parse_phandle(np, "rockchip,pmugrf", 0);
|
||||
+ if (node) {
|
||||
+ data->regmap_pmugrf = syscon_node_to_regmap(node);
|
||||
+ if (IS_ERR(data->regmap_pmugrf))
|
||||
+ return PTR_ERR(data->regmap_pmugrf);
|
||||
+ }
|
||||
+
|
||||
+ regmap_read(data->regmap_pmugrf, PX30_PMUGRF_OS_REG2, &val);
|
||||
+ data->dram_type = READ_DRAMTYPE_INFO(val);
|
||||
+ data->ch_msk = 1;
|
||||
+ data->clk = NULL;
|
||||
+
|
||||
+ desc->ops = &rockchip_dfi_ops;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static __init int rk3128_dfi_init(struct platform_device *pdev,
|
||||
+ struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc)
|
||||
+{
|
||||
+ struct device_node *np = pdev->dev.of_node, *node;
|
||||
+
|
||||
+ node = of_parse_phandle(np, "rockchip,grf", 0);
|
||||
+ if (node) {
|
||||
+ data->regmap_grf = syscon_node_to_regmap(node);
|
||||
+ if (IS_ERR(data->regmap_grf))
|
||||
+ return PTR_ERR(data->regmap_grf);
|
||||
+ }
|
||||
+
|
||||
+ desc->ops = &rk3128_dfi_ops;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static __init int rk3228_dfi_init(struct platform_device *pdev,
|
||||
+ struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc)
|
||||
{
|
||||
+ struct device_node *np = pdev->dev.of_node, *node;
|
||||
+ struct resource *res;
|
||||
struct device *dev = &pdev->dev;
|
||||
- struct rockchip_dfi *data;
|
||||
- struct devfreq_event_desc *desc;
|
||||
+ u32 val;
|
||||
+
|
||||
+ dev_notice(dev,"rk3228_dfi_init enter\n");
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ data->regs = devm_ioremap_resource(&pdev->dev, res);
|
||||
+ if (IS_ERR(data->regs))
|
||||
+ return PTR_ERR(data->regs);
|
||||
+
|
||||
+ node = of_parse_phandle(np, "rockchip,grf", 0);
|
||||
+ if (node) {
|
||||
+ data->regmap_grf = syscon_node_to_regmap(node);
|
||||
+ if (IS_ERR(data->regmap_grf))
|
||||
+ return PTR_ERR(data->regmap_grf);
|
||||
+ }
|
||||
+
|
||||
+ regmap_read(data->regmap_grf, RK3228_GRF_OS_REG2, &val);
|
||||
+ data->dram_type = READ_DRAMTYPE_INFO(val);
|
||||
+ data->ch_msk = 1;
|
||||
+ data->clk = NULL;
|
||||
+
|
||||
+ desc->ops = &rockchip_dfi_ops;
|
||||
+
|
||||
+ dev_notice(dev,"rk3228-dfi initialized, dram type: 0x%x, channels: %d\n", data->dram_type, data->ch_msk);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static __init int rk3288_dfi_init(struct platform_device *pdev,
|
||||
+ struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc)
|
||||
+{
|
||||
struct device_node *np = pdev->dev.of_node, *node;
|
||||
+ u32 val;
|
||||
|
||||
- data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
|
||||
- if (!data)
|
||||
- return -ENOMEM;
|
||||
+ node = of_parse_phandle(np, "rockchip,pmu", 0);
|
||||
+ if (node) {
|
||||
+ data->regmap_pmu = syscon_node_to_regmap(node);
|
||||
+ if (IS_ERR(data->regmap_pmu))
|
||||
+ return PTR_ERR(data->regmap_pmu);
|
||||
+ }
|
||||
+
|
||||
+ node = of_parse_phandle(np, "rockchip,grf", 0);
|
||||
+ if (node) {
|
||||
+ data->regmap_grf = syscon_node_to_regmap(node);
|
||||
+ if (IS_ERR(data->regmap_grf))
|
||||
+ return PTR_ERR(data->regmap_grf);
|
||||
+ }
|
||||
+
|
||||
+ regmap_read(data->regmap_pmu, RK3288_PMU_SYS_REG2, &val);
|
||||
+ data->dram_type = READ_DRAMTYPE_INFO(val);
|
||||
+ data->ch_msk = READ_CH_INFO(val);
|
||||
+
|
||||
+ if (data->dram_type == DDR3)
|
||||
+ regmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4,
|
||||
+ RK3288_DDR3_SEL);
|
||||
+ else
|
||||
+ regmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4,
|
||||
+ RK3288_LPDDR_SEL);
|
||||
+
|
||||
+ desc->ops = &rk3288_dfi_ops;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static __init int rk3368_dfi_init(struct platform_device *pdev,
|
||||
+ struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc)
|
||||
+{
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+
|
||||
+ if (!dev->parent || !dev->parent->of_node)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ data->regmap_grf = syscon_node_to_regmap(dev->parent->of_node);
|
||||
+ if (IS_ERR(data->regmap_grf))
|
||||
+ return PTR_ERR(data->regmap_grf);
|
||||
+
|
||||
+ desc->ops = &rk3368_dfi_ops;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static __init int rockchip_dfi_init(struct platform_device *pdev,
|
||||
+ struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc)
|
||||
+{
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ struct device_node *np = pdev->dev.of_node, *node;
|
||||
+ u32 val;
|
||||
|
||||
data->regs = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(data->regs))
|
||||
@@ -202,21 +627,98 @@ static int rockchip_dfi_probe(struct platform_device *pdev)
|
||||
if (IS_ERR(data->regmap_pmu))
|
||||
return PTR_ERR(data->regmap_pmu);
|
||||
}
|
||||
- data->dev = dev;
|
||||
+
|
||||
+ regmap_read(data->regmap_pmu, PMUGRF_OS_REG2, &val);
|
||||
+ data->dram_type = READ_DRAMTYPE_INFO(val);
|
||||
+ data->ch_msk = READ_CH_INFO(val);
|
||||
+
|
||||
+ desc->ops = &rockchip_dfi_ops;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static __init int rk3328_dfi_init(struct platform_device *pdev,
|
||||
+ struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc)
|
||||
+{
|
||||
+ struct device_node *np = pdev->dev.of_node, *node;
|
||||
+ struct resource *res;
|
||||
+ u32 val;
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ data->regs = devm_ioremap_resource(&pdev->dev, res);
|
||||
+ if (IS_ERR(data->regs))
|
||||
+ return PTR_ERR(data->regs);
|
||||
+
|
||||
+ node = of_parse_phandle(np, "rockchip,grf", 0);
|
||||
+ if (node) {
|
||||
+ data->regmap_grf = syscon_node_to_regmap(node);
|
||||
+ if (IS_ERR(data->regmap_grf))
|
||||
+ return PTR_ERR(data->regmap_grf);
|
||||
+ }
|
||||
+
|
||||
+ regmap_read(data->regmap_grf, RK3328_GRF_OS_REG2, &val);
|
||||
+ data->dram_type = READ_DRAMTYPE_INFO(val);
|
||||
+ data->ch_msk = 1;
|
||||
+ data->clk = NULL;
|
||||
+
|
||||
+ desc->ops = &rockchip_dfi_ops;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id rockchip_dfi_id_match[] = {
|
||||
+ { .compatible = "rockchip,px30-dfi", .data = px30_dfi_init },
|
||||
+ { .compatible = "rockchip,rk1808-dfi", .data = px30_dfi_init },
|
||||
+ { .compatible = "rockchip,rk3128-dfi", .data = rk3128_dfi_init },
|
||||
+ { .compatible = "rockchip,rk3228-dfi", .data = rk3228_dfi_init },
|
||||
+ { .compatible = "rockchip,rk3288-dfi", .data = rk3288_dfi_init },
|
||||
+ { .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init },
|
||||
+ { .compatible = "rockchip,rk3368-dfi", .data = rk3368_dfi_init },
|
||||
+ { .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init },
|
||||
+ { },
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);
|
||||
+
|
||||
+static int rockchip_dfi_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ struct rockchip_dfi *data;
|
||||
+ struct devfreq_event_desc *desc;
|
||||
+ struct device_node *np = pdev->dev.of_node;
|
||||
+ const struct of_device_id *match;
|
||||
+ int (*init)(struct platform_device *pdev, struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc);
|
||||
+
|
||||
+ data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
|
||||
+ if (!data)
|
||||
+ return -ENOMEM;
|
||||
|
||||
desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
|
||||
if (!desc)
|
||||
return -ENOMEM;
|
||||
|
||||
- desc->ops = &rockchip_dfi_ops;
|
||||
+ match = of_match_node(rockchip_dfi_id_match, pdev->dev.of_node);
|
||||
+ if (match) {
|
||||
+ init = match->data;
|
||||
+ if (init) {
|
||||
+ if (init(pdev, data, desc))
|
||||
+ return -EINVAL;
|
||||
+ } else {
|
||||
+ return 0;
|
||||
+ }
|
||||
+ } else {
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
desc->driver_data = data;
|
||||
desc->name = np->name;
|
||||
data->desc = desc;
|
||||
+ data->dev = dev;
|
||||
|
||||
- data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
|
||||
+ data->edev = devm_devfreq_event_add_edev(dev, desc);
|
||||
if (IS_ERR(data->edev)) {
|
||||
- dev_err(&pdev->dev,
|
||||
- "failed to add devfreq-event device\n");
|
||||
+ dev_err(dev, "failed to add devfreq-event device\n");
|
||||
return PTR_ERR(data->edev);
|
||||
}
|
||||
|
||||
--
|
||||
2.25.1
|
||||
|
||||
|
||||
1936
patch/kernel/archive/rk322x-5.16/03-0004-add-dmc-driver.patch
Normal file
1936
patch/kernel/archive/rk322x-5.16/03-0004-add-dmc-driver.patch
Normal file
File diff suppressed because it is too large
Load Diff
13
patch/kernel/archive/rk322x-5.16/1027-fix-rga-probe.patch
Normal file
13
patch/kernel/archive/rk322x-5.16/1027-fix-rga-probe.patch
Normal file
@ -0,0 +1,13 @@
|
||||
diff --git a/drivers/media/platform/rockchip/rga/rga.c b/drivers/media/platform/rockchip/rga/rga.c
|
||||
index 6759091b1..d99ea8973 100644
|
||||
--- a/drivers/media/platform/rockchip/rga/rga.c
|
||||
+++ b/drivers/media/platform/rockchip/rga/rga.c
|
||||
@@ -895,7 +895,7 @@ static int rga_probe(struct platform_device *pdev)
|
||||
}
|
||||
rga->dst_mmu_pages =
|
||||
(unsigned int *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 3);
|
||||
- if (rga->dst_mmu_pages) {
|
||||
+ if (!rga->dst_mmu_pages) {
|
||||
ret = -ENOMEM;
|
||||
goto free_src_pages;
|
||||
}
|
||||
@ -0,0 +1,333 @@
|
||||
From ff9a0ab9d920d4a855b4be9912a57ac65e8906e2 Mon Sep 17 00:00:00 2001
|
||||
From: Paolo Sabatino <paolo.sabatino@gmail.com>
|
||||
Date: Fri, 10 Sep 2021 14:10:18 +0000
|
||||
Subject: [PATCH] drm rockchip hardware cursor
|
||||
|
||||
---
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 218 +++++++++++++++++++-
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 3 +
|
||||
drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 19 +-
|
||||
3 files changed, 238 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
|
||||
index 83a926c0a..b0832320e 100644
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
|
||||
@@ -1160,6 +1160,207 @@ static void vop_plane_atomic_async_update(struct drm_plane *plane,
|
||||
}
|
||||
}
|
||||
|
||||
+static void vop_cursor_atomic_update(struct drm_plane *plane,
|
||||
+ struct drm_atomic_state *state)
|
||||
+{
|
||||
+
|
||||
+ struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
|
||||
+ plane);
|
||||
+ struct drm_crtc *crtc = new_state->crtc;
|
||||
+ struct vop_win *vop_win = to_vop_win(plane);
|
||||
+ const struct vop_win_data *win = vop_win->data;
|
||||
+ struct vop *vop = to_vop(new_state->crtc);
|
||||
+ struct drm_framebuffer *fb = new_state->fb;
|
||||
+ unsigned int actual_w, actual_h;
|
||||
+ unsigned int dsp_stx, dsp_sty;
|
||||
+ uint32_t dsp_st;
|
||||
+ struct drm_rect *src = &new_state->src;
|
||||
+ struct drm_rect *dest = &new_state->dst;
|
||||
+ struct drm_gem_object *obj;
|
||||
+ struct rockchip_gem_object *rk_obj;
|
||||
+ dma_addr_t dma_addr;
|
||||
+ uint32_t val;
|
||||
+ bool rb_swap;
|
||||
+ int win_index = VOP_WIN_TO_INDEX(vop_win);
|
||||
+ int format;
|
||||
+
|
||||
+ /*
|
||||
+ * can't update plane when vop is disabled.
|
||||
+ */
|
||||
+ if (WARN_ON(!crtc))
|
||||
+ return;
|
||||
+
|
||||
+ if (WARN_ON(!vop->is_enabled))
|
||||
+ return;
|
||||
+
|
||||
+ if (!new_state->visible) {
|
||||
+ vop_plane_atomic_disable(plane, state);
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
+ obj = fb->obj[0];
|
||||
+ rk_obj = to_rockchip_obj(obj);
|
||||
+
|
||||
+// actual_w = drm_rect_width(src) >> 16;
|
||||
+// actual_h = drm_rect_height(src) >> 16;
|
||||
+
|
||||
+ dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
|
||||
+ dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
|
||||
+ dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
|
||||
+
|
||||
+ dma_addr = rk_obj->dma_addr;
|
||||
+
|
||||
+ /*
|
||||
+ * For y-mirroring we need to move address
|
||||
+ * to the beginning of the last line.
|
||||
+ */
|
||||
+// if (new_state->rotation & DRM_MODE_REFLECT_Y)
|
||||
+// dma_addr += (actual_h - 1) * fb->pitches[0];
|
||||
+
|
||||
+ spin_lock(&vop->reg_lock);
|
||||
+
|
||||
+ if (!(vop->win_enabled & BIT(win_index))) {
|
||||
+
|
||||
+ format = vop_convert_format(fb->format->format);
|
||||
+
|
||||
+ VOP_WIN_SET(vop, win, format, format);
|
||||
+
|
||||
+// if (win->phy->scl)
|
||||
+// scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
|
||||
+// drm_rect_width(dest), drm_rect_height(dest),
|
||||
+// fb->format);
|
||||
+
|
||||
+ rb_swap = has_rb_swapped(fb->format->format);
|
||||
+ VOP_WIN_SET(vop, win, rb_swap, rb_swap);
|
||||
+
|
||||
+ /*
|
||||
+ * Blending win0 with the background color doesn't seem to work
|
||||
+ * correctly. We only get the background color, no matter the contents
|
||||
+ * of the win0 framebuffer. However, blending pre-multiplied color
|
||||
+ * with the default opaque black default background color is a no-op,
|
||||
+ * so we can just disable blending to get the correct result.
|
||||
+ */
|
||||
+ if (fb->format->has_alpha && win_index > 0) {
|
||||
+ VOP_WIN_SET(vop, win, dst_alpha_ctl,
|
||||
+ DST_FACTOR_M0(ALPHA_SRC_INVERSE));
|
||||
+ val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
|
||||
+ SRC_ALPHA_M0(ALPHA_STRAIGHT) |
|
||||
+ SRC_BLEND_M0(ALPHA_PER_PIX) |
|
||||
+ SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
|
||||
+ SRC_FACTOR_M0(ALPHA_ONE);
|
||||
+ VOP_WIN_SET(vop, win, src_alpha_ctl, val);
|
||||
+
|
||||
+ VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL);
|
||||
+ VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX);
|
||||
+ VOP_WIN_SET(vop, win, alpha_en, 1);
|
||||
+ } else {
|
||||
+ VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
|
||||
+ VOP_WIN_SET(vop, win, alpha_en, 0);
|
||||
+ }
|
||||
+
|
||||
+ // 32x32 = 0, 64x64 = 1, 96x96 = 2, 128x128 = 3
|
||||
+ VOP_WIN_SET(vop, win, hwc_size, (new_state->crtc_w >> 5) - 1);
|
||||
+
|
||||
+ VOP_WIN_SET(vop, win, enable, 1);
|
||||
+ vop->win_enabled |= BIT(win_index);
|
||||
+
|
||||
+ }
|
||||
+
|
||||
+ VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
|
||||
+ VOP_WIN_SET(vop, win, dsp_st, dsp_st);
|
||||
+
|
||||
+ spin_unlock(&vop->reg_lock);
|
||||
+
|
||||
+}
|
||||
+
|
||||
+static void vop_cursor_atomic_async_update(struct drm_plane *plane,
|
||||
+ struct drm_atomic_state *state)
|
||||
+{
|
||||
+
|
||||
+ struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
|
||||
+ plane);
|
||||
+ struct vop *vop = to_vop(plane->state->crtc);
|
||||
+ struct drm_framebuffer *old_fb = plane->state->fb;
|
||||
+
|
||||
+ plane->state->crtc_x = new_state->crtc_x;
|
||||
+ plane->state->crtc_y = new_state->crtc_y;
|
||||
+ plane->state->crtc_h = new_state->crtc_h;
|
||||
+ plane->state->crtc_w = new_state->crtc_w;
|
||||
+ plane->state->src_x = new_state->src_x;
|
||||
+ plane->state->src_y = new_state->src_y;
|
||||
+ plane->state->src_h = new_state->src_h;
|
||||
+ plane->state->src_w = new_state->src_w;
|
||||
+ swap(plane->state->fb, new_state->fb);
|
||||
+
|
||||
+ if (vop->is_enabled) {
|
||||
+ vop_cursor_atomic_update(plane, state);
|
||||
+ spin_lock(&vop->reg_lock);
|
||||
+ vop_cfg_done(vop);
|
||||
+ spin_unlock(&vop->reg_lock);
|
||||
+
|
||||
+ /*
|
||||
+ * A scanout can still be occurring, so we can't drop the
|
||||
+ * reference to the old framebuffer. To solve this we get a
|
||||
+ * reference to old_fb and set a worker to release it later.
|
||||
+ * FIXME: if we perform 500 async_update calls before the
|
||||
+ * vblank, then we can have 500 different framebuffers waiting
|
||||
+ * to be released.
|
||||
+ */
|
||||
+ if (old_fb && plane->state->fb != old_fb) {
|
||||
+ drm_framebuffer_get(old_fb);
|
||||
+ WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0);
|
||||
+ drm_flip_work_queue(&vop->fb_unref_work, old_fb);
|
||||
+ set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+}
|
||||
+
|
||||
+static int vop_cursor_atomic_check(struct drm_plane *plane,
|
||||
+ struct drm_atomic_state *state)
|
||||
+{
|
||||
+ struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
|
||||
+ plane);
|
||||
+ struct drm_crtc *crtc = new_plane_state->crtc;
|
||||
+ struct drm_crtc_state *crtc_state;
|
||||
+ struct drm_framebuffer *fb = new_plane_state->fb;
|
||||
+ int ret;
|
||||
+
|
||||
+ if (!crtc || WARN_ON(!fb))
|
||||
+ return 0;
|
||||
+
|
||||
+ crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
|
||||
+ if (WARN_ON(!crtc_state))
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
|
||||
+ DRM_PLANE_HELPER_NO_SCALING, DRM_PLANE_HELPER_NO_SCALING,
|
||||
+ true, true);
|
||||
+
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ if (!new_plane_state->visible)
|
||||
+ return 0;
|
||||
+
|
||||
+ ret = vop_convert_format(fb->format->format);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ if (new_plane_state->crtc_w != new_plane_state->crtc_h)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ if (new_plane_state->crtc_w != 0 &&
|
||||
+ new_plane_state->crtc_w != 32 &&
|
||||
+ new_plane_state->crtc_w != 64 &&
|
||||
+ new_plane_state->crtc_w != 96 &&
|
||||
+ new_plane_state->crtc_w != 128)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ return 0;
|
||||
+
|
||||
+}
|
||||
+
|
||||
static const struct drm_plane_helper_funcs plane_helper_funcs = {
|
||||
.atomic_check = vop_plane_atomic_check,
|
||||
.atomic_update = vop_plane_atomic_update,
|
||||
@@ -1169,6 +1370,15 @@ static const struct drm_plane_helper_funcs plane_helper_funcs = {
|
||||
.prepare_fb = drm_gem_plane_helper_prepare_fb,
|
||||
};
|
||||
|
||||
+static const struct drm_plane_helper_funcs cursor_plane_helper_funcs = {
|
||||
+ .atomic_check = vop_cursor_atomic_check,
|
||||
+ .atomic_update = vop_cursor_atomic_update,
|
||||
+ .atomic_disable = vop_plane_atomic_disable,
|
||||
+ .atomic_async_check = vop_plane_atomic_async_check,
|
||||
+ .atomic_async_update = vop_cursor_atomic_async_update,
|
||||
+ .prepare_fb = drm_gem_plane_helper_prepare_fb,
|
||||
+};
|
||||
+
|
||||
static const struct drm_plane_funcs vop_plane_funcs = {
|
||||
.update_plane = drm_atomic_helper_update_plane,
|
||||
.disable_plane = drm_atomic_helper_disable_plane,
|
||||
@@ -1956,6 +2166,7 @@ static int vop_create_crtc(struct vop *vop)
|
||||
struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
|
||||
struct drm_crtc *crtc = &vop->crtc;
|
||||
struct device_node *port;
|
||||
+ const struct drm_plane_helper_funcs *helper_funcs;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
@@ -1976,7 +2187,12 @@ static int vop_create_crtc(struct vop *vop)
|
||||
}
|
||||
|
||||
plane = &vop_win->base;
|
||||
- drm_plane_helper_add(plane, &plane_helper_funcs);
|
||||
+ helper_funcs = &plane_helper_funcs;
|
||||
+
|
||||
+ if ((plane->type == DRM_PLANE_TYPE_CURSOR) && (vop_data->feature & VOP_FEATURE_SPECIAL_CURSOR_PLANE))
|
||||
+ helper_funcs = &cursor_plane_helper_funcs;
|
||||
+
|
||||
+ drm_plane_helper_add(plane, helper_funcs);
|
||||
vop_plane_add_properties(plane, i, win_data, vop_data);
|
||||
if (plane->type == DRM_PLANE_TYPE_PRIMARY)
|
||||
primary = plane;
|
||||
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
|
||||
index a997578e1..42dc299d9 100644
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
|
||||
@@ -190,6 +190,8 @@ struct vop_win_phy {
|
||||
struct vop_reg alpha_mode;
|
||||
struct vop_reg alpha_en;
|
||||
struct vop_reg channel;
|
||||
+
|
||||
+ struct vop_reg hwc_size;
|
||||
};
|
||||
|
||||
struct vop_win_yuv2yuv_data {
|
||||
@@ -225,6 +227,7 @@ struct vop_data {
|
||||
|
||||
#define VOP_FEATURE_OUTPUT_RGB10 BIT(0)
|
||||
#define VOP_FEATURE_INTERNAL_RGB BIT(1)
|
||||
+#define VOP_FEATURE_SPECIAL_CURSOR_PLANE BIT(2)
|
||||
u64 feature;
|
||||
};
|
||||
|
||||
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
|
||||
index ab0a78097..70930b410 100644
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
|
||||
@@ -665,6 +665,19 @@ static const struct vop_win_phy rk3288_win23_data = {
|
||||
.dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
|
||||
};
|
||||
|
||||
+static const struct vop_win_phy rk3288_cursor_data = {
|
||||
+ .data_formats = formats_win_lite,
|
||||
+ .nformats = ARRAY_SIZE(formats_win_lite),
|
||||
+ .enable = VOP_REG(RK3288_HWC_CTRL0, 0x1, 0),
|
||||
+ .format = VOP_REG(RK3288_HWC_CTRL0, 0x7, 1),
|
||||
+ .rb_swap = VOP_REG(RK3288_HWC_CTRL0, 0x1, 12),
|
||||
+ .dsp_st = VOP_REG(RK3288_HWC_DSP_ST, 0x1fff1fff, 0),
|
||||
+ .yrgb_mst = VOP_REG(RK3288_HWC_MST, 0xffffffff, 0),
|
||||
+ .src_alpha_ctl = VOP_REG(RK3288_HWC_SRC_ALPHA_CTRL, 0xff, 0),
|
||||
+ .dst_alpha_ctl = VOP_REG(RK3288_HWC_DST_ALPHA_CTRL, 0xff, 0),
|
||||
+ .hwc_size = VOP_REG(RK3288_HWC_CTRL0, 0x3, 5),
|
||||
+};
|
||||
+
|
||||
static const struct vop_modeset rk3288_modeset = {
|
||||
.htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
|
||||
.hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
|
||||
@@ -756,6 +769,8 @@ static const struct vop_win_data rk3288_vop_win_data[] = {
|
||||
{ .base = 0x00, .phy = &rk3288_win23_data,
|
||||
.type = DRM_PLANE_TYPE_OVERLAY },
|
||||
{ .base = 0x50, .phy = &rk3288_win23_data,
|
||||
+ .type = DRM_PLANE_TYPE_OVERLAY },
|
||||
+ { .base = 0x00, .phy = &rk3288_cursor_data,
|
||||
.type = DRM_PLANE_TYPE_CURSOR },
|
||||
};
|
||||
|
||||
@@ -1066,11 +1081,13 @@ static const struct vop_win_data rk3228_vop_win_data[] = {
|
||||
.type = DRM_PLANE_TYPE_PRIMARY },
|
||||
{ .base = 0x40, .phy = &rk3228_win1_data,
|
||||
.type = DRM_PLANE_TYPE_OVERLAY },
|
||||
+ { .base = 0x00, .phy = &rk3288_cursor_data,
|
||||
+ .type = DRM_PLANE_TYPE_CURSOR },
|
||||
};
|
||||
|
||||
static const struct vop_data rk3228_vop = {
|
||||
.version = VOP_VERSION(3, 7),
|
||||
- .feature = VOP_FEATURE_OUTPUT_RGB10,
|
||||
+ .feature = VOP_FEATURE_OUTPUT_RGB10 | VOP_FEATURE_SPECIAL_CURSOR_PLANE,
|
||||
.max_output = { 4096, 2160 },
|
||||
.intr = &rk3366_vop_intr,
|
||||
.common = &rk3288_common,
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,177 @@
|
||||
From 5d68f46388c9813efb1a722e52f6ec9c4be8c0ce Mon Sep 17 00:00:00 2001
|
||||
From: Paolo Sabatino <paolo.sabatino@gmail.com>
|
||||
Date: Fri, 10 Sep 2021 14:18:08 +0000
|
||||
Subject: [PATCH] experimental drm patch
|
||||
|
||||
---
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 134 +++++++++++---------
|
||||
1 file changed, 72 insertions(+), 62 deletions(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
|
||||
index b0832320e..a0fca8a20 100644
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
|
||||
@@ -997,25 +997,78 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
|
||||
|
||||
spin_lock(&vop->reg_lock);
|
||||
|
||||
- if (rockchip_afbc(fb->modifier)) {
|
||||
- int afbc_format = vop_convert_afbc_format(fb->format->format);
|
||||
+ if (!(vop->win_enabled & BIT(win_index))) {
|
||||
|
||||
- VOP_AFBC_SET(vop, format, afbc_format | AFBC_TILE_16x16);
|
||||
- VOP_AFBC_SET(vop, hreg_block_split, 0);
|
||||
- VOP_AFBC_SET(vop, win_sel, VOP_WIN_TO_INDEX(vop_win));
|
||||
- VOP_AFBC_SET(vop, hdr_ptr, dma_addr);
|
||||
- VOP_AFBC_SET(vop, pic_size, act_info);
|
||||
- }
|
||||
+ if (rockchip_afbc(fb->modifier)) {
|
||||
+ int afbc_format = vop_convert_afbc_format(fb->format->format);
|
||||
|
||||
- VOP_WIN_SET(vop, win, format, format);
|
||||
- VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format));
|
||||
- VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4 >> skiplines));
|
||||
- VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
|
||||
- VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
|
||||
- VOP_WIN_SET(vop, win, y_mir_en,
|
||||
- (new_state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0);
|
||||
- VOP_WIN_SET(vop, win, x_mir_en,
|
||||
- (new_state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0);
|
||||
+ VOP_AFBC_SET(vop, format, afbc_format | AFBC_TILE_16x16);
|
||||
+ VOP_AFBC_SET(vop, hreg_block_split, 0);
|
||||
+ VOP_AFBC_SET(vop, win_sel, VOP_WIN_TO_INDEX(vop_win));
|
||||
+ VOP_AFBC_SET(vop, hdr_ptr, dma_addr);
|
||||
+ VOP_AFBC_SET(vop, pic_size, act_info);
|
||||
+ }
|
||||
+
|
||||
+ VOP_WIN_SET(vop, win, format, format);
|
||||
+ VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format));
|
||||
+ VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4 >> skiplines));
|
||||
+
|
||||
+ VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
|
||||
+ VOP_WIN_SET(vop, win, y_mir_en,
|
||||
+ (new_state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0);
|
||||
+ VOP_WIN_SET(vop, win, x_mir_en,
|
||||
+ (new_state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0);
|
||||
+
|
||||
+ if (is_yuv) {
|
||||
+
|
||||
+ for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) {
|
||||
+ VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop,
|
||||
+ win_yuv2yuv,
|
||||
+ y2r_coefficients[i],
|
||||
+ bt601_yuv2rgb[i]);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ if (win->phy->scl)
|
||||
+ scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
|
||||
+ drm_rect_width(dest), drm_rect_height(dest),
|
||||
+ fb->format);
|
||||
+
|
||||
+ VOP_WIN_SET(vop, win, act_info, act_info);
|
||||
+ VOP_WIN_SET(vop, win, dsp_info, dsp_info);
|
||||
+
|
||||
+ rb_swap = has_rb_swapped(fb->format->format);
|
||||
+ VOP_WIN_SET(vop, win, rb_swap, rb_swap);
|
||||
+
|
||||
+ /*
|
||||
+ * Blending win0 with the background color doesn't seem to work
|
||||
+ * correctly. We only get the background color, no matter the contents
|
||||
+ * of the win0 framebuffer. However, blending pre-multiplied color
|
||||
+ * with the default opaque black default background color is a no-op,
|
||||
+ * so we can just disable blending to get the correct result.
|
||||
+ */
|
||||
+ if (fb->format->has_alpha && win_index > 0) {
|
||||
+ VOP_WIN_SET(vop, win, dst_alpha_ctl,
|
||||
+ DST_FACTOR_M0(ALPHA_SRC_INVERSE));
|
||||
+ val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
|
||||
+ SRC_ALPHA_M0(ALPHA_STRAIGHT) |
|
||||
+ SRC_BLEND_M0(ALPHA_PER_PIX) |
|
||||
+ SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
|
||||
+ SRC_FACTOR_M0(ALPHA_ONE);
|
||||
+ VOP_WIN_SET(vop, win, src_alpha_ctl, val);
|
||||
+
|
||||
+ VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL);
|
||||
+ VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX);
|
||||
+ VOP_WIN_SET(vop, win, alpha_en, 1);
|
||||
+ } else {
|
||||
+ VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
|
||||
+ VOP_WIN_SET(vop, win, alpha_en, 0);
|
||||
+ }
|
||||
+
|
||||
+ VOP_WIN_SET(vop, win, enable, 1);
|
||||
+ vop->win_enabled |= BIT(win_index);
|
||||
+
|
||||
+ }
|
||||
|
||||
if (is_yuv) {
|
||||
int hsub = fb->format->hsub;
|
||||
@@ -1027,7 +1080,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
|
||||
|
||||
if (fb->format->block_w[1])
|
||||
offset = (src->x1 >> 16) * bpp /
|
||||
- fb->format->block_w[1] / hsub;
|
||||
+ fb->format->block_w[1] / hsub;
|
||||
else
|
||||
offset = (src->x1 >> 16) * bpp / hsub;
|
||||
offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
|
||||
@@ -1035,54 +1088,11 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
|
||||
dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
|
||||
VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4 >> skiplines));
|
||||
VOP_WIN_SET(vop, win, uv_mst, dma_addr);
|
||||
-
|
||||
- for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) {
|
||||
- VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop,
|
||||
- win_yuv2yuv,
|
||||
- y2r_coefficients[i],
|
||||
- bt601_yuv2rgb[i]);
|
||||
- }
|
||||
}
|
||||
|
||||
- if (win->phy->scl)
|
||||
- scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
|
||||
- drm_rect_width(dest), drm_rect_height(dest),
|
||||
- fb->format);
|
||||
-
|
||||
- VOP_WIN_SET(vop, win, act_info, act_info);
|
||||
- VOP_WIN_SET(vop, win, dsp_info, dsp_info);
|
||||
+ VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
|
||||
VOP_WIN_SET(vop, win, dsp_st, dsp_st);
|
||||
|
||||
- rb_swap = has_rb_swapped(fb->format->format);
|
||||
- VOP_WIN_SET(vop, win, rb_swap, rb_swap);
|
||||
-
|
||||
- /*
|
||||
- * Blending win0 with the background color doesn't seem to work
|
||||
- * correctly. We only get the background color, no matter the contents
|
||||
- * of the win0 framebuffer. However, blending pre-multiplied color
|
||||
- * with the default opaque black default background color is a no-op,
|
||||
- * so we can just disable blending to get the correct result.
|
||||
- */
|
||||
- if (fb->format->has_alpha && win_index > 0) {
|
||||
- VOP_WIN_SET(vop, win, dst_alpha_ctl,
|
||||
- DST_FACTOR_M0(ALPHA_SRC_INVERSE));
|
||||
- val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
|
||||
- SRC_ALPHA_M0(ALPHA_STRAIGHT) |
|
||||
- SRC_BLEND_M0(ALPHA_PER_PIX) |
|
||||
- SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
|
||||
- SRC_FACTOR_M0(ALPHA_ONE);
|
||||
- VOP_WIN_SET(vop, win, src_alpha_ctl, val);
|
||||
-
|
||||
- VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL);
|
||||
- VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX);
|
||||
- VOP_WIN_SET(vop, win, alpha_en, 1);
|
||||
- } else {
|
||||
- VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
|
||||
- VOP_WIN_SET(vop, win, alpha_en, 0);
|
||||
- }
|
||||
-
|
||||
- VOP_WIN_SET(vop, win, enable, 1);
|
||||
- vop->win_enabled |= BIT(win_index);
|
||||
spin_unlock(&vop->reg_lock);
|
||||
}
|
||||
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,38 @@
|
||||
From 3f6f9e704daf85eb5f45aba07997c85d927c880f Mon Sep 17 00:00:00 2001
|
||||
From: Paolo Sabatino <paolo.sabatino@gmail.com>
|
||||
Date: Fri, 17 Sep 2021 20:10:22 +0000
|
||||
Subject: [PATCH] prefer 8-bit RGB over YCbCr
|
||||
|
||||
---
|
||||
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 8 ++++----
|
||||
1 file changed, 4 insertions(+), 4 deletions(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
index 84cc52858..5db7024de 100644
|
||||
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
|
||||
@@ -2648,6 +2648,10 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
|
||||
output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
|
||||
}
|
||||
|
||||
+ /* Prefer 8-bit RGB over YCbCr formats */
|
||||
+ if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB888_1X24))
|
||||
+ output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
|
||||
+
|
||||
if ((info->color_formats & DRM_COLOR_FORMAT_YCRCB422) &&
|
||||
is_tmds_allowed(info, mode, MEDIA_BUS_FMT_UYVY8_1X16))
|
||||
output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
|
||||
@@ -2656,10 +2660,6 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
|
||||
is_tmds_allowed(info, mode, MEDIA_BUS_FMT_YUV8_1X24))
|
||||
output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
|
||||
|
||||
- /* Default 8bit RGB fallback */
|
||||
- if (is_tmds_allowed(info, mode, MEDIA_BUS_FMT_RGB888_1X24))
|
||||
- output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
|
||||
-
|
||||
*num_output_fmts = i;
|
||||
|
||||
return output_fmts;
|
||||
--
|
||||
2.30.2
|
||||
|
||||
506
patch/kernel/archive/rk322x-5.16/board-rk322x-box.patch
Normal file
506
patch/kernel/archive/rk322x-5.16/board-rk322x-box.patch
Normal file
@ -0,0 +1,506 @@
|
||||
diff --git a/arch/arm/boot/dts/rk322x-box.dts b/arch/arm/boot/dts/rk322x-box.dts
|
||||
new file mode 100644
|
||||
index 000000000..22c401d9c
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/rk322x-box.dts
|
||||
@@ -0,0 +1,500 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include <dt-bindings/pinctrl/rockchip.h>
|
||||
+#include <dt-bindings/pwm/pwm.h>
|
||||
+#include "rk322x-box.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+
|
||||
+ model = "Generic RK322x Tv Box board";
|
||||
+
|
||||
+ /delete-node/ leds;
|
||||
+
|
||||
+ /*
|
||||
+ No need to reserve memory manually as long as u-boot v2020.10 and
|
||||
+ OPTEE autoconfigure the reserved zones
|
||||
+ */
|
||||
+ /delete-node/ reserved-memory;
|
||||
+
|
||||
+ /*
|
||||
+ * Include the mmc devices into aliases table
|
||||
+ */
|
||||
+ aliases {
|
||||
+ mmc0 = &sdmmc;
|
||||
+ mmc1 = &sdio;
|
||||
+ mmc2 = &emmc;
|
||||
+ };
|
||||
+
|
||||
+ gpio_leds: gpio-leds {
|
||||
+
|
||||
+ compatible = "gpio-leds";
|
||||
+
|
||||
+ /*
|
||||
+ * Working led, available on all boards
|
||||
+ */
|
||||
+ working {
|
||||
+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
+ label = "working";
|
||||
+ default-state = "on";
|
||||
+ linux,default-trigger = "timer";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&gpio_led_working>;
|
||||
+ };
|
||||
+
|
||||
+ };
|
||||
+
|
||||
+ // Remove the gpio-keys node from included dtsi
|
||||
+ /delete-node/gpio_keys;
|
||||
+
|
||||
+ gpio_keys: gpio-keys {
|
||||
+
|
||||
+ compatible = "gpio-keys";
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ };
|
||||
+
|
||||
+ spdif_out: spdif-out {
|
||||
+ status = "okay";
|
||||
+ compatible = "linux,spdif-dit";
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ spdif-sound {
|
||||
+ status = "okay";
|
||||
+ compatible = "simple-audio-card";
|
||||
+ simple-audio-card,name = "SPDIF";
|
||||
+ simple-audio-card,cpu {
|
||||
+ sound-dai = <&spdif>;
|
||||
+ };
|
||||
+ simple-audio-card,codec {
|
||||
+ sound-dai = <&spdif_out>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ analog-sound {
|
||||
+ compatible = "simple-audio-card";
|
||||
+ simple-audio-card,format = "i2s";
|
||||
+ simple-audio-card,mclk-fs = <256>;
|
||||
+ simple-audio-card,name = "analog";
|
||||
+ simple-audio-card,cpu {
|
||||
+ sound-dai = <&i2s1>;
|
||||
+ };
|
||||
+
|
||||
+ simple-audio-card,codec {
|
||||
+ sound-dai = <&codec>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_sys: vcc-sys-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_host: vcc-host-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&host_vbus_drv>;
|
||||
+ regulator-name = "vcc_host";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vccio_1v8: vccio-1v8-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vccio_1v8";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-always-on;
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vccio_3v3: vccio-3v3-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vccio_3v3";
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-always-on;
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_otg: vcc-otg-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&otg_vbus_drv>;
|
||||
+ regulator-name = "vcc_otg_vbus";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_phy: vcc-phy-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ regulator-name = "vcc_phy";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ vin-supply = <&vccio_1v8>;
|
||||
+ };
|
||||
+
|
||||
+ vdd_arm: vdd-arm-regulator {
|
||||
+ compatible = "pwm-regulator";
|
||||
+ pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>;
|
||||
+ pwm-supply = <&vcc_sys>;
|
||||
+ regulator-name = "vdd_arm";
|
||||
+ regulator-min-microvolt = <950000>;
|
||||
+ regulator-max-microvolt = <1400000>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ };
|
||||
+
|
||||
+ vdd_log: vdd-log-regulator {
|
||||
+ compatible = "pwm-regulator";
|
||||
+ pwms = <&pwm2 0 5000 PWM_POLARITY_INVERTED>;
|
||||
+ pwm-supply = <&vcc_sys>;
|
||||
+ regulator-name = "vdd_log";
|
||||
+ regulator-min-microvolt = <1000000>;
|
||||
+ regulator-max-microvolt = <1300000>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ };
|
||||
+
|
||||
+ /delete-node/ opp-table-0;
|
||||
+
|
||||
+ cpu0_opp_table: opp-table-0 {
|
||||
+ compatible = "operating-points-v2";
|
||||
+ opp-shared;
|
||||
+
|
||||
+ /*
|
||||
+ * The 408 Mhz node causes system instabilities on some systems.
|
||||
+ * Remove it also because it is too slow.
|
||||
+ */
|
||||
+ /delete-node/opp-408000000;
|
||||
+
|
||||
+ opp-600000000 {
|
||||
+ opp-hz = /bits/ 64 <600000000>;
|
||||
+ opp-microvolt = <975000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ opp-suspend;
|
||||
+ };
|
||||
+
|
||||
+ opp-816000000 {
|
||||
+ opp-hz = /bits/ 64 <816000000>;
|
||||
+ opp-microvolt = <1000000>;
|
||||
+ };
|
||||
+
|
||||
+ opp-1008000000 {
|
||||
+ opp-hz = /bits/ 64 <1008000000>;
|
||||
+ opp-microvolt = <1175000>;
|
||||
+ };
|
||||
+
|
||||
+ opp-1200000000 {
|
||||
+ opp-hz = /bits/ 64 <1200000000>;
|
||||
+ opp-microvolt = <1275000>;
|
||||
+ };
|
||||
+
|
||||
+ };
|
||||
+
|
||||
+};
|
||||
+
|
||||
+&emmc {
|
||||
+ status = "okay";
|
||||
+ /delete-property/ mmc-ddr-1_8v;
|
||||
+ /delete-property/ pinctrl-names;
|
||||
+ /delete-property/ pinctrl-0;
|
||||
+ /delete-property/ rockchip,default-sample-phase;
|
||||
+};
|
||||
+
|
||||
+&nfc {
|
||||
+
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ /delete-property/ pinctrl-names;
|
||||
+ /delete-property/ pinctrl-0;
|
||||
+
|
||||
+ nand@0 {
|
||||
+ reg = <0>;
|
||||
+ label = "rk-nand";
|
||||
+ nand-bus-width = <8>;
|
||||
+ nand-ecc-mode = "hw";
|
||||
+ nand-ecc-step-size = <1024>;
|
||||
+ nand-ecc-strength = <60>;
|
||||
+ nand-is-boot-medium;
|
||||
+ rockchip,boot-blks = <8>;
|
||||
+ rockchip,boot-ecc-strength = <60>;
|
||||
+ };
|
||||
+
|
||||
+};
|
||||
+
|
||||
+&cpu0 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&cpu1 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&cpu2 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&cpu3 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&dmc {
|
||||
+ logic-supply = <&vdd_log>;
|
||||
+};
|
||||
+
|
||||
+&io_domains {
|
||||
+ vccio1-supply = <&vccio_3v3>;
|
||||
+ vccio2-supply = <&vccio_1v8>;
|
||||
+ vccio4-supply = <&vccio_3v3>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&gmac {
|
||||
+ phy-supply = <&vcc_phy>;
|
||||
+ tx_delay = <0x26>;
|
||||
+ rx_delay = <0x11>;
|
||||
+};
|
||||
+
|
||||
+&gpu {
|
||||
+ mali-supply = <&vdd_log>;
|
||||
+};
|
||||
+
|
||||
+&iep {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&iep_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pwm1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pwm2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2s1 {
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&codec {
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy0 {
|
||||
+ u2phy0_host: host-port {
|
||||
+ phy-supply = <&vcc_host>;
|
||||
+ };
|
||||
+
|
||||
+ u2phy0_otg: otg-port {
|
||||
+ phy-supply = <&vcc_otg>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&u2phy1 {
|
||||
+ u2phy1_host: host-port {
|
||||
+ phy-supply = <&vcc_host>;
|
||||
+ };
|
||||
+
|
||||
+ u2phy1_otg: otg-port {
|
||||
+ phy-supply = <&vcc_otg>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&ir_receiver {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_otg {
|
||||
+ dr_mode = "host";
|
||||
+};
|
||||
+
|
||||
+&sdio {
|
||||
+ mmc-pwrseq = <&sdio_pwrseq>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc {
|
||||
+ cd-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>;
|
||||
+ cd-debounce-delay-ms = <500>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&spdif {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+/** Integration to pin controller */
|
||||
+&pinctrl {
|
||||
+
|
||||
+ pcfg_pull_up_12ma: pcfg-pull-up-12ma {
|
||||
+ drive-strength = <12>;
|
||||
+ bias-pull-up;
|
||||
+ };
|
||||
+
|
||||
+ pcfg_pull_down_12ma: pcfg-pull-down-12ma {
|
||||
+ drive-strength = <12>;
|
||||
+ bias-pull-down;
|
||||
+ };
|
||||
+
|
||||
+ pcfg_pull_none_12ma: pcfg-pull-none-12ma {
|
||||
+ drive-strength = <12>;
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+
|
||||
+ pcfg_pull_up_8ma: pcfg-pull-up-8ma {
|
||||
+ drive-strength = <8>;
|
||||
+ bias-pull-up;
|
||||
+ };
|
||||
+
|
||||
+ pcfg_pull_down_8ma: pcfg-pull-down-8ma {
|
||||
+ drive-strength = <8>;
|
||||
+ bias-pull-down;
|
||||
+ };
|
||||
+
|
||||
+ pcfg_pull_none_8ma: pcfg-pull-none-8ma {
|
||||
+ drive-strength = <8>;
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+
|
||||
+ pcfg_pull_up_2ma: pcfg-pull-up-2ma {
|
||||
+ drive-strength = <2>;
|
||||
+ bias-pull-up;
|
||||
+ };
|
||||
+
|
||||
+ pcfg_pull_down_2ma: pcfg-pull-down-2ma {
|
||||
+ drive-strength = <2>;
|
||||
+ bias-pull-down;
|
||||
+ };
|
||||
+
|
||||
+ pcfg_pull_none_2ma: pcfg-pull-none-2ma {
|
||||
+ drive-strength = <2>;
|
||||
+ bias-disable;
|
||||
+ };
|
||||
+
|
||||
+ /*
|
||||
+ * Some rk322x electrical schemes report this kind of pull-up/down
|
||||
+ * pin configurations. We set them here, but we don't use it in this
|
||||
+ * device tree. These instead are useful for overlays, because they seem
|
||||
+ * to increase stability on at least one board I got here
|
||||
+ */
|
||||
+ sdmmc {
|
||||
+ sdmmc_clk: sdmmc-clk {
|
||||
+ rockchip,pins = <1 16 1 &pcfg_pull_down>;
|
||||
+ };
|
||||
+
|
||||
+ sdmmc_cmd: sdmmc-cmd {
|
||||
+ rockchip,pins = <1 15 1 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ sdmmc_bus4: sdmmc-bus4 {
|
||||
+ rockchip,pins = <1 18 1 &pcfg_pull_up>,
|
||||
+ <1 19 1 &pcfg_pull_up>,
|
||||
+ <1 20 1 &pcfg_pull_up>,
|
||||
+ <1 21 1 &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ /*
|
||||
+ * Same as above, decreasing strength of SDIO pins seems to be benefical
|
||||
+ * to stability
|
||||
+ */
|
||||
+ sdio {
|
||||
+ sdio_clk: sdio-clk {
|
||||
+ rockchip,pins = <3 0 1 &pcfg_pull_down_2ma>;
|
||||
+ };
|
||||
+
|
||||
+ sdio_cmd: sdio-cmd {
|
||||
+ rockchip,pins = <3 1 1 &pcfg_pull_up_2ma>;
|
||||
+ };
|
||||
+
|
||||
+ sdio_bus4: sdio-bus4 {
|
||||
+ rockchip,pins = <3 2 1 &pcfg_pull_up_2ma>,
|
||||
+ <3 3 1 &pcfg_pull_up_2ma>,
|
||||
+ <3 4 1 &pcfg_pull_up_2ma>,
|
||||
+ <3 5 1 &pcfg_pull_up_2ma>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ /*
|
||||
+ * Same drill as above, electrical schemes also report this pull-up/down
|
||||
+ * configurations.
|
||||
+ */
|
||||
+ emmc {
|
||||
+ emmc_clk: emmc-clk {
|
||||
+ rockchip,pins = <2 7 2 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ emmc_cmd: emmc-cmd {
|
||||
+ rockchip,pins = <1 22 2 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ emmc_bus8: emmc-bus8 {
|
||||
+ rockchip,pins = <1 24 2 &pcfg_pull_up>,
|
||||
+ <1 25 2 &pcfg_pull_up>,
|
||||
+ <1 26 2 &pcfg_pull_up>,
|
||||
+ <1 27 2 &pcfg_pull_up>,
|
||||
+ <1 28 2 &pcfg_pull_up>,
|
||||
+ <1 29 2 &pcfg_pull_up>,
|
||||
+ <1 30 2 &pcfg_pull_up>,
|
||||
+ <1 31 2 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ emmc_pwr: emmc-pwr {
|
||||
+ rockchip,pins = <2 RK_PA5 2 &pcfg_pull_down>;
|
||||
+ };
|
||||
+
|
||||
+ emmc_rst: emmc-rst {
|
||||
+ rockchip,pins = <1 RK_PC7 2 &pcfg_pull_up>;
|
||||
+ };
|
||||
+
|
||||
+ };
|
||||
+
|
||||
+
|
||||
+ gpio {
|
||||
+ gpio_led_working: gpio-led-working {
|
||||
+ rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ ir {
|
||||
+ ir_int: ir-int {
|
||||
+ rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ sdio-pwrseq {
|
||||
+ wifi_enable_h: wifi-enable-h {
|
||||
+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+};
|
||||
@ -0,0 +1,53 @@
|
||||
From f60f1605f5056d543e49fc625ffeeb05621f2ad3 Mon Sep 17 00:00:00 2001
|
||||
From: Vasily Khoruzhick
|
||||
Date: Wed, 31 Oct 2018 19:40:18 -0700
|
||||
Subject: Bluetooth: Add new quirk for broken local ext features max_page
|
||||
|
||||
Some adapters (e.g. RTL8723CS) advertise that they have more than
|
||||
2 pages for local ext features, but they don't support any features
|
||||
declared in these pages. RTL8723CS reports max_page = 2 and declares
|
||||
support for sync train and secure connection, but it responds with
|
||||
either garbage or with error in status on corresponding commands.
|
||||
|
||||
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
|
||||
---
|
||||
include/net/bluetooth/hci.h | 7 +++++++
|
||||
net/bluetooth/hci_event.c | 4 +++-
|
||||
2 files changed, 10 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/include/net/bluetooth/hci.h b/include/net/bluetooth/hci.h
|
||||
index 16ab6ce87883..8e4c16210d18 100644
|
||||
--- a/include/net/bluetooth/hci.h
|
||||
+++ b/include/net/bluetooth/hci.h
|
||||
@@ -238,6 +238,13 @@ enum {
|
||||
* HCI after resume.
|
||||
*/
|
||||
HCI_QUIRK_NO_SUSPEND_NOTIFIER,
|
||||
+
|
||||
+ /* When this quirk is set, max_page for local extended features
|
||||
+ * is set to 1, even if controller reports higher number. Some
|
||||
+ * controllers (e.g. RTL8723CS) report more pages, but they
|
||||
+ * don't actually support features declared there.
|
||||
+ */
|
||||
+ HCI_QUIRK_BROKEN_LOCAL_EXT_FTR_MAX_PAGE,
|
||||
|
||||
/*
|
||||
* When this quirk is set, LE tx power is not queried on startup
|
||||
diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c
|
||||
index cfeaee347db3..df3232828978 100644
|
||||
--- a/net/bluetooth/hci_event.c
|
||||
+++ b/net/bluetooth/hci_event.c
|
||||
@@ -700,7 +700,9 @@ static void hci_cc_read_local_ext_features(struct hci_dev *hdev,
|
||||
if (rp->status)
|
||||
return;
|
||||
|
||||
- if (hdev->max_page < rp->max_page)
|
||||
+ if (!test_bit(HCI_QUIRK_BROKEN_LOCAL_EXT_FTR_MAX_PAGE,
|
||||
+ &hdev->quirks) &&
|
||||
+ hdev->max_page < rp->max_page)
|
||||
hdev->max_page = rp->max_page;
|
||||
|
||||
if (rp->page < HCI_MAX_PAGES)
|
||||
--
|
||||
cgit v1.2.3
|
||||
|
||||
@ -0,0 +1,267 @@
|
||||
From 26e61cffb09c1f5519a4eeb9d9e99239d58b6c2d Mon Sep 17 00:00:00 2001
|
||||
From: Ondrej Jirman <megous@megous.com>
|
||||
Date: Thu, 1 Jul 2021 11:22:23 +0200
|
||||
Subject: [PATCH 302/467] Bluetooth: btrtl: add support for the RTL8723CS
|
||||
|
||||
The Realtek RTL8723CS is SDIO WiFi chip. It also contains a Bluetooth
|
||||
module which is connected via UART to the host.
|
||||
|
||||
It shares lmp subversion with 8703B, so Realtek's userspace
|
||||
initialization tool (rtk_hciattach) differentiates varieties of RTL8723CS
|
||||
(CG, VF, XX) with RTL8703B using vendor's command to read chip type.
|
||||
|
||||
Also this chip declares support for some features it doesn't support
|
||||
so add a quirk to indicate that these features are broken.
|
||||
|
||||
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
|
||||
Signed-off-by: Ondrej Jirman <megous@megous.com>
|
||||
---
|
||||
drivers/bluetooth/btrtl.c | 119 +++++++++++++++++++++++++++++++++++++-
|
||||
drivers/bluetooth/btrtl.h | 5 ++
|
||||
2 files changed, 121 insertions(+), 3 deletions(-)
|
||||
|
||||
diff --git a/drivers/bluetooth/btrtl.c b/drivers/bluetooth/btrtl.c
|
||||
index 1f8afa024..fd293a9c4 100644
|
||||
--- a/drivers/bluetooth/btrtl.c
|
||||
+++ b/drivers/bluetooth/btrtl.c
|
||||
@@ -17,7 +17,12 @@
|
||||
|
||||
#define VERSION "0.1"
|
||||
|
||||
+#define RTL_CHIP_8723CS_CG 3
|
||||
+#define RTL_CHIP_8723CS_VF 4
|
||||
+#define RTL_CHIP_8723CS_XX 5
|
||||
#define RTL_EPATCH_SIGNATURE "Realtech"
|
||||
+#define RTL_ROM_LMP_3499 0x3499
|
||||
+#define RTL_ROM_LMP_8703B 0x8703
|
||||
#define RTL_ROM_LMP_8723A 0x1200
|
||||
#define RTL_ROM_LMP_8723B 0x8723
|
||||
#define RTL_ROM_LMP_8821A 0x8821
|
||||
@@ -30,6 +35,7 @@
|
||||
#define IC_MATCH_FL_HCIREV (1 << 1)
|
||||
#define IC_MATCH_FL_HCIVER (1 << 2)
|
||||
#define IC_MATCH_FL_HCIBUS (1 << 3)
|
||||
+#define IC_MATCH_FL_CHIP_TYPE (1 << 4)
|
||||
#define IC_INFO(lmps, hcir, hciv, bus) \
|
||||
.match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_HCIREV | \
|
||||
IC_MATCH_FL_HCIVER | IC_MATCH_FL_HCIBUS, \
|
||||
@@ -57,6 +63,7 @@ struct id_table {
|
||||
__u16 hci_rev;
|
||||
__u8 hci_ver;
|
||||
__u8 hci_bus;
|
||||
+ __u8 chip_type;
|
||||
bool config_needed;
|
||||
bool has_rom_version;
|
||||
char *fw_name;
|
||||
@@ -96,6 +103,39 @@ static const struct id_table ic_id_table[] = {
|
||||
.fw_name = "rtl_bt/rtl8723b_fw.bin",
|
||||
.cfg_name = "rtl_bt/rtl8723b_config" },
|
||||
|
||||
+ /* 8723CS-CG */
|
||||
+ { .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_CHIP_TYPE |
|
||||
+ IC_MATCH_FL_HCIBUS,
|
||||
+ .lmp_subver = RTL_ROM_LMP_8703B,
|
||||
+ .chip_type = RTL_CHIP_8723CS_CG,
|
||||
+ .hci_bus = HCI_UART,
|
||||
+ .config_needed = true,
|
||||
+ .has_rom_version = true,
|
||||
+ .fw_name = "rtl_bt/rtl8723cs_cg_fw.bin",
|
||||
+ .cfg_name = "rtl_bt/rtl8723cs_cg_config" },
|
||||
+
|
||||
+ /* 8723CS-VF */
|
||||
+ { .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_CHIP_TYPE |
|
||||
+ IC_MATCH_FL_HCIBUS,
|
||||
+ .lmp_subver = RTL_ROM_LMP_8703B,
|
||||
+ .chip_type = RTL_CHIP_8723CS_VF,
|
||||
+ .hci_bus = HCI_UART,
|
||||
+ .config_needed = true,
|
||||
+ .has_rom_version = true,
|
||||
+ .fw_name = "rtl_bt/rtl8723cs_vf_fw.bin",
|
||||
+ .cfg_name = "rtl_bt/rtl8723cs_vf_config" },
|
||||
+
|
||||
+ /* 8723CS-XX */
|
||||
+ { .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_CHIP_TYPE |
|
||||
+ IC_MATCH_FL_HCIBUS,
|
||||
+ .lmp_subver = RTL_ROM_LMP_8703B,
|
||||
+ .chip_type = RTL_CHIP_8723CS_XX,
|
||||
+ .hci_bus = HCI_UART,
|
||||
+ .config_needed = true,
|
||||
+ .has_rom_version = true,
|
||||
+ .fw_name = "rtl_bt/rtl8723cs_xx_fw.bin",
|
||||
+ .cfg_name = "rtl_bt/rtl8723cs_xx_config" },
|
||||
+
|
||||
/* 8723D */
|
||||
{ IC_INFO(RTL_ROM_LMP_8723B, 0xd, 0x8, HCI_USB),
|
||||
.config_needed = true,
|
||||
@@ -175,7 +215,8 @@ static const struct id_table ic_id_table[] = {
|
||||
};
|
||||
|
||||
static const struct id_table *btrtl_match_ic(u16 lmp_subver, u16 hci_rev,
|
||||
- u8 hci_ver, u8 hci_bus)
|
||||
+ u8 hci_ver, u8 hci_bus,
|
||||
+ u8 chip_type)
|
||||
{
|
||||
int i;
|
||||
|
||||
@@ -192,6 +233,9 @@ static const struct id_table *btrtl_match_ic(u16 lmp_subver, u16 hci_rev,
|
||||
if ((ic_id_table[i].match_flags & IC_MATCH_FL_HCIBUS) &&
|
||||
(ic_id_table[i].hci_bus != hci_bus))
|
||||
continue;
|
||||
+ if ((ic_id_table[i].match_flags & IC_MATCH_FL_CHIP_TYPE) &&
|
||||
+ (ic_id_table[i].chip_type != chip_type))
|
||||
+ continue;
|
||||
|
||||
break;
|
||||
}
|
||||
@@ -274,6 +318,7 @@ static int rtlbt_parse_firmware(struct hci_dev *hdev,
|
||||
{ RTL_ROM_LMP_8723B, 1 },
|
||||
{ RTL_ROM_LMP_8821A, 2 },
|
||||
{ RTL_ROM_LMP_8761A, 3 },
|
||||
+ { RTL_ROM_LMP_8703B, 7 },
|
||||
{ RTL_ROM_LMP_8822B, 8 },
|
||||
{ RTL_ROM_LMP_8723B, 9 }, /* 8723D */
|
||||
{ RTL_ROM_LMP_8821A, 10 }, /* 8821C */
|
||||
@@ -552,6 +597,48 @@ static int btrtl_setup_rtl8723b(struct hci_dev *hdev,
|
||||
return ret;
|
||||
}
|
||||
|
||||
+static bool rtl_has_chip_type(u16 lmp_subver)
|
||||
+{
|
||||
+ switch (lmp_subver) {
|
||||
+ case RTL_ROM_LMP_8703B:
|
||||
+ return true;
|
||||
+ default:
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ return false;
|
||||
+}
|
||||
+
|
||||
+static int rtl_read_chip_type(struct hci_dev *hdev, u8 *type)
|
||||
+{
|
||||
+ struct rtl_chip_type_evt *chip_type;
|
||||
+ struct sk_buff *skb;
|
||||
+ const unsigned char cmd_buf[] = {0x00, 0x94, 0xa0, 0x00, 0xb0};
|
||||
+
|
||||
+ /* Read RTL chip type command */
|
||||
+ skb = __hci_cmd_sync(hdev, 0xfc61, 5, cmd_buf, HCI_INIT_TIMEOUT);
|
||||
+ if (IS_ERR(skb)) {
|
||||
+ rtl_dev_err(hdev, "Read chip type failed (%ld)",
|
||||
+ PTR_ERR(skb));
|
||||
+ return PTR_ERR(skb);
|
||||
+ }
|
||||
+
|
||||
+ if (skb->len != sizeof(*chip_type)) {
|
||||
+ rtl_dev_err(hdev, "RTL chip type event length mismatch");
|
||||
+ kfree_skb(skb);
|
||||
+ return -EIO;
|
||||
+ }
|
||||
+
|
||||
+ chip_type = (struct rtl_chip_type_evt *)skb->data;
|
||||
+ rtl_dev_info(hdev, "chip_type status=%x type=%x",
|
||||
+ chip_type->status, chip_type->type);
|
||||
+
|
||||
+ *type = chip_type->type & 0x0f;
|
||||
+
|
||||
+ kfree_skb(skb);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
void btrtl_free(struct btrtl_device_info *btrtl_dev)
|
||||
{
|
||||
kvfree(btrtl_dev->fw_data);
|
||||
@@ -568,7 +655,7 @@ struct btrtl_device_info *btrtl_initialize(struct hci_dev *hdev,
|
||||
struct hci_rp_read_local_version *resp;
|
||||
char cfg_name[40];
|
||||
u16 hci_rev, lmp_subver;
|
||||
- u8 hci_ver;
|
||||
+ u8 hci_ver, chip_type = 0;
|
||||
int ret;
|
||||
u16 opcode;
|
||||
u8 cmd[2];
|
||||
@@ -638,8 +725,14 @@ struct btrtl_device_info *btrtl_initialize(struct hci_dev *hdev,
|
||||
out_free:
|
||||
kfree_skb(skb);
|
||||
|
||||
+ if (rtl_has_chip_type(lmp_subver)) {
|
||||
+ ret = rtl_read_chip_type(hdev, &chip_type);
|
||||
+ if (ret)
|
||||
+ goto err_free;
|
||||
+ }
|
||||
+
|
||||
btrtl_dev->ic_info = btrtl_match_ic(lmp_subver, hci_rev, hci_ver,
|
||||
- hdev->bus);
|
||||
+ hdev->bus, chip_type);
|
||||
|
||||
if (!btrtl_dev->ic_info) {
|
||||
rtl_dev_info(hdev, "unknown IC info, lmp subver %04x, hci rev %04x, hci ver %04x",
|
||||
@@ -722,6 +815,7 @@ int btrtl_download_firmware(struct hci_dev *hdev,
|
||||
case RTL_ROM_LMP_8761A:
|
||||
case RTL_ROM_LMP_8822B:
|
||||
case RTL_ROM_LMP_8852A:
|
||||
+ case RTL_ROM_LMP_8703B:
|
||||
return btrtl_setup_rtl8723b(hdev, btrtl_dev);
|
||||
default:
|
||||
rtl_dev_info(hdev, "assuming no firmware upload needed");
|
||||
@@ -752,6 +846,19 @@ void btrtl_set_quirks(struct hci_dev *hdev, struct btrtl_device_info *btrtl_dev)
|
||||
rtl_dev_dbg(hdev, "WBS supported not enabled.");
|
||||
break;
|
||||
}
|
||||
+
|
||||
+ switch (btrtl_dev->ic_info->lmp_subver) {
|
||||
+ case RTL_ROM_LMP_8703B:
|
||||
+ /* 8723CS reports two pages for local ext features,
|
||||
+ * but it doesn't support any features from page 2 -
|
||||
+ * it either responds with garbage or with error status
|
||||
+ */
|
||||
+ set_bit(HCI_QUIRK_BROKEN_LOCAL_EXT_FTR_MAX_PAGE,
|
||||
+ &hdev->quirks);
|
||||
+ break;
|
||||
+ default:
|
||||
+ break;
|
||||
+ }
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(btrtl_set_quirks);
|
||||
|
||||
@@ -910,6 +1017,12 @@ MODULE_FIRMWARE("rtl_bt/rtl8723b_fw.bin");
|
||||
MODULE_FIRMWARE("rtl_bt/rtl8723b_config.bin");
|
||||
MODULE_FIRMWARE("rtl_bt/rtl8723bs_fw.bin");
|
||||
MODULE_FIRMWARE("rtl_bt/rtl8723bs_config.bin");
|
||||
+MODULE_FIRMWARE("rtl_bt/rtl8723cs_cg_fw.bin");
|
||||
+MODULE_FIRMWARE("rtl_bt/rtl8723cs_cg_config.bin");
|
||||
+MODULE_FIRMWARE("rtl_bt/rtl8723cs_vf_fw.bin");
|
||||
+MODULE_FIRMWARE("rtl_bt/rtl8723cs_vf_config.bin");
|
||||
+MODULE_FIRMWARE("rtl_bt/rtl8723cs_xx_fw.bin");
|
||||
+MODULE_FIRMWARE("rtl_bt/rtl8723cs_xx_config.bin");
|
||||
MODULE_FIRMWARE("rtl_bt/rtl8723ds_fw.bin");
|
||||
MODULE_FIRMWARE("rtl_bt/rtl8723ds_config.bin");
|
||||
MODULE_FIRMWARE("rtl_bt/rtl8761a_fw.bin");
|
||||
diff --git a/drivers/bluetooth/btrtl.h b/drivers/bluetooth/btrtl.h
|
||||
index 2c441bda3..1c6282241 100644
|
||||
--- a/drivers/bluetooth/btrtl.h
|
||||
+++ b/drivers/bluetooth/btrtl.h
|
||||
@@ -14,6 +14,11 @@
|
||||
|
||||
struct btrtl_device_info;
|
||||
|
||||
+struct rtl_chip_type_evt {
|
||||
+ __u8 status;
|
||||
+ __u8 type;
|
||||
+} __packed;
|
||||
+
|
||||
struct rtl_download_cmd {
|
||||
__u8 index;
|
||||
__u8 data[RTL_FRAG_LEN];
|
||||
diff --git a/drivers/bluetooth/btrtl.c b/drivers/bluetooth/btrtl.c
|
||||
index 0d4b4a86d..1c668f349 100644
|
||||
--- a/drivers/bluetooth/btrtl.c
|
||||
+++ b/drivers/bluetooth/btrtl.c
|
||||
@@ -757,7 +757,7 @@ struct btrtl_device_info *btrtl_initialize(struct hci_dev *hdev,
|
||||
lmp_subver = le16_to_cpu(resp->lmp_subver);
|
||||
|
||||
btrtl_dev->ic_info = btrtl_match_ic(lmp_subver, hci_rev, hci_ver,
|
||||
- hdev->bus);
|
||||
+ hdev->bus, chip_type);
|
||||
}
|
||||
out_free:
|
||||
kfree_skb(skb);
|
||||
@ -0,0 +1,31 @@
|
||||
From 8fc0422773dc5274fa32e2a5a6ce2e1f0a96d78c Mon Sep 17 00:00:00 2001
|
||||
From: Vasily Khoruzhick <anarsoul@gmail.com>
|
||||
Date: Wed, 31 Oct 2018 20:07:41 -0700
|
||||
Subject: [PATCH 304/467] Bluetooth: hci_h5: Add support for binding RTL8723CS
|
||||
with device tree
|
||||
|
||||
RTL8723CS is often used in ARM boards, so add ability to bind it
|
||||
using device tree.
|
||||
|
||||
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
|
||||
Signed-off-by: Ondrej Jirman <megous@megous.com>
|
||||
---
|
||||
drivers/bluetooth/hci_h5.c | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
diff --git a/drivers/bluetooth/hci_h5.c b/drivers/bluetooth/hci_h5.c
|
||||
index d49a39d17..c9b54335a 100644
|
||||
--- a/drivers/bluetooth/hci_h5.c
|
||||
+++ b/drivers/bluetooth/hci_h5.c
|
||||
@@ -1100,6 +1100,8 @@ static const struct of_device_id rtl_bluetooth_of_match[] = {
|
||||
.data = (const void *)&h5_data_rtl8723bs },
|
||||
{ .compatible = "realtek,rtl8723ds-bt",
|
||||
.data = (const void *)&h5_data_rtl8723bs },
|
||||
+ { .compatible = "realtek,rtl8723cs-bt",
|
||||
+ .data = (const void *)&h5_data_rtl8723bs },
|
||||
#endif
|
||||
{ },
|
||||
};
|
||||
--
|
||||
2.34.0
|
||||
|
||||
@ -0,0 +1,42 @@
|
||||
From f0c05140b92cca447cd55a93ad4de141d0f117f1 Mon Sep 17 00:00:00 2001
|
||||
From: Paolo Sabatino <paolo.sabatino@gmail.com>
|
||||
Date: Thu, 9 Dec 2021 22:47:36 +0000
|
||||
Subject: [PATCH] rtl8703bs: add chip type to list and info block
|
||||
|
||||
---
|
||||
drivers/bluetooth/btrtl.c | 12 ++++++++++++
|
||||
1 file changed, 12 insertions(+)
|
||||
|
||||
diff --git a/drivers/bluetooth/btrtl.c b/drivers/bluetooth/btrtl.c
|
||||
index ad4085eede4..2c227bf4e00 100644
|
||||
--- a/drivers/bluetooth/btrtl.c
|
||||
+++ b/drivers/bluetooth/btrtl.c
|
||||
@@ -20,6 +20,7 @@
|
||||
#define RTL_CHIP_8723CS_CG 3
|
||||
#define RTL_CHIP_8723CS_VF 4
|
||||
#define RTL_CHIP_8723CS_XX 5
|
||||
+#define RTL_CHIP_8703BS 7
|
||||
#define RTL_EPATCH_SIGNATURE "Realtech"
|
||||
#define RTL_ROM_LMP_3499 0x3499
|
||||
#define RTL_ROM_LMP_8703B 0x8703
|
||||
@@ -136,6 +137,17 @@ static const struct id_table ic_id_table[] = {
|
||||
.fw_name = "rtl_bt/rtl8723cs_xx_fw.bin",
|
||||
.cfg_name = "rtl_bt/rtl8723cs_xx_config" },
|
||||
|
||||
+ /* 8703BS */
|
||||
+ { .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_CHIP_TYPE |
|
||||
+ IC_MATCH_FL_HCIBUS,
|
||||
+ .lmp_subver = RTL_ROM_LMP_8703B,
|
||||
+ .chip_type = RTL_CHIP_8703BS,
|
||||
+ .hci_bus = HCI_UART,
|
||||
+ .config_needed = true,
|
||||
+ .has_rom_version = true,
|
||||
+ .fw_name = "rtl_bt/rtl8723cs_xx_fw.bin",
|
||||
+ .cfg_name = "rtl_bt/rtl8723cs_xx_config" },
|
||||
+
|
||||
/* 8723D */
|
||||
{ IC_INFO(RTL_ROM_LMP_8723B, 0xd, 0x8, HCI_USB),
|
||||
.config_needed = true,
|
||||
--
|
||||
2.30.2
|
||||
|
||||
@ -0,0 +1,108 @@
|
||||
diff --git a/arch/arm/boot/.gitignore b/arch/arm/boot/.gitignore
|
||||
index 3c79f859..4e5c1d59 100644
|
||||
--- a/arch/arm/boot/.gitignore
|
||||
+++ b/arch/arm/boot/.gitignore
|
||||
@@ -3,3 +3,5 @@ zImage
|
||||
xipImage
|
||||
bootpImage
|
||||
uImage
|
||||
+*.dtb*
|
||||
+*.scr
|
||||
diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst
|
||||
index 50d580d77..94bd15617 100644
|
||||
--- a/scripts/Makefile.dtbinst
|
||||
+++ b/scripts/Makefile.dtbinst
|
||||
@@ -18,9 +18,12 @@ include scripts/Kbuild.include
|
||||
include $(src)/Makefile
|
||||
|
||||
dtbs := $(addprefix $(dst)/, $(dtb-y) $(if $(CONFIG_OF_ALL_DTBS),$(dtb-)))
|
||||
+dtbos := $(addprefix $(dst)/, $(dtbo-y))
|
||||
+scrs := $(addprefix $(dst)/, $(scr-y))
|
||||
+readmes := $(addprefix $(dst)/, $(dtbotxt-y))
|
||||
subdirs := $(addprefix $(obj)/, $(subdir-y) $(subdir-m))
|
||||
|
||||
-__dtbs_install: $(dtbs) $(subdirs)
|
||||
+__dtbs_install: $(dtbs) $(dtbos) $(scrs) $(readmes) $(subdirs)
|
||||
@:
|
||||
|
||||
quiet_cmd_dtb_install = INSTALL $@
|
||||
@@ -29,6 +32,15 @@ quiet_cmd_dtb_install = INSTALL $@
|
||||
$(dst)/%.dtb: $(obj)/%.dtb
|
||||
$(call cmd,dtb_install)
|
||||
|
||||
+$(dst)/%.dtbo: $(obj)/%.dtbo
|
||||
+ $(call cmd,dtb_install)
|
||||
+
|
||||
+$(dst)/%.scr: $(obj)/%.scr
|
||||
+ $(call cmd,dtb_install)
|
||||
+
|
||||
+$(dst)/README.rk322x-overlays: $(src)/README.rk322x-overlays
|
||||
+ $(call cmd,dtb_install)
|
||||
+
|
||||
PHONY += $(subdirs)
|
||||
$(subdirs):
|
||||
$(Q)$(MAKE) $(dtbinst)=$@ dst=$(patsubst $(obj)/%,$(dst)/%,$@)
|
||||
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
|
||||
index 58c05e5d..2b95dda9 100644
|
||||
--- a/scripts/Makefile.lib
|
||||
+++ b/scripts/Makefile.lib
|
||||
@@ -278,6 +278,9 @@ cmd_gzip = (cat $(filter-out FORCE,$^) | gzip -n -f -9 > $@) || \
|
||||
# ---------------------------------------------------------------------------
|
||||
DTC ?= $(objtree)/scripts/dtc/dtc
|
||||
|
||||
+# Overlay support
|
||||
+DTC_FLAGS += -@ -Wno-unit_address_format -Wno-simple_bus_reg
|
||||
+
|
||||
# Disable noisy checks by default
|
||||
ifeq ($(KBUILD_ENABLE_EXTRA_GCC_CHECKS),)
|
||||
DTC_FLAGS += -Wno-unit_address_vs_reg \
|
||||
@@ -324,6 +327,23 @@ cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \
|
||||
$(obj)/%.dtb: $(src)/%.dts FORCE
|
||||
$(call if_changed_dep,dtc)
|
||||
|
||||
+quiet_cmd_dtco = DTCO $@
|
||||
+cmd_dtco = mkdir -p $(dir ${dtc-tmp}) ; \
|
||||
+ $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
|
||||
+ $(DTC) -O dtb -o $@ -b 0 \
|
||||
+ -i $(dir $<) $(DTC_FLAGS) \
|
||||
+ -d $(depfile).dtc.tmp $(dtc-tmp) ; \
|
||||
+ cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
|
||||
+
|
||||
+$(obj)/%.dtbo: $(src)/%.dts FORCE
|
||||
+ $(call if_changed_dep,dtco)
|
||||
+
|
||||
+quiet_cmd_scr = MKIMAGE $@
|
||||
+cmd_scr = mkimage -C none -A $(ARCH) -T script -d $< $@
|
||||
+
|
||||
+$(obj)/%.scr: $(src)/%.scr-cmd FORCE
|
||||
+ $(call if_changed,scr)
|
||||
+
|
||||
dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp)
|
||||
|
||||
# Bzip2
|
||||
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
|
||||
index 41c50f9461e5..387659d5b252 100644
|
||||
--- a/scripts/Makefile.lib
|
||||
+++ b/scripts/Makefile.lib
|
||||
@@ -79,6 +79,9 @@ header-test-y += $(filter-out $(header-test-), \
|
||||
|
||||
extra-$(CONFIG_HEADER_TEST) += $(addsuffix .s, $(header-test-y) $(header-test-m))
|
||||
|
||||
+# Overlay targets
|
||||
+extra-y += $(dtbo-y) $(scr-y) $(dtbotxt-y)
|
||||
+
|
||||
# Add subdir path
|
||||
|
||||
extra-y := $(addprefix $(obj)/,$(extra-y))
|
||||
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
|
||||
index e8dd99201..1e45adf97 100644
|
||||
--- a/arch/arm/boot/dts/Makefile
|
||||
+++ b/arch/arm/boot/dts/Makefile
|
||||
@@ -977,6 +984,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
|
||||
rk3288-veyron-speedy.dtb \
|
||||
rk3288-veyron-tiger.dtb \
|
||||
rk3288-vyasa.dtb
|
||||
+subdir-y := $(dts-dirs) overlay
|
||||
dtb-$(CONFIG_ARCH_S3C24XX) += \
|
||||
s3c2416-smdk2416.dtb
|
||||
dtb-$(CONFIG_ARCH_S3C64XX) += \
|
||||
@ -0,0 +1,358 @@
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/configfs-overlays.txt
|
||||
@@ -0,0 +1,31 @@
|
||||
+Howto use the configfs overlay interface.
|
||||
+
|
||||
+A device-tree configfs entry is created in /config/device-tree/overlays
|
||||
+and and it is manipulated using standard file system I/O.
|
||||
+Note that this is a debug level interface, for use by developers and
|
||||
+not necessarily something accessed by normal users due to the
|
||||
+security implications of having direct access to the kernel's device tree.
|
||||
+
|
||||
+* To create an overlay you mkdir the directory:
|
||||
+
|
||||
+ # mkdir /config/device-tree/overlays/foo
|
||||
+
|
||||
+* Either you echo the overlay firmware file to the path property file.
|
||||
+
|
||||
+ # echo foo.dtbo >/config/device-tree/overlays/foo/path
|
||||
+
|
||||
+* Or you cat the contents of the overlay to the dtbo file
|
||||
+
|
||||
+ # cat foo.dtbo >/config/device-tree/overlays/foo/dtbo
|
||||
+
|
||||
+The overlay file will be applied, and devices will be created/destroyed
|
||||
+as required.
|
||||
+
|
||||
+To remove it simply rmdir the directory.
|
||||
+
|
||||
+ # rmdir /config/device-tree/overlays/foo
|
||||
+
|
||||
+The rationalle of the dual interface (firmware & direct copy) is that each is
|
||||
+better suited to different use patterns. The firmware interface is what's
|
||||
+intended to be used by hardware managers in the kernel, while the copy interface
|
||||
+make sense for developers (since it avoids problems with namespaces).
|
||||
diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
|
||||
index 37c2ccbefecdc..d3fc81a40c0e7 100644
|
||||
--- a/drivers/of/Kconfig
|
||||
+++ b/drivers/of/Kconfig
|
||||
@@ -103,4 +103,11 @@ config OF_OVERLAY
|
||||
config OF_NUMA
|
||||
bool
|
||||
|
||||
+config OF_CONFIGFS
|
||||
+ bool "Device Tree Overlay ConfigFS interface"
|
||||
+ select CONFIGFS_FS
|
||||
+ select OF_OVERLAY
|
||||
+ help
|
||||
+ Enable a simple user-space driven DT overlay interface.
|
||||
+
|
||||
endif # OF
|
||||
diff --git a/drivers/of/Makefile b/drivers/of/Makefile
|
||||
index 663a4af0cccd5..b00a95adf5199 100644
|
||||
--- a/drivers/of/Makefile
|
||||
+++ b/drivers/of/Makefile
|
||||
@@ -1,6 +1,7 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
obj-y = base.o device.o platform.o property.o
|
||||
obj-$(CONFIG_OF_KOBJ) += kobj.o
|
||||
+obj-$(CONFIG_OF_CONFIGFS) += configfs.o
|
||||
obj-$(CONFIG_OF_DYNAMIC) += dynamic.o
|
||||
obj-$(CONFIG_OF_FLATTREE) += fdt.o
|
||||
obj-$(CONFIG_OF_EARLY_FLATTREE) += fdt_address.o
|
||||
diff --git a/drivers/of/configfs.c b/drivers/of/configfs.c
|
||||
new file mode 100644
|
||||
index 000000000..5dd509e8f
|
||||
--- /dev/null
|
||||
+++ b/drivers/of/configfs.c
|
||||
@@ -0,0 +1,290 @@
|
||||
+/*
|
||||
+ * Configfs entries for device-tree
|
||||
+ *
|
||||
+ * Copyright (C) 2013 - Pantelis Antoniou <panto@antoniou-consulting.com>
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or
|
||||
+ * modify it under the terms of the GNU General Public License
|
||||
+ * as published by the Free Software Foundation; either version
|
||||
+ * 2 of the License, or (at your option) any later version.
|
||||
+ */
|
||||
+#include <linux/ctype.h>
|
||||
+#include <linux/cpu.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/of_fdt.h>
|
||||
+#include <linux/spinlock.h>
|
||||
+#include <linux/slab.h>
|
||||
+#include <linux/proc_fs.h>
|
||||
+#include <linux/configfs.h>
|
||||
+#include <linux/types.h>
|
||||
+#include <linux/stat.h>
|
||||
+#include <linux/limits.h>
|
||||
+#include <linux/file.h>
|
||||
+#include <linux/vmalloc.h>
|
||||
+#include <linux/firmware.h>
|
||||
+#include <linux/sizes.h>
|
||||
+
|
||||
+#include "of_private.h"
|
||||
+
|
||||
+struct cfs_overlay_item {
|
||||
+ struct config_item item;
|
||||
+
|
||||
+ char path[PATH_MAX];
|
||||
+
|
||||
+ const struct firmware *fw;
|
||||
+ struct device_node *overlay;
|
||||
+ int ov_id;
|
||||
+
|
||||
+ void *dtbo;
|
||||
+ int dtbo_size;
|
||||
+};
|
||||
+
|
||||
+static int create_overlay(struct cfs_overlay_item *overlay, void *blob, u32 blob_size)
|
||||
+{
|
||||
+ int err;
|
||||
+
|
||||
+ err = of_overlay_fdt_apply(blob, blob_size, &overlay->ov_id);
|
||||
+ if (err < 0) {
|
||||
+ pr_err("%s: Failed to create overlay (err=%d)\n",
|
||||
+ __func__, err);
|
||||
+ goto out_err;
|
||||
+ }
|
||||
+
|
||||
+out_err:
|
||||
+ return err;
|
||||
+}
|
||||
+
|
||||
+static inline struct cfs_overlay_item *to_cfs_overlay_item(
|
||||
+ struct config_item *item)
|
||||
+{
|
||||
+ return item ? container_of(item, struct cfs_overlay_item, item) : NULL;
|
||||
+}
|
||||
+
|
||||
+static ssize_t cfs_overlay_item_path_show(struct config_item *item,
|
||||
+ char *page)
|
||||
+{
|
||||
+ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
|
||||
+ return sprintf(page, "%s\n", overlay->path);
|
||||
+}
|
||||
+
|
||||
+static ssize_t cfs_overlay_item_path_store(struct config_item *item,
|
||||
+ const char *page, size_t count)
|
||||
+{
|
||||
+ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
|
||||
+ const char *p = page;
|
||||
+ char *s;
|
||||
+ int err;
|
||||
+
|
||||
+ /* if it's set do not allow changes */
|
||||
+ if (overlay->path[0] != '\0' || overlay->dtbo_size > 0)
|
||||
+ return -EPERM;
|
||||
+
|
||||
+ /* copy to path buffer (and make sure it's always zero terminated */
|
||||
+ count = snprintf(overlay->path, sizeof(overlay->path) - 1, "%s", p);
|
||||
+ overlay->path[sizeof(overlay->path) - 1] = '\0';
|
||||
+
|
||||
+ /* strip trailing newlines */
|
||||
+ s = overlay->path + strlen(overlay->path);
|
||||
+ while (s > overlay->path && *--s == '\n')
|
||||
+ *s = '\0';
|
||||
+
|
||||
+ pr_debug("%s: path is '%s'\n", __func__, overlay->path);
|
||||
+
|
||||
+ err = request_firmware(&overlay->fw, overlay->path, NULL);
|
||||
+ if (err != 0)
|
||||
+ goto out_err;
|
||||
+
|
||||
+ err = create_overlay(overlay, (void *)overlay->fw->data, overlay->fw->size);
|
||||
+ if (err != 0)
|
||||
+ goto out_err;
|
||||
+
|
||||
+ return count;
|
||||
+
|
||||
+out_err:
|
||||
+
|
||||
+ release_firmware(overlay->fw);
|
||||
+ overlay->fw = NULL;
|
||||
+
|
||||
+ overlay->path[0] = '\0';
|
||||
+ return err;
|
||||
+}
|
||||
+
|
||||
+static ssize_t cfs_overlay_item_status_show(struct config_item *item,
|
||||
+ char *page)
|
||||
+{
|
||||
+ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
|
||||
+
|
||||
+ return sprintf(page, "%s\n",
|
||||
+ overlay->ov_id >= 0 ? "applied" : "unapplied");
|
||||
+}
|
||||
+
|
||||
+CONFIGFS_ATTR(cfs_overlay_item_, path);
|
||||
+CONFIGFS_ATTR_RO(cfs_overlay_item_, status);
|
||||
+
|
||||
+static struct configfs_attribute *cfs_overlay_attrs[] = {
|
||||
+ &cfs_overlay_item_attr_path,
|
||||
+ &cfs_overlay_item_attr_status,
|
||||
+ NULL,
|
||||
+};
|
||||
+
|
||||
+ssize_t cfs_overlay_item_dtbo_read(struct config_item *item,
|
||||
+ void *buf, size_t max_count)
|
||||
+{
|
||||
+ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
|
||||
+
|
||||
+ pr_debug("%s: buf=%p max_count=%zu\n", __func__,
|
||||
+ buf, max_count);
|
||||
+
|
||||
+ if (overlay->dtbo == NULL)
|
||||
+ return 0;
|
||||
+
|
||||
+ /* copy if buffer provided */
|
||||
+ if (buf != NULL) {
|
||||
+ /* the buffer must be large enough */
|
||||
+ if (overlay->dtbo_size > max_count)
|
||||
+ return -ENOSPC;
|
||||
+
|
||||
+ memcpy(buf, overlay->dtbo, overlay->dtbo_size);
|
||||
+ }
|
||||
+
|
||||
+ return overlay->dtbo_size;
|
||||
+}
|
||||
+
|
||||
+ssize_t cfs_overlay_item_dtbo_write(struct config_item *item,
|
||||
+ const void *buf, size_t count)
|
||||
+{
|
||||
+ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
|
||||
+ int err;
|
||||
+
|
||||
+ /* if it's set do not allow changes */
|
||||
+ if (overlay->path[0] != '\0' || overlay->dtbo_size > 0)
|
||||
+ return -EPERM;
|
||||
+
|
||||
+ /* copy the contents */
|
||||
+ overlay->dtbo = kmemdup(buf, count, GFP_KERNEL);
|
||||
+ if (overlay->dtbo == NULL)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ overlay->dtbo_size = count;
|
||||
+
|
||||
+ err = create_overlay(overlay, overlay->dtbo, overlay->dtbo_size);
|
||||
+ if (err != 0)
|
||||
+ goto out_err;
|
||||
+
|
||||
+ return count;
|
||||
+
|
||||
+out_err:
|
||||
+ kfree(overlay->dtbo);
|
||||
+ overlay->dtbo = NULL;
|
||||
+ overlay->dtbo_size = 0;
|
||||
+
|
||||
+ return err;
|
||||
+}
|
||||
+
|
||||
+CONFIGFS_BIN_ATTR(cfs_overlay_item_, dtbo, NULL, SZ_1M);
|
||||
+
|
||||
+static struct configfs_bin_attribute *cfs_overlay_bin_attrs[] = {
|
||||
+ &cfs_overlay_item_attr_dtbo,
|
||||
+ NULL,
|
||||
+};
|
||||
+
|
||||
+static void cfs_overlay_release(struct config_item *item)
|
||||
+{
|
||||
+ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
|
||||
+
|
||||
+ if (overlay->ov_id >= 0)
|
||||
+ of_overlay_remove(&overlay->ov_id);
|
||||
+ if (overlay->fw)
|
||||
+ release_firmware(overlay->fw);
|
||||
+ /* kfree with NULL is safe */
|
||||
+ kfree(overlay->dtbo);
|
||||
+ kfree(overlay);
|
||||
+}
|
||||
+
|
||||
+static struct configfs_item_operations cfs_overlay_item_ops = {
|
||||
+ .release = cfs_overlay_release,
|
||||
+};
|
||||
+
|
||||
+static struct config_item_type cfs_overlay_type = {
|
||||
+ .ct_item_ops = &cfs_overlay_item_ops,
|
||||
+ .ct_attrs = cfs_overlay_attrs,
|
||||
+ .ct_bin_attrs = cfs_overlay_bin_attrs,
|
||||
+ .ct_owner = THIS_MODULE,
|
||||
+};
|
||||
+
|
||||
+static struct config_item *cfs_overlay_group_make_item(
|
||||
+ struct config_group *group, const char *name)
|
||||
+{
|
||||
+ struct cfs_overlay_item *overlay;
|
||||
+
|
||||
+ overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
|
||||
+ if (!overlay)
|
||||
+ return ERR_PTR(-ENOMEM);
|
||||
+ overlay->ov_id = -1;
|
||||
+
|
||||
+ config_item_init_type_name(&overlay->item, name, &cfs_overlay_type);
|
||||
+ return &overlay->item;
|
||||
+}
|
||||
+
|
||||
+static void cfs_overlay_group_drop_item(struct config_group *group,
|
||||
+ struct config_item *item)
|
||||
+{
|
||||
+ struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
|
||||
+
|
||||
+ config_item_put(&overlay->item);
|
||||
+}
|
||||
+
|
||||
+static struct configfs_group_operations overlays_ops = {
|
||||
+ .make_item = cfs_overlay_group_make_item,
|
||||
+ .drop_item = cfs_overlay_group_drop_item,
|
||||
+};
|
||||
+
|
||||
+static struct config_item_type overlays_type = {
|
||||
+ .ct_group_ops = &overlays_ops,
|
||||
+ .ct_owner = THIS_MODULE,
|
||||
+};
|
||||
+
|
||||
+static struct configfs_group_operations of_cfs_ops = {
|
||||
+ /* empty - we don't allow anything to be created */
|
||||
+};
|
||||
+
|
||||
+static struct config_item_type of_cfs_type = {
|
||||
+ .ct_group_ops = &of_cfs_ops,
|
||||
+ .ct_owner = THIS_MODULE,
|
||||
+};
|
||||
+
|
||||
+struct config_group of_cfs_overlay_group;
|
||||
+
|
||||
+static struct configfs_subsystem of_cfs_subsys = {
|
||||
+ .su_group = {
|
||||
+ .cg_item = {
|
||||
+ .ci_namebuf = "device-tree",
|
||||
+ .ci_type = &of_cfs_type,
|
||||
+ },
|
||||
+ },
|
||||
+ .su_mutex = __MUTEX_INITIALIZER(of_cfs_subsys.su_mutex),
|
||||
+};
|
||||
+
|
||||
+static int __init of_cfs_init(void)
|
||||
+{
|
||||
+ int ret;
|
||||
+
|
||||
+ pr_info("%s\n", __func__);
|
||||
+
|
||||
+ config_group_init(&of_cfs_subsys.su_group);
|
||||
+ config_group_init_type_name(&of_cfs_overlay_group, "overlays",
|
||||
+ &overlays_type);
|
||||
+ configfs_add_default_group(&of_cfs_overlay_group,
|
||||
+ &of_cfs_subsys.su_group);
|
||||
+
|
||||
+ ret = configfs_register_subsystem(&of_cfs_subsys);
|
||||
+ if (ret != 0) {
|
||||
+ pr_err("%s: failed to register subsys\n", __func__);
|
||||
+ goto out;
|
||||
+ }
|
||||
+ pr_info("%s: OK\n", __func__);
|
||||
+out:
|
||||
+ return ret;
|
||||
+}
|
||||
+late_initcall(of_cfs_init);
|
||||
1447
patch/kernel/archive/rk322x-5.16/general-add-overlays.patch
Normal file
1447
patch/kernel/archive/rk322x-5.16/general-add-overlays.patch
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,24 @@
|
||||
diff --git a/drivers/net/wireless/realtek/Kconfig b/drivers/net/wireless/realtek/Kconfig
|
||||
index 4a1f0e64d..f0ec44158 100644
|
||||
--- a/drivers/net/wireless/realtek/Kconfig
|
||||
+++ b/drivers/net/wireless/realtek/Kconfig
|
||||
@@ -16,6 +16,7 @@ source "drivers/net/wireless/realtek/rtl818x/Kconfig"
|
||||
source "drivers/net/wireless/realtek/rtlwifi/Kconfig"
|
||||
source "drivers/net/wireless/realtek/rtl8xxxu/Kconfig"
|
||||
source "drivers/net/wireless/realtek/rtw88/Kconfig"
|
||||
+source "drivers/net/wireless/realtek/rtl8723cs/Kconfig"
|
||||
source "drivers/net/wireless/realtek/rtw89/Kconfig"
|
||||
|
||||
endif # WLAN_VENDOR_REALTEK
|
||||
diff --git a/drivers/net/wireless/realtek/Makefile b/drivers/net/wireless/realtek/Makefile
|
||||
index 9c78deb5..07b47850 100644
|
||||
--- a/drivers/net/wireless/realtek/Makefile
|
||||
+++ b/drivers/net/wireless/realtek/Makefile
|
||||
@@ -4,6 +4,7 @@
|
||||
|
||||
obj-$(CONFIG_RTL8180) += rtl818x/
|
||||
obj-$(CONFIG_RTL8187) += rtl818x/
|
||||
+obj-$(CONFIG_RTL8723CS) += rtl8723cs/
|
||||
obj-$(CONFIG_RTLWIFI) += rtlwifi/
|
||||
obj-$(CONFIG_RTL8XXXU) += rtl8xxxu/
|
||||
|
||||
349058
patch/kernel/archive/rk322x-5.16/wifi-4002-add-realtek-8723cs.patch
Normal file
349058
patch/kernel/archive/rk322x-5.16/wifi-4002-add-realtek-8723cs.patch
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,31 @@
|
||||
From 4f15b08033441eeb2004c2a7ec19c91e1e75c332 Mon Sep 17 00:00:00 2001
|
||||
From: The-going <48602507+The-going@users.noreply.github.com>
|
||||
Date: Mon, 22 Nov 2021 18:53:11 +0300
|
||||
Subject: [PATCH] wifi 4002 realtek 8723cs Fix IEEE80211_MAX_AMPDU_BUF
|
||||
redefined
|
||||
|
||||
After v4.19 linux kernel, this definition is not required.
|
||||
The 1 drivers/net/wireless/realtek/rtlwifi/base.c file uses
|
||||
the variable IEEE80211_MAX_AMPDU_BUF_HT.
|
||||
|
||||
See `git log -p b8042b3da925f390c1482b -3` command in
|
||||
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git
|
||||
---
|
||||
drivers/net/wireless/realtek/rtl8723cs/include/wifi.h | 1 -
|
||||
1 file changed, 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/net/wireless/realtek/rtl8723cs/include/wifi.h b/drivers/net/wireless/realtek/rtl8723cs/include/wifi.h
|
||||
index 9d21a5afd..8ef0fd7ff 100644
|
||||
--- a/drivers/net/wireless/realtek/rtl8723cs/include/wifi.h
|
||||
+++ b/drivers/net/wireless/realtek/rtl8723cs/include/wifi.h
|
||||
@@ -1006,7 +1006,6 @@ typedef enum _HT_CAP_AMPDU_DENSITY {
|
||||
* According to IEEE802.11n spec size varies from 8K to 64K (in powers of 2)
|
||||
*/
|
||||
#define IEEE80211_MIN_AMPDU_BUF 0x8
|
||||
-#define IEEE80211_MAX_AMPDU_BUF 0x40
|
||||
|
||||
|
||||
/* Spatial Multiplexing Power Save Modes */
|
||||
--
|
||||
2.33.1
|
||||
|
||||
49476
patch/kernel/archive/rk322x-5.16/wifi-4003-ssv-6051-driver.patch
Normal file
49476
patch/kernel/archive/rk322x-5.16/wifi-4003-ssv-6051-driver.patch
Normal file
File diff suppressed because it is too large
Load Diff
@ -1343,42 +1343,6 @@ index 618849186c39..11825909c5db 100644
|
||||
compatible = "rockchip,rk3568-pinctrl";
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Matthias Brugger <mbrugger@suse.com>
|
||||
Date: Thu, 15 Jul 2021 18:41:01 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: Disable CDN DP on Pinebook Pro
|
||||
|
||||
The CDN DP needs a PHY and a extcon to work correctly. But no extcon is
|
||||
provided by the device-tree, which leads to an error:
|
||||
cdn-dp fec00000.dp: [drm:cdn_dp_probe [rockchipdrm]] *ERROR* missing extcon or phy
|
||||
cdn-dp: probe of fec00000.dp failed with error -22
|
||||
|
||||
Disable the CDN DP to make graphic work on the Pinebook Pro.
|
||||
|
||||
Reported-by: Guillaume Gardet <guillaume.gardet@arm.com>
|
||||
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
|
||||
Link: https://lore.kernel.org/r/20210715164101.11486-1-matthias.bgg@kernel.org
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 4 ----
|
||||
1 file changed, 4 deletions(-)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
|
||||
index 2b5f001ff4a6..9e5d07f5712e 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
|
||||
@@ -385,10 +385,6 @@ mains_charger: dc-charger {
|
||||
};
|
||||
};
|
||||
|
||||
-&cdn_dp {
|
||||
- status = "okay";
|
||||
-};
|
||||
-
|
||||
&cpu_b0 {
|
||||
cpu-supply = <&vdd_cpu_b>;
|
||||
};
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Fri, 18 Jun 2021 20:12:52 +0200
|
||||
|
||||
@ -289,37 +289,6 @@ index 95fedcf56e4a..38e75b275bb6 100644
|
||||
|
||||
host->ios.clock = 0;
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Wed, 23 Jun 2021 13:59:26 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: Fix GPU register width for RK3328
|
||||
|
||||
As can be seen in RK3328's TRM the register range for the GPU is
|
||||
0xff300000 to 0xff330000.
|
||||
It would (and does in vendor kernel) overlap with the registers of
|
||||
the HEVC encoder (node/driver do not exist yet in upstream kernel).
|
||||
See already existing h265e_mmu node.
|
||||
|
||||
Fixes: 752fbc0c8da7 ("arm64: dts: rockchip: add rk3328 mali gpu node")
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
index becc1c61b182..5b2020590f53 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
@@ -599,7 +599,7 @@ saradc: adc@ff280000 {
|
||||
|
||||
gpu: gpu@ff300000 {
|
||||
compatible = "rockchip,rk3328-mali", "arm,mali-450";
|
||||
- reg = <0x0 0xff300000 0x0 0x40000>;
|
||||
+ reg = <0x0 0xff300000 0x0 0x30000>;
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Wed, 23 Jun 2021 16:59:18 +0200
|
||||
|
||||
@ -161,40 +161,6 @@ index 9852c3519f56..f3ff3e709169 100644
|
||||
WRITE_PPS(sps->log2_max_frame_num_minus4, LOG2_MAX_FRAME_NUM_MINUS4);
|
||||
WRITE_PPS(sps->max_num_ref_frames, MAX_NUM_REF_FRAMES);
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Mon, 6 Jul 2020 21:54:35 +0000
|
||||
Subject: [PATCH] media: rkvdec: h264: Do not override output buffer sizeimage
|
||||
|
||||
The output buffer sizeimage is currently forced to 2 bytes per pixel, this
|
||||
can lead to high memory usage for 4K content when multiple output buffers
|
||||
is created by userspace.
|
||||
|
||||
Do not override output buffer sizeimage and let userspace have control of
|
||||
output buffer sizeimage by only setting sizeimage if none is provided.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/staging/media/rkvdec/rkvdec-h264.c | 5 +++--
|
||||
1 file changed, 3 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
index f3ff3e709169..503ae683d0fd 100644
|
||||
--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
@@ -1015,8 +1015,9 @@ static int rkvdec_h264_adjust_fmt(struct rkvdec_ctx *ctx,
|
||||
struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp;
|
||||
|
||||
fmt->num_planes = 1;
|
||||
- fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height *
|
||||
- RKVDEC_H264_MAX_DEPTH_IN_BYTES;
|
||||
+ if (!fmt->plane_fmt[0].sizeimage)
|
||||
+ fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height *
|
||||
+ RKVDEC_H264_MAX_DEPTH_IN_BYTES;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Mon, 6 Jul 2020 21:54:35 +0000
|
||||
|
||||
@ -3650,31 +3650,6 @@ index fbaf0303f7c2..2c0c6dcbd066 100644
|
||||
}
|
||||
};
|
||||
|
||||
@@ -373,7 +421,7 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv,
|
||||
struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx;
|
||||
const struct rkvdec_coded_fmt_desc *desc;
|
||||
struct v4l2_format *cap_fmt;
|
||||
- struct vb2_queue *peer_vq;
|
||||
+ struct vb2_queue *peer_vq, *vq;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
@@ -385,6 +433,15 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv,
|
||||
if (vb2_is_busy(peer_vq))
|
||||
return -EBUSY;
|
||||
|
||||
+ /*
|
||||
+ * Some codecs like VP9 can contain dynamic resolution changes which
|
||||
+ * are currently not supported by the V4L2 API or driver, so return
|
||||
+ * an error if userspace tries to reconfigure the output format.
|
||||
+ */
|
||||
+ vq = v4l2_m2m_get_vq(m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
|
||||
+ if (vb2_is_busy(vq))
|
||||
+ return -EINVAL;
|
||||
+
|
||||
ret = rkvdec_s_fmt(file, priv, f, rkvdec_try_output_fmt);
|
||||
if (ret)
|
||||
return ret;
|
||||
diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
|
||||
index fa24bcb6ff42..18dd721172d8 100644
|
||||
--- a/drivers/staging/media/rkvdec/rkvdec.h
|
||||
|
||||
@ -0,0 +1,287 @@
|
||||
From 3ec70749ae3cb072f19d886981a217121f776415 Mon Sep 17 00:00:00 2001
|
||||
From: Igor Pecovnik <igor.pecovnik@gmail.com>
|
||||
Date: Sat, 6 Nov 2021 19:15:23 +0100
|
||||
Subject: [PATCH] Revert "net: Remove net/ipx.h and uapi/linux/ipx.h header
|
||||
files"
|
||||
|
||||
This reverts commit 6c9b40844751ea30c72f7a2f92f4d704bc6b2927.
|
||||
---
|
||||
include/net/ipx.h | 171 +++++++++++++++++++++++++++++++++++++++
|
||||
include/uapi/linux/ipx.h | 87 ++++++++++++++++++++
|
||||
2 files changed, 258 insertions(+)
|
||||
create mode 100644 include/net/ipx.h
|
||||
create mode 100644 include/uapi/linux/ipx.h
|
||||
|
||||
diff --git a/include/net/ipx.h b/include/net/ipx.h
|
||||
new file mode 100644
|
||||
index 000000000000..9d1342807b59
|
||||
--- /dev/null
|
||||
+++ b/include/net/ipx.h
|
||||
@@ -0,0 +1,171 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0 */
|
||||
+#ifndef _NET_INET_IPX_H_
|
||||
+#define _NET_INET_IPX_H_
|
||||
+/*
|
||||
+ * The following information is in its entirety obtained from:
|
||||
+ *
|
||||
+ * Novell 'IPX Router Specification' Version 1.10
|
||||
+ * Part No. 107-000029-001
|
||||
+ *
|
||||
+ * Which is available from ftp.novell.com
|
||||
+ */
|
||||
+
|
||||
+#include <linux/netdevice.h>
|
||||
+#include <net/datalink.h>
|
||||
+#include <linux/ipx.h>
|
||||
+#include <linux/list.h>
|
||||
+#include <linux/slab.h>
|
||||
+#include <linux/refcount.h>
|
||||
+
|
||||
+struct ipx_address {
|
||||
+ __be32 net;
|
||||
+ __u8 node[IPX_NODE_LEN];
|
||||
+ __be16 sock;
|
||||
+};
|
||||
+
|
||||
+#define ipx_broadcast_node "\377\377\377\377\377\377"
|
||||
+#define ipx_this_node "\0\0\0\0\0\0"
|
||||
+
|
||||
+#define IPX_MAX_PPROP_HOPS 8
|
||||
+
|
||||
+struct ipxhdr {
|
||||
+ __be16 ipx_checksum __packed;
|
||||
+#define IPX_NO_CHECKSUM cpu_to_be16(0xFFFF)
|
||||
+ __be16 ipx_pktsize __packed;
|
||||
+ __u8 ipx_tctrl;
|
||||
+ __u8 ipx_type;
|
||||
+#define IPX_TYPE_UNKNOWN 0x00
|
||||
+#define IPX_TYPE_RIP 0x01 /* may also be 0 */
|
||||
+#define IPX_TYPE_SAP 0x04 /* may also be 0 */
|
||||
+#define IPX_TYPE_SPX 0x05 /* SPX protocol */
|
||||
+#define IPX_TYPE_NCP 0x11 /* $lots for docs on this (SPIT) */
|
||||
+#define IPX_TYPE_PPROP 0x14 /* complicated flood fill brdcast */
|
||||
+ struct ipx_address ipx_dest __packed;
|
||||
+ struct ipx_address ipx_source __packed;
|
||||
+};
|
||||
+
|
||||
+/* From af_ipx.c */
|
||||
+extern int sysctl_ipx_pprop_broadcasting;
|
||||
+
|
||||
+struct ipx_interface {
|
||||
+ /* IPX address */
|
||||
+ __be32 if_netnum;
|
||||
+ unsigned char if_node[IPX_NODE_LEN];
|
||||
+ refcount_t refcnt;
|
||||
+
|
||||
+ /* physical device info */
|
||||
+ struct net_device *if_dev;
|
||||
+ struct datalink_proto *if_dlink;
|
||||
+ __be16 if_dlink_type;
|
||||
+
|
||||
+ /* socket support */
|
||||
+ unsigned short if_sknum;
|
||||
+ struct hlist_head if_sklist;
|
||||
+ spinlock_t if_sklist_lock;
|
||||
+
|
||||
+ /* administrative overhead */
|
||||
+ int if_ipx_offset;
|
||||
+ unsigned char if_internal;
|
||||
+ unsigned char if_primary;
|
||||
+
|
||||
+ struct list_head node; /* node in ipx_interfaces list */
|
||||
+};
|
||||
+
|
||||
+struct ipx_route {
|
||||
+ __be32 ir_net;
|
||||
+ struct ipx_interface *ir_intrfc;
|
||||
+ unsigned char ir_routed;
|
||||
+ unsigned char ir_router_node[IPX_NODE_LEN];
|
||||
+ struct list_head node; /* node in ipx_routes list */
|
||||
+ refcount_t refcnt;
|
||||
+};
|
||||
+
|
||||
+struct ipx_cb {
|
||||
+ u8 ipx_tctrl;
|
||||
+ __be32 ipx_dest_net;
|
||||
+ __be32 ipx_source_net;
|
||||
+ struct {
|
||||
+ __be32 netnum;
|
||||
+ int index;
|
||||
+ } last_hop;
|
||||
+};
|
||||
+
|
||||
+#include <net/sock.h>
|
||||
+
|
||||
+struct ipx_sock {
|
||||
+ /* struct sock has to be the first member of ipx_sock */
|
||||
+ struct sock sk;
|
||||
+ struct ipx_address dest_addr;
|
||||
+ struct ipx_interface *intrfc;
|
||||
+ __be16 port;
|
||||
+#ifdef CONFIG_IPX_INTERN
|
||||
+ unsigned char node[IPX_NODE_LEN];
|
||||
+#endif
|
||||
+ unsigned short type;
|
||||
+ /*
|
||||
+ * To handle special ncp connection-handling sockets for mars_nwe,
|
||||
+ * the connection number must be stored in the socket.
|
||||
+ */
|
||||
+ unsigned short ipx_ncp_conn;
|
||||
+};
|
||||
+
|
||||
+static inline struct ipx_sock *ipx_sk(struct sock *sk)
|
||||
+{
|
||||
+ return (struct ipx_sock *)sk;
|
||||
+}
|
||||
+
|
||||
+#define IPX_SKB_CB(__skb) ((struct ipx_cb *)&((__skb)->cb[0]))
|
||||
+
|
||||
+#define IPX_MIN_EPHEMERAL_SOCKET 0x4000
|
||||
+#define IPX_MAX_EPHEMERAL_SOCKET 0x7fff
|
||||
+
|
||||
+extern struct list_head ipx_routes;
|
||||
+extern rwlock_t ipx_routes_lock;
|
||||
+
|
||||
+extern struct list_head ipx_interfaces;
|
||||
+struct ipx_interface *ipx_interfaces_head(void);
|
||||
+extern spinlock_t ipx_interfaces_lock;
|
||||
+
|
||||
+extern struct ipx_interface *ipx_primary_net;
|
||||
+
|
||||
+int ipx_proc_init(void);
|
||||
+void ipx_proc_exit(void);
|
||||
+
|
||||
+const char *ipx_frame_name(__be16);
|
||||
+const char *ipx_device_name(struct ipx_interface *intrfc);
|
||||
+
|
||||
+static __inline__ void ipxitf_hold(struct ipx_interface *intrfc)
|
||||
+{
|
||||
+ refcount_inc(&intrfc->refcnt);
|
||||
+}
|
||||
+
|
||||
+void ipxitf_down(struct ipx_interface *intrfc);
|
||||
+struct ipx_interface *ipxitf_find_using_net(__be32 net);
|
||||
+int ipxitf_send(struct ipx_interface *intrfc, struct sk_buff *skb, char *node);
|
||||
+__be16 ipx_cksum(struct ipxhdr *packet, int length);
|
||||
+int ipxrtr_add_route(__be32 network, struct ipx_interface *intrfc,
|
||||
+ unsigned char *node);
|
||||
+void ipxrtr_del_routes(struct ipx_interface *intrfc);
|
||||
+int ipxrtr_route_packet(struct sock *sk, struct sockaddr_ipx *usipx,
|
||||
+ struct msghdr *msg, size_t len, int noblock);
|
||||
+int ipxrtr_route_skb(struct sk_buff *skb);
|
||||
+struct ipx_route *ipxrtr_lookup(__be32 net);
|
||||
+int ipxrtr_ioctl(unsigned int cmd, void __user *arg);
|
||||
+
|
||||
+static __inline__ void ipxitf_put(struct ipx_interface *intrfc)
|
||||
+{
|
||||
+ if (refcount_dec_and_test(&intrfc->refcnt))
|
||||
+ ipxitf_down(intrfc);
|
||||
+}
|
||||
+
|
||||
+static __inline__ void ipxrtr_hold(struct ipx_route *rt)
|
||||
+{
|
||||
+ refcount_inc(&rt->refcnt);
|
||||
+}
|
||||
+
|
||||
+static __inline__ void ipxrtr_put(struct ipx_route *rt)
|
||||
+{
|
||||
+ if (refcount_dec_and_test(&rt->refcnt))
|
||||
+ kfree(rt);
|
||||
+}
|
||||
+#endif /* _NET_INET_IPX_H_ */
|
||||
diff --git a/include/uapi/linux/ipx.h b/include/uapi/linux/ipx.h
|
||||
new file mode 100644
|
||||
index 000000000000..3168137adae8
|
||||
--- /dev/null
|
||||
+++ b/include/uapi/linux/ipx.h
|
||||
@@ -0,0 +1,87 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
|
||||
+#ifndef _IPX_H_
|
||||
+#define _IPX_H_
|
||||
+#include <linux/libc-compat.h> /* for compatibility with glibc netipx/ipx.h */
|
||||
+#include <linux/types.h>
|
||||
+#include <linux/sockios.h>
|
||||
+#include <linux/socket.h>
|
||||
+#define IPX_NODE_LEN 6
|
||||
+#define IPX_MTU 576
|
||||
+
|
||||
+#if __UAPI_DEF_SOCKADDR_IPX
|
||||
+struct sockaddr_ipx {
|
||||
+ __kernel_sa_family_t sipx_family;
|
||||
+ __be16 sipx_port;
|
||||
+ __be32 sipx_network;
|
||||
+ unsigned char sipx_node[IPX_NODE_LEN];
|
||||
+ __u8 sipx_type;
|
||||
+ unsigned char sipx_zero; /* 16 byte fill */
|
||||
+};
|
||||
+#endif /* __UAPI_DEF_SOCKADDR_IPX */
|
||||
+
|
||||
+/*
|
||||
+ * So we can fit the extra info for SIOCSIFADDR into the address nicely
|
||||
+ */
|
||||
+#define sipx_special sipx_port
|
||||
+#define sipx_action sipx_zero
|
||||
+#define IPX_DLTITF 0
|
||||
+#define IPX_CRTITF 1
|
||||
+
|
||||
+#if __UAPI_DEF_IPX_ROUTE_DEFINITION
|
||||
+struct ipx_route_definition {
|
||||
+ __be32 ipx_network;
|
||||
+ __be32 ipx_router_network;
|
||||
+ unsigned char ipx_router_node[IPX_NODE_LEN];
|
||||
+};
|
||||
+#endif /* __UAPI_DEF_IPX_ROUTE_DEFINITION */
|
||||
+
|
||||
+#if __UAPI_DEF_IPX_INTERFACE_DEFINITION
|
||||
+struct ipx_interface_definition {
|
||||
+ __be32 ipx_network;
|
||||
+ unsigned char ipx_device[16];
|
||||
+ unsigned char ipx_dlink_type;
|
||||
+#define IPX_FRAME_NONE 0
|
||||
+#define IPX_FRAME_SNAP 1
|
||||
+#define IPX_FRAME_8022 2
|
||||
+#define IPX_FRAME_ETHERII 3
|
||||
+#define IPX_FRAME_8023 4
|
||||
+#define IPX_FRAME_TR_8022 5 /* obsolete */
|
||||
+ unsigned char ipx_special;
|
||||
+#define IPX_SPECIAL_NONE 0
|
||||
+#define IPX_PRIMARY 1
|
||||
+#define IPX_INTERNAL 2
|
||||
+ unsigned char ipx_node[IPX_NODE_LEN];
|
||||
+};
|
||||
+#endif /* __UAPI_DEF_IPX_INTERFACE_DEFINITION */
|
||||
+
|
||||
+#if __UAPI_DEF_IPX_CONFIG_DATA
|
||||
+struct ipx_config_data {
|
||||
+ unsigned char ipxcfg_auto_select_primary;
|
||||
+ unsigned char ipxcfg_auto_create_interfaces;
|
||||
+};
|
||||
+#endif /* __UAPI_DEF_IPX_CONFIG_DATA */
|
||||
+
|
||||
+/*
|
||||
+ * OLD Route Definition for backward compatibility.
|
||||
+ */
|
||||
+
|
||||
+#if __UAPI_DEF_IPX_ROUTE_DEF
|
||||
+struct ipx_route_def {
|
||||
+ __be32 ipx_network;
|
||||
+ __be32 ipx_router_network;
|
||||
+#define IPX_ROUTE_NO_ROUTER 0
|
||||
+ unsigned char ipx_router_node[IPX_NODE_LEN];
|
||||
+ unsigned char ipx_device[16];
|
||||
+ unsigned short ipx_flags;
|
||||
+#define IPX_RT_SNAP 8
|
||||
+#define IPX_RT_8022 4
|
||||
+#define IPX_RT_BLUEBOOK 2
|
||||
+#define IPX_RT_ROUTED 1
|
||||
+};
|
||||
+#endif /* __UAPI_DEF_IPX_ROUTE_DEF */
|
||||
+
|
||||
+#define SIOCAIPXITFCRT (SIOCPROTOPRIVATE)
|
||||
+#define SIOCAIPXPRISLT (SIOCPROTOPRIVATE + 1)
|
||||
+#define SIOCIPXCFGDATA (SIOCPROTOPRIVATE + 2)
|
||||
+#define SIOCIPXNCPCONN (SIOCPROTOPRIVATE + 3)
|
||||
+#endif /* _IPX_H_ */
|
||||
--
|
||||
2.25.1
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,406 @@
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Sat, 10 Oct 2020 15:32:18 +0000
|
||||
Subject: [PATCH] phy/rockchip: inno-hdmi: use correct vco_div_5 macro on
|
||||
rk3328
|
||||
|
||||
inno_hdmi_phy_rk3328_clk_set_rate() is using the RK3228 macro
|
||||
when configuring vco_div_5 on RK3328.
|
||||
|
||||
Fix this by using correct vco_div_5 macro for RK3328.
|
||||
|
||||
Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy")
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
index 80acca4e9e14..15339338aae3 100644
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
@@ -790,8 +790,8 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw,
|
||||
RK3328_PRE_PLL_POWER_DOWN);
|
||||
|
||||
/* Configure pre-pll */
|
||||
- inno_update_bits(inno, 0xa0, RK3228_PCLK_VCO_DIV_5_MASK,
|
||||
- RK3228_PCLK_VCO_DIV_5(cfg->vco_div_5_en));
|
||||
+ inno_update_bits(inno, 0xa0, RK3328_PCLK_VCO_DIV_5_MASK,
|
||||
+ RK3328_PCLK_VCO_DIV_5(cfg->vco_div_5_en));
|
||||
inno_write(inno, 0xa1, RK3328_PRE_PLL_PRE_DIV(cfg->prediv));
|
||||
|
||||
val = RK3328_SPREAD_SPECTRUM_MOD_DISABLE;
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Zheng Yang <zhengyang@rock-chips.com>
|
||||
Date: Sat, 10 Oct 2020 15:32:18 +0000
|
||||
Subject: [PATCH] phy/rockchip: inno-hdmi: round fractal pixclock in rk3328
|
||||
recalc_rate
|
||||
|
||||
inno_hdmi_phy_rk3328_clk_recalc_rate() is returning a rate not found
|
||||
in the pre pll config table when the fractal divider is used.
|
||||
This can prevent proper power_on because a tmdsclock for the new rate
|
||||
is not found in the pre pll config table.
|
||||
|
||||
Fix this by saving and returning a rounded pixel rate that exist
|
||||
in the pre pll config table.
|
||||
|
||||
Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy")
|
||||
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 8 +++++---
|
||||
1 file changed, 5 insertions(+), 3 deletions(-)
|
||||
|
||||
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
index 15339338aae3..15a008a1ac7b 100644
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
@@ -745,10 +745,12 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw,
|
||||
do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2));
|
||||
}
|
||||
|
||||
- inno->pixclock = vco;
|
||||
- dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);
|
||||
+ inno->pixclock = DIV_ROUND_CLOSEST((unsigned long)vco, 1000) * 1000;
|
||||
|
||||
- return vco;
|
||||
+ dev_dbg(inno->dev, "%s rate %lu vco %llu\n",
|
||||
+ __func__, inno->pixclock, vco);
|
||||
+
|
||||
+ return inno->pixclock;
|
||||
}
|
||||
|
||||
static long inno_hdmi_phy_rk3328_clk_round_rate(struct clk_hw *hw,
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Sat, 10 Oct 2020 15:32:19 +0000
|
||||
Subject: [PATCH] phy/rockchip: inno-hdmi: remove unused no_c from rk3328
|
||||
recalc_rate
|
||||
|
||||
no_c is not used in any calculation, lets remove it.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 5 +----
|
||||
1 file changed, 1 insertion(+), 4 deletions(-)
|
||||
|
||||
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
index 15a008a1ac7b..4b936ca19920 100644
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
@@ -714,7 +714,7 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw,
|
||||
{
|
||||
struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
|
||||
unsigned long frac;
|
||||
- u8 nd, no_a, no_b, no_c, no_d;
|
||||
+ u8 nd, no_a, no_b, no_d;
|
||||
u64 vco;
|
||||
u16 nf;
|
||||
|
||||
@@ -737,9 +737,6 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw,
|
||||
no_b = inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_B_MASK;
|
||||
no_b >>= RK3328_PRE_PLL_PCLK_DIV_B_SHIFT;
|
||||
no_b += 2;
|
||||
- no_c = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_C_MASK;
|
||||
- no_c >>= RK3328_PRE_PLL_PCLK_DIV_C_SHIFT;
|
||||
- no_c = 1 << no_c;
|
||||
no_d = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_D_MASK;
|
||||
|
||||
do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2));
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Sat, 10 Oct 2020 15:32:19 +0000
|
||||
Subject: [PATCH] phy/rockchip: inno-hdmi: do not power on rk3328 post pll on
|
||||
reg write
|
||||
|
||||
inno_write is used to configure 0xaa reg, that also hold the
|
||||
POST_PLL_POWER_DOWN bit.
|
||||
When POST_PLL_REFCLK_SEL_TMDS is configured the power down bit is not
|
||||
taken into consideration.
|
||||
|
||||
Fix this by keeping the power down bit until configuration is complete.
|
||||
Also reorder the reg write order for consistency.
|
||||
|
||||
Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy")
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 6 ++++--
|
||||
1 file changed, 4 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
index 4b936ca19920..620961fcfc1d 100644
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
@@ -1020,9 +1020,10 @@ inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno,
|
||||
|
||||
inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv));
|
||||
if (cfg->postdiv == 1) {
|
||||
- inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS);
|
||||
inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) |
|
||||
RK3328_POST_PLL_PRE_DIV(cfg->prediv));
|
||||
+ inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS |
|
||||
+ RK3328_POST_PLL_POWER_DOWN);
|
||||
} else {
|
||||
v = (cfg->postdiv / 2) - 1;
|
||||
v &= RK3328_POST_PLL_POST_DIV_MASK;
|
||||
@@ -1030,7 +1031,8 @@ inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno,
|
||||
inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) |
|
||||
RK3328_POST_PLL_PRE_DIV(cfg->prediv));
|
||||
inno_write(inno, 0xaa, RK3328_POST_PLL_POST_DIV_ENABLE |
|
||||
- RK3328_POST_PLL_REFCLK_SEL_TMDS);
|
||||
+ RK3328_POST_PLL_REFCLK_SEL_TMDS |
|
||||
+ RK3328_POST_PLL_POWER_DOWN);
|
||||
}
|
||||
|
||||
for (v = 0; v < 14; v++)
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Huicong Xu <xhc@rock-chips.com>
|
||||
Date: Sat, 10 Oct 2020 15:32:20 +0000
|
||||
Subject: [PATCH] phy/rockchip: inno-hdmi: force set_rate on power_on
|
||||
|
||||
Regular 8-bit and Deep Color video formats mainly differ in TMDS rate and
|
||||
not in pixel clock rate.
|
||||
When the hdmiphy clock is configured with the same pixel clock rate using
|
||||
clk_set_rate() the clock framework do not signal the hdmi phy driver
|
||||
to set_rate when switching between 8-bit and Deep Color.
|
||||
This result in pre/post pll not being re-configured when switching between
|
||||
regular 8-bit and Deep Color video formats.
|
||||
|
||||
Fix this by calling set_rate in power_on to force pre pll re-configuration.
|
||||
|
||||
Signed-off-by: Huicong Xu <xhc@rock-chips.com>
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 13 +++++++++++++
|
||||
1 file changed, 13 insertions(+)
|
||||
|
||||
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
index 620961fcfc1d..2f01259823ea 100644
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
|
||||
@@ -245,6 +245,7 @@ struct inno_hdmi_phy {
|
||||
struct clk_hw hw;
|
||||
struct clk *phyclk;
|
||||
unsigned long pixclock;
|
||||
+ unsigned long tmdsclock;
|
||||
};
|
||||
|
||||
struct pre_pll_config {
|
||||
@@ -485,6 +486,8 @@ static int inno_hdmi_phy_power_on(struct phy *phy)
|
||||
|
||||
dev_dbg(inno->dev, "Inno HDMI PHY Power On\n");
|
||||
|
||||
+ inno->plat_data->clk_ops->set_rate(&inno->hw, inno->pixclock, 24000000);
|
||||
+
|
||||
ret = clk_prepare_enable(inno->phyclk);
|
||||
if (ret)
|
||||
return ret;
|
||||
@@ -509,6 +512,8 @@ static int inno_hdmi_phy_power_off(struct phy *phy)
|
||||
|
||||
clk_disable_unprepare(inno->phyclk);
|
||||
|
||||
+ inno->tmdsclock = 0;
|
||||
+
|
||||
dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n");
|
||||
|
||||
return 0;
|
||||
@@ -628,6 +633,9 @@ static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw,
|
||||
dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",
|
||||
__func__, rate, tmdsclock);
|
||||
|
||||
+ if (inno->pixclock == rate && inno->tmdsclock == tmdsclock)
|
||||
+ return 0;
|
||||
+
|
||||
cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate);
|
||||
if (IS_ERR(cfg))
|
||||
return PTR_ERR(cfg);
|
||||
@@ -670,6 +678,7 @@ static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw,
|
||||
}
|
||||
|
||||
inno->pixclock = rate;
|
||||
+ inno->tmdsclock = tmdsclock;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -781,6 +790,9 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw,
|
||||
dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",
|
||||
__func__, rate, tmdsclock);
|
||||
|
||||
+ if (inno->pixclock == rate && inno->tmdsclock == tmdsclock)
|
||||
+ return 0;
|
||||
+
|
||||
cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate);
|
||||
if (IS_ERR(cfg))
|
||||
return PTR_ERR(cfg);
|
||||
@@ -820,6 +832,7 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw,
|
||||
}
|
||||
|
||||
inno->pixclock = rate;
|
||||
+ inno->tmdsclock = tmdsclock;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Sun, 17 Feb 2019 22:14:38 +0000
|
||||
Subject: [PATCH] mmc: core: set initial signal voltage on power off
|
||||
|
||||
Some boards have SD card connectors where the power rail cannot be switched
|
||||
off by the driver. If the card has not been power cycled, it may still be
|
||||
using 1.8V signaling after a warm re-boot. Bootroms expecting 3.3V signaling
|
||||
will fail to boot from a UHS card that continue to use 1.8V signaling.
|
||||
|
||||
Set initial signal voltage in mmc_power_off() to allow re-boot to function.
|
||||
|
||||
This fixes re-boot with UHS cards on Asus Tinker Board (Rockchip RK3288),
|
||||
same issue have been seen on some Rockchip RK3399 boards.
|
||||
|
||||
I am sending this as a RFC because I have no insights into SD/MMC subsystem,
|
||||
this change fix a re-boot issue on my boards and does not break emmc/sdio.
|
||||
Is this an acceptable workaround? Any advice is appreciated.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/mmc/core/core.c | 8 ++++++++
|
||||
1 file changed, 8 insertions(+)
|
||||
|
||||
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
|
||||
index 95fedcf56e4a..38e75b275bb6 100644
|
||||
--- a/drivers/mmc/core/core.c
|
||||
+++ b/drivers/mmc/core/core.c
|
||||
@@ -1355,6 +1355,14 @@ void mmc_power_off(struct mmc_host *host)
|
||||
if (host->ios.power_mode == MMC_POWER_OFF)
|
||||
return;
|
||||
|
||||
+ mmc_set_initial_signal_voltage(host);
|
||||
+
|
||||
+ /*
|
||||
+ * This delay should be sufficient to allow the power supply
|
||||
+ * to reach the minimum voltage.
|
||||
+ */
|
||||
+ mmc_delay(host->ios.power_delay_ms);
|
||||
+
|
||||
mmc_pwrseq_power_off(host);
|
||||
|
||||
host->ios.clock = 0;
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Wed, 23 Jun 2021 16:59:18 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add sdmmc_ext for RK3328
|
||||
|
||||
RK3328 SoC has a fourth mmc controller called SDMMC_EXT. Some
|
||||
boards have sdio wifi connected to it. In order to use it
|
||||
one would have to add the pinctrls from sdmmc0ext group which
|
||||
is done on board level.
|
||||
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 14 ++++++++++++++
|
||||
1 file changed, 14 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
index 5b2020590f53..df46edbec82c 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
@@ -975,6 +975,20 @@ usb_host0_ohci: usb@ff5d0000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ sdmmc_ext: mmc@ff5f0000 {
|
||||
+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
+ reg = <0x0 0xff5f0000 0x0 0x4000>;
|
||||
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>,
|
||||
+ <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>;
|
||||
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
+ fifo-depth = <0x100>;
|
||||
+ max-frequency = <150000000>;
|
||||
+ resets = <&cru SRST_SDMMCEXT>;
|
||||
+ reset-names = "reset";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
usbdrd3: usb@ff600000 {
|
||||
compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
|
||||
reg = <0x0 0xff600000 0x0 0x100000>;
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Wed, 23 Jun 2021 17:02:08 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add sdmmc/sdio/emmc reset controls for
|
||||
RK3328
|
||||
|
||||
The DW MCI controller driver will use them to reset the IP block before
|
||||
initialisation.
|
||||
|
||||
Fixes: d717f7352ec6 ("arm64: dts: rockchip: add sdmmc/sdio/emmc nodes for RK3328 SoCs")
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 ++++++
|
||||
1 file changed, 6 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
index df46edbec82c..cfc57be009a6 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
@@ -853,6 +853,8 @@ sdmmc: mmc@ff500000 {
|
||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
fifo-depth = <0x100>;
|
||||
max-frequency = <150000000>;
|
||||
+ resets = <&cru SRST_MMC0>;
|
||||
+ reset-names = "reset";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -865,6 +867,8 @@ sdio: mmc@ff510000 {
|
||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
fifo-depth = <0x100>;
|
||||
max-frequency = <150000000>;
|
||||
+ resets = <&cru SRST_SDIO>;
|
||||
+ reset-names = "reset";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -877,6 +881,8 @@ emmc: mmc@ff520000 {
|
||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
fifo-depth = <0x100>;
|
||||
max-frequency = <150000000>;
|
||||
+ resets = <&cru SRST_EMMC>;
|
||||
+ reset-names = "reset";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Sat, 21 Aug 2021 19:13:31 +0200
|
||||
Subject: [PATCH] Commit a728c10dd62a ("arm64: dts: rockchip: remove
|
||||
interrupt-names from iommu nodes") intended to remove the interrupt-names
|
||||
property for the mmu nodes. It also removed them for the vpu node in
|
||||
rk3399.dtsi which currently results in a non-working driver. Fix this by
|
||||
re-adding them.
|
||||
|
||||
Fixes: a728c10dd62a ("arm64: dts: rockchip: remove interrupt-names from iommu nodes")
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
index 9db9484ca38f..44def886b391 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
@@ -1240,6 +1240,7 @@ vpu: video-codec@ff650000 {
|
||||
reg = <0x0 0xff650000 0x0 0x800>;
|
||||
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
+ interrupt-names = "vepu", "vdpu";
|
||||
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
|
||||
clock-names = "aclk", "hclk";
|
||||
iommus = <&vpu_mmu>;
|
||||
@ -0,0 +1,735 @@
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Mon, 6 Jul 2020 21:54:33 +0000
|
||||
Subject: [PATCH] media: rkvdec: h264: Fix reference frame_num wrap for second
|
||||
field
|
||||
|
||||
When decoding the second field in a complementary field pair the second
|
||||
field is sharing the same frame_num with the first field.
|
||||
|
||||
Currently the frame_num for the first field is wrapped when it matches the
|
||||
field being decoded, this cause issues to decode the second field in a
|
||||
complementary field pair.
|
||||
|
||||
Fix this by using inclusive comparison, less than or equal.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
|
||||
---
|
||||
drivers/staging/media/rkvdec/rkvdec-h264.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
index 76e97cbe2512..af44a16c0c4a 100644
|
||||
--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
@@ -752,7 +752,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx,
|
||||
continue;
|
||||
|
||||
if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM ||
|
||||
- dpb[i].frame_num < dec_params->frame_num) {
|
||||
+ dpb[i].frame_num <= dec_params->frame_num) {
|
||||
p[i] = dpb[i].frame_num;
|
||||
continue;
|
||||
}
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Mon, 6 Jul 2020 21:54:34 +0000
|
||||
Subject: [PATCH] media: rkvdec: Ensure decoded resolution fit coded resolution
|
||||
|
||||
Ensure decoded CAPTURE buffer resolution is larger or equal to the coded
|
||||
OPTUPT buffer resolution.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/staging/media/rkvdec/rkvdec.c | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
|
||||
index 7131156c1f2c..65a8334a188b 100644
|
||||
--- a/drivers/staging/media/rkvdec/rkvdec.c
|
||||
+++ b/drivers/staging/media/rkvdec/rkvdec.c
|
||||
@@ -233,6 +233,8 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv,
|
||||
pix_mp->pixelformat = coded_desc->decoded_fmts[0];
|
||||
|
||||
/* Always apply the frmsize constraint of the coded end. */
|
||||
+ pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width);
|
||||
+ pix_mp->height = max(pix_mp->height, ctx->coded_fmt.fmt.pix_mp.height);
|
||||
v4l2_apply_frmsize_constraints(&pix_mp->width,
|
||||
&pix_mp->height,
|
||||
&coded_desc->frmsize);
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Mon, 6 Jul 2020 21:54:34 +0000
|
||||
Subject: [PATCH] media: rkvdec: h264: Validate and use pic width and height in
|
||||
mbs
|
||||
|
||||
The width and height in mbs is currently configured based on OUTPUT buffer
|
||||
resolution, this works for frame pictures but can cause issues for field
|
||||
pictures.
|
||||
|
||||
When frame_mbs_only_flag is 0 the height in mbs should be height of
|
||||
the field instead of height of frame.
|
||||
|
||||
Validate pic_width_in_mbs_minus1 and pic_height_in_map_units_minus1
|
||||
against OUTPUT buffer resolution and use these values to configure HW.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/staging/media/rkvdec/rkvdec-h264.c | 4 ++--
|
||||
drivers/staging/media/rkvdec/rkvdec.c | 10 ++++++++++
|
||||
2 files changed, 12 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
index af44a16c0c4a..9852c3519f56 100644
|
||||
--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
@@ -671,8 +671,8 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx,
|
||||
LOG2_MAX_PIC_ORDER_CNT_LSB_MINUS4);
|
||||
WRITE_PPS(!!(sps->flags & V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO),
|
||||
DELTA_PIC_ORDER_ALWAYS_ZERO_FLAG);
|
||||
- WRITE_PPS(DIV_ROUND_UP(ctx->coded_fmt.fmt.pix_mp.width, 16), PIC_WIDTH_IN_MBS);
|
||||
- WRITE_PPS(DIV_ROUND_UP(ctx->coded_fmt.fmt.pix_mp.height, 16), PIC_HEIGHT_IN_MBS);
|
||||
+ WRITE_PPS(sps->pic_width_in_mbs_minus1 + 1, PIC_WIDTH_IN_MBS);
|
||||
+ WRITE_PPS(sps->pic_height_in_map_units_minus1 + 1, PIC_HEIGHT_IN_MBS);
|
||||
WRITE_PPS(!!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY),
|
||||
FRAME_MBS_ONLY_FLAG);
|
||||
WRITE_PPS(!!(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD),
|
||||
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
|
||||
index 65a8334a188b..f4c5ee4a1e26 100644
|
||||
--- a/drivers/staging/media/rkvdec/rkvdec.c
|
||||
+++ b/drivers/staging/media/rkvdec/rkvdec.c
|
||||
@@ -29,8 +29,11 @@
|
||||
|
||||
static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
|
||||
{
|
||||
+ struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
|
||||
+
|
||||
if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) {
|
||||
const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps;
|
||||
+ unsigned int width, height;
|
||||
/*
|
||||
* TODO: The hardware supports 10-bit and 4:2:2 profiles,
|
||||
* but it's currently broken in the driver.
|
||||
@@ -45,6 +48,13 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
|
||||
if (sps->bit_depth_luma_minus8 != 0)
|
||||
/* Only 8-bit is supported */
|
||||
return -EINVAL;
|
||||
+
|
||||
+ width = (sps->pic_width_in_mbs_minus1 + 1) * 16;
|
||||
+ height = (sps->pic_height_in_map_units_minus1 + 1) * 16;
|
||||
+
|
||||
+ if (width > ctx->coded_fmt.fmt.pix_mp.width ||
|
||||
+ height > ctx->coded_fmt.fmt.pix_mp.height)
|
||||
+ return -EINVAL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Mon, 6 Jul 2020 21:54:35 +0000
|
||||
Subject: [PATCH] media: rkvdec: h264: Fix bit depth wrap in pps packet
|
||||
|
||||
The luma and chroma bit depth fields in the pps packet is 3 bits wide.
|
||||
8 is wrongly added to the bit depth value written to these 3-bit fields.
|
||||
Because only the 3 LSB is written the hardware is configured correctly.
|
||||
|
||||
Correct this by not adding 8 to the luma and chroma bit depth value.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com>
|
||||
---
|
||||
drivers/staging/media/rkvdec/rkvdec-h264.c | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
index 9852c3519f56..f3ff3e709169 100644
|
||||
--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
@@ -661,8 +661,8 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx,
|
||||
WRITE_PPS(0xff, PROFILE_IDC);
|
||||
WRITE_PPS(1, CONSTRAINT_SET3_FLAG);
|
||||
WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC);
|
||||
- WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA);
|
||||
- WRITE_PPS(sps->bit_depth_chroma_minus8 + 8, BIT_DEPTH_CHROMA);
|
||||
+ WRITE_PPS(sps->bit_depth_luma_minus8, BIT_DEPTH_LUMA);
|
||||
+ WRITE_PPS(sps->bit_depth_chroma_minus8, BIT_DEPTH_CHROMA);
|
||||
WRITE_PPS(0, QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG);
|
||||
WRITE_PPS(sps->log2_max_frame_num_minus4, LOG2_MAX_FRAME_NUM_MINUS4);
|
||||
WRITE_PPS(sps->max_num_ref_frames, MAX_NUM_REF_FRAMES);
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Mon, 6 Jul 2020 21:54:35 +0000
|
||||
Subject: [PATCH] media: v4l2-common: Add helpers to calculate bytesperline and
|
||||
sizeimage
|
||||
|
||||
Add helper functions to calculate plane bytesperline and sizeimage, these
|
||||
new helpers consider block width and height when calculating plane
|
||||
bytesperline and sizeimage.
|
||||
|
||||
This prepare support for new pixel formats added in next patch that make
|
||||
use of block width and height.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/media/v4l2-core/v4l2-common.c | 77 +++++++++++++--------------
|
||||
1 file changed, 38 insertions(+), 39 deletions(-)
|
||||
|
||||
diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c
|
||||
index 04af03285a20..ae585828c388 100644
|
||||
--- a/drivers/media/v4l2-core/v4l2-common.c
|
||||
+++ b/drivers/media/v4l2-core/v4l2-common.c
|
||||
@@ -333,6 +333,33 @@ static inline unsigned int v4l2_format_block_height(const struct v4l2_format_inf
|
||||
return info->block_h[plane];
|
||||
}
|
||||
|
||||
+static inline unsigned int v4l2_format_plane_width(const struct v4l2_format_info *info, int plane,
|
||||
+ unsigned int width)
|
||||
+{
|
||||
+ unsigned int hdiv = plane ? info->hdiv : 1;
|
||||
+ unsigned int bytes = DIV_ROUND_UP(width * info->bpp[plane],
|
||||
+ v4l2_format_block_width(info, plane) *
|
||||
+ v4l2_format_block_height(info, plane));
|
||||
+
|
||||
+ return DIV_ROUND_UP(bytes, hdiv);
|
||||
+}
|
||||
+
|
||||
+static inline unsigned int v4l2_format_plane_height(const struct v4l2_format_info *info, int plane,
|
||||
+ unsigned int height)
|
||||
+{
|
||||
+ unsigned int vdiv = plane ? info->vdiv : 1;
|
||||
+ unsigned int lines = ALIGN(height, v4l2_format_block_height(info, plane));
|
||||
+
|
||||
+ return DIV_ROUND_UP(lines, vdiv);
|
||||
+}
|
||||
+
|
||||
+static inline unsigned int v4l2_format_plane_size(const struct v4l2_format_info *info, int plane,
|
||||
+ unsigned int width, unsigned int height)
|
||||
+{
|
||||
+ return v4l2_format_plane_width(info, plane, width) *
|
||||
+ v4l2_format_plane_height(info, plane, height);
|
||||
+}
|
||||
+
|
||||
void v4l2_apply_frmsize_constraints(u32 *width, u32 *height,
|
||||
const struct v4l2_frmsize_stepwise *frmsize)
|
||||
{
|
||||
@@ -368,37 +395,19 @@ int v4l2_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt,
|
||||
|
||||
if (info->mem_planes == 1) {
|
||||
plane = &pixfmt->plane_fmt[0];
|
||||
- plane->bytesperline = ALIGN(width, v4l2_format_block_width(info, 0)) * info->bpp[0];
|
||||
+ plane->bytesperline = v4l2_format_plane_width(info, 0, width);
|
||||
plane->sizeimage = 0;
|
||||
|
||||
- for (i = 0; i < info->comp_planes; i++) {
|
||||
- unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
|
||||
- unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
|
||||
- unsigned int aligned_width;
|
||||
- unsigned int aligned_height;
|
||||
-
|
||||
- aligned_width = ALIGN(width, v4l2_format_block_width(info, i));
|
||||
- aligned_height = ALIGN(height, v4l2_format_block_height(info, i));
|
||||
-
|
||||
- plane->sizeimage += info->bpp[i] *
|
||||
- DIV_ROUND_UP(aligned_width, hdiv) *
|
||||
- DIV_ROUND_UP(aligned_height, vdiv);
|
||||
- }
|
||||
+ for (i = 0; i < info->comp_planes; i++)
|
||||
+ plane->sizeimage +=
|
||||
+ v4l2_format_plane_size(info, i, width, height);
|
||||
} else {
|
||||
for (i = 0; i < info->comp_planes; i++) {
|
||||
- unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
|
||||
- unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
|
||||
- unsigned int aligned_width;
|
||||
- unsigned int aligned_height;
|
||||
-
|
||||
- aligned_width = ALIGN(width, v4l2_format_block_width(info, i));
|
||||
- aligned_height = ALIGN(height, v4l2_format_block_height(info, i));
|
||||
-
|
||||
plane = &pixfmt->plane_fmt[i];
|
||||
plane->bytesperline =
|
||||
- info->bpp[i] * DIV_ROUND_UP(aligned_width, hdiv);
|
||||
- plane->sizeimage =
|
||||
- plane->bytesperline * DIV_ROUND_UP(aligned_height, vdiv);
|
||||
+ v4l2_format_plane_width(info, i, width);
|
||||
+ plane->sizeimage = plane->bytesperline *
|
||||
+ v4l2_format_plane_height(info, i, height);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
@@ -422,22 +431,12 @@ int v4l2_fill_pixfmt(struct v4l2_pix_format *pixfmt, u32 pixelformat,
|
||||
pixfmt->width = width;
|
||||
pixfmt->height = height;
|
||||
pixfmt->pixelformat = pixelformat;
|
||||
- pixfmt->bytesperline = ALIGN(width, v4l2_format_block_width(info, 0)) * info->bpp[0];
|
||||
+ pixfmt->bytesperline = v4l2_format_plane_width(info, 0, width);
|
||||
pixfmt->sizeimage = 0;
|
||||
|
||||
- for (i = 0; i < info->comp_planes; i++) {
|
||||
- unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
|
||||
- unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
|
||||
- unsigned int aligned_width;
|
||||
- unsigned int aligned_height;
|
||||
-
|
||||
- aligned_width = ALIGN(width, v4l2_format_block_width(info, i));
|
||||
- aligned_height = ALIGN(height, v4l2_format_block_height(info, i));
|
||||
-
|
||||
- pixfmt->sizeimage += info->bpp[i] *
|
||||
- DIV_ROUND_UP(aligned_width, hdiv) *
|
||||
- DIV_ROUND_UP(aligned_height, vdiv);
|
||||
- }
|
||||
+ for (i = 0; i < info->comp_planes; i++)
|
||||
+ pixfmt->sizeimage +=
|
||||
+ v4l2_format_plane_size(info, i, width, height);
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(v4l2_fill_pixfmt);
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Mon, 6 Jul 2020 21:54:36 +0000
|
||||
Subject: [PATCH] media: v4l2: Add NV15 and NV20 pixel formats
|
||||
|
||||
Add NV15 and NV20 pixel formats used by the Rockchip Video Decoder for
|
||||
10-bit buffers.
|
||||
|
||||
NV15 and NV20 is a packed 10-bit 4:2:0/4:2:2 semi-planar Y/CbCr format
|
||||
similar to P010 and P210 but has no padding between components. Instead,
|
||||
luminance and chrominance samples are grouped into 4s so that each group is
|
||||
packed into an integer number of bytes:
|
||||
|
||||
YYYY = UVUV = 4 * 10 bits = 40 bits = 5 bytes
|
||||
|
||||
The '15' and '20' suffix refers to the optimum effective bits per pixel
|
||||
which is achieved when the total number of luminance samples is a multiple
|
||||
of 8 for NV15 and 4 for NV20.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/media/v4l2-core/v4l2-common.c | 3 +++
|
||||
drivers/media/v4l2-core/v4l2-ioctl.c | 2 ++
|
||||
include/uapi/linux/videodev2.h | 3 +++
|
||||
3 files changed, 8 insertions(+)
|
||||
|
||||
diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c
|
||||
index ae585828c388..5bafbdbe30b0 100644
|
||||
--- a/drivers/media/v4l2-core/v4l2-common.c
|
||||
+++ b/drivers/media/v4l2-core/v4l2-common.c
|
||||
@@ -267,6 +267,9 @@ const struct v4l2_format_info *v4l2_format_info(u32 format)
|
||||
{ .format = V4L2_PIX_FMT_NV24, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 1, .vdiv = 1 },
|
||||
{ .format = V4L2_PIX_FMT_NV42, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 1, .vdiv = 1 },
|
||||
|
||||
+ { .format = V4L2_PIX_FMT_NV15, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .hdiv = 2, .vdiv = 2, .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } },
|
||||
+ { .format = V4L2_PIX_FMT_NV20, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .hdiv = 2, .vdiv = 1, .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } },
|
||||
+
|
||||
{ .format = V4L2_PIX_FMT_YUV410, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 4 },
|
||||
{ .format = V4L2_PIX_FMT_YVU410, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 4 },
|
||||
{ .format = V4L2_PIX_FMT_YUV411P, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 1 },
|
||||
diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c
|
||||
index 9ac557b8e..0573d9a6a 100644
|
||||
--- a/drivers/media/v4l2-core/v4l2-ioctl.c
|
||||
+++ b/drivers/media/v4l2-core/v4l2-ioctl.c
|
||||
@@ -1299,6 +1299,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
|
||||
case V4L2_PIX_FMT_NV61: descr = "Y/CrCb 4:2:2"; break;
|
||||
case V4L2_PIX_FMT_NV24: descr = "Y/CbCr 4:4:4"; break;
|
||||
case V4L2_PIX_FMT_NV42: descr = "Y/CrCb 4:4:4"; break;
|
||||
+ case V4L2_PIX_FMT_NV15: descr = "10-bit Y/CbCr 4:2:0 (Packed)"; break;
|
||||
+ case V4L2_PIX_FMT_NV20: descr = "10-bit Y/CbCr 4:2:2 (Packed)"; break;
|
||||
case V4L2_PIX_FMT_NV12_4L4: descr = "Y/CbCr 4:2:0 (4x4 Linear)"; break;
|
||||
case V4L2_PIX_FMT_NV12_16L16: descr = "Y/CbCr 4:2:0 (16x16 Linear)"; break;
|
||||
case V4L2_PIX_FMT_NV12_32L32: descr = "Y/CbCr 4:2:0 (32x32 Linear)"; break;
|
||||
diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
|
||||
index 9260791b8438..169f8ad6fade 100644
|
||||
--- a/include/uapi/linux/videodev2.h
|
||||
+++ b/include/uapi/linux/videodev2.h
|
||||
@@ -603,6 +603,9 @@ struct v4l2_pix_format {
|
||||
#define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/CrCb 4:4:4 */
|
||||
#define V4L2_PIX_FMT_HM12 v4l2_fourcc('H', 'M', '1', '2') /* 8 YUV 4:2:0 16x16 macroblocks */
|
||||
|
||||
+#define V4L2_PIX_FMT_NV15 v4l2_fourcc('N', 'V', '1', '5') /* 15 Y/CbCr 4:2:0 10-bit packed */
|
||||
+#define V4L2_PIX_FMT_NV20 v4l2_fourcc('N', 'V', '2', '0') /* 20 Y/CbCr 4:2:2 10-bit packed */
|
||||
+
|
||||
/* two non contiguous planes - one Y, one Cr + Cb interleaved */
|
||||
#define V4L2_PIX_FMT_NV12M v4l2_fourcc('N', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 */
|
||||
#define V4L2_PIX_FMT_NV21M v4l2_fourcc('N', 'M', '2', '1') /* 21 Y/CrCb 4:2:0 */
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Mon, 6 Jul 2020 21:54:36 +0000
|
||||
Subject: [PATCH] media: rkvdec: h264: Use bytesperline and buffer height to
|
||||
calculate stride
|
||||
|
||||
Use bytesperline and buffer height to calculate the strides configured.
|
||||
|
||||
This does not really change anything other than ensuring the bytesperline
|
||||
that is signaled to userspace matches what is configured in HW.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/staging/media/rkvdec/rkvdec-h264.c | 10 +++++-----
|
||||
1 file changed, 5 insertions(+), 5 deletions(-)
|
||||
|
||||
diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
index 503ae683d0fd..88f5f4bb320b 100644
|
||||
--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
@@ -893,9 +893,9 @@ static void config_registers(struct rkvdec_ctx *ctx,
|
||||
dma_addr_t rlc_addr;
|
||||
dma_addr_t refer_addr;
|
||||
u32 rlc_len;
|
||||
- u32 hor_virstride = 0;
|
||||
- u32 ver_virstride = 0;
|
||||
- u32 y_virstride = 0;
|
||||
+ u32 hor_virstride;
|
||||
+ u32 ver_virstride;
|
||||
+ u32 y_virstride;
|
||||
u32 yuv_virstride = 0;
|
||||
u32 offset;
|
||||
dma_addr_t dst_addr;
|
||||
@@ -906,8 +906,8 @@ static void config_registers(struct rkvdec_ctx *ctx,
|
||||
|
||||
f = &ctx->decoded_fmt;
|
||||
dst_fmt = &f->fmt.pix_mp;
|
||||
- hor_virstride = (sps->bit_depth_luma_minus8 + 8) * dst_fmt->width / 8;
|
||||
- ver_virstride = round_up(dst_fmt->height, 16);
|
||||
+ hor_virstride = dst_fmt->plane_fmt[0].bytesperline;
|
||||
+ ver_virstride = dst_fmt->height;
|
||||
y_virstride = hor_virstride * ver_virstride;
|
||||
|
||||
if (sps->chroma_format_idc == 0)
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Mon, 6 Jul 2020 21:54:37 +0000
|
||||
Subject: [PATCH] media: rkvdec: Extract rkvdec_fill_decoded_pixfmt helper
|
||||
method
|
||||
|
||||
This extract setting decoded pixfmt into a helper method, current code is
|
||||
replaced with a call to the new helper method.
|
||||
|
||||
The helper method is also called from a new function in next patch.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/staging/media/rkvdec/rkvdec.c | 29 ++++++++++++++-------------
|
||||
1 file changed, 15 insertions(+), 14 deletions(-)
|
||||
|
||||
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
|
||||
index f4c5ee4a1e26..d8d0eab9e25d 100644
|
||||
--- a/drivers/staging/media/rkvdec/rkvdec.c
|
||||
+++ b/drivers/staging/media/rkvdec/rkvdec.c
|
||||
@@ -27,6 +27,17 @@
|
||||
#include "rkvdec.h"
|
||||
#include "rkvdec-regs.h"
|
||||
|
||||
+static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx,
|
||||
+ struct v4l2_pix_format_mplane *pix_mp)
|
||||
+{
|
||||
+ v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat,
|
||||
+ pix_mp->width, pix_mp->height);
|
||||
+ pix_mp->plane_fmt[0].sizeimage += 128 *
|
||||
+ DIV_ROUND_UP(pix_mp->width, 16) *
|
||||
+ DIV_ROUND_UP(pix_mp->height, 16);
|
||||
+ pix_mp->field = V4L2_FIELD_NONE;
|
||||
+}
|
||||
+
|
||||
static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
|
||||
{
|
||||
struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
|
||||
@@ -177,13 +188,9 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx)
|
||||
|
||||
rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]);
|
||||
f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
|
||||
- v4l2_fill_pixfmt_mp(&f->fmt.pix_mp,
|
||||
- ctx->coded_fmt_desc->decoded_fmts[0],
|
||||
- ctx->coded_fmt.fmt.pix_mp.width,
|
||||
- ctx->coded_fmt.fmt.pix_mp.height);
|
||||
- f->fmt.pix_mp.plane_fmt[0].sizeimage += 128 *
|
||||
- DIV_ROUND_UP(f->fmt.pix_mp.width, 16) *
|
||||
- DIV_ROUND_UP(f->fmt.pix_mp.height, 16);
|
||||
+ f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width;
|
||||
+ f->fmt.pix_mp.height = ctx->coded_fmt.fmt.pix_mp.height;
|
||||
+ rkvdec_fill_decoded_pixfmt(ctx, &f->fmt.pix_mp);
|
||||
}
|
||||
|
||||
static int rkvdec_enum_framesizes(struct file *file, void *priv,
|
||||
@@ -249,13 +256,7 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv,
|
||||
&pix_mp->height,
|
||||
&coded_desc->frmsize);
|
||||
|
||||
- v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat,
|
||||
- pix_mp->width, pix_mp->height);
|
||||
- pix_mp->plane_fmt[0].sizeimage +=
|
||||
- 128 *
|
||||
- DIV_ROUND_UP(pix_mp->width, 16) *
|
||||
- DIV_ROUND_UP(pix_mp->height, 16);
|
||||
- pix_mp->field = V4L2_FIELD_NONE;
|
||||
+ rkvdec_fill_decoded_pixfmt(ctx, pix_mp);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Mon, 6 Jul 2020 21:54:37 +0000
|
||||
Subject: [PATCH] media: rkvdec: Lock capture pixel format in s_ctrl and s_fmt
|
||||
|
||||
Add an optional valid_fmt operation that should return the valid
|
||||
pixelformat of CAPTURE buffers.
|
||||
|
||||
This is used in next patch to ensure correct pixelformat is used for 10-bit
|
||||
and 4:2:2 content.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/staging/media/rkvdec/rkvdec.c | 59 ++++++++++++++++++++++++---
|
||||
drivers/staging/media/rkvdec/rkvdec.h | 2 +
|
||||
2 files changed, 55 insertions(+), 6 deletions(-)
|
||||
|
||||
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
|
||||
index d8d0eab9e25d..d31344c4acaa 100644
|
||||
--- a/drivers/staging/media/rkvdec/rkvdec.c
|
||||
+++ b/drivers/staging/media/rkvdec/rkvdec.c
|
||||
@@ -38,6 +38,16 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx,
|
||||
pix_mp->field = V4L2_FIELD_NONE;
|
||||
}
|
||||
|
||||
+static u32 rkvdec_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
|
||||
+{
|
||||
+ const struct rkvdec_coded_fmt_desc *coded_desc = ctx->coded_fmt_desc;
|
||||
+
|
||||
+ if (coded_desc->ops->valid_fmt)
|
||||
+ return coded_desc->ops->valid_fmt(ctx, ctrl);
|
||||
+
|
||||
+ return ctx->valid_fmt;
|
||||
+}
|
||||
+
|
||||
static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
|
||||
{
|
||||
struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
|
||||
@@ -60,6 +70,10 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
|
||||
/* Only 8-bit is supported */
|
||||
return -EINVAL;
|
||||
|
||||
+ if (ctx->valid_fmt && ctx->valid_fmt != rkvdec_valid_fmt(ctx, ctrl))
|
||||
+ /* Only current valid format */
|
||||
+ return -EINVAL;
|
||||
+
|
||||
width = (sps->pic_width_in_mbs_minus1 + 1) * 16;
|
||||
height = (sps->pic_height_in_map_units_minus1 + 1) * 16;
|
||||
|
||||
@@ -70,8 +84,27 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl)
|
||||
+{
|
||||
+ struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
|
||||
+
|
||||
+ if (ctrl->id == V4L2_CID_STATELESS_H264_SPS && !ctx->valid_fmt) {
|
||||
+ ctx->valid_fmt = rkvdec_valid_fmt(ctx, ctrl);
|
||||
+ if (ctx->valid_fmt) {
|
||||
+ struct v4l2_pix_format_mplane *pix_mp;
|
||||
+
|
||||
+ pix_mp = &ctx->decoded_fmt.fmt.pix_mp;
|
||||
+ pix_mp->pixelformat = ctx->valid_fmt;
|
||||
+ rkvdec_fill_decoded_pixfmt(ctx, pix_mp);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static const struct v4l2_ctrl_ops rkvdec_ctrl_ops = {
|
||||
.try_ctrl = rkvdec_try_ctrl,
|
||||
+ .s_ctrl = rkvdec_s_ctrl,
|
||||
};
|
||||
|
||||
static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = {
|
||||
@@ -186,6 +219,7 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx)
|
||||
{
|
||||
struct v4l2_format *f = &ctx->decoded_fmt;
|
||||
|
||||
+ ctx->valid_fmt = 0;
|
||||
rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]);
|
||||
f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
|
||||
f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width;
|
||||
@@ -241,13 +275,17 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv,
|
||||
if (WARN_ON(!coded_desc))
|
||||
return -EINVAL;
|
||||
|
||||
- for (i = 0; i < coded_desc->num_decoded_fmts; i++) {
|
||||
- if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat)
|
||||
- break;
|
||||
- }
|
||||
+ if (ctx->valid_fmt) {
|
||||
+ pix_mp->pixelformat = ctx->valid_fmt;
|
||||
+ } else {
|
||||
+ for (i = 0; i < coded_desc->num_decoded_fmts; i++) {
|
||||
+ if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat)
|
||||
+ break;
|
||||
+ }
|
||||
|
||||
- if (i == coded_desc->num_decoded_fmts)
|
||||
- pix_mp->pixelformat = coded_desc->decoded_fmts[0];
|
||||
+ if (i == coded_desc->num_decoded_fmts)
|
||||
+ pix_mp->pixelformat = coded_desc->decoded_fmts[0];
|
||||
+ }
|
||||
|
||||
/* Always apply the frmsize constraint of the coded end. */
|
||||
pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width);
|
||||
@@ -322,6 +360,7 @@ static int rkvdec_s_capture_fmt(struct file *file, void *priv,
|
||||
return ret;
|
||||
|
||||
ctx->decoded_fmt = *f;
|
||||
+ ctx->valid_fmt = f->fmt.pix_mp.pixelformat;
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -411,6 +450,14 @@ static int rkvdec_enum_capture_fmt(struct file *file, void *priv,
|
||||
if (WARN_ON(!ctx->coded_fmt_desc))
|
||||
return -EINVAL;
|
||||
|
||||
+ if (ctx->valid_fmt) {
|
||||
+ if (f->index)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ f->pixelformat = ctx->valid_fmt;
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
if (f->index >= ctx->coded_fmt_desc->num_decoded_fmts)
|
||||
return -EINVAL;
|
||||
|
||||
diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
|
||||
index 52ac3874c5e5..7b6f44ee8a1a 100644
|
||||
--- a/drivers/staging/media/rkvdec/rkvdec.h
|
||||
+++ b/drivers/staging/media/rkvdec/rkvdec.h
|
||||
@@ -62,6 +62,7 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf)
|
||||
struct rkvdec_coded_fmt_ops {
|
||||
int (*adjust_fmt)(struct rkvdec_ctx *ctx,
|
||||
struct v4l2_format *f);
|
||||
+ u32 (*valid_fmt)(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl);
|
||||
int (*start)(struct rkvdec_ctx *ctx);
|
||||
void (*stop)(struct rkvdec_ctx *ctx);
|
||||
int (*run)(struct rkvdec_ctx *ctx);
|
||||
@@ -95,6 +96,7 @@ struct rkvdec_ctx {
|
||||
struct v4l2_fh fh;
|
||||
struct v4l2_format coded_fmt;
|
||||
struct v4l2_format decoded_fmt;
|
||||
+ u32 valid_fmt;
|
||||
const struct rkvdec_coded_fmt_desc *coded_fmt_desc;
|
||||
struct v4l2_ctrl_handler ctrl_hdl;
|
||||
struct rkvdec_dev *dev;
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Mon, 6 Jul 2020 21:54:37 +0000
|
||||
Subject: [PATCH] media: rkvdec: h264: Support High 10 and 4:2:2 profiles
|
||||
|
||||
Add support and enable decoding of H264 High 10 and 4:2:2 profiles.
|
||||
|
||||
Decoded CAPTURE buffer width is aligned to 64 pixels to accommodate HW
|
||||
requirement on 10-bit format buffers.
|
||||
|
||||
The new valid_fmt operation is implemented and return a valid pixelformat
|
||||
for the provided SPS control.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/staging/media/rkvdec/rkvdec-h264.c | 20 ++++++++++++++++++++
|
||||
drivers/staging/media/rkvdec/rkvdec.c | 19 +++++++++----------
|
||||
2 files changed, 29 insertions(+), 10 deletions(-)
|
||||
|
||||
diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
index 88f5f4bb320b..c9a551dbd9bc 100644
|
||||
--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
|
||||
@@ -1021,6 +1021,25 @@ static int rkvdec_h264_adjust_fmt(struct rkvdec_ctx *ctx,
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static u32 rkvdec_h264_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
|
||||
+{
|
||||
+ const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps;
|
||||
+
|
||||
+ if (sps->bit_depth_luma_minus8 == 0) {
|
||||
+ if (sps->chroma_format_idc == 2)
|
||||
+ return V4L2_PIX_FMT_NV16;
|
||||
+ else
|
||||
+ return V4L2_PIX_FMT_NV12;
|
||||
+ } else if (sps->bit_depth_luma_minus8 == 2) {
|
||||
+ if (sps->chroma_format_idc == 2)
|
||||
+ return V4L2_PIX_FMT_NV20;
|
||||
+ else
|
||||
+ return V4L2_PIX_FMT_NV15;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int rkvdec_h264_start(struct rkvdec_ctx *ctx)
|
||||
{
|
||||
struct rkvdec_dev *rkvdec = ctx->dev;
|
||||
@@ -1124,6 +1143,7 @@ static int rkvdec_h264_run(struct rkvdec_ctx *ctx)
|
||||
|
||||
const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops = {
|
||||
.adjust_fmt = rkvdec_h264_adjust_fmt,
|
||||
+ .valid_fmt = rkvdec_h264_valid_fmt,
|
||||
.start = rkvdec_h264_start,
|
||||
.stop = rkvdec_h264_stop,
|
||||
.run = rkvdec_h264_run,
|
||||
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
|
||||
index d31344c4acaa..d068383aeea8 100644
|
||||
--- a/drivers/staging/media/rkvdec/rkvdec.c
|
||||
+++ b/drivers/staging/media/rkvdec/rkvdec.c
|
||||
@@ -31,7 +31,7 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx,
|
||||
struct v4l2_pix_format_mplane *pix_mp)
|
||||
{
|
||||
v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat,
|
||||
- pix_mp->width, pix_mp->height);
|
||||
+ ALIGN(pix_mp->width, 64), pix_mp->height);
|
||||
pix_mp->plane_fmt[0].sizeimage += 128 *
|
||||
DIV_ROUND_UP(pix_mp->width, 16) *
|
||||
DIV_ROUND_UP(pix_mp->height, 16);
|
||||
@@ -55,19 +55,15 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
|
||||
if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) {
|
||||
const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps;
|
||||
unsigned int width, height;
|
||||
- /*
|
||||
- * TODO: The hardware supports 10-bit and 4:2:2 profiles,
|
||||
- * but it's currently broken in the driver.
|
||||
- * Reject them for now, until it's fixed.
|
||||
- */
|
||||
- if (sps->chroma_format_idc > 1)
|
||||
- /* Only 4:0:0 and 4:2:0 are supported */
|
||||
+
|
||||
+ if (sps->chroma_format_idc > 2)
|
||||
+ /* Only 4:0:0, 4:2:0 and 4:2:2 are supported */
|
||||
return -EINVAL;
|
||||
if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
|
||||
/* Luma and chroma bit depth mismatch */
|
||||
return -EINVAL;
|
||||
- if (sps->bit_depth_luma_minus8 != 0)
|
||||
- /* Only 8-bit is supported */
|
||||
+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
|
||||
+ /* Only 8-bit and 10-bit is supported */
|
||||
return -EINVAL;
|
||||
|
||||
if (ctx->valid_fmt && ctx->valid_fmt != rkvdec_valid_fmt(ctx, ctrl))
|
||||
@@ -155,6 +151,9 @@ static const struct rkvdec_ctrls rkvdec_h264_ctrls = {
|
||||
|
||||
static const u32 rkvdec_h264_decoded_fmts[] = {
|
||||
V4L2_PIX_FMT_NV12,
|
||||
+ V4L2_PIX_FMT_NV15,
|
||||
+ V4L2_PIX_FMT_NV16,
|
||||
+ V4L2_PIX_FMT_NV20,
|
||||
};
|
||||
|
||||
static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
|
||||
|
||||
@ -0,0 +1,531 @@
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Mon, 6 Jul 2020 22:30:13 +0000
|
||||
Subject: [PATCH] drm: drm_fourcc: add NV20 and NV30 YUV formats
|
||||
|
||||
DRM_FORMAT_NV20 and DRM_FORMAT_NV30 formats is the 2x1 and non-subsampled
|
||||
variant of NV15, a 10-bit 2-plane YUV format that has no padding between
|
||||
components. Instead, luminance and chrominance samples are grouped into 4s
|
||||
so that each group is packed into an integer number of bytes:
|
||||
|
||||
YYYY = UVUV = 4 * 10 bits = 40 bits = 5 bytes
|
||||
|
||||
The '20' and '30' suffix refers to the optimum effective bits per pixel
|
||||
which is achieved when the total number of luminance samples is a multiple
|
||||
of 4.
|
||||
|
||||
V2: Added NV30 format
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
Reviewed-by: Sandy Huang <hjc@rock-chips.com>
|
||||
---
|
||||
drivers/gpu/drm/drm_fourcc.c | 8 ++++++++
|
||||
include/uapi/drm/drm_fourcc.h | 2 ++
|
||||
2 files changed, 10 insertions(+)
|
||||
|
||||
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
|
||||
index eda832f9200d..9498e9d466fb 100644
|
||||
--- a/drivers/gpu/drm/drm_fourcc.c
|
||||
+++ b/drivers/gpu/drm/drm_fourcc.c
|
||||
@@ -258,6 +258,14 @@ const struct drm_format_info *__drm_format_info(u32 format)
|
||||
.num_planes = 2, .char_per_block = { 5, 5, 0 },
|
||||
.block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 2,
|
||||
.vsub = 2, .is_yuv = true },
|
||||
+ { .format = DRM_FORMAT_NV20, .depth = 0,
|
||||
+ .num_planes = 2, .char_per_block = { 5, 5, 0 },
|
||||
+ .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 2,
|
||||
+ .vsub = 1, .is_yuv = true },
|
||||
+ { .format = DRM_FORMAT_NV30, .depth = 0,
|
||||
+ .num_planes = 2, .char_per_block = { 5, 5, 0 },
|
||||
+ .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 1,
|
||||
+ .vsub = 1, .is_yuv = true },
|
||||
{ .format = DRM_FORMAT_Q410, .depth = 0,
|
||||
.num_planes = 3, .char_per_block = { 2, 2, 2 },
|
||||
.block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, .hsub = 0,
|
||||
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
|
||||
index f7156322aba5..a30bb7ef7632 100644
|
||||
--- a/include/uapi/drm/drm_fourcc.h
|
||||
+++ b/include/uapi/drm/drm_fourcc.h
|
||||
@@ -279,6 +279,8 @@ extern "C" {
|
||||
* index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
|
||||
*/
|
||||
#define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
|
||||
+#define DRM_FORMAT_NV20 fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */
|
||||
+#define DRM_FORMAT_NV30 fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
|
||||
|
||||
/*
|
||||
* 2 plane YCbCr MSB aligned
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Mon, 6 Jul 2020 22:30:13 +0000
|
||||
Subject: [PATCH] drm: rockchip: add NV15, NV20 and NV30 support
|
||||
|
||||
Add support for displaying 10-bit 4:2:0 and 4:2:2 formats produced by the
|
||||
Rockchip Video Decoder on RK322X, RK3288, RK3328, RK3368 and RK3399.
|
||||
Also add support for 10-bit 4:4:4 format while at it.
|
||||
|
||||
V2: Added NV30 support
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
Reviewed-by: Sandy Huang <hjc@rock-chips.com>
|
||||
---
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 29 +++++++++++++++++--
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 +
|
||||
drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 32 +++++++++++++++++----
|
||||
3 files changed, 54 insertions(+), 8 deletions(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
|
||||
index f5b9028a16a3..9df4a271f3aa 100644
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
|
||||
@@ -262,6 +262,18 @@ static bool has_rb_swapped(uint32_t format)
|
||||
}
|
||||
}
|
||||
|
||||
+static bool is_fmt_10(uint32_t format)
|
||||
+{
|
||||
+ switch (format) {
|
||||
+ case DRM_FORMAT_NV15:
|
||||
+ case DRM_FORMAT_NV20:
|
||||
+ case DRM_FORMAT_NV30:
|
||||
+ return true;
|
||||
+ default:
|
||||
+ return false;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
static enum vop_data_format vop_convert_format(uint32_t format)
|
||||
{
|
||||
switch (format) {
|
||||
@@ -277,10 +289,13 @@ static enum vop_data_format vop_convert_format(uint32_t format)
|
||||
case DRM_FORMAT_BGR565:
|
||||
return VOP_FMT_RGB565;
|
||||
case DRM_FORMAT_NV12:
|
||||
+ case DRM_FORMAT_NV15:
|
||||
return VOP_FMT_YUV420SP;
|
||||
case DRM_FORMAT_NV16:
|
||||
+ case DRM_FORMAT_NV20:
|
||||
return VOP_FMT_YUV422SP;
|
||||
case DRM_FORMAT_NV24:
|
||||
+ case DRM_FORMAT_NV30:
|
||||
return VOP_FMT_YUV444SP;
|
||||
default:
|
||||
DRM_ERROR("unsupported format[%08x]\n", format);
|
||||
@@ -931,7 +946,12 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
|
||||
dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
|
||||
dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
|
||||
|
||||
- offset = (src->x1 >> 16) * fb->format->cpp[0];
|
||||
+ if (fb->format->block_w[0])
|
||||
+ offset = (src->x1 >> 16) * fb->format->char_per_block[0] /
|
||||
+ fb->format->block_w[0];
|
||||
+ else
|
||||
+ offset = (src->x1 >> 16) * fb->format->cpp[0];
|
||||
+
|
||||
offset += (src->y1 >> 16) * fb->pitches[0];
|
||||
dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
|
||||
|
||||
@@ -957,6 +977,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
|
||||
}
|
||||
|
||||
VOP_WIN_SET(vop, win, format, format);
|
||||
+ VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format));
|
||||
VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
|
||||
VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
|
||||
VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
|
||||
@@ -973,7 +994,11 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
|
||||
uv_obj = fb->obj[1];
|
||||
rk_uv_obj = to_rockchip_obj(uv_obj);
|
||||
|
||||
- offset = (src->x1 >> 16) * bpp / hsub;
|
||||
+ if (fb->format->block_w[1])
|
||||
+ offset = (src->x1 >> 16) * bpp /
|
||||
+ fb->format->block_w[1] / hsub;
|
||||
+ else
|
||||
+ offset = (src->x1 >> 16) * bpp / hsub;
|
||||
offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
|
||||
|
||||
dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
|
||||
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
|
||||
index 857d97cdc67c..b7169010622a 100644
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
|
||||
@@ -165,6 +165,7 @@ struct vop_win_phy {
|
||||
struct vop_reg enable;
|
||||
struct vop_reg gate;
|
||||
struct vop_reg format;
|
||||
+ struct vop_reg fmt_10;
|
||||
struct vop_reg rb_swap;
|
||||
struct vop_reg act_info;
|
||||
struct vop_reg dsp_info;
|
||||
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
|
||||
index ca7cc82125cb..fff9c3387b9d 100644
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
|
||||
@@ -50,6 +50,23 @@ static const uint32_t formats_win_full[] = {
|
||||
DRM_FORMAT_NV24,
|
||||
};
|
||||
|
||||
+static const uint32_t formats_win_full_10[] = {
|
||||
+ DRM_FORMAT_XRGB8888,
|
||||
+ DRM_FORMAT_ARGB8888,
|
||||
+ DRM_FORMAT_XBGR8888,
|
||||
+ DRM_FORMAT_ABGR8888,
|
||||
+ DRM_FORMAT_RGB888,
|
||||
+ DRM_FORMAT_BGR888,
|
||||
+ DRM_FORMAT_RGB565,
|
||||
+ DRM_FORMAT_BGR565,
|
||||
+ DRM_FORMAT_NV12,
|
||||
+ DRM_FORMAT_NV16,
|
||||
+ DRM_FORMAT_NV24,
|
||||
+ DRM_FORMAT_NV15,
|
||||
+ DRM_FORMAT_NV20,
|
||||
+ DRM_FORMAT_NV30,
|
||||
+};
|
||||
+
|
||||
static const uint64_t format_modifiers_win_full[] = {
|
||||
DRM_FORMAT_MOD_LINEAR,
|
||||
DRM_FORMAT_MOD_INVALID,
|
||||
@@ -613,11 +630,12 @@ static const struct vop_scl_regs rk3288_win_full_scl = {
|
||||
|
||||
static const struct vop_win_phy rk3288_win01_data = {
|
||||
.scl = &rk3288_win_full_scl,
|
||||
- .data_formats = formats_win_full,
|
||||
- .nformats = ARRAY_SIZE(formats_win_full),
|
||||
+ .data_formats = formats_win_full_10,
|
||||
+ .nformats = ARRAY_SIZE(formats_win_full_10),
|
||||
.format_modifiers = format_modifiers_win_full,
|
||||
.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
|
||||
.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
|
||||
+ .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
|
||||
.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
|
||||
.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
|
||||
.dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
|
||||
@@ -747,11 +765,12 @@ static const struct vop_intr rk3368_vop_intr = {
|
||||
|
||||
static const struct vop_win_phy rk3368_win01_data = {
|
||||
.scl = &rk3288_win_full_scl,
|
||||
- .data_formats = formats_win_full,
|
||||
- .nformats = ARRAY_SIZE(formats_win_full),
|
||||
+ .data_formats = formats_win_full_10,
|
||||
+ .nformats = ARRAY_SIZE(formats_win_full_10),
|
||||
.format_modifiers = format_modifiers_win_full,
|
||||
.enable = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 0),
|
||||
.format = VOP_REG(RK3368_WIN0_CTRL0, 0x7, 1),
|
||||
+ .fmt_10 = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 4),
|
||||
.rb_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 12),
|
||||
.x_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 21),
|
||||
.y_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 22),
|
||||
@@ -896,11 +915,12 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_big_win_yuv2yuv_data[] = {
|
||||
|
||||
static const struct vop_win_phy rk3399_win01_data = {
|
||||
.scl = &rk3288_win_full_scl,
|
||||
- .data_formats = formats_win_full,
|
||||
- .nformats = ARRAY_SIZE(formats_win_full),
|
||||
+ .data_formats = formats_win_full_10,
|
||||
+ .nformats = ARRAY_SIZE(formats_win_full_10),
|
||||
.format_modifiers = format_modifiers_win_full_afbc,
|
||||
.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
|
||||
.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
|
||||
+ .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
|
||||
.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
|
||||
.y_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 22),
|
||||
.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Qinglang Miao <miaoqinglang@huawei.com>
|
||||
Date: Tue, 1 Dec 2020 20:54:57 +0800
|
||||
Subject: [PATCH] drm/rockchip: cdn-dp: fix reference leak when
|
||||
pm_runtime_get_sync fails
|
||||
|
||||
The PM reference count is not expected to be incremented on
|
||||
return in cdn_dp_clk_enable.
|
||||
|
||||
However, pm_runtime_get_sync will increment the PM reference
|
||||
count even failed. Forgetting to putting operation will result
|
||||
in a reference leak here.
|
||||
|
||||
Replace it with pm_runtime_resume_and_get to keep usage
|
||||
counter balanced.
|
||||
|
||||
Fixes: efe0220fc2d2 ("drm/rockchip: cdn-dp: Fix error handling")
|
||||
Reported-by: Hulk Robot <hulkci@huawei.com>
|
||||
Signed-off-by: Qinglang Miao <miaoqinglang@huawei.com>
|
||||
---
|
||||
drivers/gpu/drm/rockchip/cdn-dp-core.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c
|
||||
index 8ab3247dbc4a..8429c6706ec5 100644
|
||||
--- a/drivers/gpu/drm/rockchip/cdn-dp-core.c
|
||||
+++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c
|
||||
@@ -100,7 +100,7 @@ static int cdn_dp_clk_enable(struct cdn_dp_device *dp)
|
||||
goto err_core_clk;
|
||||
}
|
||||
|
||||
- ret = pm_runtime_get_sync(dp->dev);
|
||||
+ ret = pm_runtime_resume_and_get(dp->dev);
|
||||
if (ret < 0) {
|
||||
DRM_DEV_ERROR(dp->dev, "cannot get pm runtime %d\n", ret);
|
||||
goto err_pm_runtime_get;
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Qinglang Miao <miaoqinglang@huawei.com>
|
||||
Date: Tue, 1 Dec 2020 20:54:58 +0800
|
||||
Subject: [PATCH] drm/rockchip: vop: fix reference leak when
|
||||
pm_runtime_get_sync fails
|
||||
|
||||
The PM reference count is not expected to be incremented on
|
||||
return in functions vop_enable and vop_enable.
|
||||
|
||||
However, pm_runtime_get_sync will increment the PM reference
|
||||
count even failed. Forgetting to putting operation will result
|
||||
in a reference leak here.
|
||||
|
||||
Replace it with pm_runtime_resume_and_get to keep usage
|
||||
counter balanced.
|
||||
|
||||
Fixes: 5e570373c015 ("drm/rockchip: vop: Enable pm domain before vop_initial")
|
||||
Reported-by: Hulk Robot <hulkci@huawei.com>
|
||||
Signed-off-by: Qinglang Miao <miaoqinglang@huawei.com>
|
||||
---
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
|
||||
index 9df4a271f3aa..c3c0de25b8e6 100644
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
|
||||
@@ -603,7 +603,7 @@ static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state)
|
||||
struct vop *vop = to_vop(crtc);
|
||||
int ret, i;
|
||||
|
||||
- ret = pm_runtime_get_sync(vop->dev);
|
||||
+ ret = pm_runtime_resume_and_get(vop->dev);
|
||||
if (ret < 0) {
|
||||
DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
|
||||
return ret;
|
||||
@@ -1956,7 +1956,7 @@ static int vop_initial(struct vop *vop)
|
||||
return PTR_ERR(vop->dclk);
|
||||
}
|
||||
|
||||
- ret = pm_runtime_get_sync(vop->dev);
|
||||
+ ret = pm_runtime_resume_and_get(vop->dev);
|
||||
if (ret < 0) {
|
||||
DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
|
||||
return ret;
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Qinglang Miao <miaoqinglang@huawei.com>
|
||||
Date: Tue, 1 Dec 2020 20:54:59 +0800
|
||||
Subject: [PATCH] drm/rockchip: lvds: fix reference leak when
|
||||
pm_runtime_get_sync fails
|
||||
|
||||
The PM reference count is not expected to be incremented on
|
||||
return in functions rk3288_lvds_poweron and px30_lvds_poweron.
|
||||
|
||||
However, pm_runtime_get_sync will increment the PM reference
|
||||
count even failed. Forgetting to putting operation will result
|
||||
in a reference leak here.
|
||||
|
||||
Replace it with pm_runtime_resume_and_get to keep usage
|
||||
counter balanced.
|
||||
|
||||
Fixes: cca1705c3d89 ("drm/rockchip: lvds: Add PX30 support")
|
||||
Reported-by: Hulk Robot <hulkci@huawei.com>
|
||||
Signed-off-by: Qinglang Miao <miaoqinglang@huawei.com>
|
||||
---
|
||||
drivers/gpu/drm/rockchip/rockchip_lvds.c | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c b/drivers/gpu/drm/rockchip/rockchip_lvds.c
|
||||
index 489d63c05c0d..aaf0b6bbcb85 100644
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_lvds.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c
|
||||
@@ -145,7 +145,7 @@ static int rk3288_lvds_poweron(struct rockchip_lvds *lvds)
|
||||
DRM_DEV_ERROR(lvds->dev, "failed to enable lvds pclk %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
- ret = pm_runtime_get_sync(lvds->dev);
|
||||
+ ret = pm_runtime_resume_and_get(lvds->dev);
|
||||
if (ret < 0) {
|
||||
DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret);
|
||||
clk_disable(lvds->pclk);
|
||||
@@ -329,7 +329,7 @@ static int px30_lvds_poweron(struct rockchip_lvds *lvds)
|
||||
{
|
||||
int ret;
|
||||
|
||||
- ret = pm_runtime_get_sync(lvds->dev);
|
||||
+ ret = pm_runtime_resume_and_get(lvds->dev);
|
||||
if (ret < 0) {
|
||||
DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret);
|
||||
return ret;
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Thomas Zimmermann <tzimmermann@suse.de>
|
||||
Date: Thu, 24 Jun 2021 11:55:02 +0200
|
||||
Subject: [PATCH] drm/rockchip: Implement mmap as GEM object function
|
||||
|
||||
Moving the driver-specific mmap code into a GEM object function allows
|
||||
for using DRM helpers for various mmap callbacks.
|
||||
|
||||
The respective rockchip functions are being removed. The file_operations
|
||||
structure fops is now being created by the helper macro
|
||||
DEFINE_DRM_GEM_FOPS().
|
||||
|
||||
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
|
||||
Tested-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 13 +-----
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c | 3 +-
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 44 +++++--------------
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_gem.h | 7 ---
|
||||
4 files changed, 15 insertions(+), 52 deletions(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
|
||||
index b730b8d5d949..2e3ab573a817 100644
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
|
||||
@@ -208,16 +208,7 @@ static void rockchip_drm_unbind(struct device *dev)
|
||||
drm_dev_put(drm_dev);
|
||||
}
|
||||
|
||||
-static const struct file_operations rockchip_drm_driver_fops = {
|
||||
- .owner = THIS_MODULE,
|
||||
- .open = drm_open,
|
||||
- .mmap = rockchip_gem_mmap,
|
||||
- .poll = drm_poll,
|
||||
- .read = drm_read,
|
||||
- .unlocked_ioctl = drm_ioctl,
|
||||
- .compat_ioctl = drm_compat_ioctl,
|
||||
- .release = drm_release,
|
||||
-};
|
||||
+DEFINE_DRM_GEM_FOPS(rockchip_drm_driver_fops);
|
||||
|
||||
static const struct drm_driver rockchip_drm_driver = {
|
||||
.driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
|
||||
@@ -226,7 +217,7 @@ static const struct drm_driver rockchip_drm_driver = {
|
||||
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
|
||||
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
|
||||
.gem_prime_import_sg_table = rockchip_gem_prime_import_sg_table,
|
||||
- .gem_prime_mmap = rockchip_gem_mmap_buf,
|
||||
+ .gem_prime_mmap = drm_gem_prime_mmap,
|
||||
.fops = &rockchip_drm_driver_fops,
|
||||
.name = DRIVER_NAME,
|
||||
.desc = DRIVER_DESC,
|
||||
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c
|
||||
index 2fdc455c4ad7..d8418dd39d0e 100644
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c
|
||||
@@ -7,6 +7,7 @@
|
||||
#include <drm/drm.h>
|
||||
#include <drm/drm_fb_helper.h>
|
||||
#include <drm/drm_fourcc.h>
|
||||
+#include <drm/drm_prime.h>
|
||||
#include <drm/drm_probe_helper.h>
|
||||
|
||||
#include "rockchip_drm_drv.h"
|
||||
@@ -24,7 +25,7 @@ static int rockchip_fbdev_mmap(struct fb_info *info,
|
||||
struct drm_fb_helper *helper = info->par;
|
||||
struct rockchip_drm_private *private = to_drm_private(helper);
|
||||
|
||||
- return rockchip_gem_mmap_buf(private->fbdev_bo, vma);
|
||||
+ return drm_gem_prime_mmap(private->fbdev_bo, vma);
|
||||
}
|
||||
|
||||
static const struct fb_ops rockchip_drm_fbdev_ops = {
|
||||
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
|
||||
index 7971f57436dd..63eb73b624aa 100644
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
|
||||
@@ -240,12 +240,22 @@ static int rockchip_drm_gem_object_mmap(struct drm_gem_object *obj,
|
||||
int ret;
|
||||
struct rockchip_gem_object *rk_obj = to_rockchip_obj(obj);
|
||||
|
||||
+ /*
|
||||
+ * Set vm_pgoff (used as a fake buffer offset by DRM) to 0 and map the
|
||||
+ * whole buffer from the start.
|
||||
+ */
|
||||
+ vma->vm_pgoff = 0;
|
||||
+
|
||||
/*
|
||||
* We allocated a struct page table for rk_obj, so clear
|
||||
* VM_PFNMAP flag that was set by drm_gem_mmap_obj()/drm_gem_mmap().
|
||||
*/
|
||||
+ vma->vm_flags |= VM_IO | VM_DONTEXPAND | VM_DONTDUMP;
|
||||
vma->vm_flags &= ~VM_PFNMAP;
|
||||
|
||||
+ vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
|
||||
+ vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot);
|
||||
+
|
||||
if (rk_obj->pages)
|
||||
ret = rockchip_drm_gem_object_mmap_iommu(obj, vma);
|
||||
else
|
||||
@@ -257,39 +267,6 @@ static int rockchip_drm_gem_object_mmap(struct drm_gem_object *obj,
|
||||
return ret;
|
||||
}
|
||||
|
||||
-int rockchip_gem_mmap_buf(struct drm_gem_object *obj,
|
||||
- struct vm_area_struct *vma)
|
||||
-{
|
||||
- int ret;
|
||||
-
|
||||
- ret = drm_gem_mmap_obj(obj, obj->size, vma);
|
||||
- if (ret)
|
||||
- return ret;
|
||||
-
|
||||
- return rockchip_drm_gem_object_mmap(obj, vma);
|
||||
-}
|
||||
-
|
||||
-/* drm driver mmap file operations */
|
||||
-int rockchip_gem_mmap(struct file *filp, struct vm_area_struct *vma)
|
||||
-{
|
||||
- struct drm_gem_object *obj;
|
||||
- int ret;
|
||||
-
|
||||
- ret = drm_gem_mmap(filp, vma);
|
||||
- if (ret)
|
||||
- return ret;
|
||||
-
|
||||
- /*
|
||||
- * Set vm_pgoff (used as a fake buffer offset by DRM) to 0 and map the
|
||||
- * whole buffer from the start.
|
||||
- */
|
||||
- vma->vm_pgoff = 0;
|
||||
-
|
||||
- obj = vma->vm_private_data;
|
||||
-
|
||||
- return rockchip_drm_gem_object_mmap(obj, vma);
|
||||
-}
|
||||
-
|
||||
static void rockchip_gem_release_object(struct rockchip_gem_object *rk_obj)
|
||||
{
|
||||
drm_gem_object_release(&rk_obj->base);
|
||||
@@ -301,6 +278,7 @@ static const struct drm_gem_object_funcs rockchip_gem_object_funcs = {
|
||||
.get_sg_table = rockchip_gem_prime_get_sg_table,
|
||||
.vmap = rockchip_gem_prime_vmap,
|
||||
.vunmap = rockchip_gem_prime_vunmap,
|
||||
+ .mmap = rockchip_drm_gem_object_mmap,
|
||||
.vm_ops = &drm_gem_cma_vm_ops,
|
||||
};
|
||||
|
||||
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.h b/drivers/gpu/drm/rockchip/rockchip_drm_gem.h
|
||||
index 5a70a56cd406..47c1861eece0 100644
|
||||
--- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.h
|
||||
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.h
|
||||
@@ -34,13 +34,6 @@ rockchip_gem_prime_import_sg_table(struct drm_device *dev,
|
||||
int rockchip_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map);
|
||||
void rockchip_gem_prime_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map);
|
||||
|
||||
-/* drm driver mmap file operations */
|
||||
-int rockchip_gem_mmap(struct file *filp, struct vm_area_struct *vma);
|
||||
-
|
||||
-/* mmap a gem object to userspace. */
|
||||
-int rockchip_gem_mmap_buf(struct drm_gem_object *obj,
|
||||
- struct vm_area_struct *vma);
|
||||
-
|
||||
struct rockchip_gem_object *
|
||||
rockchip_gem_create_object(struct drm_device *drm, unsigned int size,
|
||||
bool alloc_kmap);
|
||||
|
||||
3505
patch/kernel/archive/rockchip-5.16/01-linux-1000-drm-rockchip.patch
Normal file
3505
patch/kernel/archive/rockchip-5.16/01-linux-1000-drm-rockchip.patch
Normal file
File diff suppressed because it is too large
Load Diff
1023
patch/kernel/archive/rockchip-5.16/01-linux-1001-v4l2-rockchip.patch
Normal file
1023
patch/kernel/archive/rockchip-5.16/01-linux-1001-v4l2-rockchip.patch
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,647 @@
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Wed, 2 Sep 2020 19:52:02 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: add gpu powerdomain, gpu opp-table and
|
||||
cooling cell for RK3328
|
||||
|
||||
Note: since the regulator that supplies the GPU usually also supplies
|
||||
other SoC components, we have to make sure voltage is never lower then
|
||||
1075 mV.
|
||||
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 34 ++++++++++++++++++++++++
|
||||
1 file changed, 34 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
index 23021373e15b..ca03c8ed9708 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
@@ -300,6 +300,11 @@ power: power-controller {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
+ power-domain@RK3328_PD_GPU {
|
||||
+ reg = <RK3328_PD_GPU>;
|
||||
+ clocks = <&cru ACLK_GPU>;
|
||||
+ #power-domain-cells = <0>;
|
||||
+ };
|
||||
power-domain@RK3328_PD_HEVC {
|
||||
reg = <RK3328_PD_HEVC>;
|
||||
#power-domain-cells = <0>;
|
||||
@@ -539,6 +544,11 @@ map0 {
|
||||
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
contribution = <4096>;
|
||||
};
|
||||
+ map1 {
|
||||
+ trip = <&target>;
|
||||
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
+ contribution = <4096>;
|
||||
+ };
|
||||
};
|
||||
};
|
||||
|
||||
@@ -620,7 +630,31 @@ gpu: gpu@ff300000 {
|
||||
"ppmmu1";
|
||||
clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
|
||||
clock-names = "bus", "core";
|
||||
+ operating-points-v2 = <&gpu_opp_table>;
|
||||
+ power-domains = <&power RK3328_PD_GPU>;
|
||||
resets = <&cru SRST_GPU_A>;
|
||||
+ #cooling-cells = <2>;
|
||||
+ };
|
||||
+
|
||||
+ gpu_opp_table: gpu-opp-table {
|
||||
+ compatible = "operating-points-v2";
|
||||
+
|
||||
+ opp-200000000 {
|
||||
+ opp-hz = /bits/ 64 <200000000>;
|
||||
+ opp-microvolt = <1075000>;
|
||||
+ };
|
||||
+ opp-300000000 {
|
||||
+ opp-hz = /bits/ 64 <300000000>;
|
||||
+ opp-microvolt = <1075000>;
|
||||
+ };
|
||||
+ opp-400000000 {
|
||||
+ opp-hz = /bits/ 64 <400000000>;
|
||||
+ opp-microvolt = <1075000>;
|
||||
+ };
|
||||
+ opp-500000000 {
|
||||
+ opp-hz = /bits/ 64 <500000000>;
|
||||
+ opp-microvolt = <1150000>;
|
||||
+ };
|
||||
};
|
||||
|
||||
h265e_mmu: iommu@ff330200 {
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Tue, 2 Feb 2021 17:22:21 +0200
|
||||
Subject: [PATCH] ARM: dts: RK3288 miqi add hdmi sound nodes
|
||||
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
---
|
||||
arch/arm/boot/dts/rk3288-miqi.dts | 20 ++++++++++++++++++++
|
||||
1 file changed, 20 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
|
||||
index 713f55e143c6..8d30c49f406e 100644
|
||||
--- a/arch/arm/boot/dts/rk3288-miqi.dts
|
||||
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
|
||||
@@ -78,6 +78,21 @@ vcc_sys: vsys-regulator {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
+
|
||||
+ sound {
|
||||
+ compatible = "simple-audio-card";
|
||||
+ simple-audio-card,format = "i2s";
|
||||
+ simple-audio-card,name = "HDMI";
|
||||
+ simple-audio-card,mclk-fs = <512>;
|
||||
+
|
||||
+ simple-audio-card,codec {
|
||||
+ sound-dai = <&hdmi>;
|
||||
+ };
|
||||
+
|
||||
+ simple-audio-card,cpu {
|
||||
+ sound-dai = <&i2s>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
@@ -284,6 +299,11 @@ &i2c5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&i2s {
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&io_domains {
|
||||
status = "okay";
|
||||
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Fri, 2 Apr 2021 17:54:22 +0200
|
||||
Subject: [PATCH] ARM/arm64: dts: rockchip: align sound card names
|
||||
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
---
|
||||
arch/arm/boot/dts/rk3288-tinker.dtsi | 2 +-
|
||||
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +-
|
||||
2 files changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi
|
||||
index 9c1e38c54eae..ee332fc9cf1f 100644
|
||||
--- a/arch/arm/boot/dts/rk3288-tinker.dtsi
|
||||
+++ b/arch/arm/boot/dts/rk3288-tinker.dtsi
|
||||
@@ -75,7 +75,7 @@ sdio_pwrseq: sdio-pwrseq {
|
||||
sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,format = "i2s";
|
||||
- simple-audio-card,name = "rockchip,tinker-codec";
|
||||
+ simple-audio-card,name = "HDMI";
|
||||
simple-audio-card,mclk-fs = <512>;
|
||||
|
||||
simple-audio-card,codec {
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
index ec3561d147d5..b2ed593a229c 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
@@ -1807,7 +1807,7 @@ hdmi_sound: hdmi-sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,mclk-fs = <256>;
|
||||
- simple-audio-card,name = "hdmi-sound";
|
||||
+ simple-audio-card,name = "HDMI";
|
||||
status = "disabled";
|
||||
|
||||
simple-audio-card,cpu {
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Wed, 10 Feb 2021 18:44:56 +0200
|
||||
Subject: [PATCH] HACK: drm/gem: suppress warning about missing vm_flags
|
||||
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
---
|
||||
drivers/gpu/drm/drm_gem.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
|
||||
index d62fb1a3c916..e46165bed006 100644
|
||||
--- a/drivers/gpu/drm/drm_gem.c
|
||||
+++ b/drivers/gpu/drm/drm_gem.c
|
||||
@@ -1073,7 +1073,7 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size,
|
||||
ret = obj->funcs->mmap(obj, vma);
|
||||
if (ret)
|
||||
goto err_drm_gem_object_put;
|
||||
- WARN_ON(!(vma->vm_flags & VM_DONTEXPAND));
|
||||
+ //WARN_ON(!(vma->vm_flags & VM_DONTEXPAND));
|
||||
} else {
|
||||
if (!vma->vm_ops) {
|
||||
ret = -EINVAL;
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Sun, 25 Mar 2018 22:17:06 +0200
|
||||
Subject: [PATCH] ASoC: hdmi-codec: fix channel allocation
|
||||
|
||||
---
|
||||
sound/soc/codecs/hdmi-codec.c | 113 ++++++++++++++++------------------
|
||||
1 file changed, 52 insertions(+), 61 deletions(-)
|
||||
|
||||
diff --git a/sound/soc/codecs/hdmi-codec.c b/sound/soc/codecs/hdmi-codec.c
|
||||
index b61f980cabdc..3ad50ae8c93d 100644
|
||||
--- a/sound/soc/codecs/hdmi-codec.c
|
||||
+++ b/sound/soc/codecs/hdmi-codec.c
|
||||
@@ -194,78 +194,69 @@ static const struct snd_pcm_chmap_elem hdmi_codec_8ch_chmaps[] = {
|
||||
*/
|
||||
static const struct hdmi_codec_cea_spk_alloc hdmi_codec_channel_alloc[] = {
|
||||
{ .ca_id = 0x00, .n_ch = 2,
|
||||
- .mask = FL | FR},
|
||||
- /* 2.1 */
|
||||
- { .ca_id = 0x01, .n_ch = 4,
|
||||
- .mask = FL | FR | LFE},
|
||||
- /* Dolby Surround */
|
||||
+ .mask = FL | FR },
|
||||
+ { .ca_id = 0x03, .n_ch = 4,
|
||||
+ .mask = FL | FR | LFE | FC },
|
||||
{ .ca_id = 0x02, .n_ch = 4,
|
||||
.mask = FL | FR | FC },
|
||||
- /* surround51 */
|
||||
+ { .ca_id = 0x01, .n_ch = 4,
|
||||
+ .mask = FL | FR | LFE },
|
||||
{ .ca_id = 0x0b, .n_ch = 6,
|
||||
- .mask = FL | FR | LFE | FC | RL | RR},
|
||||
- /* surround40 */
|
||||
- { .ca_id = 0x08, .n_ch = 6,
|
||||
- .mask = FL | FR | RL | RR },
|
||||
- /* surround41 */
|
||||
- { .ca_id = 0x09, .n_ch = 6,
|
||||
- .mask = FL | FR | LFE | RL | RR },
|
||||
- /* surround50 */
|
||||
+ .mask = FL | FR | LFE | FC | RL | RR },
|
||||
{ .ca_id = 0x0a, .n_ch = 6,
|
||||
.mask = FL | FR | FC | RL | RR },
|
||||
- /* 6.1 */
|
||||
- { .ca_id = 0x0f, .n_ch = 8,
|
||||
- .mask = FL | FR | LFE | FC | RL | RR | RC },
|
||||
- /* surround71 */
|
||||
+ { .ca_id = 0x09, .n_ch = 6,
|
||||
+ .mask = FL | FR | LFE | RL | RR },
|
||||
+ { .ca_id = 0x08, .n_ch = 6,
|
||||
+ .mask = FL | FR | RL | RR },
|
||||
+ { .ca_id = 0x07, .n_ch = 6,
|
||||
+ .mask = FL | FR | LFE | FC | RC },
|
||||
+ { .ca_id = 0x06, .n_ch = 6,
|
||||
+ .mask = FL | FR | FC | RC },
|
||||
+ { .ca_id = 0x05, .n_ch = 6,
|
||||
+ .mask = FL | FR | LFE | RC },
|
||||
+ { .ca_id = 0x04, .n_ch = 6,
|
||||
+ .mask = FL | FR | RC },
|
||||
{ .ca_id = 0x13, .n_ch = 8,
|
||||
.mask = FL | FR | LFE | FC | RL | RR | RLC | RRC },
|
||||
- /* others */
|
||||
- { .ca_id = 0x03, .n_ch = 8,
|
||||
- .mask = FL | FR | LFE | FC },
|
||||
- { .ca_id = 0x04, .n_ch = 8,
|
||||
- .mask = FL | FR | RC},
|
||||
- { .ca_id = 0x05, .n_ch = 8,
|
||||
- .mask = FL | FR | LFE | RC },
|
||||
- { .ca_id = 0x06, .n_ch = 8,
|
||||
- .mask = FL | FR | FC | RC },
|
||||
- { .ca_id = 0x07, .n_ch = 8,
|
||||
- .mask = FL | FR | LFE | FC | RC },
|
||||
- { .ca_id = 0x0c, .n_ch = 8,
|
||||
- .mask = FL | FR | RC | RL | RR },
|
||||
- { .ca_id = 0x0d, .n_ch = 8,
|
||||
- .mask = FL | FR | LFE | RL | RR | RC },
|
||||
- { .ca_id = 0x0e, .n_ch = 8,
|
||||
- .mask = FL | FR | FC | RL | RR | RC },
|
||||
- { .ca_id = 0x10, .n_ch = 8,
|
||||
- .mask = FL | FR | RL | RR | RLC | RRC },
|
||||
- { .ca_id = 0x11, .n_ch = 8,
|
||||
- .mask = FL | FR | LFE | RL | RR | RLC | RRC },
|
||||
+ { .ca_id = 0x1f, .n_ch = 8,
|
||||
+ .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC },
|
||||
{ .ca_id = 0x12, .n_ch = 8,
|
||||
.mask = FL | FR | FC | RL | RR | RLC | RRC },
|
||||
- { .ca_id = 0x14, .n_ch = 8,
|
||||
- .mask = FL | FR | FLC | FRC },
|
||||
- { .ca_id = 0x15, .n_ch = 8,
|
||||
- .mask = FL | FR | LFE | FLC | FRC },
|
||||
- { .ca_id = 0x16, .n_ch = 8,
|
||||
- .mask = FL | FR | FC | FLC | FRC },
|
||||
- { .ca_id = 0x17, .n_ch = 8,
|
||||
- .mask = FL | FR | LFE | FC | FLC | FRC },
|
||||
- { .ca_id = 0x18, .n_ch = 8,
|
||||
- .mask = FL | FR | RC | FLC | FRC },
|
||||
- { .ca_id = 0x19, .n_ch = 8,
|
||||
- .mask = FL | FR | LFE | RC | FLC | FRC },
|
||||
- { .ca_id = 0x1a, .n_ch = 8,
|
||||
- .mask = FL | FR | RC | FC | FLC | FRC },
|
||||
- { .ca_id = 0x1b, .n_ch = 8,
|
||||
- .mask = FL | FR | LFE | RC | FC | FLC | FRC },
|
||||
- { .ca_id = 0x1c, .n_ch = 8,
|
||||
- .mask = FL | FR | RL | RR | FLC | FRC },
|
||||
- { .ca_id = 0x1d, .n_ch = 8,
|
||||
- .mask = FL | FR | LFE | RL | RR | FLC | FRC },
|
||||
{ .ca_id = 0x1e, .n_ch = 8,
|
||||
.mask = FL | FR | FC | RL | RR | FLC | FRC },
|
||||
- { .ca_id = 0x1f, .n_ch = 8,
|
||||
- .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC },
|
||||
+ { .ca_id = 0x11, .n_ch = 8,
|
||||
+ .mask = FL | FR | LFE | RL | RR | RLC | RRC },
|
||||
+ { .ca_id = 0x1d, .n_ch = 8,
|
||||
+ .mask = FL | FR | LFE | RL | RR | FLC | FRC },
|
||||
+ { .ca_id = 0x10, .n_ch = 8,
|
||||
+ .mask = FL | FR | RL | RR | RLC | RRC },
|
||||
+ { .ca_id = 0x1c, .n_ch = 8,
|
||||
+ .mask = FL | FR | RL | RR | FLC | FRC },
|
||||
+ { .ca_id = 0x0f, .n_ch = 8,
|
||||
+ .mask = FL | FR | LFE | FC | RL | RR | RC },
|
||||
+ { .ca_id = 0x1b, .n_ch = 8,
|
||||
+ .mask = FL | FR | LFE | RC | FC | FLC | FRC },
|
||||
+ { .ca_id = 0x0e, .n_ch = 8,
|
||||
+ .mask = FL | FR | FC | RL | RR | RC },
|
||||
+ { .ca_id = 0x1a, .n_ch = 8,
|
||||
+ .mask = FL | FR | RC | FC | FLC | FRC },
|
||||
+ { .ca_id = 0x0d, .n_ch = 8,
|
||||
+ .mask = FL | FR | LFE | RL | RR | RC },
|
||||
+ { .ca_id = 0x19, .n_ch = 8,
|
||||
+ .mask = FL | FR | LFE | RC | FLC | FRC },
|
||||
+ { .ca_id = 0x0c, .n_ch = 8,
|
||||
+ .mask = FL | FR | RC | RL | RR },
|
||||
+ { .ca_id = 0x18, .n_ch = 8,
|
||||
+ .mask = FL | FR | RC | FLC | FRC },
|
||||
+ { .ca_id = 0x17, .n_ch = 8,
|
||||
+ .mask = FL | FR | LFE | FC | FLC | FRC },
|
||||
+ { .ca_id = 0x16, .n_ch = 8,
|
||||
+ .mask = FL | FR | FC | FLC | FRC },
|
||||
+ { .ca_id = 0x15, .n_ch = 8,
|
||||
+ .mask = FL | FR | LFE | FLC | FRC },
|
||||
+ { .ca_id = 0x14, .n_ch = 8,
|
||||
+ .mask = FL | FR | FLC | FRC },
|
||||
};
|
||||
|
||||
struct hdmi_codec_priv {
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Sun, 2 May 2021 20:44:21 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: Fix gmac delays for rockpro64 board
|
||||
|
||||
Values are measured by RK's delayline tool in vendor kernel
|
||||
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
|
||||
index 83db4ca67334..06d2a1e3e340 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
|
||||
@@ -289,8 +289,8 @@ &gmac {
|
||||
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 10000 50000>;
|
||||
- tx_delay = <0x28>;
|
||||
- rx_delay = <0x11>;
|
||||
+ tx_delay = <0x23>;
|
||||
+ rx_delay = <0x1e>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Sat, 27 Feb 2021 17:52:02 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: add SPDIF nodes for RK3328 A1 board
|
||||
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 23 ++++++++++++++++++++++
|
||||
1 file changed, 23 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
|
||||
index de2d3e88e27f..68b74ed080f3 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
|
||||
@@ -57,6 +57,24 @@ ir-receiver {
|
||||
gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
|
||||
linux,rc-map-name = "rc-beelink-gs1";
|
||||
};
|
||||
+
|
||||
+ spdif_sound: spdif-sound {
|
||||
+ compatible = "simple-audio-card";
|
||||
+ simple-audio-card,name = "SPDIF";
|
||||
+
|
||||
+ simple-audio-card,cpu {
|
||||
+ sound-dai = <&spdif>;
|
||||
+ };
|
||||
+
|
||||
+ simple-audio-card,codec {
|
||||
+ sound-dai = <&spdif_dit>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ spdif_dit: spdif-dit {
|
||||
+ compatible = "linux,spdif-dit";
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ };
|
||||
};
|
||||
|
||||
&analog_sound {
|
||||
@@ -324,6 +342,11 @@ &sdmmc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&spdif {
|
||||
+ pinctrl-0 = <&spdifm0_tx>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <0>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Sat, 27 Feb 2021 18:01:13 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add ir-receiver node for RK3328 ROC CC
|
||||
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 14 ++++++++++++++
|
||||
1 file changed, 14 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
|
||||
index aa22a0c22265..a78fbddd21df 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
|
||||
@@ -88,6 +88,13 @@ vcc_phy: vcc-phy-regulator {
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
+ ir-receiver {
|
||||
+ compatible = "gpio-ir-receiver";
|
||||
+ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
|
||||
+ pinctrl-0 = <&ir_int>;
|
||||
+ pinctrl-names = "default";
|
||||
+ };
|
||||
+
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
@@ -308,6 +315,13 @@ &io_domains {
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
+
|
||||
+ ir {
|
||||
+ ir_int: ir-int {
|
||||
+ rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
pmic {
|
||||
pmic_int_l: pmic-int-l {
|
||||
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Mon, 1 Mar 2021 21:24:15 +0100
|
||||
Subject: [PATCH] ARM: dts: add cec pinctrl for RK3288 miqi board
|
||||
|
||||
---
|
||||
arch/arm/boot/dts/rk3288-miqi.dts | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
|
||||
index 8d30c49f406e..6d90db5a3b75 100644
|
||||
--- a/arch/arm/boot/dts/rk3288-miqi.dts
|
||||
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
|
||||
@@ -145,6 +145,8 @@ &gpu {
|
||||
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&i2c5>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&hdmi_cec_c0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Mon, 1 Mar 2021 19:22:15 +0100
|
||||
Subject: [PATCH] HACK: arm64: dts: enable FE phy for Beelink A1 also
|
||||
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 8 ++++++++
|
||||
1 file changed, 8 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
|
||||
index 68b74ed080f3..6736b5dc53e4 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
|
||||
@@ -147,6 +147,14 @@ rtl8211f: ethernet-phy@0 {
|
||||
};
|
||||
};
|
||||
|
||||
+&gmac2phy {
|
||||
+ clock_in_out = "output";
|
||||
+ assigned-clock-rate = <50000000>;
|
||||
+ assigned-clocks = <&cru SCLK_MAC2PHY>;
|
||||
+ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&gpu {
|
||||
mali-supply = <&vdd_logic>;
|
||||
};
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Tue, 26 Feb 2019 20:45:14 +0000
|
||||
Subject: [PATCH] WIP: dw-hdmi-cec: sleep 100ms on error
|
||||
|
||||
---
|
||||
drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c | 18 ++++++++++++++++--
|
||||
1 file changed, 16 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c
|
||||
index 70ab4fbdc23e..bf54bc70624f 100644
|
||||
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c
|
||||
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c
|
||||
@@ -4,6 +4,7 @@
|
||||
*
|
||||
* Copyright (C) 2015-2017 Russell King.
|
||||
*/
|
||||
+#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
@@ -129,8 +130,15 @@ static irqreturn_t dw_hdmi_cec_hardirq(int irq, void *data)
|
||||
|
||||
dw_hdmi_write(cec, stat, HDMI_IH_CEC_STAT0);
|
||||
|
||||
- if (stat & CEC_STAT_ERROR_INIT) {
|
||||
- cec->tx_status = CEC_TX_STATUS_ERROR;
|
||||
+ /* Status with both done and error_initiator bits have been seen
|
||||
+ * on Rockchip RK3328 devices, transmit attempt seems to have failed
|
||||
+ * when this happens, report as low drive and block cec-framework
|
||||
+ * 100ms before core retransmits the failed message, this seems to
|
||||
+ * mitigate the issue with failed transmit attempts.
|
||||
+ */
|
||||
+ if ((stat & (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) == (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) {
|
||||
+ pr_debug("dw_hdmi_cec_hardirq: stat=%02x LOW_DRIVE\n", stat);
|
||||
+ cec->tx_status = CEC_TX_STATUS_LOW_DRIVE;
|
||||
cec->tx_done = true;
|
||||
ret = IRQ_WAKE_THREAD;
|
||||
} else if (stat & CEC_STAT_DONE) {
|
||||
@@ -141,6 +149,10 @@ static irqreturn_t dw_hdmi_cec_hardirq(int irq, void *data)
|
||||
cec->tx_status = CEC_TX_STATUS_NACK;
|
||||
cec->tx_done = true;
|
||||
ret = IRQ_WAKE_THREAD;
|
||||
+ } else if (stat & CEC_STAT_ERROR_INIT) {
|
||||
+ cec->tx_status = CEC_TX_STATUS_ERROR;
|
||||
+ cec->tx_done = true;
|
||||
+ ret = IRQ_WAKE_THREAD;
|
||||
}
|
||||
|
||||
if (stat & CEC_STAT_EOM) {
|
||||
@@ -173,6 +185,8 @@ static irqreturn_t dw_hdmi_cec_thread(int irq, void *data)
|
||||
|
||||
if (cec->tx_done) {
|
||||
cec->tx_done = false;
|
||||
+ if (cec->tx_status == CEC_TX_STATUS_LOW_DRIVE)
|
||||
+ msleep(100);
|
||||
cec_transmit_attempt_done(adap, cec->tx_status);
|
||||
}
|
||||
if (cec->rx_done) {
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Wed, 5 May 2021 19:11:12 +0200
|
||||
Subject: [PATCH] arm64: boot: dts: Increase ACLK_PERILP0 clock rate for RK3399
|
||||
|
||||
As per vendor kernel. Leaving this clock at the lower rate will
|
||||
result in poor DMA controller performance
|
||||
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
index b2ed593a229c..27938ff0d208 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
@@ -1393,7 +1393,7 @@ cru: clock-controller@ff760000 {
|
||||
<1000000000>,
|
||||
<150000000>, <75000000>,
|
||||
<37500000>,
|
||||
- <100000000>, <100000000>,
|
||||
+ <300000000>, <100000000>,
|
||||
<50000000>, <600000000>,
|
||||
<100000000>, <50000000>,
|
||||
<400000000>, <400000000>,
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Sat, 21 Aug 2021 17:04:46 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: Enable USB3 for rk3328 Beelink A1
|
||||
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 5 +++++
|
||||
1 file changed, 5 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
|
||||
index 6736b5dc53e4..9000fae2a5ee 100644
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
|
||||
@@ -388,6 +388,11 @@ &usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&usbdrd3 {
|
||||
+ dr_mode = "host";
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&vop {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Alex Bee <knaerzche@gmail.com>
|
||||
Date: Sat, 21 Aug 2021 14:03:25 +0200
|
||||
Subject: [PATCH] HACK: media: hantro: rockchip: disable H264 for RK3328
|
||||
|
||||
Signed-off-by: Alex Bee <knaerzche@gmail.com>
|
||||
---
|
||||
drivers/staging/media/hantro/rockchip_vpu_hw.c | 3 +--
|
||||
1 file changed, 1 insertion(+), 2 deletions(-)
|
||||
|
||||
diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c
|
||||
index 3d98e2251ea5..b201700ccc8a 100644
|
||||
--- a/drivers/staging/media/hantro/rockchip_vpu_hw.c
|
||||
+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c
|
||||
@@ -530,8 +530,7 @@ const struct hantro_variant rk3328_vpu_variant = {
|
||||
.dec_offset = 0x400,
|
||||
.dec_fmts = rk3399_vpu_dec_fmts,
|
||||
.num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
|
||||
- .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
|
||||
- HANTRO_H264_DECODER,
|
||||
+ .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER,
|
||||
.codec_ops = rk3399_vpu_codec_ops,
|
||||
.irqs = rockchip_vdpu2_irqs,
|
||||
.num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs),
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,74 @@
|
||||
Patches act8846 regulator providing the proper reset handle and exploit
|
||||
the SIPC bit in GLB_POWER_OFF register. Mainly used to reset some rockchip
|
||||
boards.
|
||||
|
||||
Origin: <https://patchwork.kernel.org/patch/6409521/>
|
||||
|
||||
diff --git a/drivers/regulator/act8865-regulator.c b/drivers/regulator/act8865-regulator.c
|
||||
index 2ff73d7..836d10b 100644
|
||||
--- a/drivers/regulator/act8865-regulator.c
|
||||
+++ b/drivers/regulator/act8865-regulator.c
|
||||
@@ -27,6 +27,7 @@
|
||||
#include <linux/regulator/of_regulator.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <dt-bindings/regulator/active-semi,8865-regulator.h>
|
||||
+#include <linux/reboot.h>
|
||||
|
||||
/*
|
||||
* ACT8600 Global Register Map.
|
||||
@@ -133,6 +134,8 @@
|
||||
#define ACT8865_VOLTAGE_NUM 64
|
||||
#define ACT8600_SUDCDC_VOLTAGE_NUM 255
|
||||
|
||||
+#define ACT8846_SIPC_MASK 0x01
|
||||
+
|
||||
struct act8865 {
|
||||
struct regmap *regmap;
|
||||
int off_reg;
|
||||
@@ -402,6 +405,22 @@ static void act8865_power_off(void)
|
||||
while (1);
|
||||
}
|
||||
|
||||
+static int act8846_power_cycle(struct notifier_block *this,
|
||||
+ unsigned long code, void *unused)
|
||||
+{
|
||||
+ struct act8865 *act8846;
|
||||
+
|
||||
+ act8846 = i2c_get_clientdata(act8865_i2c_client);
|
||||
+ regmap_write(act8846->regmap, ACT8846_GLB_OFF_CTRL, ACT8846_SIPC_MASK);
|
||||
+
|
||||
+ return NOTIFY_DONE;
|
||||
+}
|
||||
+
|
||||
+static struct notifier_block act8846_restart_handler = {
|
||||
+ .notifier_call = act8846_power_cycle,
|
||||
+ .priority = 129,
|
||||
+};
|
||||
+
|
||||
static int act8865_pmic_probe(struct i2c_client *client,
|
||||
const struct i2c_device_id *i2c_id)
|
||||
{
|
||||
@@ -484,6 +503,8 @@ static int act8865_pmic_probe(struct i2c_client *client,
|
||||
}
|
||||
|
||||
if (of_device_is_system_power_controller(dev->of_node)) {
|
||||
+ int ret;
|
||||
+
|
||||
if (!pm_power_off && (off_reg > 0)) {
|
||||
act8865_i2c_client = client;
|
||||
act8865->off_reg = off_reg;
|
||||
@@ -492,6 +513,14 @@ static int act8865_pmic_probe(struct i2c_client *client,
|
||||
} else {
|
||||
dev_err(dev, "Failed to set poweroff capability, already defined\n");
|
||||
}
|
||||
+
|
||||
+ if (type == ACT8846) {
|
||||
+ act8865_i2c_client = client;
|
||||
+ ret = register_restart_handler(&act8846_restart_handler);
|
||||
+ if (ret)
|
||||
+ pr_err("%s: cannot register restart handler, %d\n",
|
||||
+ __func__, ret);
|
||||
+ }
|
||||
}
|
||||
|
||||
/* Finally register devices */
|
||||
@ -0,0 +1,35 @@
|
||||
From 604ea7fc311af2b3a41e7fe3b4fbde0ee03dfb9c Mon Sep 17 00:00:00 2001
|
||||
From: Myy Miouyouyou <myy@miouyouyou.fr>
|
||||
Date: Thu, 19 Oct 2017 21:09:50 +0200
|
||||
Subject: [PATCH 04/28] dts: rk3288: miqi: Enabling the Mali GPU node
|
||||
|
||||
Why is the MiQi the only one left without a working mali GPU node ?
|
||||
|
||||
Seriously, is there a rk3288 chipset WITHOUT a mali GPU ? Couldn't
|
||||
they enable it once in the DTSI, instead of defining it as "disabled"
|
||||
and enabling it in every DTS file ?
|
||||
|
||||
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
|
||||
---
|
||||
arch/arm/boot/dts/rk3288-miqi.dts | 5 +++++
|
||||
1 file changed, 5 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
|
||||
index 4d923aa6..3cd60674 100644
|
||||
--- a/arch/arm/boot/dts/rk3288-miqi.dts
|
||||
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
|
||||
@@ -149,6 +149,11 @@
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
+&gpu {
|
||||
+ mali-supply = <&vdd_gpu>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&i2c5>;
|
||||
status = "okay";
|
||||
--
|
||||
2.11.0
|
||||
|
||||
@ -0,0 +1,45 @@
|
||||
From 89e5763110ca77d68a4be00cd97a638adc2401d5 Mon Sep 17 00:00:00 2001
|
||||
From: Willy Tarreau <w@1wt.eu>
|
||||
Date: Tue, 2 Aug 2016 08:31:00 +0200
|
||||
Subject: [PATCH 05/28] ARM: dts: rockchip: fix the regulator's voltage range
|
||||
on MiQi board
|
||||
|
||||
The board declared too narrow a voltage range for the CPU and GPU
|
||||
regulators, preventing it from using the full CPU frequency range.
|
||||
The regulators support 712500 to 1500000 microvolts.
|
||||
|
||||
Signed-off-by: Willy Tarreau <w@1wt.eu>
|
||||
(cherry picked from commit 95330e63a9295a2632cee8cce5db80677f01857a)
|
||||
---
|
||||
arch/arm/boot/dts/rk3288-miqi.dts | 8 ++++----
|
||||
1 file changed, 4 insertions(+), 4 deletions(-)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
|
||||
index 3cd60674..a1c3cdaa 100644
|
||||
--- a/arch/arm/boot/dts/rk3288-miqi.dts
|
||||
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
|
||||
@@ -168,8 +168,8 @@
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
reg = <0x40>;
|
||||
regulator-name = "vdd_cpu";
|
||||
- regulator-min-microvolt = <850000>;
|
||||
- regulator-max-microvolt = <1350000>;
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-enable-ramp-delay = <300>;
|
||||
@@ -182,8 +182,8 @@
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
reg = <0x41>;
|
||||
regulator-name = "vdd_gpu";
|
||||
- regulator-min-microvolt = <850000>;
|
||||
- regulator-max-microvolt = <1350000>;
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
--
|
||||
2.11.0
|
||||
|
||||
@ -0,0 +1,45 @@
|
||||
From c27e445527e949f3ef46d5326066196969c17d23 Mon Sep 17 00:00:00 2001
|
||||
From: Myy <myy@miouyouyou.fr>
|
||||
Date: Sun, 12 Mar 2017 19:43:15 +0000
|
||||
Subject: [PATCH 06/28] ARM: dts: rockchip: add the MiQi board's fan definition
|
||||
|
||||
The MiQi board is sold with an enclosure in which a fan is connected
|
||||
to the second LED output, and configured by default in "heartbeat"
|
||||
mode so that it rotates slowly and increases when the CPU load
|
||||
increases, ensuring appropriate cooling by default. This LED output
|
||||
is called "Fan" in the original kernel and connected to GPIO18
|
||||
(gpiochip 0, pin 18). Here we called it "miqi:green:fan" to stay
|
||||
consistent with the kernel's naming conventions.
|
||||
|
||||
It's worth noting that without this patch the fan doesn't work at
|
||||
all, risking to make the board overheat.
|
||||
|
||||
Fixes: 162718c (v4.7)
|
||||
Cc: Heiko Stuebner <heiko@sntech.de>
|
||||
Signed-off-by: Willy Tarreau <w@1wt.eu>
|
||||
|
||||
Signed-off-by: Myy <myy@miouyouyou.fr>
|
||||
---
|
||||
arch/arm/boot/dts/rk3288-miqi.dts | 7 +++++++
|
||||
1 file changed, 7 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
|
||||
index a1c3cdaa..0e383595 100644
|
||||
--- a/arch/arm/boot/dts/rk3288-miqi.dts
|
||||
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
|
||||
@@ -67,6 +67,13 @@
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
+ fan {
|
||||
+ gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
|
||||
+ label = "miqi:green:fan";
|
||||
+ linux,default-trigger = "heartbeat";
|
||||
+ };
|
||||
+
|
||||
+
|
||||
work_led: led-0 {
|
||||
gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||
label = "miqi:green:user";
|
||||
--
|
||||
2.11.0
|
||||
@ -0,0 +1,31 @@
|
||||
From 062488e4b8fd552c01e1104b3bc91a6f7ffe6c41 Mon Sep 17 00:00:00 2001
|
||||
From: Myy Miouyouyou <myy@miouyouyou.fr>
|
||||
Date: Thu, 19 Oct 2017 21:24:47 +0200
|
||||
Subject: [PATCH 10/28] RK3288: DTSI: rk3288.dtsi: Add missing SPI2 pinctrl
|
||||
|
||||
The spi2_cs1 pin reference is missing in the spi2 first pin control
|
||||
definition.
|
||||
|
||||
This patch is taken from the patches provided by the ARMbian team.
|
||||
|
||||
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
|
||||
---
|
||||
arch/arm/boot/dts/rk3288.dtsi | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
|
||||
index 5b789528..9ed532cc 100644
|
||||
--- a/arch/arm/boot/dts/rk3288.dtsi
|
||||
+++ b/arch/arm/boot/dts/rk3288.dtsi
|
||||
@@ -334,7 +334,7 @@
|
||||
dma-names = "tx", "rx";
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
- pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
|
||||
+ pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0 &spi2_cs1>;
|
||||
reg = <0x0 0xff130000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
--
|
||||
2.11.0
|
||||
|
||||
@ -0,0 +1,27 @@
|
||||
From ac220d592aa38b9b717d36f7bb93f7be5a08f6b3 Mon Sep 17 00:00:00 2001
|
||||
From: Myy Miouyouyou <myy@miouyouyou.fr>
|
||||
Date: Thu, 19 Oct 2017 21:43:51 +0200
|
||||
Subject: [PATCH 14/28] ARM: DTSI: rk3288.dtsi: Adding missing EDP power domain
|
||||
|
||||
Imported from Rockchip 4.4 kernel patches.
|
||||
|
||||
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
|
||||
---
|
||||
arch/arm/boot/dts/rk3288.dtsi | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
|
||||
index 14ef8202..10ecebb4 100644
|
||||
--- a/arch/arm/boot/dts/rk3288.dtsi
|
||||
+++ b/arch/arm/boot/dts/rk3288.dtsi
|
||||
@@ -1105,6 +1105,7 @@
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
|
||||
clock-names = "dp", "pclk";
|
||||
+ power-domains = <&power RK3288_PD_VIO>;
|
||||
phys = <&edp_phy>;
|
||||
phy-names = "dp";
|
||||
resets = <&cru SRST_EDP>;
|
||||
--
|
||||
2.11.0
|
||||
|
||||
@ -0,0 +1,31 @@
|
||||
From a0602b2724893de7ac9b4190a7a6bb66458da2d5 Mon Sep 17 00:00:00 2001
|
||||
From: Myy Miouyouyou <myy@miouyouyou.fr>
|
||||
Date: Thu, 19 Oct 2017 21:54:37 +0200
|
||||
Subject: [PATCH 17/28] ARM: DTSI: rk3288.dtsi: Fixed the SPDIF node address
|
||||
|
||||
Now, the typo is only in the name of the node itself, not in the
|
||||
actual registers addresses definition.
|
||||
|
||||
Still, this ought to be fixed one day !
|
||||
|
||||
Signed-off-by: Myy Miouyouyou <myy@miouyouyou.fr>
|
||||
---
|
||||
arch/arm/boot/dts/rk3288.dtsi | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
|
||||
index 125f8835..e5d3d3c9 100644
|
||||
--- a/arch/arm/boot/dts/rk3288.dtsi
|
||||
+++ b/arch/arm/boot/dts/rk3288.dtsi
|
||||
@@ -922,7 +922,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
- spdif: sound@ff88b0000 {
|
||||
+ spdif: sound@ff8b0000 {
|
||||
compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
|
||||
reg = <0x0 0xff8b0000 0x0 0x10000>;
|
||||
#sound-dai-cells = <0>;
|
||||
--
|
||||
2.11.0
|
||||
|
||||
@ -0,0 +1,98 @@
|
||||
From d5d5c53173c484a13cda62a537cbf75a5df4b0e4 Mon Sep 17 00:00:00 2001
|
||||
From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
|
||||
Date: Mon, 5 Nov 2018 21:58:56 +0100
|
||||
Subject: [PATCH] ARM: DTS: rk3288-tinker: Enabling SDIO and Wifi
|
||||
|
||||
Adding the appropriate nodes in order to exploit the WiFi capabilities
|
||||
of the board.
|
||||
Since these capabilities are provided through SDIO, and the SDIO
|
||||
nodes were not defined, these were added too.
|
||||
|
||||
These seems to depend on each other so they are added in one big
|
||||
patch.
|
||||
|
||||
Split if necessary.
|
||||
|
||||
Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
|
||||
---
|
||||
arch/arm/boot/dts/rk3288-tinker.dts | 62 +++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 62 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
|
||||
index 1e43527aa..d4df13bed 100644
|
||||
--- a/arch/arm/boot/dts/rk3288-tinker.dts
|
||||
+++ b/arch/arm/boot/dts/rk3288-tinker.dts
|
||||
@@ -6,8 +6,70 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3288-tinker.dtsi"
|
||||
+#include <dt-bindings/clock/rockchip,rk808.h>
|
||||
|
||||
/ {
|
||||
model = "Rockchip RK3288 Asus Tinker Board";
|
||||
compatible = "asus,rk3288-tinker", "rockchip,rk3288";
|
||||
+
|
||||
+ /* This is essential to get SDIO devices working.
|
||||
+ The Wifi depends on SDIO ! */
|
||||
+ sdio_pwrseq: sdio-pwrseq {
|
||||
+ compatible = "mmc-pwrseq-simple";
|
||||
+ clocks = <&rk808 RK808_CLKOUT1>;
|
||||
+ clock-names = "ext_clock";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&chip_enable_h>, <&wifi_enable_h>;
|
||||
+
|
||||
+ /*
|
||||
+ * On the module itself this is one of these (depending
|
||||
+ * on the actual card populated):
|
||||
+ * - SDIO_RESET_L_WL_REG_ON
|
||||
+ * - PDN (power down when low)
|
||||
+ */
|
||||
+ reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>, <&gpio4 27 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+
|
||||
+ wireless-wlan {
|
||||
+ compatible = "wlan-platdata";
|
||||
+ rockchip,grf = <&grf>;
|
||||
+ sdio_vref = <1800>;
|
||||
+ status = "okay";
|
||||
+ wifi_chip_type = "8723bs";
|
||||
+ WIFI,host_wake_irq = <&gpio4 30 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&io_domains {
|
||||
+ wifi-supply = <&vcc_18>;
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ sdio-pwrseq {
|
||||
+ wifi_enable_h: wifienable-h {
|
||||
+ rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ chip_enable_h: chip-enable-h {
|
||||
+ rockchip,pins = <4 27 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&sdio0 {
|
||||
+ bus-width = <4>;
|
||||
+ cap-sd-highspeed;
|
||||
+ cap-sdio-irq;
|
||||
+ clock-frequency = <50000000>;
|
||||
+ clock-freq-min-max = <200000 50000000>;
|
||||
+ disable-wp;
|
||||
+ keep-power-in-suspend;
|
||||
+ mmc-pwrseq = <&sdio_pwrseq>;
|
||||
+ non-removable;
|
||||
+ num-slots = <1>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
|
||||
+ sd-uhs-sdr104;
|
||||
+ status = "okay";
|
||||
+ supports-sdio;
|
||||
};
|
||||
--
|
||||
2.16.4
|
||||
|
||||
@ -0,0 +1,62 @@
|
||||
From 2c2e60256f2cbb2fce50a6317f85b1500efd1a6c Mon Sep 17 00:00:00 2001
|
||||
From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
|
||||
Date: Mon, 5 Nov 2018 22:03:26 +0100
|
||||
Subject: [PATCH] ARM: DTS: rk3288-tinker: Setup the Bluetooth UART pins
|
||||
|
||||
The most essential being the RTS pin, which is clearly needed to
|
||||
upload the initial configuration into the Realtek Bluetooth
|
||||
chip, and make the Bluetooth chip work.
|
||||
|
||||
Now, the Bluetooth chip also needs 3 other GPIOS to be enabled.
|
||||
I'll see how I do that through the DTS file in a near future.
|
||||
|
||||
The 3 GPIOS being :
|
||||
Bluetooth Reset : <&gpio4 29 GPIO_ACTIVE_HIGH>
|
||||
Bluetooth Wake : <&gpio4 26 GPIO_ACTIVE_HIGH>
|
||||
Bluetooth Wake_Host_IRQ : <&gpio4 31 GPIO_ACTIVE_HIGH>
|
||||
|
||||
These are currently setup manually, through scripts. But it seems that
|
||||
GPIO handling through /sys entries might not be possible in the long
|
||||
term, the replacement being libgpio.
|
||||
Anyway, if you're interesting in enabling the Bluetooth GPIO by hand,
|
||||
here are the commands :
|
||||
|
||||
cd /sys/class/gpio &&
|
||||
echo 146 > export &&
|
||||
echo 149 > export &&
|
||||
echo 151 > export &&
|
||||
echo high > gpio146/direction &&
|
||||
echo high > gpio149/direction &&
|
||||
echo high > gpio151/direction
|
||||
|
||||
Resetting the chip is done like this :
|
||||
|
||||
echo "Resetting the Bluetooth chip"
|
||||
cd /sys/class/gpio/gpio149 &&
|
||||
echo 0 > value &&
|
||||
sleep 1 &&
|
||||
echo 1 > value &&
|
||||
sleep 1
|
||||
|
||||
Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
|
||||
---
|
||||
arch/arm/boot/dts/rk3288-tinker.dts | 6 ++++++
|
||||
1 file changed, 6 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
|
||||
index d4df13bed..b92e59c1e 100644
|
||||
--- a/arch/arm/boot/dts/rk3288-tinker.dts
|
||||
+++ b/arch/arm/boot/dts/rk3288-tinker.dts
|
||||
@@ -73,3 +73,9 @@
|
||||
status = "okay";
|
||||
supports-sdio;
|
||||
};
|
||||
+
|
||||
+&uart0 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>;
|
||||
+};
|
||||
+
|
||||
--
|
||||
2.16.4
|
||||
|
||||
@ -0,0 +1,28 @@
|
||||
From ebc29962ac27264772a4227f5abd6900cb72fa79 Mon Sep 17 00:00:00 2001
|
||||
From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
|
||||
Date: Mon, 5 Nov 2018 20:16:05 +0100
|
||||
Subject: [PATCH] ARM: DTSI: rk3288-tinker: Improving the CPU max voltage
|
||||
|
||||
Taken from the various patches provided by @TonyMac32 .
|
||||
|
||||
Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
|
||||
---
|
||||
arch/arm/boot/dts/rk3288-tinker.dtsi | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi
|
||||
index aa107ee41..3da1c830f 100644
|
||||
--- a/arch/arm/boot/dts/rk3288-tinker.dtsi
|
||||
+++ b/arch/arm/boot/dts/rk3288-tinker.dtsi
|
||||
@@ -164,7 +164,7 @@
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
- regulator-max-microvolt = <1400000>;
|
||||
+ regulator-max-microvolt = <1450000>;
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-ramp-delay = <6000>;
|
||||
regulator-state-mem {
|
||||
--
|
||||
2.16.4
|
||||
|
||||
@ -0,0 +1,53 @@
|
||||
From a72e0749acad92df7b854e38e97e1dc7b4799abe Mon Sep 17 00:00:00 2001
|
||||
From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
|
||||
Date: Mon, 5 Nov 2018 22:11:24 +0100
|
||||
Subject: [PATCH] ARM: DTS: rk3288-tinker: Defined the I2C interfaces
|
||||
|
||||
And all the hardware behind.
|
||||
|
||||
Taken from @TonyMac32, Butchered by @Miouyouyou .
|
||||
|
||||
Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
|
||||
---
|
||||
arch/arm/boot/dts/rk3288-tinker.dts | 25 +++++++++++++++++++++++++
|
||||
1 file changed, 25 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
|
||||
index b92e59c1e..96d05fc6b 100644
|
||||
--- a/arch/arm/boot/dts/rk3288-tinker.dts
|
||||
+++ b/arch/arm/boot/dts/rk3288-tinker.dts
|
||||
@@ -40,6 +40,31 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&i2c1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c2 {
|
||||
+ afc0:af-controller@0 {
|
||||
+ status = "okay";
|
||||
+ compatible = "silicon touch,vm149C-v4l2-i2c-subdev";
|
||||
+ reg = <0x0 0x0c>;
|
||||
+ };
|
||||
+
|
||||
+ eeprom:m24c08@50 {
|
||||
+ compatible = "at,24c08";
|
||||
+ reg = <0x50>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2c3 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c4 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&io_domains {
|
||||
wifi-supply = <&vcc_18>;
|
||||
};
|
||||
--
|
||||
2.16.4
|
||||
|
||||
@ -0,0 +1,50 @@
|
||||
From b24b8f83e150811ad54ee2a4843e44cd1421fafa Mon Sep 17 00:00:00 2001
|
||||
From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
|
||||
Date: Mon, 5 Nov 2018 22:15:14 +0100
|
||||
Subject: [PATCH] ARM: DTS: rk3288-tinker: Defining the SPI interface
|
||||
|
||||
Taken from, and tested by @TonyMac32 .
|
||||
|
||||
Well, the original one was tested by him but I had to adapt the
|
||||
registers definitions to the new 64-bits LPAE-compliant syntax.
|
||||
|
||||
Therefore that *might* break, along with a few other patches.
|
||||
|
||||
Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
|
||||
---
|
||||
arch/arm/boot/dts/rk3288-tinker.dts | 19 +++++++++++++++++++
|
||||
1 file changed, 19 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
|
||||
index 96d05fc6b..17bfea298 100644
|
||||
--- a/arch/arm/boot/dts/rk3288-tinker.dts
|
||||
+++ b/arch/arm/boot/dts/rk3288-tinker.dts
|
||||
@@ -99,6 +99,25 @@
|
||||
supports-sdio;
|
||||
};
|
||||
|
||||
+&spi2 {
|
||||
+ max-freq = <50000000>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ spidev@0 {
|
||||
+ compatible = "rockchip,spi_tinker";
|
||||
+ reg = <0x0 0>;
|
||||
+ spi-max-frequency = <50000000>;
|
||||
+ spi-cpha = <1>;
|
||||
+ };
|
||||
+
|
||||
+ spidev@1 {
|
||||
+ compatible = "rockchip,spi_tinker";
|
||||
+ reg = <0x1>;
|
||||
+ spi-max-frequency = <50000000>;
|
||||
+ spi-cpha = <1>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>;
|
||||
--
|
||||
2.16.4
|
||||
|
||||
@ -0,0 +1,33 @@
|
||||
From 487db7cefc9861fdaf30579c378a98f0360690ae Mon Sep 17 00:00:00 2001
|
||||
From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
|
||||
Date: Mon, 5 Nov 2018 20:27:14 +0100
|
||||
Subject: [PATCH] ARM: DTSI: rk3288-tinker: Defining SDMMC properties
|
||||
|
||||
I never knew if these properties were required to fix the dreaded
|
||||
reboot issue...
|
||||
|
||||
Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
|
||||
---
|
||||
arch/arm/boot/dts/rk3288-tinker.dtsi | 5 +++++
|
||||
1 file changed, 5 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi
|
||||
index dd1090728..8edd6f681 100644
|
||||
--- a/arch/arm/boot/dts/rk3288-tinker.dtsi
|
||||
+++ b/arch/arm/boot/dts/rk3288-tinker.dtsi
|
||||
@@ -436,7 +436,12 @@
|
||||
disable-wp; /* wp not hooked up */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
|
||||
+ sd-uhs-sdr12;
|
||||
+ sd-uhs-sdr25;
|
||||
+ sd-uhs-sdr50;
|
||||
+ sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
+ supports-sd;
|
||||
vmmc-supply = <&vcc33_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
};
|
||||
--
|
||||
2.16.4
|
||||
|
||||
@ -0,0 +1,46 @@
|
||||
From 4ab4f88649468dada5d609e1a6f8a71a7d5610c9 Mon Sep 17 00:00:00 2001
|
||||
From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
|
||||
Date: Sat, 29 Sep 2018 02:48:59 +0200
|
||||
Subject: [PATCH 4/6] dts: rk3288: support for dedicating npll to a vop
|
||||
|
||||
This patch is taken from Urja Rannikko ( @urjaman ) patchset here :
|
||||
https://github.com/urjaman/arch-c201/blob/master/linux-c201/0020-RK3288-HDMI-clock-hacks-combined.patch
|
||||
https://www.spinics.net/lists/arm-kernel/msg673156.html
|
||||
|
||||
The original description was :
|
||||
|
||||
Add the VOP DCLKs to the assigned clocks list so their
|
||||
parents can be set in the dts include files for
|
||||
devices that do dedicate npll to a vop.
|
||||
|
||||
https://www.spinics.net/lists/arm-kernel/msg673162.html
|
||||
|
||||
Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
|
||||
---
|
||||
arch/arm/boot/dts/rk3288.dtsi | 6 ++++--
|
||||
1 file changed, 4 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
|
||||
index d23c7fa55..ff04aab5e 100644
|
||||
--- a/arch/arm/boot/dts/rk3288.dtsi
|
||||
+++ b/arch/arm/boot/dts/rk3288.dtsi
|
||||
@@ -867,12 +867,14 @@
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
- assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
|
||||
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
|
||||
+ <&cru PLL_GPLL>, <&cru PLL_CPLL>,
|
||||
<&cru PLL_NPLL>, <&cru ACLK_CPU>,
|
||||
<&cru HCLK_CPU>, <&cru PCLK_CPU>,
|
||||
<&cru ACLK_PERI>, <&cru HCLK_PERI>,
|
||||
<&cru PCLK_PERI>;
|
||||
- assigned-clock-rates = <594000000>, <400000000>,
|
||||
+ assigned-clock-rates = <0>, <0>,
|
||||
+ <594000000>, <400000000>,
|
||||
<500000000>, <300000000>,
|
||||
<150000000>, <75000000>,
|
||||
<300000000>, <150000000>,
|
||||
--
|
||||
2.16.4
|
||||
|
||||
@ -0,0 +1,32 @@
|
||||
From 9177b30ab083dbda2bede3b3d61ef71ad4b1ffe0 Mon Sep 17 00:00:00 2001
|
||||
From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
|
||||
Date: Thu, 1 Nov 2018 21:31:26 +0100
|
||||
Subject: [PATCH 2/2] arm: dts: veyron: Added a flag to disable cache flush
|
||||
during reset
|
||||
|
||||
Flushing the MMC cache of ASUS Chromebooks during initialization or
|
||||
"recovery" generates 10 minutes hangup, according to @SolidHal.
|
||||
|
||||
This is an adaptation of @SolidHal, in order to pinpoint the fix to
|
||||
Veyron Chromebooks, and avoiding issues other RK3288 boards.
|
||||
|
||||
Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
|
||||
---
|
||||
arch/arm/boot/dts/rk3288-veyron.dtsi | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
|
||||
index 2075120cf..fa4951fd7 100644
|
||||
--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
|
||||
+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
|
||||
@@ -123,6 +123,7 @@
|
||||
mmc-hs200-1_8v;
|
||||
mmc-pwrseq = <&emmc_pwrseq>;
|
||||
non-removable;
|
||||
+ no-recovery-cache-flush;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
|
||||
};
|
||||
--
|
||||
2.16.4
|
||||
|
||||
@ -0,0 +1,40 @@
|
||||
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
|
||||
index 0cd88774d..07681f1f0 100644
|
||||
--- a/arch/arm/boot/dts/rk3288.dtsi
|
||||
+++ b/arch/arm/boot/dts/rk3288.dtsi
|
||||
@@ -420,8 +420,6 @@
|
||||
reg-io-width = <4>;
|
||||
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
- dmas = <&dmac_peri 1>, <&dmac_peri 2>;
|
||||
- dma-names = "tx", "rx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_xfer>;
|
||||
status = "disabled";
|
||||
@@ -435,8 +433,6 @@
|
||||
reg-io-width = <4>;
|
||||
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
- dmas = <&dmac_peri 3>, <&dmac_peri 4>;
|
||||
- dma-names = "tx", "rx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_xfer>;
|
||||
status = "disabled";
|
||||
@@ -463,8 +459,6 @@
|
||||
reg-io-width = <4>;
|
||||
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
- dmas = <&dmac_peri 7>, <&dmac_peri 8>;
|
||||
- dma-names = "tx", "rx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3_xfer>;
|
||||
status = "disabled";
|
||||
@@ -478,8 +472,6 @@
|
||||
reg-io-width = <4>;
|
||||
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
- dmas = <&dmac_peri 9>, <&dmac_peri 10>;
|
||||
- dma-names = "tx", "rx";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4_xfer>;
|
||||
status = "disabled";
|
||||
@ -0,0 +1,42 @@
|
||||
From 73258d32daf3a661281bb5c77c5e2e06c7ff714e Mon Sep 17 00:00:00 2001
|
||||
From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
|
||||
Date: Fri, 3 Jul 2020 02:02:18 +0200
|
||||
Subject: [PATCH] arm: dtsi: rk3288: add GPU 500 Mhz OPP again
|
||||
|
||||
Undoing the very bizarre mainline kernel patch,
|
||||
75481833c6dbab4c29d15452f6b4337c16f5407b
|
||||
which main purpose is to sync some 3.14 kernels hacks to
|
||||
mainline kernels, for reasons that only matter for a few Chromebooks,
|
||||
and shove it down the throat of every RK3288 user.
|
||||
|
||||
If you need to avoid the GPU going to 500 Mhz on Chromebooks,
|
||||
remove the OPP entry inside the DTS that actually matters to RK3288
|
||||
Chromebooks.
|
||||
|
||||
Meanwhile, the 600 Mhz operating point can prove to be unstable on
|
||||
some RK3288 boards, while 500 Mhz works fine.
|
||||
https://forum.armbian.com/topic/13515-panfrost-on-rk3288-and-gpu-on-600mhz-problems/
|
||||
|
||||
Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
|
||||
---
|
||||
arch/arm/boot/dts/rk3288.dtsi | 4 ++++
|
||||
1 file changed, 4 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
|
||||
index a66412547..ef7457f79 100644
|
||||
--- a/arch/arm/boot/dts/rk3288.dtsi
|
||||
+++ b/arch/arm/boot/dts/rk3288.dtsi
|
||||
@@ -1312,6 +1312,10 @@ opp-400000000 {
|
||||
opp-hz = /bits/ 64 <400000000>;
|
||||
opp-microvolt = <1100000>;
|
||||
};
|
||||
+ opp-500000000 {
|
||||
+ opp-hz = /bits/ 64 <500000000>;
|
||||
+ opp-microvolt = <1200000>;
|
||||
+ };
|
||||
opp-600000000 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
opp-microvolt = <1250000>;
|
||||
--
|
||||
2.27.0
|
||||
|
||||
13
patch/kernel/archive/rockchip-5.16/1027-fix-rga-probe.patch
Normal file
13
patch/kernel/archive/rockchip-5.16/1027-fix-rga-probe.patch
Normal file
@ -0,0 +1,13 @@
|
||||
diff --git a/drivers/media/platform/rockchip/rga/rga.c b/drivers/media/platform/rockchip/rga/rga.c
|
||||
index 6759091b1..d99ea8973 100644
|
||||
--- a/drivers/media/platform/rockchip/rga/rga.c
|
||||
+++ b/drivers/media/platform/rockchip/rga/rga.c
|
||||
@@ -895,7 +895,7 @@ static int rga_probe(struct platform_device *pdev)
|
||||
}
|
||||
rga->dst_mmu_pages =
|
||||
(unsigned int *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 3);
|
||||
- if (rga->dst_mmu_pages) {
|
||||
+ if (!rga->dst_mmu_pages) {
|
||||
ret = -ENOMEM;
|
||||
goto free_src_pages;
|
||||
}
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user