rockchip64-6.18: media-0001-Add-rkvdec-Support-v5: drop upstreamed patch (:12)
- See 21368fcbb1
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@ -3960,110 +3960,6 @@ index 111111111111..222222222222 100644
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--
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Armbian
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
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Date: Mon, 23 Jun 2025 18:05:29 +0200
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Subject: bitmap: introduce hardware-specific bitfield operations
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Hardware of various vendors, but very notably Rockchip, often uses
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32-bit registers where the upper 16-bit half of the register is a
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write-enable mask for the lower half.
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This type of hardware setup allows for more granular concurrent register
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write access.
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Over the years, many drivers have hand-rolled their own version of this
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macro, usually without any checks, often called something like
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HIWORD_UPDATE or FIELD_PREP_HIWORD, commonly with slightly different
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semantics between them.
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Clearly there is a demand for such a macro, and thus the demand should
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be satisfied in a common header file. As this is a convention that spans
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across multiple vendors, and similar conventions may also have
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cross-vendor adoption, it's best if it lives in a vendor-agnostic header
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file that can be expanded over time.
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Add hw_bitfield.h with two macros: FIELD_PREP_WM16, and
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FIELD_PREP_WM16_CONST. The latter is a version that can be used in
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initializers, like FIELD_PREP_CONST.
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Suggested-by:
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Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
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---
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include/linux/hw_bitfield.h | 62 ++++++++++
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1 file changed, 62 insertions(+)
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diff --git a/include/linux/hw_bitfield.h b/include/linux/hw_bitfield.h
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new file mode 100644
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index 000000000000..111111111111
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--- /dev/null
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+++ b/include/linux/hw_bitfield.h
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@@ -0,0 +1,62 @@
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+/* SPDX-License-Identifier: GPL-2.0-or-later */
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+/*
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+ * Copyright (C) 2025, Collabora Ltd.
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+ */
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+
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+#ifndef _LINUX_HW_BITFIELD_H
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+#define _LINUX_HW_BITFIELD_H
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+
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+#include <linux/bitfield.h>
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+#include <linux/build_bug.h>
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+#include <linux/limits.h>
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+
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+/**
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+ * FIELD_PREP_WM16() - prepare a bitfield element with a mask in the upper half
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+ * @_mask: shifted mask defining the field's length and position
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+ * @_val: value to put in the field
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+ *
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+ * FIELD_PREP_WM16() masks and shifts up the value, as well as bitwise ORs the
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+ * result with the mask shifted up by 16.
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+ *
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+ * This is useful for a common design of hardware registers where the upper
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+ * 16-bit half of a 32-bit register is used as a write-enable mask. In such a
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+ * register, a bit in the lower half is only updated if the corresponding bit
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+ * in the upper half is high.
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+ */
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+#define FIELD_PREP_WM16(_mask, _val) \
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+ ({ \
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+ typeof(_val) __val = _val; \
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+ typeof(_mask) __mask = _mask; \
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+ __BF_FIELD_CHECK(__mask, ((u16)0U), __val, \
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+ "HWORD_UPDATE: "); \
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+ (((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) | \
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+ ((__mask) << 16); \
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+ })
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+
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+/**
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+ * FIELD_PREP_WM16_CONST() - prepare a constant bitfield element with a mask in
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+ * the upper half
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+ * @_mask: shifted mask defining the field's length and position
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+ * @_val: value to put in the field
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+ *
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+ * FIELD_PREP_WM16_CONST() masks and shifts up the value, as well as bitwise ORs
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+ * the result with the mask shifted up by 16.
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+ *
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+ * This is useful for a common design of hardware registers where the upper
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+ * 16-bit half of a 32-bit register is used as a write-enable mask. In such a
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+ * register, a bit in the lower half is only updated if the corresponding bit
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+ * in the upper half is high.
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+ *
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+ * Unlike FIELD_PREP_WM16(), this is a constant expression and can therefore
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+ * be used in initializers. Error checking is less comfortable for this
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+ * version.
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+ */
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+#define FIELD_PREP_WM16_CONST(_mask, _val) \
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+ ( \
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+ FIELD_PREP_CONST(_mask, _val) | \
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+ (BUILD_BUG_ON_ZERO(const_true((u64)(_mask) > U16_MAX)) + \
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+ ((_mask) << 16)) \
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+ )
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+
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+
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+#endif /* _LINUX_HW_BITFIELD_H */
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--
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Armbian
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Detlev Casanova <detlev.casanova@collabora.com>
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Date: Thu, 26 Jun 2025 08:53:07 -0400
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