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Fix compilation errors on mvebu current / dev

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Fixed by reverting https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/drivers/gpio?h=v5.10.12&id=43f2e6077f441d681f0337ab91f7c4c2d4c62761 which needs closer examination when time permits.
This commit is contained in:
Igor Pecovnik 2021-01-30 19:17:25 +01:00
parent de89592d84
commit 0829882144
29 changed files with 133 additions and 10150 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

110
config/kernel/linux-mvebu-current.config
View File

@ -1,6 +1,6 @@
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm 5.10.6 Kernel Configuration
# Linux/arm 5.10.12 Kernel Configuration
#
CONFIG_CC_VERSION_TEXT="arm-linux-gnueabihf-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0"
CONFIG_CC_IS_GCC=y
@ -113,6 +113,8 @@ CONFIG_RCU_EXPERT=y
CONFIG_SRCU=y
CONFIG_TREE_SRCU=y
CONFIG_TASKS_RCU_GENERIC=y
CONFIG_TASKS_RCU=y
CONFIG_TASKS_RUDE_RCU=y
CONFIG_TASKS_TRACE_RCU=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RCU_NEED_SEGCBLIST=y
@ -1383,7 +1385,7 @@ CONFIG_NET_DSA_TAG_EDSA=m
CONFIG_NET_DSA_TAG_MTK=m
CONFIG_NET_DSA_TAG_KSZ=m
CONFIG_NET_DSA_TAG_RTL4_A=m
# CONFIG_NET_DSA_TAG_OCELOT is not set
CONFIG_NET_DSA_TAG_OCELOT=m
CONFIG_NET_DSA_TAG_QCA=m
CONFIG_NET_DSA_TAG_LAN9303=m
CONFIG_NET_DSA_TAG_SJA1105=m
@ -1551,7 +1553,9 @@ CONFIG_NET_NSH=m
CONFIG_HSR=m
CONFIG_NET_SWITCHDEV=y
CONFIG_NET_L3_MASTER_DEV=y
# CONFIG_QRTR is not set
CONFIG_QRTR=m
CONFIG_QRTR_TUN=m
CONFIG_QRTR_MHI=m
CONFIG_NET_NCSI=y
CONFIG_NCSI_OEM_CMD_GET_MAC=y
CONFIG_RPS=y
@ -1600,7 +1604,7 @@ CONFIG_CAN_RAW=m
CONFIG_CAN_BCM=m
CONFIG_CAN_GW=m
CONFIG_CAN_J1939=m
# CONFIG_CAN_ISOTP is not set
CONFIG_CAN_ISOTP=m
#
# CAN Device Drivers
@ -1643,7 +1647,8 @@ CONFIG_CAN_SOFTING=m
#
CONFIG_CAN_HI311X=m
CONFIG_CAN_MCP251X=m
# CONFIG_CAN_MCP251XFD is not set
CONFIG_CAN_MCP251XFD=m
# CONFIG_CAN_MCP251XFD_SANITY is not set
# end of CAN SPI interfaces
#
@ -1950,6 +1955,7 @@ CONFIG_REGMAP_SPI=m
CONFIG_REGMAP_W1=m
CONFIG_REGMAP_MMIO=y
CONFIG_REGMAP_IRQ=y
CONFIG_REGMAP_SPI_AVMM=m
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DMA_FENCE_TRACE is not set
CONFIG_GENERIC_ARCH_TOPOLOGY=y
@ -1964,7 +1970,8 @@ CONFIG_ARM_CCI=y
CONFIG_MVEBU_MBUS=y
CONFIG_SIMPLE_PM_BUS=y
# CONFIG_VEXPRESS_CONFIG is not set
# CONFIG_MHI_BUS is not set
CONFIG_MHI_BUS=m
# CONFIG_MHI_BUS_DEBUG is not set
# end of Bus devices
# CONFIG_CONNECTOR is not set
@ -2180,7 +2187,7 @@ CONFIG_SRAM_EXEC=y
# CONFIG_XILINX_SDFEC is not set
CONFIG_MISC_RTSX=m
CONFIG_PVPANIC=m
# CONFIG_HISI_HIKEY_USB is not set
CONFIG_HISI_HIKEY_USB=m
# CONFIG_C2PORT is not set
#
@ -2531,7 +2538,7 @@ CONFIG_NET_DSA_MV88E6060=m
CONFIG_NET_DSA_MV88E6XXX=m
CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y
# CONFIG_NET_DSA_MV88E6XXX_PTP is not set
# CONFIG_NET_DSA_MSCC_SEVILLE is not set
CONFIG_NET_DSA_MSCC_SEVILLE=m
# CONFIG_NET_DSA_AR9331 is not set
CONFIG_NET_DSA_SJA1105=m
# CONFIG_NET_DSA_SJA1105_PTP is not set
@ -2589,11 +2596,13 @@ CONFIG_MVNETA_BM=y
CONFIG_MVPP2=y
# CONFIG_SKGE is not set
# CONFIG_SKY2 is not set
# CONFIG_PRESTERA is not set
CONFIG_PRESTERA=m
CONFIG_PRESTERA_PCI=m
# CONFIG_NET_VENDOR_MELLANOX is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MICROCHIP is not set
CONFIG_NET_VENDOR_MICROSEMI=y
CONFIG_MSCC_OCELOT_SWITCH_LIB=m
# CONFIG_MSCC_OCELOT_SWITCH is not set
# CONFIG_NET_VENDOR_MYRI is not set
# CONFIG_FEALNX is not set
@ -2717,7 +2726,8 @@ CONFIG_MDIO_I2C=m
#
# PCS device drivers
#
# CONFIG_PCS_XPCS is not set
CONFIG_PCS_XPCS=m
CONFIG_PCS_LYNX=m
# end of PCS device drivers
CONFIG_PLIP=m
@ -2824,7 +2834,10 @@ CONFIG_ATH10K_USB=m
# CONFIG_ATH10K_DEBUG is not set
# CONFIG_ATH10K_DEBUGFS is not set
# CONFIG_WCN36XX is not set
# CONFIG_ATH11K is not set
CONFIG_ATH11K=m
CONFIG_ATH11K_PCI=m
# CONFIG_ATH11K_DEBUG is not set
# CONFIG_ATH11K_DEBUGFS is not set
# CONFIG_WLAN_VENDOR_ATMEL is not set
CONFIG_WLAN_VENDOR_BROADCOM=y
CONFIG_B43=m
@ -3135,7 +3148,7 @@ CONFIG_MOUSE_PS2_SMBUS=y
CONFIG_INPUT_JOYSTICK=y
# CONFIG_JOYSTICK_ANALOG is not set
# CONFIG_JOYSTICK_A3D is not set
# CONFIG_JOYSTICK_ADC is not set
CONFIG_JOYSTICK_ADC=m
# CONFIG_JOYSTICK_ADI is not set
# CONFIG_JOYSTICK_COBRA is not set
# CONFIG_JOYSTICK_GF2K is not set
@ -3155,15 +3168,15 @@ CONFIG_JOYSTICK_IFORCE_USB=m
# CONFIG_JOYSTICK_STINGER is not set
# CONFIG_JOYSTICK_TWIDJOY is not set
# CONFIG_JOYSTICK_ZHENHUA is not set
# CONFIG_JOYSTICK_DB9 is not set
CONFIG_JOYSTICK_DB9=m
# CONFIG_JOYSTICK_GAMECON is not set
# CONFIG_JOYSTICK_TURBOGRAFX is not set
CONFIG_JOYSTICK_TURBOGRAFX=m
# CONFIG_JOYSTICK_AS5011 is not set
# CONFIG_JOYSTICK_JOYDUMP is not set
CONFIG_JOYSTICK_XPAD=m
CONFIG_JOYSTICK_XPAD_FF=y
CONFIG_JOYSTICK_XPAD_LEDS=y
# CONFIG_JOYSTICK_WALKERA0701 is not set
CONFIG_JOYSTICK_WALKERA0701=m
# CONFIG_JOYSTICK_PSXPAD_SPI is not set
# CONFIG_JOYSTICK_PXRC is not set
# CONFIG_JOYSTICK_FSIA6B is not set
@ -3291,7 +3304,7 @@ CONFIG_HW_RANDOM=m
CONFIG_HW_RANDOM_VIRTIO=m
CONFIG_HW_RANDOM_OPTEE=m
# CONFIG_HW_RANDOM_CCTRNG is not set
# CONFIG_HW_RANDOM_XIPHERA is not set
CONFIG_HW_RANDOM_XIPHERA=m
# CONFIG_APPLICOM is not set
CONFIG_DEVMEM=y
CONFIG_DEVKMEM=y
@ -3667,7 +3680,7 @@ CONFIG_CHARGER_BQ24257=m
CONFIG_CHARGER_BQ24735=m
# CONFIG_CHARGER_BQ2515X is not set
CONFIG_CHARGER_BQ25890=m
# CONFIG_CHARGER_BQ25980 is not set
CONFIG_CHARGER_BQ25980=m
CONFIG_CHARGER_SMB347=m
CONFIG_BATTERY_GAUGE_LTC2941=m
CONFIG_CHARGER_RT9455=m
@ -3747,7 +3760,7 @@ CONFIG_SENSORS_MAX6697=m
CONFIG_SENSORS_MAX31790=m
CONFIG_SENSORS_MCP3021=m
CONFIG_SENSORS_TC654=m
# CONFIG_SENSORS_MR75203 is not set
CONFIG_SENSORS_MR75203=m
CONFIG_SENSORS_ADCXX=m
CONFIG_SENSORS_LM63=m
CONFIG_SENSORS_LM70=m
@ -3778,7 +3791,7 @@ CONFIG_SENSORS_OCC=m
CONFIG_SENSORS_PCF8591=m
CONFIG_PMBUS=m
CONFIG_SENSORS_PMBUS=m
# CONFIG_SENSORS_ADM1266 is not set
CONFIG_SENSORS_ADM1266=m
CONFIG_SENSORS_ADM1275=m
# CONFIG_SENSORS_BEL_PFE is not set
CONFIG_SENSORS_IBM_CFFPS=m
@ -3797,7 +3810,7 @@ CONFIG_SENSORS_MAX20751=m
CONFIG_SENSORS_MAX31785=m
CONFIG_SENSORS_MAX34440=m
CONFIG_SENSORS_MAX8688=m
# CONFIG_SENSORS_MP2975 is not set
CONFIG_SENSORS_MP2975=m
CONFIG_SENSORS_PXE1610=m
CONFIG_SENSORS_TPS40422=m
CONFIG_SENSORS_TPS53679=m
@ -3851,6 +3864,7 @@ CONFIG_SENSORS_W83773G=m
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
CONFIG_SENSORS_INTEL_M10_BMC_HWMON=m
CONFIG_THERMAL=y
# CONFIG_THERMAL_NETLINK is not set
# CONFIG_THERMAL_STATISTICS is not set
@ -4055,7 +4069,7 @@ CONFIG_MFD_ROHM_BD718XX=m
CONFIG_MFD_STPMIC1=m
CONFIG_MFD_STMFX=m
# CONFIG_RAVE_SP_CORE is not set
# CONFIG_MFD_INTEL_M10_BMC is not set
CONFIG_MFD_INTEL_M10_BMC=m
# end of Multifunction device drivers
CONFIG_REGULATOR=y
@ -4099,10 +4113,10 @@ CONFIG_REGULATOR_MCP16502=m
# CONFIG_REGULATOR_PV88080 is not set
# CONFIG_REGULATOR_PV88090 is not set
# CONFIG_REGULATOR_PWM is not set
# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m
CONFIG_REGULATOR_ROHM=m
# CONFIG_REGULATOR_RT4801 is not set
# CONFIG_REGULATOR_RTMV20 is not set
CONFIG_REGULATOR_RT4801=m
CONFIG_REGULATOR_RTMV20=m
# CONFIG_REGULATOR_SLG51000 is not set
CONFIG_REGULATOR_STPMIC1=m
# CONFIG_REGULATOR_SY8106A is not set
@ -4602,7 +4616,7 @@ CONFIG_LCD_LMS501KF03=m
CONFIG_LCD_HX8357=m
CONFIG_LCD_OTM3225A=m
CONFIG_BACKLIGHT_CLASS_DEVICE=m
# CONFIG_BACKLIGHT_KTD253 is not set
CONFIG_BACKLIGHT_KTD253=m
CONFIG_BACKLIGHT_PWM=m
# CONFIG_BACKLIGHT_QCOM_WLED is not set
CONFIG_BACKLIGHT_ADP8860=m
@ -4720,7 +4734,7 @@ CONFIG_HID_MACALLY=m
# CONFIG_HID_GFRM is not set
# CONFIG_HID_GLORIOUS is not set
# CONFIG_HID_HOLTEK is not set
# CONFIG_HID_VIVALDI is not set
CONFIG_HID_VIVALDI=m
# CONFIG_HID_GT683R is not set
# CONFIG_HID_KEYTOUCH is not set
# CONFIG_HID_KYE is not set
@ -5080,7 +5094,7 @@ CONFIG_LEDS_LM3692X=m
CONFIG_LEDS_GPIO=y
# CONFIG_LEDS_LP3944 is not set
# CONFIG_LEDS_LP3952 is not set
# CONFIG_LEDS_LP50XX is not set
CONFIG_LEDS_LP50XX=m
# CONFIG_LEDS_LP55XX_COMMON is not set
# CONFIG_LEDS_LP8860 is not set
# CONFIG_LEDS_PCA955X is not set
@ -5189,7 +5203,7 @@ CONFIG_RTC_DRV_S35390A=y
# CONFIG_RTC_DRV_RX8025 is not set
# CONFIG_RTC_DRV_EM3027 is not set
CONFIG_RTC_DRV_RV3028=m
# CONFIG_RTC_DRV_RV3032 is not set
CONFIG_RTC_DRV_RV3032=m
# CONFIG_RTC_DRV_RV8803 is not set
CONFIG_RTC_DRV_SD3078=m
@ -5531,6 +5545,7 @@ CONFIG_SOC_BRCMSTB=y
#
# Qualcomm SoC drivers
#
CONFIG_QCOM_QMI_HELPERS=m
# end of Qualcomm SoC drivers
# CONFIG_SOC_TI is not set
@ -5561,8 +5576,8 @@ CONFIG_MVEBU_DEVBUS=y
CONFIG_IIO=m
CONFIG_IIO_BUFFER=y
CONFIG_IIO_BUFFER_CB=m
# CONFIG_IIO_BUFFER_DMA is not set
# CONFIG_IIO_BUFFER_DMAENGINE is not set
CONFIG_IIO_BUFFER_DMA=m
CONFIG_IIO_BUFFER_DMAENGINE=m
# CONFIG_IIO_BUFFER_HW_CONSUMER is not set
CONFIG_IIO_KFIFO_BUF=m
CONFIG_IIO_TRIGGERED_BUFFER=m
@ -5798,7 +5813,7 @@ CONFIG_ADF4371=m
# CONFIG_ADIS16130 is not set
# CONFIG_ADIS16136 is not set
# CONFIG_ADIS16260 is not set
# CONFIG_ADXRS290 is not set
CONFIG_ADXRS290=m
# CONFIG_ADXRS450 is not set
# CONFIG_BMG160 is not set
# CONFIG_FXAS21002C is not set
@ -5827,7 +5842,7 @@ CONFIG_MAX30102=m
CONFIG_AM2315=m
CONFIG_DHT11=m
CONFIG_HDC100X=m
# CONFIG_HDC2010 is not set
CONFIG_HDC2010=m
CONFIG_HTS221=m
CONFIG_HTS221_I2C=m
CONFIG_HTS221_SPI=m
@ -5867,7 +5882,7 @@ CONFIG_ADJD_S311=m
CONFIG_AL3320A=m
CONFIG_APDS9300=m
CONFIG_APDS9960=m
# CONFIG_AS73211 is not set
CONFIG_AS73211=m
CONFIG_BH1750=m
CONFIG_BH1780=m
CONFIG_CM32181=m
@ -6068,7 +6083,7 @@ CONFIG_ORION_IRQCHIP=y
#
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PHY_MIPI_DPHY=y
# CONFIG_USB_LGM_PHY is not set
CONFIG_USB_LGM_PHY=m
# CONFIG_BCM_KONA_USB2_PHY is not set
# CONFIG_PHY_CADENCE_TORRENT is not set
# CONFIG_PHY_CADENCE_DPHY is not set
@ -6163,7 +6178,7 @@ CONFIG_FTM_QUADDEC=m
# CONFIG_MICROCHIP_TCB_CAPTURE is not set
CONFIG_MOST=m
# CONFIG_MOST_USB_HDM is not set
# CONFIG_MOST_CDEV is not set
CONFIG_MOST_CDEV=m
# end of Device Drivers
#
@ -6406,6 +6421,24 @@ CONFIG_EROFS_FS_XATTR=y
CONFIG_EROFS_FS_POSIX_ACL=y
CONFIG_EROFS_FS_SECURITY=y
# CONFIG_EROFS_FS_ZIP is not set
CONFIG_AUFS_FS=m
CONFIG_AUFS_BRANCH_MAX_127=y
# CONFIG_AUFS_BRANCH_MAX_511 is not set
# CONFIG_AUFS_BRANCH_MAX_1023 is not set
# CONFIG_AUFS_BRANCH_MAX_32767 is not set
CONFIG_AUFS_SBILIST=y
# CONFIG_AUFS_HNOTIFY is not set
# CONFIG_AUFS_EXPORT is not set
# CONFIG_AUFS_XATTR is not set
# CONFIG_AUFS_FHSM is not set
# CONFIG_AUFS_RDU is not set
# CONFIG_AUFS_DIRREN is not set
# CONFIG_AUFS_SHWH is not set
# CONFIG_AUFS_BR_RAMFS is not set
# CONFIG_AUFS_BR_FUSE is not set
CONFIG_AUFS_BR_HFSPLUS=y
CONFIG_AUFS_BDEV_LOOP=y
# CONFIG_AUFS_DEBUG is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=m
CONFIG_NFS_V2=m
@ -6663,7 +6696,7 @@ CONFIG_CRYPTO_DH=y
CONFIG_CRYPTO_ECC=m
CONFIG_CRYPTO_ECDH=m
CONFIG_CRYPTO_ECRDSA=m
# CONFIG_CRYPTO_SM2 is not set
CONFIG_CRYPTO_SM2=m
# CONFIG_CRYPTO_CURVE25519 is not set
#
@ -7071,7 +7104,7 @@ CONFIG_LOCK_DEBUGGING_SUPPORT=y
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
# CONFIG_LOCK_TORTURE_TEST is not set
# CONFIG_WW_MUTEX_SELFTEST is not set
# CONFIG_SCF_TORTURE_TEST is not set
CONFIG_SCF_TORTURE_TEST=m
# end of Lock Debugging (spinlocks, mutexes, etc...)
# CONFIG_STACKTRACE is not set
@ -7093,7 +7126,8 @@ CONFIG_LOCK_DEBUGGING_SUPPORT=y
#
# RCU Debugging
#
# CONFIG_RCU_SCALE_TEST is not set
CONFIG_TORTURE_TEST=m
CONFIG_RCU_SCALE_TEST=m
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_REF_SCALE_TEST is not set
CONFIG_RCU_CPU_STALL_TIMEOUT=21

7237
config/kernel/linux-mvebu-dev.config
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File diff suppressed because it is too large Load Diff

1
config/kernel/linux-mvebu-dev.config Symbolic link
View File

@ -0,0 +1 @@
linux-mvebu-current.config

59
patch/kernel/mvebu-current/0001-Revert-gpio-mvebu-fix-pwm-.get_state-period-calculat.patch Normal file
View File

@ -0,0 +1,59 @@
From 0ef9299ef1afce1dbf847e75cdd16e2343d89bf9 Mon Sep 17 00:00:00 2001
From: Igor Pecovnik <igor.pecovnik@gmail.com>
Date: Sat, 30 Jan 2021 19:06:41 +0100
Subject: [PATCH] Revert "gpio: mvebu: fix pwm .get_state period calculation"
This reverts commit 43f2e6077f441d681f0337ab91f7c4c2d4c62761.
---
drivers/gpio/gpio-mvebu.c | 25 +++++++++++++++----------
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index ed7c5fc47f52..2f245594a90a 100644
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -660,8 +660,9 @@ static void mvebu_pwm_get_state(struct pwm_chip *chip,
spin_lock_irqsave(&mvpwm->lock, flags);
- u = readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
- val = (unsigned long long) u * NSEC_PER_SEC;
+ val = (unsigned long long)
+ readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
+ val *= NSEC_PER_SEC;
do_div(val, mvpwm->clk_rate);
if (val > UINT_MAX)
state->duty_cycle = UINT_MAX;
@@ -670,17 +671,21 @@ static void mvebu_pwm_get_state(struct pwm_chip *chip,
else
state->duty_cycle = 1;
- val = (unsigned long long) u; /* on duration */
- /* period = on + off duration */
- val += readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
+ val = (unsigned long long)
+ readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
val *= NSEC_PER_SEC;
do_div(val, mvpwm->clk_rate);
- if (val > UINT_MAX)
- state->period = UINT_MAX;
- else if (val)
- state->period = val;
- else
+ if (val < state->duty_cycle) {
state->period = 1;
+ } else {
+ val -= state->duty_cycle;
+ if (val > UINT_MAX)
+ state->period = UINT_MAX;
+ else if (val)
+ state->period = val;
+ else
+ state->period = 1;
+ }
regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u);
if (u)
--
2.25.1

1
patch/kernel/mvebu-dev Symbolic link
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@ -0,0 +1 @@
mvebu-current

43
patch/kernel/mvebu-dev/0001-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch
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@ -1,43 +0,0 @@
From: Russell King <rmk+kernel@arm.linux.org.uk>
Subject: [PATCH 01/30] cpuidle: mvebu: indicate failure to enter deeper sleep
states
MIME-Version: 1.0
Content-Disposition: inline
Content-Transfer-Encoding: 8bit
Content-Type: text/plain; charset="utf-8"
The cpuidle ->enter method expects the return value to be the sleep
state we entered. Returning negative numbers or other codes is not
permissible since coupled CPU idle was merged.
At least some of the mvebu_v7_cpu_suspend() implementations return the
value from cpu_suspend(), which returns zero if the CPU vectors back
into the kernel via cpu_resume() (the success case), or the non-zero
return value of the suspend actor, or one (failure cases).
We do not want to be returning the failure case value back to CPU idle
as that indicates that we successfully entered one of the deeper idle
states. Always return zero instead, indicating that we slept for the
shortest amount of time.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
drivers/cpuidle/cpuidle-mvebu-v7.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
--- a/drivers/cpuidle/cpuidle-mvebu-v7.c
+++ b/drivers/cpuidle/cpuidle-mvebu-v7.c
@@ -39,8 +39,12 @@ static int mvebu_v7_enter_idle(struct cp
ret = mvebu_v7_cpu_suspend(deepidle);
cpu_pm_exit();
+ /*
+ * If we failed to enter the desired state, indicate that we
+ * slept lightly.
+ */
if (ret)
- return ret;
+ return 0;
return index;
}

398
patch/kernel/mvebu-dev/10-mvebu-clearfog-pcie-updates.patch
View File

@ -1,398 +0,0 @@
From 527312a74d9d85ba9520c8cb2979004f6d23c4da Mon Sep 17 00:00:00 2001
From: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Tue, 29 Nov 2016 10:13:46 +0000
Subject: [PATCH] mvebu/clearfog pcie updates
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
drivers/pci/controller/pci-mvebu.c | 112 ++++++++++++++++++++++++++++-
drivers/pci/pci-bridge-emul.c | 83 ++++++++++++---------
drivers/pci/pci-bridge-emul.h | 15 ++++
drivers/pci/pcie/aspm.c | 6 ++
drivers/pci/pcie/portdrv_core.c | 2 +
5 files changed, 184 insertions(+), 34 deletions(-)
--- a/drivers/pci/controller/pci-mvebu.c
+++ b/drivers/pci/controller/pci-mvebu.c
@@ -52,7 +52,14 @@
PCIE_CONF_ADDR_EN)
#define PCIE_CONF_DATA_OFF 0x18fc
#define PCIE_MASK_OFF 0x1910
+#define PCIE_MASK_PM_PME BIT(28)
#define PCIE_MASK_ENABLE_INTS 0x0f000000
+#define PCIE_MASK_ERR_COR BIT(18)
+#define PCIE_MASK_ERR_NONFATAL BIT(17)
+#define PCIE_MASK_ERR_FATAL BIT(16)
+#define PCIE_MASK_FERR_DET BIT(10)
+#define PCIE_MASK_NFERR_DET BIT(9)
+#define PCIE_MASK_CORERR_DET BIT(8)
#define PCIE_CTRL_OFF 0x1a00
#define PCIE_CTRL_X1_MODE 0x0001
#define PCIE_STAT_OFF 0x1a04
@@ -430,6 +437,54 @@ static void mvebu_pcie_handle_membase_ch
&port->memwin);
}
+static void mvebu_pcie_handle_irq_change(struct mvebu_pcie_port *port)
+{
+ u32 reg, old;
+ u16 devctl, rtctl;
+
+ /*
+ * Errors from downstream devices:
+ * bridge control register SERR: enables reception of errors
+ * Errors from this device, or received errors:
+ * command SERR: enables ERR_NONFATAL and ERR_FATAL messages
+ * => when enabled, these conditions also flag SERR in status register
+ * devctl CERE: enables ERR_CORR messages
+ * devctl NFERE: enables ERR_NONFATAL messages
+ * devctl FERE: enables ERR_FATAL messages
+ * Enabled messages then have three paths:
+ * 1. rtctl: enables system error indication
+ * 2. root error status register updated
+ * 3. root error command register: forwarding via MSI
+ */
+ old = mvebu_readl(port, PCIE_MASK_OFF);
+ reg = old & ~(PCIE_MASK_PM_PME | PCIE_MASK_FERR_DET |
+ PCIE_MASK_NFERR_DET | PCIE_MASK_CORERR_DET |
+ PCIE_MASK_ERR_COR | PCIE_MASK_ERR_NONFATAL |
+ PCIE_MASK_ERR_FATAL);
+
+ devctl = port->bridge.pcie_conf.devctl;
+ if (devctl & PCI_EXP_DEVCTL_FERE)
+ reg |= PCIE_MASK_FERR_DET | PCIE_MASK_ERR_FATAL;
+ if (devctl & PCI_EXP_DEVCTL_NFERE)
+ reg |= PCIE_MASK_NFERR_DET | PCIE_MASK_ERR_NONFATAL;
+ if (devctl & PCI_EXP_DEVCTL_CERE)
+ reg |= PCIE_MASK_CORERR_DET | PCIE_MASK_ERR_COR;
+ if (port->bridge.conf.command & PCI_COMMAND_SERR)
+ reg |= PCIE_MASK_FERR_DET | PCIE_MASK_NFERR_DET |
+ PCIE_MASK_ERR_FATAL | PCIE_MASK_ERR_NONFATAL;
+
+ if (!(port->bridge.conf.bridgectrl & PCI_BRIDGE_CTL_SERR))
+ reg &= ~(PCIE_MASK_ERR_COR | PCIE_MASK_ERR_NONFATAL |
+ PCIE_MASK_ERR_FATAL);
+
+ rtctl = port->bridge.pcie_conf.rootctl;
+ if (rtctl & PCI_EXP_RTCTL_PMEIE)
+ reg |= PCIE_MASK_PM_PME;
+
+ if (old != reg)
+ mvebu_writel(port, reg, PCIE_MASK_OFF);
+}
+
static pci_bridge_emul_read_status_t
mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
int reg, u32 *value)
@@ -475,6 +530,30 @@ mvebu_pci_bridge_emul_pcie_conf_read(str
return PCI_BRIDGE_EMUL_HANDLED;
}
+static pci_bridge_emul_read_status_t
+mvebu_pci_bridge_emul_pcie_ext_read(struct pci_bridge_emul *bridge,
+ int reg, u32 *value)
+{
+ struct mvebu_pcie_port *port = bridge->data;
+
+ switch (reg) {
+ case 0x00 ... 0x28:
+ *value = mvebu_readl(port, 0x100 + (reg & ~3));
+ break;
+
+ case PCI_ERR_ROOT_COMMAND:
+ case PCI_ERR_ROOT_STATUS:
+ case PCI_ERR_ROOT_ERR_SRC:
+ *value = 0;
+ break;
+
+ default:
+ return PCI_BRIDGE_EMUL_NOT_HANDLED;
+ }
+
+ return PCI_BRIDGE_EMUL_HANDLED;
+}
+
static void
mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
int reg, u32 old, u32 new, u32 mask)
@@ -492,7 +571,8 @@ mvebu_pci_bridge_emul_base_conf_write(st
mvebu_pcie_handle_iobase_change(port);
if ((old ^ new) & PCI_COMMAND_MEMORY)
mvebu_pcie_handle_membase_change(port);
-
+ if ((old ^ new) & PCI_COMMAND_SERR)
+ mvebu_pcie_handle_irq_change(port);
break;
}
@@ -515,6 +595,11 @@ mvebu_pci_bridge_emul_base_conf_write(st
mvebu_pcie_handle_iobase_change(port);
break;
+ case PCI_INTERRUPT_LINE:
+ if (((old ^ new) >> 16) & PCI_BRIDGE_CTL_SERR)
+ mvebu_pcie_handle_irq_change(port);
+ break;
+
case PCI_PRIMARY_BUS:
mvebu_pcie_set_local_bus_nr(port, conf->secondary_bus);
break;
@@ -532,6 +617,10 @@ mvebu_pci_bridge_emul_pcie_conf_write(st
switch (reg) {
case PCI_EXP_DEVCTL:
+ if ((new ^ old) & (PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_NFERE |
+ PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_URRE))
+ mvebu_pcie_handle_irq_change(port);
+
/*
* Armada370 data says these bits must always
* be zero when in root complex mode.
@@ -557,6 +646,25 @@ mvebu_pci_bridge_emul_pcie_conf_write(st
case PCI_EXP_RTSTA:
mvebu_writel(port, new, PCIE_RC_RTSTA);
break;
+
+ case PCI_EXP_RTCTL:
+ if ((new ^ old) & (PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
+ PCI_EXP_RTCTL_SEFEE | PCI_EXP_RTCTL_PMEIE))
+ mvebu_pcie_handle_irq_change(port);
+ break;
+ }
+}
+
+static void
+mvebu_pci_bridge_emul_pcie_ext_write(struct pci_bridge_emul *bridge,
+ int reg, u32 old, u32 new, u32 mask)
+{
+ struct mvebu_pcie_port *port = bridge->data;
+
+ switch (reg) {
+ case 0x00 ... 0x28:
+ mvebu_writel(port, new, 0x100 + (reg & ~3));
+ break;
}
}
@@ -564,6 +672,8 @@ static struct pci_bridge_emul_ops mvebu_
.write_base = mvebu_pci_bridge_emul_base_conf_write,
.read_pcie = mvebu_pci_bridge_emul_pcie_conf_read,
.write_pcie = mvebu_pci_bridge_emul_pcie_conf_write,
+ .read_ext = mvebu_pci_bridge_emul_pcie_ext_read,
+ .write_ext = mvebu_pci_bridge_emul_pcie_ext_write,
};
/*
--- a/drivers/pci/pci-bridge-emul.c
+++ b/drivers/pci/pci-bridge-emul.c
@@ -151,6 +151,7 @@ static const struct pci_bridge_reg_behav
.rw = (GENMASK(7, 0) |
((PCI_BRIDGE_CTL_PARITY |
PCI_BRIDGE_CTL_SERR |
+ /* NOTE: PCIe does not allow ISA, VGA, MASTER_ABORT */
PCI_BRIDGE_CTL_ISA |
PCI_BRIDGE_CTL_VGA |
PCI_BRIDGE_CTL_MASTER_ABORT |
@@ -264,6 +265,7 @@ int pci_bridge_emul_init(struct pci_brid
bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE;
bridge->conf.cache_line_size = 0x10;
bridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST);
+ bridge->conf.bridgectrl = cpu_to_le16(PCI_BRIDGE_CTL_SERR);
bridge->pci_regs_behavior = kmemdup(pci_regs_behavior,
sizeof(pci_regs_behavior),
GFP_KERNEL);
@@ -323,25 +325,26 @@ int pci_bridge_emul_conf_read(struct pci
__le32 *cfgspace;
const struct pci_bridge_reg_behavior *behavior;
- if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) {
- *value = 0;
- return PCIBIOS_SUCCESSFUL;
- }
-
- if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) {
+ if (reg < PCI_CAP_PCIE_START) {
+ read_op = bridge->ops->read_base;
+ cfgspace = (__le32 *) &bridge->conf;
+ behavior = bridge->pci_regs_behavior;
+ } else if (!bridge->has_pcie) {
*value = 0;
return PCIBIOS_SUCCESSFUL;
- }
-
- if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
+ } else if (reg < PCI_CAP_PCIE_END) {
reg -= PCI_CAP_PCIE_START;
read_op = bridge->ops->read_pcie;
cfgspace = (__le32 *) &bridge->pcie_conf;
behavior = bridge->pcie_cap_regs_behavior;
+ } else if (reg < 0x100) {
+ *value = 0;
+ return PCIBIOS_SUCCESSFUL;
} else {
- read_op = bridge->ops->read_base;
- cfgspace = (__le32 *) &bridge->conf;
- behavior = bridge->pci_regs_behavior;
+ reg -= 0x100;
+ read_op = bridge->ops->read_ext;
+ cfgspace = NULL;
+ behavior = NULL;
}
if (read_op)
@@ -349,15 +352,20 @@ int pci_bridge_emul_conf_read(struct pci
else
ret = PCI_BRIDGE_EMUL_NOT_HANDLED;
- if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED)
- *value = le32_to_cpu(cfgspace[reg / 4]);
+ if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED) {
+ if (cfgspace)
+ *value = le32_to_cpu(cfgspace[reg / 4]);
+ else
+ *value = 0;
+ }
/*
* Make sure we never return any reserved bit with a value
* different from 0.
*/
- *value &= behavior[reg / 4].ro | behavior[reg / 4].rw |
- behavior[reg / 4].w1c;
+ if (behavior)
+ *value &= behavior[reg / 4].ro | behavior[reg / 4].rw |
+ behavior[reg / 4].w1c;
if (size == 1)
*value = (*value >> (8 * (where & 3))) & 0xff;
@@ -385,12 +393,6 @@ int pci_bridge_emul_conf_write(struct pc
__le32 *cfgspace;
const struct pci_bridge_reg_behavior *behavior;
- if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END)
- return PCIBIOS_SUCCESSFUL;
-
- if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END)
- return PCIBIOS_SUCCESSFUL;
-
shift = (where & 0x3) * 8;
if (size == 4)
@@ -406,27 +408,42 @@ int pci_bridge_emul_conf_write(struct pc
if (ret != PCIBIOS_SUCCESSFUL)
return ret;
- if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
+ if (reg < PCI_CAP_PCIE_START) {
+ write_op = bridge->ops->write_base;
+ cfgspace = (__le32 *) &bridge->conf;
+ behavior = bridge->pci_regs_behavior;
+ } else if (!bridge->has_pcie) {
+ return PCIBIOS_SUCCESSFUL;
+ } else if (reg < PCI_CAP_PCIE_END) {
reg -= PCI_CAP_PCIE_START;
write_op = bridge->ops->write_pcie;
cfgspace = (__le32 *) &bridge->pcie_conf;
behavior = bridge->pcie_cap_regs_behavior;
+ } else if (reg < 0x100) {
+ return PCIBIOS_SUCCESSFUL;
} else {
- write_op = bridge->ops->write_base;
- cfgspace = (__le32 *) &bridge->conf;
- behavior = bridge->pci_regs_behavior;
+ reg -= 0x100;
+ write_op = bridge->ops->write_ext;
+ cfgspace = NULL;
+ behavior = NULL;
}
- /* Keep all bits, except the RW bits */
- new = old & (~mask | ~behavior[reg / 4].rw);
+ if (behavior) {
+ /* Keep all bits, except the RW bits */
+ new = old & (~mask | ~behavior[reg / 4].rw);
- /* Update the value of the RW bits */
- new |= (value << shift) & (behavior[reg / 4].rw & mask);
+ /* Update the value of the RW bits */
+ new |= (value << shift) & (behavior[reg / 4].rw & mask);
- /* Clear the W1C bits */
- new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
+ /* Clear the W1C bits */
+ new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
+ } else {
+ new = old & ~mask;
+ new |= (value << shift) & mask;
+ }
- cfgspace[reg / 4] = cpu_to_le32(new);
+ if (cfgspace)
+ cfgspace[reg / 4] = cpu_to_le32(new);
if (write_op)
write_op(bridge, reg, old, new, mask);
--- a/drivers/pci/pci-bridge-emul.h
+++ b/drivers/pci/pci-bridge-emul.h
@@ -90,6 +90,14 @@ struct pci_bridge_emul_ops {
*/
pci_bridge_emul_read_status_t (*read_pcie)(struct pci_bridge_emul *bridge,
int reg, u32 *value);
+
+ /*
+ * Same as ->read_base(), except it is for reading from the
+ * PCIe extended capability configuration space.
+ */
+ pci_bridge_emul_read_status_t (*read_ext)(struct pci_bridge_emul *bridge,
+ int reg, u32 *value);
+
/*
* Called when writing to the regular PCI bridge configuration
* space. old is the current value, new is the new value being
@@ -105,6 +113,13 @@ struct pci_bridge_emul_ops {
*/
void (*write_pcie)(struct pci_bridge_emul *bridge, int reg,
u32 old, u32 new, u32 mask);
+
+ /*
+ * Same as ->write_base(), except it is for writing from the
+ * PCIe extended capability configuration space.
+ */
+ void (*write_ext)(struct pci_bridge_emul *bridge, int reg,
+ u32 old, u32 new, u32 mask);
};
struct pci_bridge_reg_behavior;
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -578,6 +578,12 @@ static void pcie_aspm_cap_init(struct pc
pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap);
pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl);
pcie_capability_read_word(child, PCI_EXP_LNKCTL, &child_lnkctl);
+dev_info(&parent->dev, "up support %x enabled %x\n",
+ (parent_lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10,
+ !!(parent_lnkctl & PCI_EXP_LNKCTL_ASPMC));
+dev_info(&parent->dev, "dn support %x enabled %x\n",
+ (child_lnkcap & PCI_EXP_LNKCAP_ASPMS) >> 10,
+ !!(child_lnkctl & PCI_EXP_LNKCTL_ASPMC));
/*
* Setup L0s state
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -325,6 +325,7 @@ int pcie_port_device_register(struct pci
/* Get and check PCI Express port services */
capabilities = get_port_device_capability(dev);
+dev_info(&dev->dev, "PCIe capabilities: 0x%x\n", capabilities);
if (!capabilities)
return 0;
@@ -337,6 +338,7 @@ int pcie_port_device_register(struct pci
* if that is to be used.
*/
status = pcie_init_service_irqs(dev, irqs, capabilities);
+dev_info(&dev->dev, "init_service_irqs: %d\n", status);
if (status) {
capabilities &= PCIE_PORT_SERVICE_HP;
if (!capabilities)

55
patch/kernel/mvebu-dev/11-implement-slot-capabilities-SSPL.patch
View File

@ -1,55 +0,0 @@
From 2298f59cecc69b0fc6471c5fd3f7629af2d274b2 Mon Sep 17 00:00:00 2001
From: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Tue, 29 Nov 2016 10:13:48 +0000
Subject: [PATCH] implement slot capabilities (SSPL)
---
drivers/pci/controller/pci-mvebu.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
--- a/drivers/pci/controller/pci-mvebu.c
+++ b/drivers/pci/controller/pci-mvebu.c
@@ -66,6 +66,12 @@
#define PCIE_STAT_BUS 0xff00
#define PCIE_STAT_DEV 0x1f0000
#define PCIE_STAT_LINK_DOWN BIT(0)
+#define PCIE_SSPL 0x1a0c
+#define PCIE_SSPL_MSGEN BIT(14)
+#define PCIE_SSPL_SPLS(x) (((x) & 3) << 8)
+#define PCIE_SSPL_SPLS_VAL(x) (((x) >> 8) & 3)
+#define PCIE_SSPL_SPLV(x) ((x) & 0xff)
+#define PCIE_SSPL_SPLV_VAL(x) ((x) & 0xff)
#define PCIE_RC_RTSTA 0x1a14
#define PCIE_DEBUG_CTRL 0x1a60
#define PCIE_DEBUG_SOFT_RESET BIT(20)
@@ -515,6 +521,14 @@ mvebu_pci_bridge_emul_pcie_conf_read(str
*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
break;
+ case PCI_EXP_SLTCAP:
+ {
+ u32 tmp = mvebu_readl(port, PCIE_SSPL);
+ *value = PCIE_SSPL_SPLS_VAL(tmp) << 15 |
+ PCIE_SSPL_SPLV_VAL(tmp) << 7;
+ break;
+ }
+
case PCI_EXP_SLTCTL:
*value = PCI_EXP_SLTSTA_PDS << 16;
break;
@@ -643,6 +657,15 @@ mvebu_pci_bridge_emul_pcie_conf_write(st
mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
break;
+ case PCI_EXP_SLTCAP:
+ {
+ u32 sspl = PCIE_SSPL_SPLV((new & PCI_EXP_SLTCAP_SPLV) >> 7) |
+ PCIE_SSPL_SPLS((new & PCI_EXP_SLTCAP_SPLS) >> 15) |
+ PCIE_SSPL_MSGEN;
+ mvebu_writel(port, sspl, PCIE_SSPL);
+ break;
+ }
+
case PCI_EXP_RTSTA:
mvebu_writel(port, new, PCIE_RC_RTSTA);
break;

432
patch/kernel/mvebu-dev/402-sfp-display-SFP-module-information.patch
View File

@ -1,432 +0,0 @@
From 88e942a0b703fe54dad925f27f033869e4f10fba Mon Sep 17 00:00:00 2001
From: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Sun, 13 Sep 2015 01:06:31 +0100
Subject: [PATCH] net: sfp: display SFP module information [*not for
mainline*]
Display SFP module information verbosely, splitting the generic parts
into a separate file.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
drivers/net/phy/Makefile | 2 +-
drivers/net/phy/sff.c | 114 ++++++++++++++++++++
drivers/net/phy/sff.h | 16 +++
drivers/net/phy/sfp.c | 228 +++++++++++++++++++++++++++++++++++++--
4 files changed, 349 insertions(+), 11 deletions(-)
create mode 100644 drivers/net/phy/sff.c
create mode 100644 drivers/net/phy/sff.h
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -26,7 +26,7 @@ obj-$(CONFIG_PHYLIB) += libphy.o
obj-$(CONFIG_NETWORK_PHY_TIMESTAMPING) += mii_timestamper.o
-obj-$(CONFIG_SFP) += sfp.o
+obj-$(CONFIG_SFP) += sff.o sfp.o
sfp-obj-$(CONFIG_SFP) += sfp-bus.o
obj-y += $(sfp-obj-y) $(sfp-obj-m)
--- /dev/null
+++ b/drivers/net/phy/sff.c
@@ -0,0 +1,114 @@
+#include <linux/kernel.h>
+#include <linux/sfp.h>
+#include "sff.h"
+
+const char *sff_link_len(char *buf, size_t size, unsigned int length,
+ unsigned int multiplier)
+{
+ if (length == 0)
+ return "unsupported/unspecified";
+
+ if (length == 255) {
+ *buf++ = '>';
+ size -= 1;
+ length -= 1;
+ }
+
+ length *= multiplier;
+
+ if (length >= 1000)
+ snprintf(buf, size, "%u.%0*ukm",
+ length / 1000,
+ multiplier > 100 ? 1 :
+ multiplier > 10 ? 2 : 3,
+ length % 1000);
+ else
+ snprintf(buf, size, "%um", length);
+
+ return buf;
+}
+EXPORT_SYMBOL_GPL(sff_link_len);
+
+const char *sff_bitfield(char *buf, size_t size,
+ const struct sff_bitfield *bits, unsigned int val)
+{
+ char *p = buf;
+ int n;
+
+ *p = '\0';
+ while (bits->mask) {
+ if ((val & bits->mask) == bits->val) {
+ n = snprintf(p, size, "%s%s",
+ buf != p ? ", " : "",
+ bits->str);
+ if (n == size)
+ break;
+ p += n;
+ size -= n;
+ }
+ bits++;
+ }
+
+ return buf;
+}
+EXPORT_SYMBOL_GPL(sff_bitfield);
+
+const char *sff_connector(unsigned int connector)
+{
+ switch (connector) {
+ case SFF8024_CONNECTOR_UNSPEC:
+ return "unknown/unspecified";
+ case SFF8024_CONNECTOR_SC:
+ return "SC";
+ case SFF8024_CONNECTOR_FIBERJACK:
+ return "Fiberjack";
+ case SFF8024_CONNECTOR_LC:
+ return "LC";
+ case SFF8024_CONNECTOR_MT_RJ:
+ return "MT-RJ";
+ case SFF8024_CONNECTOR_MU:
+ return "MU";
+ case SFF8024_CONNECTOR_SG:
+ return "SG";
+ case SFF8024_CONNECTOR_OPTICAL_PIGTAIL:
+ return "Optical pigtail";
+ case SFF8024_CONNECTOR_MPO_1X12:
+ return "MPO 1X12";
+ case SFF8024_CONNECTOR_MPO_2X16:
+ return "MPO 2X16";
+ case SFF8024_CONNECTOR_HSSDC_II:
+ return "HSSDC II";
+ case SFF8024_CONNECTOR_COPPER_PIGTAIL:
+ return "Copper pigtail";
+ case SFF8024_CONNECTOR_RJ45:
+ return "RJ45";
+ case SFF8024_CONNECTOR_MXC_2X16:
+ return "MXC 2X16";
+ default:
+ return "unknown";
+ }
+}
+EXPORT_SYMBOL_GPL(sff_connector);
+
+const char *sff_encoding(unsigned int encoding)
+{
+ switch (encoding) {
+ case SFF8024_ENCODING_UNSPEC:
+ return "unspecified";
+ case SFF8024_ENCODING_8472_64B66B:
+ return "64b66b";
+ case SFF8024_ENCODING_8B10B:
+ return "8b10b";
+ case SFF8024_ENCODING_4B5B:
+ return "4b5b";
+ case SFF8024_ENCODING_NRZ:
+ return "NRZ";
+ case SFF8024_ENCODING_8472_MANCHESTER:
+ return "MANCHESTER";
+ default:
+ return "unknown";
+ }
+}
+EXPORT_SYMBOL_GPL(sff_encoding);
+
+MODULE_LICENSE("GPL");
--- /dev/null
+++ b/drivers/net/phy/sff.h
@@ -0,0 +1,16 @@
+#ifndef SFF_H
+#define SFF_H
+
+struct sff_bitfield {
+ unsigned int mask;
+ unsigned int val;
+ const char *str;
+};
+
+const char *sff_link_len(char *buf, size_t size, unsigned int length,
+ unsigned int multiplier);
+const char *sff_bitfield(char *buf, size_t size,
+ const struct sff_bitfield *bits, unsigned int val);
+const char *sff_connector(unsigned int connector);
+const char *sff_encoding(unsigned int encoding);
+#endif
--- a/drivers/net/phy/sfp.c
+++ b/drivers/net/phy/sfp.c
@@ -17,6 +17,7 @@
#include <linux/slab.h>
#include <linux/workqueue.h>
+#include "sff.h"
#include "sfp.h"
#include "swphy.h"
@@ -1363,6 +1364,114 @@ static void sfp_hwmon_exit(struct sfp *s
}
#endif
+static const struct sff_bitfield sfp_options[] = {
+ {
+ .mask = SFP_OPTIONS_HIGH_POWER_LEVEL,
+ .val = SFP_OPTIONS_HIGH_POWER_LEVEL,
+ .str = "hpl",
+ }, {
+ .mask = SFP_OPTIONS_PAGING_A2,
+ .val = SFP_OPTIONS_PAGING_A2,
+ .str = "paginga2",
+ }, {
+ .mask = SFP_OPTIONS_RETIMER,
+ .val = SFP_OPTIONS_RETIMER,
+ .str = "retimer",
+ }, {
+ .mask = SFP_OPTIONS_COOLED_XCVR,
+ .val = SFP_OPTIONS_COOLED_XCVR,
+ .str = "cooled",
+ }, {
+ .mask = SFP_OPTIONS_POWER_DECL,
+ .val = SFP_OPTIONS_POWER_DECL,
+ .str = "powerdecl",
+ }, {
+ .mask = SFP_OPTIONS_RX_LINEAR_OUT,
+ .val = SFP_OPTIONS_RX_LINEAR_OUT,
+ .str = "rxlinear",
+ }, {
+ .mask = SFP_OPTIONS_RX_DECISION_THRESH,
+ .val = SFP_OPTIONS_RX_DECISION_THRESH,
+ .str = "rxthresh",
+ }, {
+ .mask = SFP_OPTIONS_TUNABLE_TX,
+ .val = SFP_OPTIONS_TUNABLE_TX,
+ .str = "tunabletx",
+ }, {
+ .mask = SFP_OPTIONS_RATE_SELECT,
+ .val = SFP_OPTIONS_RATE_SELECT,
+ .str = "ratesel",
+ }, {
+ .mask = SFP_OPTIONS_TX_DISABLE,
+ .val = SFP_OPTIONS_TX_DISABLE,
+ .str = "txdisable",
+ }, {
+ .mask = SFP_OPTIONS_TX_FAULT,
+ .val = SFP_OPTIONS_TX_FAULT,
+ .str = "txfault",
+ }, {
+ .mask = SFP_OPTIONS_LOS_INVERTED,
+ .val = SFP_OPTIONS_LOS_INVERTED,
+ .str = "los-",
+ }, {
+ .mask = SFP_OPTIONS_LOS_NORMAL,
+ .val = SFP_OPTIONS_LOS_NORMAL,
+ .str = "los+",
+ }, { }
+};
+
+static const struct sff_bitfield diagmon[] = {
+ {
+ .mask = SFP_DIAGMON_DDM,
+ .val = SFP_DIAGMON_DDM,
+ .str = "ddm",
+ }, {
+ .mask = SFP_DIAGMON_INT_CAL,
+ .val = SFP_DIAGMON_INT_CAL,
+ .str = "intcal",
+ }, {
+ .mask = SFP_DIAGMON_EXT_CAL,
+ .val = SFP_DIAGMON_EXT_CAL,
+ .str = "extcal",
+ }, {
+ .mask = SFP_DIAGMON_RXPWR_AVG,
+ .val = SFP_DIAGMON_RXPWR_AVG,
+ .str = "rxpwravg",
+ }, { }
+};
+
+static const struct sff_bitfield sfp_enhopts[] = {
+ {
+ .mask = SFP_ENHOPTS_ALARMWARN,
+ .val = SFP_ENHOPTS_ALARMWARN,
+ .str = "alarmwarn",
+ }, {
+ .mask = SFP_ENHOPTS_SOFT_TX_DISABLE,
+ .val = SFP_ENHOPTS_SOFT_TX_DISABLE,
+ .str = "soft_tx_dis",
+ }, {
+ .mask = SFP_ENHOPTS_SOFT_TX_FAULT,
+ .val = SFP_ENHOPTS_SOFT_TX_FAULT,
+ .str = "soft_tx_fault",
+ }, {
+ .mask = SFP_ENHOPTS_SOFT_RX_LOS,
+ .val = SFP_ENHOPTS_SOFT_RX_LOS,
+ .str = "soft_rx_los",
+ }, {
+ .mask = SFP_ENHOPTS_SOFT_RATE_SELECT,
+ .val = SFP_ENHOPTS_SOFT_RATE_SELECT,
+ .str = "soft_rs",
+ }, {
+ .mask = SFP_ENHOPTS_APP_SELECT_SFF8079,
+ .val = SFP_ENHOPTS_APP_SELECT_SFF8079,
+ .str = "app_sel",
+ }, {
+ .mask = SFP_ENHOPTS_SOFT_RATE_SFF8431,
+ .val = SFP_ENHOPTS_SOFT_RATE_SFF8431,
+ .str = "soft_r8431",
+ }, { }
+};
+
/* Helpers */
static void sfp_module_tx_disable(struct sfp *sfp)
{
@@ -1664,6 +1773,110 @@ static int sfp_cotsworks_fixup_check(str
return 0;
}
+static void sfp_print_module_info(struct sfp *sfp, const struct sfp_eeprom_id *id, bool cotsworks)
+{
+ unsigned int br_nom, br_min, br_max;
+ char date[9];
+ char options[80];
+
+ /* Cotsworks also gets the date code wrong. */
+ date[0] = id->ext.datecode[4 - 2 * cotsworks];
+ date[1] = id->ext.datecode[5 - 2 * cotsworks];
+ date[2] = '-';
+ date[3] = id->ext.datecode[2 + 2 * cotsworks];
+ date[4] = id->ext.datecode[3 + 2 * cotsworks];
+ date[5] = '-';
+ date[6] = id->ext.datecode[0];
+ date[7] = id->ext.datecode[1];
+ date[8] = '\0';
+
+ if (id->base.br_nominal == 0) {
+ br_min = br_nom = br_max = 0;
+ } else if (id->base.br_nominal == 255) {
+ br_nom = 250 * id->ext.br_max;
+ br_max = br_nom + br_nom * id->ext.br_min / 100;
+ br_min = br_nom - br_nom * id->ext.br_min / 100;
+ } else {
+ br_nom = id->base.br_nominal * 100;
+ br_min = br_nom - id->base.br_nominal * id->ext.br_min;
+ br_max = br_nom + id->base.br_nominal * id->ext.br_max;
+ }
+
+ dev_info(sfp->dev, "module %.*s %.*s rev %.*s sn %.*s dc %s\n",
+ (int)sizeof(id->base.vendor_name), id->base.vendor_name,
+ (int)sizeof(id->base.vendor_pn), id->base.vendor_pn,
+ (int)sizeof(id->base.vendor_rev), id->base.vendor_rev,
+ (int)sizeof(id->ext.vendor_sn), id->ext.vendor_sn, date);
+ dev_info(sfp->dev, " %s connector, encoding %s, bitrate %u.%03u (%u.%03u-%u.%03u) Gbps\n",
+ sff_connector(id->base.connector),
+ sff_encoding(id->base.encoding),
+ br_nom / 1000, br_nom % 1000,
+ br_min / 1000, br_min % 1000, br_max / 1000, br_max % 1000);
+ dev_info(sfp->dev, " 1000BaseSX%c 1000BaseLX%c 1000BaseCX%c 1000BaseT%c 100BaseLX%c 100BaseFX%c BaseBX10%c BasePX%c\n",
+ id->base.e1000_base_sx ? '+' : '-',
+ id->base.e1000_base_lx ? '+' : '-',
+ id->base.e1000_base_cx ? '+' : '-',
+ id->base.e1000_base_t ? '+' : '-',
+ id->base.e100_base_lx ? '+' : '-',
+ id->base.e100_base_fx ? '+' : '-',
+ id->base.e_base_bx10 ? '+' : '-',
+ id->base.e_base_px ? '+' : '-');
+ dev_info(sfp->dev, " 10GBaseSR%c 10GBaseLR%c 10GBaseLRM%c 10GBaseER%c\n",
+ id->base.e10g_base_sr ? '+' : '-',
+ id->base.e10g_base_lr ? '+' : '-',
+ id->base.e10g_base_lrm ? '+' : '-',
+ id->base.e10g_base_er ? '+' : '-');
+
+ if (!id->base.sfp_ct_passive && !id->base.sfp_ct_active &&
+ !id->base.e1000_base_t) {
+ char len_9um[16], len_om[16];
+
+ dev_info(sfp->dev, " Wavelength %unm, fiber lengths:\n",
+ be16_to_cpup(&id->base.optical_wavelength));
+
+ if (id->base.link_len[0] == 255)
+ strcpy(len_9um, ">254km");
+ else if (id->base.link_len[1] && id->base.link_len[1] != 255)
+ sprintf(len_9um, "%um",
+ id->base.link_len[1] * 100);
+ else if (id->base.link_len[0])
+ sprintf(len_9um, "%ukm", id->base.link_len[0]);
+ else if (id->base.link_len[1] == 255)
+ strcpy(len_9um, ">25.4km");
+ else
+ strcpy(len_9um, "unsupported");
+
+ dev_info(sfp->dev, " 9µm SM : %s\n", len_9um);
+ dev_info(sfp->dev, " 62.5µm MM OM1: %s\n",
+ sff_link_len(len_om, sizeof(len_om),
+ id->base.link_len[3], 10));
+ dev_info(sfp->dev, " 50µm MM OM2: %s\n",
+ sff_link_len(len_om, sizeof(len_om),
+ id->base.link_len[2], 10));
+ dev_info(sfp->dev, " 50µm MM OM3: %s\n",
+ sff_link_len(len_om, sizeof(len_om),
+ id->base.link_len[5], 10));
+ dev_info(sfp->dev, " 50µm MM OM4: %s\n",
+ sff_link_len(len_om, sizeof(len_om),
+ id->base.link_len[4], 10));
+ } else {
+ char len[16];
+ dev_info(sfp->dev, " Copper length: %s\n",
+ sff_link_len(len, sizeof(len),
+ id->base.link_len[4], 1));
+ }
+
+ dev_info(sfp->dev, " Options: %s\n",
+ sff_bitfield(options, sizeof(options), sfp_options,
+ be16_to_cpu(id->ext.options)));
+ dev_info(sfp->dev, " Diagnostics: %s\n",
+ sff_bitfield(options, sizeof(options), diagmon,
+ id->ext.diagmon));
+ dev_info(sfp->dev, " EnhOpts: %s\n",
+ sff_bitfield(options, sizeof(options), sfp_enhopts,
+ id->ext.enhopts));
+}
+
static int sfp_sm_mod_probe(struct sfp *sfp, bool report)
{
/* SFP module inserted - read I2C data */
@@ -1685,9 +1898,9 @@ static int sfp_sm_mod_probe(struct sfp *
return -EAGAIN;
}
- /* Cotsworks do not seem to update the checksums when they
- * do the final programming with the final module part number,
- * serial number and date code.
+ /* Cotsworks do not seem to update the checksums when they update the
+ * module part number, serial number and date code. They also format
+ * the date code incorrectly.
*/
cotsworks = !memcmp(id.base.vendor_name, "COTSWORKS ", 16);
cotsworks_sfbg = !memcmp(id.base.vendor_pn, "SFBG", 4);
@@ -1735,14 +1948,9 @@ static int sfp_sm_mod_probe(struct sfp *
}
}
- sfp->id = id;
+ sfp_print_module_info(sfp, &id, cotsworks);
- dev_info(sfp->dev, "module %.*s %.*s rev %.*s sn %.*s dc %.*s\n",
- (int)sizeof(id.base.vendor_name), id.base.vendor_name,
- (int)sizeof(id.base.vendor_pn), id.base.vendor_pn,
- (int)sizeof(id.base.vendor_rev), id.base.vendor_rev,
- (int)sizeof(id.ext.vendor_sn), id.ext.vendor_sn,
- (int)sizeof(id.ext.datecode), id.ext.datecode);
+ sfp->id = id;
/* Check whether we support this module */
if (!sfp->type->module_supported(&id)) {

87
patch/kernel/mvebu-dev/412-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch
View File

@ -1,87 +0,0 @@
From 8137da20701c776ad3481115305a5e8e410871ba Mon Sep 17 00:00:00 2001
From: Russell King <rmk+kernel@armlinux.org.uk>
Date: Tue, 29 Nov 2016 10:15:45 +0000
Subject: ARM: dts: armada388-clearfog: emmc on clearfog base
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
arch/arm/boot/dts/armada-388-clearfog-base.dts | 1 +
.../dts/armada-38x-solidrun-microsom-emmc.dtsi | 62 ++++++++++++++++++++++
2 files changed, 63 insertions(+)
create mode 100644 arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi
--- a/arch/arm/boot/dts/armada-388-clearfog-base.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "armada-388-clearfog.dtsi"
+#include "armada-38x-solidrun-microsom-emmc.dtsi"
/ {
model = "SolidRun Clearfog Base A1";
--- /dev/null
+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi
@@ -0,0 +1,62 @@
+/*
+ * Device Tree file for SolidRun Armada 38x Microsom add-on for eMMC
+ *
+ * Copyright (C) 2015 Russell King
+ *
+ * This board is in development; the contents of this file work with
+ * the A1 rev 2.0 of the board, which does not represent final
+ * production board. Things will change, don't expect this file to
+ * remain compatible info the future.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/ {
+ soc {
+ internal-regs {
+ sdhci@d8000 {
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+ pinctrl-0 = <&microsom_sdhci_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ wp-inverted;
+ };
+ };
+ };
+};

149
patch/kernel/mvebu-dev/91-01-libata-add-ledtrig-support.patch
View File

@ -1,149 +0,0 @@
From: Daniel Golle <daniel@makrotopia.org>
Subject: libata: add ledtrig support
This adds a LED trigger for each ATA port indicating disk activity.
As this is needed only on specific platforms (NAS SoCs and such),
these platforms should define ARCH_WANTS_LIBATA_LEDS if there
are boards with LED(s) intended to indicate ATA disk activity and
need the OS to take care of that.
In that way, if not selected, LED trigger support not will be
included in libata-core and both, codepaths and structures remain
untouched.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/ata/Kconfig | 16 ++++++++++++++++
drivers/ata/libata-core.c | 41 +++++++++++++++++++++++++++++++++++++++++
include/linux/libata.h | 9 +++++++++
3 files changed, 66 insertions(+)
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -67,6 +67,22 @@ config ATA_FORCE
If unsure, say Y.
+config ARCH_WANT_LIBATA_LEDS
+ bool
+
+config ATA_LEDS
+ bool "support ATA port LED triggers"
+ depends on ARCH_WANT_LIBATA_LEDS
+ select NEW_LEDS
+ select LEDS_CLASS
+ select LEDS_TRIGGERS
+ default y
+ help
+ This option adds a LED trigger for each registered ATA port.
+ It is used to drive disk activity leds connected via GPIO.
+
+ If unsure, say N.
+
config ATA_ACPI
bool "ATA ACPI Support"
depends on ACPI
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -650,6 +650,19 @@ u64 ata_tf_read_block(const struct ata_t
return block;
}
+#ifdef CONFIG_ATA_LEDS
+#define LIBATA_BLINK_DELAY 20 /* ms */
+static inline void ata_led_act(struct ata_port *ap)
+{
+ unsigned long led_delay = LIBATA_BLINK_DELAY;
+
+ if (unlikely(!ap->ledtrig))
+ return;
+
+ led_trigger_blink_oneshot(ap->ledtrig, &led_delay, &led_delay, 0);
+}
+#endif
+
/**
* ata_build_rw_tf - Build ATA taskfile for given read/write request
* @tf: Target ATA taskfile
@@ -4513,6 +4526,9 @@ struct ata_queued_cmd *ata_qc_new_init(s
if (tag < 0)
return NULL;
}
+#ifdef CONFIG_ATA_LEDS
+ ata_led_act(ap);
+#endif
qc = __ata_qc_from_tag(ap, tag);
qc->tag = qc->hw_tag = tag;
@@ -5291,6 +5307,9 @@ struct ata_port *ata_port_alloc(struct a
ap->stats.unhandled_irq = 1;
ap->stats.idle_irq = 1;
#endif
+#ifdef CONFIG_ATA_LEDS
+ ap->ledtrig = kzalloc(sizeof(struct led_trigger), GFP_KERNEL);
+#endif
ata_sff_port_init(ap);
return ap;
@@ -5326,6 +5345,12 @@ static void ata_host_release(struct kref
kfree(ap->pmp_link);
kfree(ap->slave_link);
+#ifdef CONFIG_ATA_LEDS
+ if (ap->ledtrig) {
+ led_trigger_unregister(ap->ledtrig);
+ kfree(ap->ledtrig);
+ };
+#endif
kfree(ap);
host->ports[i] = NULL;
}
@@ -5732,7 +5757,23 @@ int ata_host_register(struct ata_host *h
host->ports[i]->print_id = atomic_inc_return(&ata_print_id);
host->ports[i]->local_port_no = i + 1;
}
+#ifdef CONFIG_ATA_LEDS
+ for (i = 0; i < host->n_ports; i++) {
+ if (unlikely(!host->ports[i]->ledtrig))
+ continue;
+ snprintf(host->ports[i]->ledtrig_name,
+ sizeof(host->ports[i]->ledtrig_name), "ata%u",
+ host->ports[i]->print_id);
+
+ host->ports[i]->ledtrig->name = host->ports[i]->ledtrig_name;
+
+ if (led_trigger_register(host->ports[i]->ledtrig)) {
+ kfree(host->ports[i]->ledtrig);
+ host->ports[i]->ledtrig = NULL;
+ }
+ }
+#endif
/* Create associated sysfs transport objects */
for (i = 0; i < host->n_ports; i++) {
rc = ata_tport_add(host->dev,host->ports[i]);
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -23,6 +23,9 @@
#include <linux/cdrom.h>
#include <linux/sched.h>
#include <linux/async.h>
+#ifdef CONFIG_ATA_LEDS
+#include <linux/leds.h>
+#endif
/*
* Define if arch has non-standard setup. This is a _PCI_ standard
@@ -882,6 +885,12 @@ struct ata_port {
#ifdef CONFIG_ATA_ACPI
struct ata_acpi_gtm __acpi_init_gtm; /* use ata_acpi_init_gtm() */
#endif
+
+#ifdef CONFIG_ATA_LEDS
+ struct led_trigger *ledtrig;
+ char ledtrig_name[8];
+#endif
+
/* owned by EH */
u8 sector_buf[ATA_SECT_SIZE] ____cacheline_aligned;
};

30
patch/kernel/mvebu-dev/91-02-Enable-ATA-port-LED-trigger.patch
View File

@ -1,30 +0,0 @@
From 9ee6345ef82f7af5f98e17a40e667f8ad6b2fa1b Mon Sep 17 00:00:00 2001
From: aprayoga <adit.prayoga@gmail.com>
Date: Sun, 3 Sep 2017 18:10:12 +0800
Subject: Enable ATA port LED trigger
---
arch/arm/configs/mvebu_v7_defconfig | 1 +
arch/arm/mach-mvebu/Kconfig | 1 +
2 files changed, 2 insertions(+)
--- a/arch/arm/configs/mvebu_v7_defconfig
+++ b/arch/arm/configs/mvebu_v7_defconfig
@@ -58,6 +58,7 @@ CONFIG_MTD_UBI=y
CONFIG_EEPROM_AT24=y
CONFIG_BLK_DEV_SD=y
CONFIG_ATA=y
+CONFIG_ATA_LEDS=y
CONFIG_SATA_AHCI=y
CONFIG_AHCI_MVEBU=y
CONFIG_SATA_MV=y
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -56,6 +56,7 @@ config MACH_ARMADA_375
config MACH_ARMADA_38X
bool "Marvell Armada 380/385 boards"
depends on ARCH_MULTI_V7
+ select ARCH_WANT_LIBATA_LEDS
select ARM_ERRATA_720789
select PL310_ERRATA_753970
select ARM_GIC

88
patch/kernel/mvebu-dev/92-mvebu-gpio-add_wake_on_gpio_support.patch
View File

@ -1,88 +0,0 @@
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -40,6 +40,7 @@
#include <linux/gpio/consumer.h>
#include <linux/gpio/machine.h>
#include <linux/init.h>
+#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
@@ -111,7 +112,7 @@ struct mvebu_gpio_chip {
struct regmap *regs;
u32 offset;
struct regmap *percpu_regs;
- int irqbase;
+ int bank_irq[4];
struct irq_domain *domain;
int soc_variant;
@@ -601,6 +602,33 @@ static void mvebu_gpio_irq_handler(struc
}
/*
+ * Set interrupt number "irq" in the GPIO as a wake-up source.
+ * While system is running, all registered GPIO interrupts need to have
+ * wake-up enabled. When system is suspended, only selected GPIO interrupts
+ * need to have wake-up enabled.
+ * @param irq interrupt source number
+ * @param enable enable as wake-up if equal to non-zero
+ * @return This function returns 0 on success.
+ */
+static int mvebu_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
+{
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+ struct mvebu_gpio_chip *mvchip = gc->private;
+ int irq;
+ int bank;
+
+ bank = d->hwirq % 8;
+ irq = mvchip->bank_irq[bank];
+
+ if (enable)
+ enable_irq_wake(irq);
+ else
+ disable_irq_wake(irq);
+
+ return 0;
+}
+
+/*
* Functions implementing the pwm_chip methods
*/
static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip)
@@ -1219,7 +1247,7 @@ static int mvebu_gpio_probe(struct platf
err = irq_alloc_domain_generic_chips(
mvchip->domain, ngpios, 2, np->name, handle_level_irq,
- IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0);
+ IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, IRQ_GC_INIT_NESTED_LOCK);
if (err) {
dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n",
mvchip->chip.label);
@@ -1237,6 +1265,8 @@ static int mvebu_gpio_probe(struct platf
ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
+ ct->chip.irq_set_wake = mvebu_gpio_set_wake_irq;
+ ct->chip.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
ct->chip.name = mvchip->chip.label;
ct = &gc->chip_types[1];
@@ -1245,6 +1275,8 @@ static int mvebu_gpio_probe(struct platf
ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
+ ct->chip.irq_set_wake = mvebu_gpio_set_wake_irq;
+ ct->chip.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
ct->handler = handle_edge_irq;
ct->chip.name = mvchip->chip.label;
@@ -1260,6 +1292,7 @@ static int mvebu_gpio_probe(struct platf
continue;
irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler,
mvchip);
+ mvchip->bank_irq[i] = irq;
}
return 0;

123
patch/kernel/mvebu-dev/92-mvebu-gpio-remove-hardcoded-timer-assignment-2.patch
View File

@ -1,123 +0,0 @@
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -641,39 +641,81 @@ static int mvebu_pwm_request(struct pwm_
struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
struct gpio_desc *desc;
+ enum mvebu_pwm_ctrl id;
unsigned long flags;
int ret = 0;
+ struct mvebu_pwm_chip_drv *chip_data;
- spin_lock_irqsave(&mvpwm->lock, flags);
+ spin_lock_irqsave(&mvpwm->controller.lock, flags);
- if (mvpwm->gpiod) {
- ret = -EBUSY;
- } else {
- desc = gpiochip_request_own_desc(&mvchip->chip,
+ regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
+ &mvchip->blink_en_reg);
+
+ if (pwm->chip_data || (mvchip->blink_en_reg & BIT(pwm->hwpwm)))
+ return -EBUSY;
+
+ desc = gpiochip_request_own_desc(&mvchip->chip,
pwm->hwpwm, "mvebu-pwm",
GPIO_ACTIVE_HIGH,
GPIOD_OUT_LOW);
- if (IS_ERR(desc)) {
- ret = PTR_ERR(desc);
- goto out;
- }
+ if (IS_ERR(desc)) {
+ ret = PTR_ERR(desc);
+ goto out;
+ }
+
+ ret = gpiod_direction_output(desc, 0);
+ if (ret) {
+ gpiochip_free_own_desc(desc);
+ goto out;
+ }
- mvpwm->gpiod = desc;
+ chip_data = kzalloc(sizeof(struct mvebu_pwm_chip_drv), GFP_KERNEL);
+ if (!chip_data) {
+ gpiochip_free_own_desc(desc);
+ ret = -ENOMEM;
+ goto out;
}
+
+ for (id = MVEBU_PWM_CTRL_SET_A;id < MVEBU_PWM_CTRL_MAX; id++) {
+ if (!mvebu_pwm_list[id]->in_use) {
+ chip_data->ctrl = id;
+ chip_data->master = true;
+ mvebu_pwm_list[id]->in_use = true;
+ break;
+ }
+ }
+
+ if (!chip_data->master)
+ chip_data->ctrl = mvpwm->default_counter;
+
+ regmap_update_bits(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
+ BIT(pwm->hwpwm), chip_data->ctrl ? BIT(pwm->hwpwm) : 0);
+
+ chip_data->gpiod = desc;
+ pwm->chip_data = chip_data;
+
+ regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
+ &mvpwm->blink_select);
+
out:
- spin_unlock_irqrestore(&mvpwm->lock, flags);
+ spin_unlock_irqrestore(&mvpwm->controller.lock, flags);
return ret;
}
static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
+ struct mvebu_pwm_chip_drv *chip_data = (struct mvebu_pwm_chip_drv*) pwm->chip_data;
unsigned long flags;
- spin_lock_irqsave(&mvpwm->lock, flags);
- gpiochip_free_own_desc(mvpwm->gpiod);
- mvpwm->gpiod = NULL;
- spin_unlock_irqrestore(&mvpwm->lock, flags);
+ spin_lock_irqsave(&mvpwm->controller.lock, flags);
+ if (chip_data->master)
+ mvebu_pwm_list[chip_data->ctrl]->in_use = false;
+
+ gpiochip_free_own_desc(chip_data->gpiod);
+ kfree(chip_data);
+ pwm->chip_data = NULL;
+ spin_unlock_irqrestore(&mvpwm->controller.lock, flags);
}
static void mvebu_pwm_get_state(struct pwm_chip *chip,
@@ -721,19 +763,21 @@ static void mvebu_pwm_get_state(struct p
else
state->enabled = false;
- spin_unlock_irqrestore(&mvpwm->lock, flags);
+ spin_unlock_irqrestore(&controller->lock, flags);
}
static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
const struct pwm_state *state)
{
struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
+ struct mvebu_pwm_chip_drv *chip_data = (struct mvebu_pwm_chip_drv*) pwm->chip_data;
+ struct mvebu_pwmchip *controller = mvebu_pwm_list[chip_data->ctrl];
struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
unsigned long long val;
unsigned long flags;
unsigned int on, off;
- val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle;
+ val = (unsigned long long) controller->clk_rate * state->duty_cycle;
do_div(val, NSEC_PER_SEC);
if (val > UINT_MAX)
return -EINVAL;

223
patch/kernel/mvebu-dev/92-mvebu-gpio-remove-hardcoded-timer-assignment.patch
View File

@ -1,223 +0,0 @@
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -93,20 +93,41 @@
#define MVEBU_MAX_GPIO_PER_BANK 32
-struct mvebu_pwm {
+enum mvebu_pwm_ctrl {
+ MVEBU_PWM_CTRL_SET_A = 0,
+ MVEBU_PWM_CTRL_SET_B,
+ MVEBU_PWM_CTRL_MAX
+};
+
+struct mvebu_pwmchip {
void __iomem *membase;
unsigned long clk_rate;
+ spinlock_t lock;
+ bool in_use;
+
+ /* Used to preserve GPIO/PWM registers across suspend/resume */
+ u32 blink_on_duration;
+ u32 blink_off_duration;
+};
+
+struct mvebu_pwm_chip_drv {
+ enum mvebu_pwm_ctrl ctrl;
struct gpio_desc *gpiod;
+ bool master;
+};
+
+struct mvebu_pwm {
struct pwm_chip chip;
- spinlock_t lock;
struct mvebu_gpio_chip *mvchip;
+ struct mvebu_pwmchip controller;
+ enum mvebu_pwm_ctrl default_counter;
/* Used to preserve GPIO/PWM registers across suspend/resume */
u32 blink_select;
- u32 blink_on_duration;
- u32 blink_off_duration;
};
+static struct mvebu_pwmchip *mvebu_pwm_list[MVEBU_PWM_CTRL_MAX];
+
struct mvebu_gpio_chip {
struct gpio_chip chip;
struct regmap *regs;
@@ -283,12 +304,12 @@ mvebu_gpio_write_level_mask(struct mvebu
* Functions returning addresses of individual registers for a given
* PWM controller.
*/
-static void __iomem *mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm)
+static void __iomem *mvebu_pwmreg_blink_on_duration(struct mvebu_pwmchip *mvpwm)
{
return mvpwm->membase + PWM_BLINK_ON_DURATION_OFF;
}
-static void __iomem *mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm)
+static void __iomem *mvebu_pwmreg_blink_off_duration(struct mvebu_pwmchip *mvpwm)
{
return mvpwm->membase + PWM_BLINK_OFF_DURATION_OFF;
}
@@ -723,17 +744,24 @@ static void mvebu_pwm_get_state(struct p
struct pwm_state *state) {
struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
+ struct mvebu_pwm_chip_drv *chip_data = (struct mvebu_pwm_chip_drv*) pwm->chip_data;
+ struct mvebu_pwmchip *controller;
struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
unsigned long long val;
unsigned long flags;
u32 u;
- spin_lock_irqsave(&mvpwm->lock, flags);
+ if (chip_data)
+ controller = mvebu_pwm_list[chip_data->ctrl];
+ else
+ controller = &mvpwm->controller;
+
+ spin_lock_irqsave(&controller->lock, flags);
val = (unsigned long long)
- readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
+ readl_relaxed(mvebu_pwmreg_blink_on_duration(controller));
val *= NSEC_PER_SEC;
- do_div(val, mvpwm->clk_rate);
+ do_div(val, controller->clk_rate);
if (val > UINT_MAX)
state->duty_cycle = UINT_MAX;
else if (val)
@@ -742,9 +770,9 @@ static void mvebu_pwm_get_state(struct p
state->duty_cycle = 1;
val = (unsigned long long)
- readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
+ readl_relaxed(mvebu_pwmreg_blink_off_duration(controller));
val *= NSEC_PER_SEC;
- do_div(val, mvpwm->clk_rate);
+ do_div(val, controller->clk_rate);
if (val < state->duty_cycle) {
state->period = 1;
} else {
@@ -786,7 +814,7 @@ static int mvebu_pwm_apply(struct pwm_ch
else
on = 1;
- val = (unsigned long long) mvpwm->clk_rate *
+ val = (unsigned long long) controller->clk_rate *
(state->period - state->duty_cycle);
do_div(val, NSEC_PER_SEC);
if (val > UINT_MAX)
@@ -796,16 +824,16 @@ static int mvebu_pwm_apply(struct pwm_ch
else
off = 1;
- spin_lock_irqsave(&mvpwm->lock, flags);
+ spin_lock_irqsave(&controller->lock, flags);
- writel_relaxed(on, mvebu_pwmreg_blink_on_duration(mvpwm));
- writel_relaxed(off, mvebu_pwmreg_blink_off_duration(mvpwm));
+ writel_relaxed(on, mvebu_pwmreg_blink_on_duration(controller));
+ writel_relaxed(off, mvebu_pwmreg_blink_off_duration(controller));
if (state->enabled)
mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1);
else
mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0);
- spin_unlock_irqrestore(&mvpwm->lock, flags);
+ spin_unlock_irqrestore(&controller->lock, flags);
return 0;
}
@@ -824,10 +852,10 @@ static void __maybe_unused mvebu_pwm_sus
regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
&mvpwm->blink_select);
- mvpwm->blink_on_duration =
- readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm));
- mvpwm->blink_off_duration =
- readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm));
+ mvpwm->controller.blink_on_duration =
+ readl_relaxed(mvebu_pwmreg_blink_on_duration(&mvpwm->controller));
+ mvpwm->controller.blink_off_duration =
+ readl_relaxed(mvebu_pwmreg_blink_off_duration(&mvpwm->controller));
}
static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip)
@@ -836,10 +864,10 @@ static void __maybe_unused mvebu_pwm_res
regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
mvpwm->blink_select);
- writel_relaxed(mvpwm->blink_on_duration,
- mvebu_pwmreg_blink_on_duration(mvpwm));
- writel_relaxed(mvpwm->blink_off_duration,
- mvebu_pwmreg_blink_off_duration(mvpwm));
+ writel_relaxed(mvpwm->controller.blink_on_duration,
+ mvebu_pwmreg_blink_on_duration(&mvpwm->controller));
+ writel_relaxed(mvpwm->controller.blink_off_duration,
+ mvebu_pwmreg_blink_off_duration(&mvpwm->controller));
}
static int mvebu_pwm_probe(struct platform_device *pdev,
@@ -849,6 +877,7 @@ static int mvebu_pwm_probe(struct platfo
struct device *dev = &pdev->dev;
struct mvebu_pwm *mvpwm;
u32 set;
+ enum mvebu_pwm_ctrl ctrl_set;
if (!of_device_is_compatible(mvchip->chip.of_node,
"marvell,armada-370-gpio"))
@@ -870,12 +899,15 @@ static int mvebu_pwm_probe(struct platfo
* Use set A for lines of GPIO chip with id 0, B for GPIO chip
* with id 1. Don't allow further GPIO chips to be used for PWM.
*/
- if (id == 0)
+ if (id == 0) {
set = 0;
- else if (id == 1)
+ ctrl_set = MVEBU_PWM_CTRL_SET_A;
+ } else if (id == 1) {
set = U32_MAX;
- else
+ ctrl_set = MVEBU_PWM_CTRL_SET_B;
+ } else {
return -EINVAL;
+ }
regmap_write(mvchip->regs,
GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set);
@@ -885,15 +917,13 @@ static int mvebu_pwm_probe(struct platfo
mvchip->mvpwm = mvpwm;
mvpwm->mvchip = mvchip;
- mvpwm->membase = devm_platform_ioremap_resource_byname(pdev, "pwm");
- if (IS_ERR(mvpwm->membase))
- return PTR_ERR(mvpwm->membase);
-
- mvpwm->clk_rate = clk_get_rate(mvchip->clk);
- if (!mvpwm->clk_rate) {
- dev_err(dev, "failed to get clock rate\n");
+ mvpwm->controller.membase = devm_platform_ioremap_resource_byname(pdev, "pwm");
+ if (IS_ERR(mvpwm->controller.membase))
+ return PTR_ERR(mvpwm->controller.membase);
+
+ mvpwm->controller.clk_rate = clk_get_rate(mvchip->clk);
+ if (!mvpwm->controller.clk_rate)
return -EINVAL;
- }
mvpwm->chip.dev = dev;
mvpwm->chip.ops = &mvebu_pwm_ops;
@@ -906,7 +936,9 @@ static int mvebu_pwm_probe(struct platfo
*/
mvpwm->chip.base = -1;
- spin_lock_init(&mvpwm->lock);
+ spin_lock_init(&mvpwm->controller.lock);
+ mvpwm->default_counter = ctrl_set;
+ mvebu_pwm_list[ctrl_set] = &mvpwm->controller;
return pwmchip_add(&mvpwm->chip);
}

21
patch/kernel/mvebu-dev/94-helios4-dts-add-wake-on-lan-support.patch
View File

@ -1,21 +0,0 @@
--- a/arch/arm/boot/dts/armada-388-helios4.dts
+++ b/arch/arm/boot/dts/armada-388-helios4.dts
@@ -84,6 +84,18 @@
};
};
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&microsom_phy0_int_pins>;
+
+ wol {
+ label = "Wake-On-LAN";
+ linux,code = <KEY_WAKEUP>;
+ gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+ };
+
io-leds {
compatible = "gpio-leds";
sata1-led {

67
patch/kernel/mvebu-dev/95-helios4-dts-assign-pinctrl-to-fan-and-led.patch
View File

@ -1,67 +0,0 @@
--- a/arch/arm/boot/dts/armada-388-helios4.dts
+++ b/arch/arm/boot/dts/armada-388-helios4.dts
@@ -70,6 +70,9 @@
system-leds {
compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&helios_system_led_pins>;
+
status-led {
label = "helios4:green:status";
gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
@@ -98,6 +101,9 @@
io-leds {
compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&helios_io_led_pins>;
+
sata1-led {
label = "helios4:green:ata1";
gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
@@ -133,11 +139,15 @@
fan1: j10-pwm {
compatible = "pwm-fan";
pwms = <&gpio1 9 40000>; /* Target freq:25 kHz */
+ pinctrl-names = "default";
+ pinctrl-0 = <&j10_pins>;
};
fan2: j17-pwm {
compatible = "pwm-fan";
pwms = <&gpio1 23 40000>; /* Target freq:25 kHz */
+ pinctrl-names = "default";
+ pinctrl-0 = <&j17_pins>;
};
usb2_phy: usb2-phy {
@@ -298,16 +308,23 @@
"mpp39", "mpp40";
marvell,function = "sd0";
};
- helios_led_pins: helios-led-pins {
- marvell,pins = "mpp24", "mpp25",
+ helios_system_led_pins: helios-system-led-pins {
+ marvell,pins = "mpp24", "mpp25";
+ marvell,function = "gpio";
+ };
+ helios_io_led_pins: helios-io-led-pins {
+ marvell,pins = "mpp49", "mpp50",
"mpp49", "mpp50",
"mpp52", "mpp53",
"mpp54";
marvell,function = "gpio";
};
- helios_fan_pins: helios-fan-pins {
- marvell,pins = "mpp41", "mpp43",
- "mpp48", "mpp55";
+ j10_pins: fan-j10-pins {
+ marvell,pins = "mpp41", "mpp43";
+ marvell,function = "gpio";
+ };
+ j17_pins: fan-j17-pins {
+ marvell,pins = "mpp48", "mpp55";
marvell,function = "gpio";
};
microsom_spi1_cs_pins: spi1-cs-pins {

12
patch/kernel/mvebu-dev/compile-dtb-with-symbol-support.patch
View File

@ -1,12 +0,0 @@
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -277,6 +277,9 @@ quiet_cmd_gzip = GZIP $@
DTC ?= $(objtree)/scripts/dtc/dtc
DTC_FLAGS += -Wno-interrupt_provider
+# Enable overlay support
+DTC_FLAGS += -@
+
# Disable noisy checks by default
ifeq ($(findstring 1,$(KBUILD_EXTRA_WARN)),)
DTC_FLAGS += -Wno-unit_address_vs_reg \

399
patch/kernel/mvebu-dev/disabled/800-Add_Armada_38x_support_for_clk-cpu.patch
View File

@ -1,399 +0,0 @@
This patch first shortens the registers definition and also introduces
difference between Armada XP value and Armada 38x value.
Then it adds specific functions for Armada 38x in order to support cpu
freq on these SoCs.
Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
--- a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
@@ -1,11 +1,14 @@
Device Tree Clock bindings for cpu clock of Marvell EBU platforms
Required properties:
-- compatible : shall be one of the following:
+- compatible : shall be the following:
"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
+ "marvell,armada-38x-cpu-clock", "marvell,armada-xp-cpu-clock" - cpu
+ clocks for Armada 38x
"marvell,mv98dx3236-cpu-clock" - cpu clocks for 98DX3236 SoC
- reg : Address and length of the clock complex register set, followed
- by address and length of the PMU DFS registers
+ by address and length of the PMU DFS registers, for Armada 38x
+ a third register set must be addeed: DFX server.
- #clock-cells : should be set to 1.
- clocks : shall be the input parent clock phandle for the clock.
@@ -21,3 +24,23 @@ cpu@0 {
reg = <0>;
clocks = <&cpuclk 0>;
};
+
+or for Armada38x
+
+cpuclk: clock-complex at 18700 {
+ compatible = "marvell,armada-380-cpu-clock",
+ "marvell,armada-xp-cpu-clock";
+ reg = <0x18700 0xA0>, <0x1c054 0x40>,
+ <0xe4260 0x8>;
+ clocks = <&coreclk 1>;
+ #clock-cells = <1>;
+};
+
+cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ clocks = <&cpuclk 0>;
+ clock-latency = <1000000>;
+ clock-names = "cpu0";
+};
--- a/drivers/clk/mvebu/clk-cpu.c
+++ b/drivers/clk/mvebu/clk-cpu.c
@@ -18,16 +18,34 @@
#include <linux/mvebu-pmsu.h>
#include <asm/smp_plat.h>
-#define SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET 0x0
-#define SYS_CTRL_CLK_DIVIDER_CTRL_RESET_ALL 0xff
-#define SYS_CTRL_CLK_DIVIDER_CTRL_RESET_SHIFT 8
-#define SYS_CTRL_CLK_DIVIDER_CTRL2_OFFSET 0x8
-#define SYS_CTRL_CLK_DIVIDER_CTRL2_NBCLK_RATIO_SHIFT 16
-#define SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET 0xC
-#define SYS_CTRL_CLK_DIVIDER_MASK 0x3F
-
-#define PMU_DFS_RATIO_SHIFT 16
-#define PMU_DFS_RATIO_MASK 0x3F
+/* Clock complex registers */
+#define SYS_CTRL_CLK_DIV_CTRL_OFFSET 0x0
+#define SYS_CTRL_CLK_DIV_CTRL_RESET_ALL 0xFF
+#define SYS_CTRL_CLK_DIV_CTRL_RESET_SHIFT 8
+#define SYS_CTRL_CLK_DIV_VALUE_A38X_OFFSET 0x4
+#define SYS_CTRL_CLK_DIV_CTRL2_OFFSET 0x8
+#define SYS_CTRL_CLK_DIV_CTRL2_NBCLK_RATIO_SHIFT 16
+#define SYS_CTRL_CLK_DIV_VALUE_AXP_OFFSET 0xC
+#define SYS_CTRL_CLK_DIV_MASK 0x3F
+
+/* PMU registers */
+#define PMU_DFS_CTRL1_OFFSET 0x0
+#define PMU_DFS_RATIO_SHIFT 16
+#define PMU_DFS_RATIO_MASK 0x3F
+#define PMUL_ACTIVATE_IF_CTRL_OFFSET 0x3C
+#define PMUL_ACTIVATE_IF_CTRL_PMU_DFS_OVRD_EN_MASK 0xFF
+#define PMUL_ACTIVATE_IF_CTRL_PMU_DFS_OVRD_EN_SHIFT 17
+#define PMUL_ACTIVATE_IF_CTRL_PMU_DFS_OVRD_EN 0x1
+
+/* DFX server registers */
+#define DFX_CPU_PLL_CLK_DIV_CTRL0_OFFSET 0x0
+#define DFX_CPU_PLL_CLK_DIV_CTRL0_RELOAD_SMOOTH_MASK 0xFF
+#define DFX_CPU_PLL_CLK_DIV_CTRL0_RELOAD_SMOOTH_SHIFT 0x8
+#define DFX_CPU_PLL_CLK_DIV_CTRL0_RELOAD_SMOOTH_PCLK 0x10
+#define DFX_CPU_PLL_CLK_DIV_CTRL1_OFFSET 0x4
+#define DFX_CPU_PLL_CLK_DIV_CTRL1_RESET_MASK_MASK 0xFF
+#define DFX_CPU_PLL_CLK_DIV_CTRL1_RESET_MASK_SHIFT 0x0
+#define DFX_CPU_PLL_CLK_DIV_CTRL1_RESET_MASK_PCLK 0x10
#define MAX_CPU 4
struct cpu_clk {
@@ -37,6 +55,7 @@ struct cpu_clk {
const char *parent_name;
void __iomem *reg_base;
void __iomem *pmu_dfs;
+ void __iomem *dfx_server_base;
};
static struct clk **clks;
@@ -45,14 +64,30 @@ static struct clk_onecell_data clk_data;
#define to_cpu_clk(p) container_of(p, struct cpu_clk, hw)
-static unsigned long clk_cpu_recalc_rate(struct clk_hw *hwclk,
+static unsigned long armada_xp_clk_cpu_recalc_rate(struct clk_hw *hwclk,
+ unsigned long parent_rate)
+{
+ struct cpu_clk *cpuclk = to_cpu_clk(hwclk);
+ u32 reg, div;
+
+ reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIV_VALUE_AXP_OFFSET);
+ div = (reg >> (cpuclk->cpu * 8)) & SYS_CTRL_CLK_DIV_MASK;
+ return parent_rate / div;
+}
+
+static unsigned long armada_38x_clk_cpu_recalc_rate(struct clk_hw *hwclk,
unsigned long parent_rate)
{
struct cpu_clk *cpuclk = to_cpu_clk(hwclk);
u32 reg, div;
- reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET);
- div = (reg >> (cpuclk->cpu * 8)) & SYS_CTRL_CLK_DIVIDER_MASK;
+ if (__clk_is_enabled(hwclk->clk) == false) {
+ /* for clock init - don't use divider, set maximal rate */
+ return parent_rate;
+ }
+
+ reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIV_VALUE_A38X_OFFSET);
+ div = (reg >> (cpuclk->cpu * 8)) & SYS_CTRL_CLK_DIV_MASK;
return parent_rate / div;
}
@@ -71,42 +106,43 @@ static long clk_cpu_round_rate(struct cl
return *parent_rate / div;
}
-static int clk_cpu_off_set_rate(struct clk_hw *hwclk, unsigned long rate,
- unsigned long parent_rate)
-
+static int armada_xp_clk_cpu_off_set_rate(struct clk_hw *hwclk,
+ unsigned long rate,
+ unsigned long parent_rate)
{
struct cpu_clk *cpuclk = to_cpu_clk(hwclk);
u32 reg, div;
u32 reload_mask;
div = parent_rate / rate;
- reg = (readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET)
- & (~(SYS_CTRL_CLK_DIVIDER_MASK << (cpuclk->cpu * 8))))
+ reg = (readl(cpuclk->reg_base + SYS_CTRL_CLK_DIV_VALUE_AXP_OFFSET)
+ & (~(SYS_CTRL_CLK_DIV_MASK << (cpuclk->cpu * 8))))
| (div << (cpuclk->cpu * 8));
- writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET);
+ writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIV_VALUE_AXP_OFFSET);
/* Set clock divider reload smooth bit mask */
reload_mask = 1 << (20 + cpuclk->cpu);
- reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET)
+ reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIV_CTRL_OFFSET)
| reload_mask;
- writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
+ writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIV_CTRL_OFFSET);
/* Now trigger the clock update */
- reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET)
+ reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIV_CTRL_OFFSET)
| 1 << 24;
- writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
+ writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIV_CTRL_OFFSET);
/* Wait for clocks to settle down then clear reload request */
udelay(1000);
reg &= ~(reload_mask | 1 << 24);
- writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
+ writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIV_CTRL_OFFSET);
udelay(1000);
return 0;
}
-static int clk_cpu_on_set_rate(struct clk_hw *hwclk, unsigned long rate,
- unsigned long parent_rate)
+static int armada_xp_clk_cpu_on_set_rate(struct clk_hw *hwclk,
+ unsigned long rate,
+ unsigned long parent_rate)
{
u32 reg;
unsigned long fabric_div, target_div, cur_rate;
@@ -121,9 +157,9 @@ static int clk_cpu_on_set_rate(struct cl
cur_rate = clk_hw_get_rate(hwclk);
- reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL2_OFFSET);
- fabric_div = (reg >> SYS_CTRL_CLK_DIVIDER_CTRL2_NBCLK_RATIO_SHIFT) &
- SYS_CTRL_CLK_DIVIDER_MASK;
+ reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIV_CTRL2_OFFSET);
+ fabric_div = (reg >> SYS_CTRL_CLK_DIV_CTRL2_NBCLK_RATIO_SHIFT) &
+ SYS_CTRL_CLK_DIV_MASK;
/* Frequency is going up */
if (rate == 2 * cur_rate)
@@ -140,40 +176,101 @@ static int clk_cpu_on_set_rate(struct cl
reg |= (target_div << PMU_DFS_RATIO_SHIFT);
writel(reg, cpuclk->pmu_dfs);
- reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
- reg |= (SYS_CTRL_CLK_DIVIDER_CTRL_RESET_ALL <<
- SYS_CTRL_CLK_DIVIDER_CTRL_RESET_SHIFT);
- writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
+ reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIV_CTRL_OFFSET);
+ reg |= (SYS_CTRL_CLK_DIV_CTRL_RESET_ALL <<
+ SYS_CTRL_CLK_DIV_CTRL_RESET_SHIFT);
+ writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIV_CTRL_OFFSET);
return mvebu_pmsu_dfs_request(cpuclk->cpu);
}
-static int clk_cpu_set_rate(struct clk_hw *hwclk, unsigned long rate,
+static int armada_xp_clk_cpu_set_rate(struct clk_hw *hwclk, unsigned long rate,
unsigned long parent_rate)
{
if (__clk_is_enabled(hwclk->clk))
- return clk_cpu_on_set_rate(hwclk, rate, parent_rate);
+ return armada_xp_clk_cpu_on_set_rate(hwclk, rate, parent_rate);
+ else
+ return armada_xp_clk_cpu_off_set_rate(hwclk, rate, parent_rate);
+}
+static int armada_38x_clk_cpu_set_rate(struct clk_hw *hwclk, unsigned long rate,
+ unsigned long parent_rate)
+{
+ u32 reg;
+ u32 target_div;
+ unsigned long cur_rate;
+ struct cpu_clk *cpuclk = to_cpu_clk(hwclk);
+
+ /*
+ * PMU DFS registers are not mapped, Device Tree does not
+ * describes them. We cannot change the frequency dynamically.
+ */
+ if (!cpuclk->pmu_dfs)
+ return -ENODEV;
+
+ cur_rate = clk_hw_get_rate(hwclk);
+
+ /* Frequency is going up */
+ if (rate >= cur_rate)
+ target_div = 1;
+ /* Frequency is going down */
else
- return clk_cpu_off_set_rate(hwclk, rate, parent_rate);
+ target_div = 2;
+
+ reg = readl(cpuclk->dfx_server_base + DFX_CPU_PLL_CLK_DIV_CTRL0_OFFSET);
+ reg &= ~(DFX_CPU_PLL_CLK_DIV_CTRL0_RELOAD_SMOOTH_MASK <<
+ DFX_CPU_PLL_CLK_DIV_CTRL0_RELOAD_SMOOTH_SHIFT);
+ reg |= (DFX_CPU_PLL_CLK_DIV_CTRL0_RELOAD_SMOOTH_PCLK <<
+ DFX_CPU_PLL_CLK_DIV_CTRL0_RELOAD_SMOOTH_SHIFT);
+ writel(reg, cpuclk->dfx_server_base + DFX_CPU_PLL_CLK_DIV_CTRL0_OFFSET);
+
+ reg = readl(cpuclk->dfx_server_base + DFX_CPU_PLL_CLK_DIV_CTRL1_OFFSET);
+ reg &= ~(DFX_CPU_PLL_CLK_DIV_CTRL1_RESET_MASK_MASK <<
+ DFX_CPU_PLL_CLK_DIV_CTRL1_RESET_MASK_SHIFT);
+ reg |= (DFX_CPU_PLL_CLK_DIV_CTRL1_RESET_MASK_PCLK <<
+ DFX_CPU_PLL_CLK_DIV_CTRL1_RESET_MASK_SHIFT);
+ writel(reg, cpuclk->dfx_server_base + DFX_CPU_PLL_CLK_DIV_CTRL1_OFFSET);
+
+ reg = readl(cpuclk->pmu_dfs);
+ reg &= ~(PMU_DFS_RATIO_MASK << PMU_DFS_RATIO_SHIFT);
+ reg |= (target_div << PMU_DFS_RATIO_SHIFT);
+ writel(reg, cpuclk->pmu_dfs);
+
+ reg = readl(cpuclk->pmu_dfs + PMUL_ACTIVATE_IF_CTRL_OFFSET);
+ reg &= ~(PMUL_ACTIVATE_IF_CTRL_PMU_DFS_OVRD_EN_MASK <<
+ PMUL_ACTIVATE_IF_CTRL_PMU_DFS_OVRD_EN_SHIFT);
+ reg |= (PMUL_ACTIVATE_IF_CTRL_PMU_DFS_OVRD_EN <<
+ PMUL_ACTIVATE_IF_CTRL_PMU_DFS_OVRD_EN_SHIFT);
+ writel(reg, cpuclk->pmu_dfs + PMUL_ACTIVATE_IF_CTRL_OFFSET);
+
+ return mvebu_pmsu_dfs_request(cpuclk->cpu);
}
-static const struct clk_ops cpu_ops = {
- .recalc_rate = clk_cpu_recalc_rate,
+static const struct clk_ops armada_xp_cpu_ops = {
+ .recalc_rate = armada_xp_clk_cpu_recalc_rate,
+ .round_rate = clk_cpu_round_rate,
+ .set_rate = armada_xp_clk_cpu_set_rate,
+};
+
+static const struct clk_ops armada_38x_cpu_ops = {
+ .recalc_rate = armada_38x_clk_cpu_recalc_rate,
.round_rate = clk_cpu_round_rate,
- .set_rate = clk_cpu_set_rate,
+ .set_rate = armada_38x_clk_cpu_set_rate,
};
-static void __init of_cpu_clk_setup(struct device_node *node)
+static void __init common_cpu_clk_init(struct device_node *node, bool cortexa9)
{
struct cpu_clk *cpuclk;
void __iomem *clock_complex_base = of_iomap(node, 0);
void __iomem *pmu_dfs_base = of_iomap(node, 1);
+ void __iomem *dfx_server_base = of_iomap(node, 2);
int ncpus = 0;
struct device_node *dn;
+ bool independent_clocks = true;
+ const struct clk_ops *cpu_ops = NULL;
if (clock_complex_base == NULL) {
pr_err("%s: clock-complex base register not set\n",
- __func__);
+ __func__);
return;
}
@@ -184,6 +281,21 @@ static void __init of_cpu_clk_setup(stru
for_each_of_cpu_node(dn)
ncpus++;
+ if (cortexa9) {
+ if (dfx_server_base == NULL) {
+ pr_err("%s: DFX server base register not set\n",
+ __func__);
+ return;
+ }
+ cpu_ops = &armada_38x_cpu_ops;
+ independent_clocks = false;
+ ncpus = 1;
+ } else {
+ cpu_ops = &armada_xp_cpu_ops;
+ for_each_node_by_type(dn, "cpu")
+ ncpus++;
+ }
+
cpuclk = kcalloc(ncpus, sizeof(*cpuclk), GFP_KERNEL);
if (WARN_ON(!cpuclk))
goto cpuclk_out;
@@ -213,10 +325,12 @@ static void __init of_cpu_clk_setup(stru
cpuclk[cpu].reg_base = clock_complex_base;
if (pmu_dfs_base)
cpuclk[cpu].pmu_dfs = pmu_dfs_base + 4 * cpu;
+
+ cpuclk[cpu].dfx_server_base = dfx_server_base;
cpuclk[cpu].hw.init = &init;
init.name = cpuclk[cpu].clk_name;
- init.ops = &cpu_ops;
+ init.ops = cpu_ops;
init.flags = 0;
init.parent_names = &cpuclk[cpu].parent_name;
init.num_parents = 1;
@@ -225,6 +339,11 @@ static void __init of_cpu_clk_setup(stru
if (WARN_ON(IS_ERR(clk)))
goto bail_out;
clks[cpu] = clk;
+
+ if (independent_clocks == false) {
+ /* use 1 clock to all cpus */
+ break;
+ }
}
clk_data.clk_num = MAX_CPU;
clk_data.clks = clks;
@@ -239,10 +358,25 @@ clks_out:
kfree(cpuclk);
cpuclk_out:
iounmap(clock_complex_base);
+ iounmap(pmu_dfs_base);
+ iounmap(dfx_server_base);
+}
+
+static void __init armada_xp_cpu_clk_init(struct device_node *node)
+{
+ common_cpu_clk_init(node, false);
+}
+
+static void __init armada_38x_cpu_clk_init(struct device_node *node)
+{
+ common_cpu_clk_init(node, true);
}
CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
- of_cpu_clk_setup);
+ armada_xp_cpu_clk_init);
+CLK_OF_DECLARE(armada_38x_cpu_clock, "marvell,armada-380-cpu-clock",
+ armada_38x_cpu_clk_init);
+
static void __init of_mv98dx3236_cpu_clk_setup(struct device_node *node)
{

166
patch/kernel/mvebu-dev/disabled/801-Use_shorter_register_definition_in_pmsu_c.patch
View File

@ -1,166 +0,0 @@
The register definition were too verbose. Shorten them in order to
have something more readable and avoiding having most of the
instruction on two lines.
Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -45,27 +45,29 @@
#define PMSU_REG_SIZE 0x1000
/* PMSU MP registers */
-#define PMSU_CONTROL_AND_CONFIG(cpu) ((cpu * 0x100) + 0x104)
-#define PMSU_CONTROL_AND_CONFIG_DFS_REQ BIT(18)
-#define PMSU_CONTROL_AND_CONFIG_PWDDN_REQ BIT(16)
-#define PMSU_CONTROL_AND_CONFIG_L2_PWDDN BIT(20)
+#define PMSU_CTL_CFG(cpu) ((cpu * 0x100) + 0x104)
+#define PMSU_CTL_CFG_CPU0_FRQ_ID_SFT 4
+#define PMSU_CTL_CFG_CPU0_FRQ_ID_MSK 0xF
+#define PMSU_CTL_CFG_DFS_REQ BIT(18)
+#define PMSU_CTL_CFG_PWDDN_REQ BIT(16)
+#define PMSU_CTL_CFG_L2_PWDDN BIT(20)
#define PMSU_CPU_POWER_DOWN_CONTROL(cpu) ((cpu * 0x100) + 0x108)
#define PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP BIT(0)
-#define PMSU_STATUS_AND_MASK(cpu) ((cpu * 0x100) + 0x10c)
-#define PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT BIT(16)
-#define PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT BIT(17)
-#define PMSU_STATUS_AND_MASK_IRQ_WAKEUP BIT(20)
-#define PMSU_STATUS_AND_MASK_FIQ_WAKEUP BIT(21)
-#define PMSU_STATUS_AND_MASK_DBG_WAKEUP BIT(22)
-#define PMSU_STATUS_AND_MASK_IRQ_MASK BIT(24)
-#define PMSU_STATUS_AND_MASK_FIQ_MASK BIT(25)
-
-#define PMSU_EVENT_STATUS_AND_MASK(cpu) ((cpu * 0x100) + 0x120)
-#define PMSU_EVENT_STATUS_AND_MASK_DFS_DONE BIT(1)
-#define PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK BIT(17)
+#define PMSU_STATUS_MSK(cpu) ((cpu * 0x100) + 0x10c)
+#define PMSU_STATUS_MSK_CPU_IDLE_WAIT BIT(16)
+#define PMSU_STATUS_MSK_SNP_Q_EMPTY_WAIT BIT(17)
+#define PMSU_STATUS_MSK_IRQ_WAKEUP BIT(20)
+#define PMSU_STATUS_MSK_FIQ_WAKEUP BIT(21)
+#define PMSU_STATUS_MSK_DBG_WAKEUP BIT(22)
+#define PMSU_STATUS_MSK_IRQ_MASK BIT(24)
+#define PMSU_STATUS_MSK_FIQ_MASK BIT(25)
+
+#define PMSU_EVENT_STATUS_MSK(cpu) ((cpu * 0x100) + 0x120)
+#define PMSU_EVENT_STATUS_MSK_DFS_DONE BIT(1)
+#define PMSU_EVENT_STATUS_MSK_DFS_DONE_MASK BIT(17)
#define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x124)
@@ -237,23 +239,23 @@ static int mvebu_v7_pmsu_idle_prepare(un
* IRQ and FIQ as wakeup events, set wait for snoop queue empty
* indication and mask IRQ and FIQ from CPU
*/
- reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
- reg |= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT |
- PMSU_STATUS_AND_MASK_IRQ_WAKEUP |
- PMSU_STATUS_AND_MASK_FIQ_WAKEUP |
- PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT |
- PMSU_STATUS_AND_MASK_IRQ_MASK |
- PMSU_STATUS_AND_MASK_FIQ_MASK;
- writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
+ reg = readl(pmsu_mp_base + PMSU_STATUS_MSK(hw_cpu));
+ reg |= PMSU_STATUS_MSK_CPU_IDLE_WAIT |
+ PMSU_STATUS_MSK_IRQ_WAKEUP |
+ PMSU_STATUS_MSK_FIQ_WAKEUP |
+ PMSU_STATUS_MSK_SNP_Q_EMPTY_WAIT |
+ PMSU_STATUS_MSK_IRQ_MASK |
+ PMSU_STATUS_MSK_FIQ_MASK;
+ writel(reg, pmsu_mp_base + PMSU_STATUS_MSK(hw_cpu));
- reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
+ reg = readl(pmsu_mp_base + PMSU_CTL_CFG(hw_cpu));
/* ask HW to power down the L2 Cache if needed */
if (flags & PMSU_PREPARE_DEEP_IDLE)
- reg |= PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
+ reg |= PMSU_CTL_CFG_L2_PWDDN;
/* request power down */
- reg |= PMSU_CONTROL_AND_CONFIG_PWDDN_REQ;
- writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
+ reg |= PMSU_CTL_CFG_PWDDN_REQ;
+ writel(reg, pmsu_mp_base + PMSU_CTL_CFG(hw_cpu));
if (flags & PMSU_PREPARE_SNOOP_DISABLE) {
/* Disable snoop disable by HW - SW is taking care of it */
@@ -346,17 +348,17 @@ void mvebu_v7_pmsu_idle_exit(void)
if (pmsu_mp_base == NULL)
return;
/* cancel ask HW to power down the L2 Cache if possible */
- reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
- reg &= ~PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
- writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
+ reg = readl(pmsu_mp_base + PMSU_CTL_CFG(hw_cpu));
+ reg &= ~PMSU_CTL_CFG_L2_PWDDN;
+ writel(reg, pmsu_mp_base + PMSU_CTL_CFG(hw_cpu));
/* cancel Enable wakeup events and mask interrupts */
- reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
- reg &= ~(PMSU_STATUS_AND_MASK_IRQ_WAKEUP | PMSU_STATUS_AND_MASK_FIQ_WAKEUP);
- reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT;
- reg &= ~PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT;
- reg &= ~(PMSU_STATUS_AND_MASK_IRQ_MASK | PMSU_STATUS_AND_MASK_FIQ_MASK);
- writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
+ reg = readl(pmsu_mp_base + PMSU_STATUS_MSK(hw_cpu));
+ reg &= ~(PMSU_STATUS_MSK_IRQ_WAKEUP | PMSU_STATUS_MSK_FIQ_WAKEUP);
+ reg &= ~PMSU_STATUS_MSK_CPU_IDLE_WAIT;
+ reg &= ~PMSU_STATUS_MSK_SNP_Q_EMPTY_WAIT;
+ reg &= ~(PMSU_STATUS_MSK_IRQ_MASK | PMSU_STATUS_MSK_FIQ_MASK);
+ writel(reg, pmsu_mp_base + PMSU_STATUS_MSK(hw_cpu));
}
static int mvebu_v7_cpu_pm_notify(struct notifier_block *self,
@@ -543,16 +545,16 @@ static void mvebu_pmsu_dfs_request_local
local_irq_save(flags);
/* Prepare to enter idle */
- reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
- reg |= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT |
- PMSU_STATUS_AND_MASK_IRQ_MASK |
- PMSU_STATUS_AND_MASK_FIQ_MASK;
- writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
+ reg = readl(pmsu_mp_base + PMSU_STATUS_MSK(cpu));
+ reg |= PMSU_STATUS_MSK_CPU_IDLE_WAIT |
+ PMSU_STATUS_MSK_IRQ_MASK |
+ PMSU_STATUS_MSK_FIQ_MASK;
+ writel(reg, pmsu_mp_base + PMSU_STATUS_MSK(cpu));
/* Request the DFS transition */
- reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu));
- reg |= PMSU_CONTROL_AND_CONFIG_DFS_REQ;
- writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu));
+ reg = readl(pmsu_mp_base + PMSU_CTL_CFG(cpu));
+ reg |= PMSU_CTL_CFG_DFS_REQ;
+ writel(reg, pmsu_mp_base + PMSU_CTL_CFG(cpu));
/* The fact of entering idle will trigger the DFS transition */
wfi();
@@ -561,9 +563,9 @@ static void mvebu_pmsu_dfs_request_local
* We're back from idle, the DFS transition has completed,
* clear the idle wait indication.
*/
- reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
- reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT;
- writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
+ reg = readl(pmsu_mp_base + PMSU_STATUS_MSK(cpu));
+ reg &= ~PMSU_STATUS_MSK_CPU_IDLE_WAIT;
+ writel(reg, pmsu_mp_base + PMSU_STATUS_MSK(cpu));
local_irq_restore(flags);
}
@@ -591,8 +593,8 @@ int mvebu_pmsu_dfs_request(int cpu)
/* Poll until the DFS done event is generated */
timeout = jiffies + HZ;
while (time_before(jiffies, timeout)) {
- reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
- if (reg & PMSU_EVENT_STATUS_AND_MASK_DFS_DONE)
+ reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_MSK(hwcpu));
+ if (reg & PMSU_EVENT_STATUS_MSK_DFS_DONE)
break;
udelay(10);
}

126
patch/kernel/mvebu-dev/disabled/802-Made_the_dynamic_frequency_scaling_support_more_generic.patch
View File

@ -1,126 +0,0 @@
In preparation to support cpufreq for Armada 38x:
- rename the function to be more generic.
- move masking interrupt to the _dfs_request_local function in order
to be use by both SoCs.
- add stubs allowing registering the support for a new SoC
Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
Original patch adapted by Turris for kernel 4.4 has been adapted
for kernel 4.9:
* use include/linux/mvebu-pmsu.h to pass variables and functions
between pmsu.c and cpufreq.c
* cpufreq-dt does not have parameters any more, so revert to
simple registration
Signed-off-by: Hannu Nyman <hannu.nyman@iki.fi>
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -104,6 +104,7 @@ static phys_addr_t pmsu_mp_phys_base;
static void __iomem *pmsu_mp_base;
static void *mvebu_cpu_resume;
+int (*mvebu_pmsu_dfs_request_ptr)(int cpu);
static const struct of_device_id of_pmsu_table[] = {
{ .compatible = "marvell,armada-370-pmsu", },
@@ -544,6 +545,14 @@ static void mvebu_pmsu_dfs_request_local
local_irq_save(flags);
+ /* Clear any previous DFS DONE event */
+ reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_MSK(cpu));
+ reg &= ~PMSU_EVENT_STATUS_MSK_DFS_DONE;
+
+ /* Mask the DFS done interrupt, since we are going to poll */
+ reg |= PMSU_EVENT_STATUS_MSK_DFS_DONE_MASK;
+ writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_MSK(cpu));
+
/* Prepare to enter idle */
reg = readl(pmsu_mp_base + PMSU_STATUS_MSK(cpu));
reg |= PMSU_STATUS_MSK_CPU_IDLE_WAIT |
@@ -567,25 +576,20 @@ static void mvebu_pmsu_dfs_request_local
reg &= ~PMSU_STATUS_MSK_CPU_IDLE_WAIT;
writel(reg, pmsu_mp_base + PMSU_STATUS_MSK(cpu));
+ /* Restore the DFS mask to its original state */
+ reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_MSK(cpu));
+ reg &= ~PMSU_EVENT_STATUS_MSK_DFS_DONE_MASK;
+ writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_MSK(cpu));
+
local_irq_restore(flags);
}
-int mvebu_pmsu_dfs_request(int cpu)
+int armada_xp_pmsu_dfs_request(int cpu)
{
unsigned long timeout;
int hwcpu = cpu_logical_map(cpu);
u32 reg;
- /* Clear any previous DFS DONE event */
- reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
- reg &= ~PMSU_EVENT_STATUS_AND_MASK_DFS_DONE;
- writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
-
- /* Mask the DFS done interrupt, since we are going to poll */
- reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
- reg |= PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK;
- writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
-
/* Trigger the DFS on the appropriate CPU */
smp_call_function_single(cpu, mvebu_pmsu_dfs_request_local,
NULL, false);
@@ -601,11 +605,10 @@ int mvebu_pmsu_dfs_request(int cpu)
if (time_after(jiffies, timeout))
return -ETIME;
-
- /* Restore the DFS mask to its original state */
- reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
- reg &= ~PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK;
- writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
-
return 0;
}
+
+int mvebu_pmsu_dfs_request(int cpu)
+{
+ return mvebu_pmsu_dfs_request_ptr(cpu);
+}
--- a/drivers/cpufreq/mvebu-cpufreq.c
+++ b/drivers/cpufreq/mvebu-cpufreq.c
@@ -22,8 +22,9 @@
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <linux/resource.h>
+#include <linux/mvebu-pmsu.h>
-static int __init armada_xp_pmsu_cpufreq_init(void)
+static int __init mvebu_pmsu_cpufreq_init(void)
{
struct device_node *np;
struct resource res;
@@ -98,7 +99,8 @@ static int __init armada_xp_pmsu_cpufreq
clk_put(clk);
}
+ mvebu_pmsu_dfs_request_ptr = armada_xp_pmsu_dfs_request;
platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
return 0;
}
-device_initcall(armada_xp_pmsu_cpufreq_init);
+device_initcall(mvebu_pmsu_cpufreq_init);
--- a/include/linux/mvebu-pmsu.h
+++ b/include/linux/mvebu-pmsu.h
@@ -16,5 +16,7 @@ int mvebu_pmsu_dfs_request(int cpu);
#else
static inline int mvebu_pmsu_dfs_request(int cpu) { return -ENODEV; }
#endif
+extern int (*mvebu_pmsu_dfs_request_ptr)(int cpu);
+int armada_xp_pmsu_dfs_request(int cpu);
#endif /* __MVEBU_PMSU_H__ */

121
patch/kernel/mvebu-dev/disabled/803-Armada_38x_Add_dynamic_frequency_scaling_support_in_pmsu.patch
View File

@ -1,121 +0,0 @@
This commit add the last missing piece of code enabling dynamic
frequency scaling support for Armada 38x.
The main difference with Armada XP is that the Cortex A9 CPU
frequencies of the Armada 38x SoCs are not independent. Even if a SoC
contains a single CPU, some specific initialization has to be done at
pmsu level: this unit must not wait for the second CPU when the
frequency is modified.
Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
Original patch adapted by Turris for kernel 4.4 has been adapted
for kernel 4.9:
* use include/linux/mvebu-pmsu.h to pass variables and functions
between pmsu.c and cpufreq.c
* cpufreq-dt does not have parameters any more, so revert to
simple registration
Signed-off-by: Hannu Nyman <hannu.nyman@iki.fi>
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -351,6 +351,13 @@ void mvebu_v7_pmsu_idle_exit(void)
/* cancel ask HW to power down the L2 Cache if possible */
reg = readl(pmsu_mp_base + PMSU_CTL_CFG(hw_cpu));
reg &= ~PMSU_CTL_CFG_L2_PWDDN;
+
+ /*
+ * When exiting from idle state such as cpuidle or hotplug,
+ * Enable PMU wait for the CPU to enter WFI when doing DFS
+ * by setting CPUx Frequency ID to 1
+ */
+ reg |= 1 << PMSU_CTL_CFG_CPU0_FRQ_ID_SFT;
writel(reg, pmsu_mp_base + PMSU_CTL_CFG(hw_cpu));
/* cancel Enable wakeup events and mask interrupts */
@@ -608,6 +615,38 @@ int armada_xp_pmsu_dfs_request(int cpu)
return 0;
}
+void mvebu_v7_pmsu_disable_dfs_cpu(int hw_cpu)
+{
+ u32 reg;
+
+ if (pmsu_mp_base == NULL)
+ return;
+ /*
+ * Disable PMU wait for the CPU to enter WFI when doing DFS
+ * by setting CPUx Frequency ID to 0
+ */
+ reg = readl(pmsu_mp_base + PMSU_CTL_CFG(hw_cpu));
+ reg &= ~(PMSU_CTL_CFG_CPU0_FRQ_ID_MSK << PMSU_CTL_CFG_CPU0_FRQ_ID_SFT);
+ writel(reg, pmsu_mp_base + PMSU_CTL_CFG(hw_cpu));
+}
+
+int armada_38x_pmsu_dfs_request(int cpu)
+{
+ /*
+ * Protect CPU DFS from changing the number of online cpus number during
+ * frequency transition by temporarily disable cpu hotplug
+ */
+ cpu_hotplug_disable();
+
+ /* Trigger the DFS on all the CPUs */
+ on_each_cpu(mvebu_pmsu_dfs_request_local,
+ NULL, false);
+
+ cpu_hotplug_enable();
+
+ return 0;
+}
+
int mvebu_pmsu_dfs_request(int cpu)
{
return mvebu_pmsu_dfs_request_ptr(cpu);
--- a/drivers/cpufreq/mvebu-cpufreq.c
+++ b/drivers/cpufreq/mvebu-cpufreq.c
@@ -30,7 +30,8 @@ static int __init mvebu_pmsu_cpufreq_ini
struct resource res;
int ret, cpu;
- if (!of_machine_is_compatible("marvell,armadaxp"))
+ if (!of_machine_is_compatible("marvell,armadaxp") &&
+ !of_machine_is_compatible("marvell,armada380"))
return 0;
/*
@@ -77,6 +78,8 @@ static int __init mvebu_pmsu_cpufreq_ini
return PTR_ERR(clk);
}
+ clk_prepare_enable(clk);
+
ret = dev_pm_opp_add(cpu_dev, clk_get_rate(clk), 0);
if (ret) {
clk_put(clk);
@@ -99,7 +102,14 @@ static int __init mvebu_pmsu_cpufreq_ini
clk_put(clk);
}
- mvebu_pmsu_dfs_request_ptr = armada_xp_pmsu_dfs_request;
+ if (of_machine_is_compatible("marvell,armada380")) {
+ if (num_online_cpus() == 1)
+ mvebu_v7_pmsu_disable_dfs_cpu(1);
+
+ mvebu_pmsu_dfs_request_ptr = armada_38x_pmsu_dfs_request;
+ } else if (of_machine_is_compatible("marvell,armadaxp")) {
+ mvebu_pmsu_dfs_request_ptr = armada_xp_pmsu_dfs_request;
+ }
platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
return 0;
}
--- a/include/linux/mvebu-pmsu.h
+++ b/include/linux/mvebu-pmsu.h
@@ -18,5 +18,7 @@ static inline int mvebu_pmsu_dfs_request
#endif
extern int (*mvebu_pmsu_dfs_request_ptr)(int cpu);
int armada_xp_pmsu_dfs_request(int cpu);
+int armada_38x_pmsu_dfs_request(int cpu);
+void mvebu_v7_pmsu_disable_dfs_cpu(int hw_cpu);
#endif /* __MVEBU_PMSU_H__ */

59
patch/kernel/mvebu-dev/disabled/804-Update_Armada_38x_DT_for_dynamic_frequency_scaling.patch
View File

@ -1,59 +0,0 @@
In order to support dynamic frequency scaling:
- the cpuclk Device Tree node must be added
- the clock property of the CPUs must be filled including the
clock-latency property.
Signed-off-by: Gregory CLEMENT <gregory.clement at free-electrons.com>
--- a/arch/arm/boot/dts/armada-380.dtsi
+++ b/arch/arm/boot/dts/armada-380.dtsi
@@ -24,6 +24,9 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
+ clocks = <&cpuclk 0>;
+ clock-latency = <1000000>;
+ clock-names = "cpu0";
};
};
--- a/arch/arm/boot/dts/armada-385.dtsi
+++ b/arch/arm/boot/dts/armada-385.dtsi
@@ -24,11 +24,17 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
+ clocks = <&cpuclk 0>;
+ clock-latency = <1000000>;
+ clock-names = "cpu0";
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
+ clocks = <&cpuclk 0>;
+ clock-latency = <1000000>;
+ clock-names = "cpu1";
};
};
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -384,6 +384,15 @@
#clock-cells = <1>;
};
+ cpuclk: clock-complex@18700 {
+ compatible = "marvell,armada-380-cpu-clock",
+ "marvell,armada-xp-cpu-clock";
+ reg = <0x18700 0xA0>, <0x1c054 0x40>,
+ <0xe4260 0x8>;
+ clocks = <&coreclk 1>;
+ #clock-cells = <1>;
+ };
+
mbusc: mbus-controller@20000 {
compatible = "marvell,mbus-controller";
reg = <0x20000 0x100>, <0x20180 0x20>,

25
patch/kernel/mvebu-dev/disabled/806-disable-clocksource.patch
View File

@ -1,25 +0,0 @@
Revert upstream patch that enabled new clocksources.
Signed-off-by: Hannu Nyman <hannu.nyman@iki.fi>
Upstream patch to be reverted:
Subject: ARM: mvebu: enable ARM_GLOBAL_TIMER compilation Armada 38x platforms
Armada 38x SoCs along with legacy timer (time-armada-370-xp.c),
comprise generic Cortex-A9 global timer (arm_global_timer.c).
Enable its compilation. The system clocksource subsystem
will pick one of above two available ones in case the global
timer node is present in the device tree.
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -59,8 +59,6 @@ config MACH_ARMADA_38X
select ARM_ERRATA_720789
select PL310_ERRATA_753970
select ARM_GIC
- select ARM_GLOBAL_TIMER
- select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
select ARMADA_370_XP_IRQ
select ARMADA_38X_CLK
select HAVE_ARM_SCU

10
patch/kernel/mvebu-dev/dts-disable-spi-flash-on-a388-microsom.patch
View File

@ -1,10 +0,0 @@
--- a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
@@ -107,6 +107,7 @@
compatible = "w25q32", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <3000000>;
+ status = "disabled";
};
};

11
patch/kernel/mvebu-dev/general-increasing_DMA_block_memory_allocation_to_2048.patch
View File

@ -1,11 +0,0 @@
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -315,7 +315,7 @@ static void *__alloc_remap_buffer(struct
pgprot_t prot, struct page **ret_page,
const void *caller, bool want_vaddr);
-#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
+#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_2M
static struct gen_pool *atomic_pool __ro_after_init;
static size_t atomic_pool_size __initdata = DEFAULT_DMA_COHERENT_POOL_SIZE;

70
patch/kernel/mvebu-dev/unlock_atheros_regulatory_restrictions.patch
View File

@ -1,70 +0,0 @@
--- a/drivers/net/wireless/ath/regd.c
+++ b/drivers/net/wireless/ath/regd.c
@@ -50,12 +50,9 @@ static int __ath_regd_init(struct ath_re
#define ATH_5GHZ_5725_5850 REG_RULE(5725-10, 5850+10, 80, 0, 30,\
NL80211_RRF_NO_IR)
-#define ATH_2GHZ_ALL ATH_2GHZ_CH01_11, \
- ATH_2GHZ_CH12_13, \
- ATH_2GHZ_CH14
+#define ATH_2GHZ_ALL REG_RULE(2400, 2483, 40, 0, 30, 0)
-#define ATH_5GHZ_ALL ATH_5GHZ_5150_5350, \
- ATH_5GHZ_5470_5850
+#define ATH_5GHZ_ALL REG_RULE(5140, 5860, 40, 0, 30, 0)
/* This one skips what we call "mid band" */
#define ATH_5GHZ_NO_MIDBAND ATH_5GHZ_5150_5350, \
@@ -77,9 +74,8 @@ static const struct ieee80211_regdomain
.n_reg_rules = 4,
.alpha2 = "99",
.reg_rules = {
- ATH_2GHZ_CH01_11,
- ATH_2GHZ_CH12_13,
- ATH_5GHZ_NO_MIDBAND,
+ ATH_2GHZ_ALL,
+ ATH_5GHZ_ALL,
}
};
@@ -88,8 +84,8 @@ static const struct ieee80211_regdomain
.n_reg_rules = 3,
.alpha2 = "99",
.reg_rules = {
- ATH_2GHZ_CH01_11,
- ATH_5GHZ_NO_MIDBAND,
+ ATH_2GHZ_ALL,
+ ATH_5GHZ_ALL,
}
};
@@ -98,7 +94,7 @@ static const struct ieee80211_regdomain
.n_reg_rules = 3,
.alpha2 = "99",
.reg_rules = {
- ATH_2GHZ_CH01_11,
+ ATH_2GHZ_ALL,
ATH_5GHZ_ALL,
}
};
@@ -108,8 +104,7 @@ static const struct ieee80211_regdomain
.n_reg_rules = 4,
.alpha2 = "99",
.reg_rules = {
- ATH_2GHZ_CH01_11,
- ATH_2GHZ_CH12_13,
+ ATH_2GHZ_ALL,
ATH_5GHZ_ALL,
}
};
@@ -258,9 +253,7 @@ static bool ath_is_radar_freq(u16 center
struct ath_regulatory *reg)
{
- if (reg->country_code == CTRY_INDIA)
- return (center_freq >= 5500 && center_freq <= 5700);
- return (center_freq >= 5260 && center_freq <= 5700);
+ return false;
}
static void ath_force_clear_no_ir_chan(struct wiphy *wiphy,

39
patch/kernel/mvebu-dev/use-1000BaseX-clearfog-switch.patch
View File

@ -1,39 +0,0 @@
From 219f80b5cc03dab87fd05210b95c0b1a5afa8d33 Mon Sep 17 00:00:00 2001
From: Russell King <rmk+kernel@armlinux.org.uk>
Date: Thu, 14 Jul 2016 15:31:42 +0100
Subject: ARM: dts: armada388-clearfog: use 1000BaseX mode for 88e6176 switch
Use 1000BaseX mode for the 88e6176 switch, which allows mvneta to
negotiate correctly without needing to be forced.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
arch/arm/boot/dts/armada-388-clearfog.dts | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
@@ -47,10 +47,8 @@
&eth1 {
/* ethernet@30000 */
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
+ phy-mode = "1000base-x";
+ managed = "in-band-status";
};
&expander0 {
@@ -131,10 +129,6 @@
reg = <5>;
label = "cpu";
ethernet = <&eth1>;
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
};
port@6 {

62
patch/kernel/mvebu-dev/wifi-4003-fix-sha256_state-clashes.patch
View File

@ -1,62 +0,0 @@
diff --git a/drivers/net/wireless/rtl8811cu/include/rtw_security.h b/drivers/net/wireless/rtl8811cu/include/rtw_security.h
index ac8432e..5f74fb7 100755
--- a/drivers/net/wireless/rtl8811cu/include/rtw_security.h
+++ b/drivers/net/wireless/rtl8811cu/include/rtw_security.h
@@ -249,7 +249,7 @@ struct security_priv {
#define SEC_IS_BIP_KEY_INSTALLED(sec) _FALSE
#endif
-struct sha256_state {
+struct rtl_sha256_state {
u64 length;
u32 state[8], curlen;
u8 buf[64];
diff --git a/drivers/net/wireless/rtl8811cu/core/rtw_security.c b/drivers/net/wireless/rtl8811cu/core/rtw_security.c
index b537a26..f8c42f4 100755
--- a/drivers/net/wireless/rtl8811cu/core/rtw_security.c
+++ b/drivers/net/wireless/rtl8811cu/core/rtw_security.c
@@ -2133,7 +2133,7 @@ BIP_exit:
#ifndef PLATFORM_FREEBSD
#if defined(CONFIG_TDLS)
/* compress 512-bits */
-static int sha256_compress(struct sha256_state *md, unsigned char *buf)
+static int sha256_compress(struct rtl_sha256_state *md, unsigned char *buf)
{
u32 S[8], W[64], t0, t1;
u32 t;
@@ -2181,7 +2181,7 @@ static int sha256_compress(struct sha256_state *md, unsigned char *buf)
}
/* Initialize the hash state */
-static void sha256_init(struct sha256_state *md)
+static void sha256_init(struct rtl_sha256_state *md)
{
md->curlen = 0;
md->length = 0;
@@ -2202,7 +2202,7 @@ static void sha256_init(struct sha256_state *md)
@param inlen The length of the data (octets)
@return CRYPT_OK if successful
*/
-static int sha256_process(struct sha256_state *md, unsigned char *in,
+static int sha256_process(struct rtl_sha256_state *md, unsigned char *in,
unsigned long inlen)
{
unsigned long n;
@@ -2243,7 +2243,7 @@ static int sha256_process(struct sha256_state *md, unsigned char *in,
@param out [out] The destination of the hash (32 bytes)
@return CRYPT_OK if successful
*/
-static int sha256_done(struct sha256_state *md, unsigned char *out)
+static int sha256_done(struct rtl_sha256_state *md, unsigned char *out)
{
int i;
@@ -2293,7 +2293,7 @@ static int sha256_done(struct sha256_state *md, unsigned char *out)
static int sha256_vector(size_t num_elem, u8 *addr[], size_t *len,
u8 *mac)
{
- struct sha256_state ctx;
+ struct rtl_sha256_state ctx;
size_t i;
sha256_init(&ctx);

59
patch/kernel/mvebu-dev/wifi-4004-fix-cfg80211-for-5.8.patch
View File

@ -1,59 +0,0 @@
diff --git a/drivers/net/wireless/rtl8811cu/os_dep/linux/ioctl_cfg80211.c b/drivers/net/wireless/rtl8811cu/os_dep/linux/ioctl_cfg80211.c
index c0df148..9bff924 100755
--- a/drivers/net/wireless/rtl8811cu/os_dep/linux/ioctl_cfg80211.c
+++ b/drivers/net/wireless/rtl8811cu/os_dep/linux/ioctl_cfg80211.c
@@ -7143,6 +7143,33 @@ exit:
return ret;
}
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0))
+
+static void
+cfg80211_rtw_update_mgmt_frame_registrations(struct wiphy *wiphy,
+ struct wireless_dev *wdev,
+ struct mgmt_frame_regs *upd)
+{
+ struct net_device *ndev = wdev_to_ndev(wdev);
+ struct rtw_wdev_priv *pwdev_priv;
+ _adapter *adapter;
+
+ if (ndev == NULL)
+ return;
+
+ adapter = (_adapter *)rtw_netdev_priv(ndev);
+ pwdev_priv = adapter_wdev_data(adapter);
+
+#ifdef CONFIG_DEBUG_CFG80211
+ RTW_INFO(FUNC_ADPT_FMT" stypes:%x\n", FUNC_ADPT_ARG(adapter),
+ upd->interface_stypes);
+#endif
+
+ /* not implemented, see bellow */
+}
+
+#else
+
static void cfg80211_rtw_mgmt_frame_register(struct wiphy *wiphy,
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
struct wireless_dev *wdev,
@@ -7187,6 +7214,8 @@ exit:
return;
}
+#endif
+
#if defined(CONFIG_TDLS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0))
static int cfg80211_rtw_tdls_mgmt(struct wiphy *wiphy,
struct net_device *ndev,
@@ -9457,7 +9486,11 @@ static struct cfg80211_ops rtw_cfg80211_ops = {
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)
.mgmt_tx = cfg80211_rtw_mgmt_tx,
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0))
+ .update_mgmt_frame_registrations = cfg80211_rtw_update_mgmt_frame_registrations,
+#else
.mgmt_frame_register = cfg80211_rtw_mgmt_frame_register,
+#endif
#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34) && LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35))
.action = cfg80211_rtw_mgmt_tx,
#endif