diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-common.dtsi
index 7cff5d61..d2e1334b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-common.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-common.dtsi
@@ -67,24 +67,6 @@
 		model = "NanoPi 4 Series";
 	};
 
-	fiq_debugger: fiq-debugger {
-		compatible = "rockchip,fiq-debugger";
-		rockchip,serial-id = <2>;
-		rockchip,signal-irq = <182>;
-		rockchip,wake-irq = <0>;
-		rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
-		rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
-		pinctrl-names = "default";
-		pinctrl-0 = <&uart2c_xfer>;
-	};
-
-	xin32k: xin32k {
-		compatible = "fixed-clock";
-		clock-frequency = <32768>;
-		clock-output-names = "xin32k";
-		#clock-cells = <0>;
-	};
-
 	clkin_gmac: external-gmac-clock {
 		compatible = "fixed-clock";
 		clock-frequency = <125000000>;
@@ -475,14 +457,8 @@
 	status = "okay";
 };
 
-&uart4 {
-	status = "okay";
-};
-
 &vopb {
 	status = "okay";
-	assigned-clocks = <&cru DCLK_VOP0_DIV>;
-	assigned-clock-parents = <&cru PLL_VPLL>;
 };
 
 &vopb_mmu {
@@ -491,8 +467,6 @@
 
 &vopl {
 	status = "okay";
-	assigned-clocks = <&cru DCLK_VOP1_DIV>;
-	assigned-clock-parents = <&cru PLL_CPLL>;
 };
 
 &vopl_mmu {
@@ -511,18 +485,13 @@
 	//allocator = <0>;
 };
 
-&rga {
-	status = "okay";
-};
-
 &display_subsystem {
 	status = "okay";
 };
 
 &edp {
-	status = "okay";
+	status = "disabled";
 	force-hpd;
-	/delete-property/ pinctrl-0;
 
 	ports {
 		port@1 {
@@ -535,45 +504,28 @@
 	};
 };
 
-&edp_in_vopb {
+&edp_in_vopl {
 	status = "disabled";
 };
 
 &route_edp {
 	status = "okay";
-	logo,mode = "center";
-	connect = <&vopl_out_edp>;
 };
 
 &cdn_dp {
-	status = "okay";
+	status = "disabled";
 	extcon = <&fusb0>;
 	phys = <&tcphy0_dp>;
 };
 
-&dp_in_vopl {
-	status = "disabled";
-};
-
-&hdmi_in_vopl {
-	status = "disabled";
-};
-
 &hdmi {
-	/* remove the hdmi_i2c_xfer */
-	pinctrl-0 = <&hdmi_cec>;
+	/* remove the hdmi_cec, reused by edp_hpd */
+	pinctrl-0 = <&hdmi_i2c_xfer>;
 	#address-cells = <1>;
 	#size-cells = <0>;
 	#sound-dai-cells = <0>;
 	status = "okay";
 	ddc-i2c-bus = <&i2c7>;
-	rockchip,defaultmode = <16>; /* CEA 1920x1080@60Hz */
-};
-
-&route_hdmi {
-	status = "disabled";
-	logo,mode = "center";
-	connect = <&vopb_out_hdmi>;
 };
 
 &cif_isp0 {
@@ -848,13 +800,11 @@
 		compatible = "omnivision,ov13850-v4l2-i2c-subdev";
 		reg = <0x10>;
 		device_type = "v4l2-i2c-subdev";
-
 		clocks = <&cru SCLK_CIF_OUT>;
 		clock-names = "clk_cif_out";
 		pinctrl-names = "rockchip,camera_default", "rockchip,camera_sleep";
 		pinctrl-0 = <&cam0_default_pins>;
 		pinctrl-1 = <&cam0_sleep_pins>;
-
 		rockchip,pd-gpio = <&gpio2 28 GPIO_ACTIVE_LOW>;
 		rockchip,rst-gpio = <&gpio2 27 GPIO_ACTIVE_LOW>;
 
@@ -939,11 +889,6 @@
 	#sound-dai-cells = <0>;
 };
 
-&i2s1 {
-	assigned-clocks = <&cru SCLK_I2S_8CH>;
-	assigned-clock-parents = <&cru SCLK_I2S1_8CH>;
-};
-
 &i2s2 {
 	#sound-dai-cells = <0>;
 	status = "okay";
@@ -968,9 +913,16 @@
 };
 
 &pcie0 {
-	status = "okay";
-	ep-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
-	num-lanes = <4>;
+       assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
+       assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
+       assigned-clock-rates = <100000000>;
+       status = "okay";
+       ep-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
+       num-lanes = <4>;
+       vpcie3v3-supply = <&vcc3v3_sys>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie_clkreqn_cpm>;
+       max-link-speed = <2>;
 };
 
 &pwm_bl {
@@ -1154,14 +1106,6 @@
 };
 
 &pinctrl {
-	edp {
-		/delete-node/ edp-hpd;
-	};
-
-	hdmi {
-		/delete-node/ hdmi-i2c-xfer;
-	};
-
 	pmic {
 		pmic_int_l: pmic-int-l {
 			rockchip,pins = <1 21 RK_FUNC_GPIO &pcfg_pull_up>;