diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 1524130..58b5973 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -51,29 +51,51 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "allwinner,sun6i-a31"; cpu@0 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; +// enable-method = "psci"; }; cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; +// enable-method = "psci"; }; cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; +// enable-method = "psci"; }; cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; +// enable-method = "psci"; + }; + }; + +//from A64 +// psci { +// compatible = "arm,psci-0.2", "arm,psci"; +// method = "smc"; +//// cpu_suspend = <0xc4000001>; +//// cpu_off = <0x84000002>; +//// cpu_on = <0xc4000003>; +// }; + + thermal-zones { + cpu_thermal: cpu_thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&ths 0>; }; }; @@ -83,6 +105,9 @@ , , ; +// from hdg and jens + clock-frequency = <24000000>; + arm,cpu-registers-not-fw-configured; }; clocks { @@ -104,7 +129,7 @@ clock-output-names = "osc32k"; }; - pll1: clk@01c20000 { + pll1: clk@01c20000 { /* PLL CPUX */ #clock-cells = <0>; compatible = "allwinner,sun8i-a23-pll1-clk"; reg = <0x01c20000 0x4>; @@ -112,6 +137,22 @@ clock-output-names = "pll1"; }; + pll2: clk@01c20008 { /* PLL_AUDIO */ + #clock-cells = <1>; + compatible = "allwinner,sun8i-h3-pll2-clk"; + reg = <0x01c20008 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll2", "pll2x2", "pll2x4", "pll2x8"; + }; + + pll3: clk@01c20010 { /* PLL_VIDEO */ + #clock-cells = <0>; + compatible = "allwinner,sun6i-pll3-clk"; + reg = <0x01c20010 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll3"; + }; + /* dummy clock until actually implemented */ pll5: pll5_clk { #clock-cells = <0>; @@ -120,29 +161,63 @@ clock-output-names = "pll5"; }; - pll6: clk@01c20028 { - #clock-cells = <1>; - compatible = "allwinner,sun6i-a31-pll6-clk"; + pll6x2: clk@01c20028 { + #clock-cells = <0>; + compatible = "allwinner,pll-periphx2-clk"; reg = <0x01c20028 0x4>; clocks = <&osc24M>; - clock-output-names = "pll6", "pll6x2"; + clock-output-names = "pll6x2"; }; - - pll6d2: pll6d2_clk { + pll6: pll6_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <2>; clock-mult = <1>; - clocks = <&pll6 0>; + clocks = <&pll6x2>; + clock-output-names = "pll6"; + assigned-clocks = <&pll6x2>; + assigned-clock-rates = <1200000000>; + }; + pll6d2: pll6d2_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <4>; + clock-mult = <1>; + clocks = <&pll6x2>; clock-output-names = "pll6d2"; }; - /* dummy clock until pll6 can be reused */ + pll8x2: clk@01c20044 { /* PLL_PERIPH1 */ + #clock-cells = <0>; + compatible = "allwinner,pll-periphx2-clk"; + reg = <0x01c20044 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll8x2"; + }; pll8: pll8_clk { #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <2>; + clock-mult = <1>; + clocks = <&pll8x2>; + clock-output-names = "pll8"; + assigned-clocks = <&pll8x2>; + assigned-clock-rates = <1200000000>; + }; + + pll10: clk@01c20048 { /* PLL_DE */ + #clock-cells = <0>; + compatible = "allwinner,sun6i-pll3-clk"; + reg = <0x01c20048 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll10"; + }; + + dum: dum_clk { /* (don't use) */ + #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <1>; - clock-output-names = "pll8"; + clock-output-names = "dum"; }; cpu: cpu_clk@01c20050 { @@ -165,8 +240,10 @@ #clock-cells = <0>; compatible = "allwinner,sun6i-a31-ahb1-clk"; reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>; clock-output-names = "ahb1"; + assigned-clocks = <&ahb1>; + assigned-clock-parents = <&pll6>; }; ahb2: ahb2_clk@01c2005c { @@ -175,6 +252,8 @@ reg = <0x01c2005c 0x4>; clocks = <&ahb1>, <&pll6d2>; clock-output-names = "ahb2"; + assigned-clocks = <&ahb2>; + assigned-clock-parents = <&ahb1>; }; apb1: apb1_clk@01c20054 { @@ -189,8 +268,11 @@ #clock-cells = <0>; compatible = "allwinner,sun4i-a10-apb1-clk"; reg = <0x01c20058 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; + clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; clock-output-names = "apb2"; +//fixme: does not work +// assigned-clocks = <&apb2>; +// assigned-clock-parents = <&osc24M>; }; bus_gates: clk@01c20060 { @@ -239,41 +321,126 @@ "bus_scr", "bus_ephy", "bus_dbg"; }; + ths_clk: clk@01c20074 { + #clock-cells = <0>; + compatible = "allwinner,sun8i-h3-ths-clk"; + reg = <0x01c20074 0x4>; + clocks = <&osc24M>; + clock-output-names = "ths"; + }; + mmc0_clk: clk@01c20088 { #clock-cells = <1>; compatible = "allwinner,sun4i-a10-mmc-clk"; reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 0>, <&pll8>; + clocks = <&osc24M>, <&pll6>, <&pll8>; clock-output-names = "mmc0", "mmc0_output", "mmc0_sample"; +//fixme: does not work +// assigned-clocks = <&mmc0_clk>; +// assigned-clock-parents = <&pll8>; }; mmc1_clk: clk@01c2008c { #clock-cells = <1>; compatible = "allwinner,sun4i-a10-mmc-clk"; reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6 0>, <&pll8>; + clocks = <&osc24M>, <&pll6>, <&pll8>; clock-output-names = "mmc1", "mmc1_output", "mmc1_sample"; +//fixme: does not work +// assigned-clocks = <&mmc1_clk>; +// assigned-clock-parents = <&pll8>; }; mmc2_clk: clk@01c20090 { #clock-cells = <1>; compatible = "allwinner,sun4i-a10-mmc-clk"; reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6 0>, <&pll8>; +//fixme: test pll8 - pll8 problem... + clocks = <&osc24M>, <&pll6>, <&pll8>; +// clocks = <&dum>, <&dum>, <&pll8>; clock-output-names = "mmc2", "mmc2_output", "mmc2_sample"; +//fixme: does not work +// assigned-clocks = <&mmc2_clk>; +// assigned-clock-parents = <&pll8>; + }; + + i2s2_clk: clk@01c200b8 { /* I2S/PCM 2 (HDMI) */ + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200b8 0x4>; +//fixme: to check again... +// clocks = <&pll2 3>, <&pll2 2>, <&pll2 1>, <&pll2 0>; + clocks = <&dum>, <&dum>, <&dum>, <&pll2 0>; + clock-output-names = "i2s2"; +//fixme: test +// assigned-clocks = <&pll2 0>; +// assigned-clock-rates = <24576000>; + }; + + usb_clk: clk@01c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun8i-h3-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&osc24M>; + clock-output-names = "usb_phy0", "usb_phy1", + "usb_phy2", "usb_phy3", + "usb_ohci0", "usb_ohci1", + "usb_ohci2", "usb_ohci3"; + }; + + de_clk: clk@01c20104 { + #clock-cells = <0>; + compatible = "allwinner,sun6i-display-clk"; + reg = <0x01c20104 0x4>; +//change with assigned-clocks + clocks = <&pll6x2>, <&pll10>; /* PERIPH0 x2, DE */ +// clocks = <&dum>, <&pll10>; /* force PLL DE only */ + clock-output-names = "de"; + assigned-clocks = <&de_clk>; + assigned-clock-parents = <&pll10>; + }; + + tcon0_clk: clk@1c20118 { + #clock-cells = <0>; + compatible = "allwinner,sun6i-display-clk"; + reg = <0x01c20118 0x4>; + clocks = <&pll3>; + clock-output-names = "tcon0"; + }; +// tve_clk: clk@01c20120 { +// #clock-cells = <0>; +// compatible = "allwinner,sun6i-display-clk"; +// reg = <0x01c20120 0x4>; +// clocks = <&pll10>, <&pll8>; /* DE, PERIPH1 */ +// clock-output-names = "tve"; +// }; + hdmi_clk: clk@01c20150 { + #clock-cells = <0>; + compatible = "allwinner,sun6i-display-clk"; + reg = <0x01c20150 0x4>; + clocks = <&pll3>; + clock-output-names = "hdmi"; + }; + hdmi_slow_clk: clk@01c20154 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-codec-clk"; + reg = <0x01c20154 0x4>; + clocks = <&osc24M>; + clock-output-names = "hdmi-slow"; }; mbus_clk: clk@01c2015c { #clock-cells = <0>; compatible = "allwinner,sun8i-a23-mbus-clk"; reg = <0x01c2015c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5>; + clocks = <&osc24M>, <&pll6x2>, <&pll5>; clock-output-names = "mbus"; }; }; @@ -284,6 +451,18 @@ #size-cells = <1>; ranges; + de: de-controller@01000000 { + compatible = "allwinner,sun8i-h3-display-engine"; + reg = <0x01000000 0x400000>; + clocks = <&bus_gates 44>, <&de_clk>; + clock-names = "gate", "clock"; + resets = <&ahb_rst 44>; +//fixme: tv to be added +// ports = <&lcd0_p>, <&lcd1_p>; + ports = <&lcd0_p>; + status = "disabled"; + }; + dma: dma-controller@01c02000 { compatible = "allwinner,sun8i-h3-dma"; reg = <0x01c02000 0x1000>; @@ -293,6 +472,42 @@ #dma-cells = <1>; }; + lcd0: lcd-controller@01c0c000 { + compatible = "allwinner,sun8i-h3-lcd"; +// reg = <0x01c0c000 0x1000>; + reg = <0x01c0c000 0x400>; + clocks = <&bus_gates 35>, <&tcon0_clk>; + clock-names = "gate", "clock"; + resets = <&ahb_rst 35>; + interrupts = ; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + lcd0_p: port { + lcd0_ep: endpoint { + remote-endpoint = <&hdmi_ep>; + }; + }; + }; + +// lcd1: lcd-controller@01c0d000 { +// compatible = "allwinner,sun8i-h3-lcd"; +//// reg = <0x01c0d000 0x1000>; +// reg = <0x01c0d000 0x400>; +// clocks = <&bus_gates 36>, <&??>; +// clock-names = "gate", "clock"; +// resets = <&ahb_rst 36>; +// interrupts = ; +// status = "disabled"; +// #address-cells = <1>; +// #size-cells = <0>; +// lcd1_p: port { +// lcd1_ep: endpoint { +// remote-endpoint = <&tve_ep>; +// }; +// }; +// }; + mmc0: mmc@01c0f000 { compatible = "allwinner,sun5i-a13-mmc"; reg = <0x01c0f000 0x1000>; @@ -308,8 +523,8 @@ reset-names = "ahb"; interrupts = ; status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; +// #address-cells = <1>; +// #size-cells = <0>; }; mmc1: mmc@01c10000 { @@ -327,8 +542,8 @@ reset-names = "ahb"; interrupts = ; status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; +// #address-cells = <1>; +// #size-cells = <0>; }; mmc2: mmc@01c11000 { @@ -346,8 +561,136 @@ reset-names = "ahb"; interrupts = ; status = "disabled"; +// #address-cells = <1>; +// #size-cells = <0>; + }; + + sid: eeprom@01c14000 { + compatible = "allwinner,sun4i-a10-sid"; + reg = <0x01c14000 0x400>; #address-cells = <1>; - #size-cells = <0>; + #size-cells = <1>; + + ths_calibration: calib@234 { + reg = <0x234 0x4>; + }; + }; + +//fixme: to see later +//?? otg not described +// usb_otg: usb@01c19000 { +// compatible = "allwinner,sun8i-a33-musb"; +// reg = <0x01c19000 0x0458>; +// clocks = <&bus_gates 23>; +// resets = <&ahb_rst 23>; +////?? +// interrupts = ; +// interrupt-names = "mc"; +// phys = <&usbphy 0>; +// phy-names = "usb"; +// extcon = <&usbphy 0>; +// status = "disabled"; +// }; +// + usbphy: phy@01c19400 { + compatible = "allwinner,sun8i-h3-usb-phy"; + reg = <0x01c19400 0x2c>, + <0x01c1a800 0x4>, + <0x01c1b800 0x4>, + <0x01c1c800 0x4>, + <0x01c1d800 0x4>; + reg-names = "phy_ctrl", + "pmu0", + "pmu1", + "pmu2", + "pmu3"; + clocks = <&usb_clk 8>, + <&usb_clk 9>, + <&usb_clk 10>, + <&usb_clk 11>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy", + "usb3_phy"; + resets = <&usb_clk 0>, + <&usb_clk 1>, + <&usb_clk 2>, + <&usb_clk 3>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset", + "usb3_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci1: usb@01c1b000 { + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; + reg = <0x01c1b000 0x100>; + interrupts = ; + clocks = <&bus_gates 25>, <&bus_gates 29>; + resets = <&ahb_rst 25>, <&ahb_rst 29>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@01c1b400 { + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; + reg = <0x01c1b400 0x100>; + interrupts = ; + clocks = <&bus_gates 29>, <&bus_gates 25>, + <&usb_clk 17>; + resets = <&ahb_rst 29>, <&ahb_rst 25>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci2: usb@01c1c000 { + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; + reg = <0x01c1c000 0x100>; + interrupts = ; + clocks = <&bus_gates 26>, <&bus_gates 30>; + resets = <&ahb_rst 26>, <&ahb_rst 30>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci2: usb@01c1c400 { + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; + reg = <0x01c1c400 0x100>; + interrupts = ; + clocks = <&bus_gates 30>, <&bus_gates 26>, + <&usb_clk 18>; + resets = <&ahb_rst 30>, <&ahb_rst 26>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci3: usb@01c1d000 { + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; + reg = <0x01c1d000 0x100>; + interrupts = ; + clocks = <&bus_gates 27>, <&bus_gates 31>; + resets = <&ahb_rst 27>, <&ahb_rst 31>; + phys = <&usbphy 3>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci3: usb@01c1d400 { + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; + reg = <0x01c1d400 0x100>; + interrupts = ; + clocks = <&bus_gates 31>, <&bus_gates 27>, + <&usb_clk 19>; + resets = <&ahb_rst 31>, <&ahb_rst 27>; + phys = <&usbphy 3>; + phy-names = "usb"; + status = "disabled"; }; pio: pinctrl@01c20800 { @@ -359,7 +702,7 @@ gpio-controller; #gpio-cells = <3>; interrupt-controller; - #interrupt-cells = <2>; + #interrupt-cells = <3>; uart0_pins_a: uart0@0 { allwinner,pins = "PA4", "PA5"; @@ -424,6 +767,29 @@ interrupts = ; }; + i2s2: i2s@1c22800 { + compatible = "allwinner,sun8i-h3-hdmi-audio"; + reg = <0x01c22800 0x60>; + resets = <&apb1_rst 14>; + clocks = <&bus_gates 78>, <&pll2 0>, <&i2s2_clk>; + clock-names = "gate", "clock", "i2s2"; + dmas = <&dma 27>; + dma-names = "tx"; + status = "disabled"; + }; + + ths: ths@01c25000 { + #thermal-sensor-cells = <0>; + compatible = "allwinner,sun8i-h3-ths"; + reg = <0x01c25000 0x88>; + interrupts = ; + resets = <&apb1_rst 8>; + clocks = <&bus_gates 72>, <&ths_clk>; + clock-names = "ahb", "ths"; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + }; + uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; @@ -487,11 +853,101 @@ interrupts = ; }; +// tve { +// compatible = "allwinner,sun8i-h3-tve"; +// reg = <0x01e00000 0x10000>; +// clocks = <&bus_gates 41>, <&tve_clk>; +// clock-names = "gate", "clock"; +// resets = <&ahb_rst 41> +// status = "disabled"; +// #address-cells = <1>; +// #size-cells = <0>; +// port { +// tve_ep: endpoint { +// remote-endpoint = <&lcd1_ep>; +// }; +// }; +// }; + + hdmi: hdmi@01ee0000 { + compatible = "allwinner,sun8i-h3-hdmi"; + reg = <0x01ee0000 0x20000>; +//fixme: hack - see hdmi_slow_clk + clocks = <&bus_gates 43>, <&hdmi_clk>, + <&hdmi_slow_clk 31>; + clock-names = "gate", "clock", "ddc-clock"; + resets = <&ahb_rst 42>, <&ahb_rst 43>; + reset-names = "hdmi0", "hdmi1"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + port { + hdmi_ep: endpoint { + remote-endpoint = <&lcd0_ep>; + }; + }; + }; + rtc: rtc@01f00000 { compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01f00000 0x54>; interrupts = , ; }; + + prcm@01f01400 { + compatible = "allwinner,sun6i-a31-prcm"; + reg = <0x01f01400 0x200>; + + ar100: ar100_clk { + compatible = "allwinner,sun6i-a31-ar100-clk"; + #clock-cells = <0>; + clocks = <&osc32k>, <&osc24M>, <&pll6>, + <&pll6>; + clock-output-names = "ar100"; + }; + ahb0: ahb0_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&ar100>; + clock-output-names = "ahb0"; + }; + + apb0: apb0_clk { + compatible = "allwinner,sun6i-a31-apb0-clk"; + #clock-cells = <0>; + clocks = <&ahb0>; + clock-output-names = "apb0"; + }; + + apb0_gates: apb0_gates_clk { + compatible = "allwinner,sun6i-a31-apb0-gates-clk"; + #clock-cells = <1>; + clocks = <&apb0>; + clock-output-names = "apb0_pio", "apb0_ir", + "apb0_timer", "apb0_p2wi", + "apb0_uart", "apb0_1wire", + "apb0_i2c"; + }; + +// ir_clk: ir_clk { +// #clock-cells = <0>; +// compatible = "allwinner,sun4i-a10-mod0-clk"; +// clocks = <&osc32k>, <&osc24M>; +// clock-output-names = "ir"; +// }; + + apb0_rst: apb0_rst { + compatible = "allwinner,sun6i-a31-clock-reset"; + #reset-cells = <1>; + }; + }; + + cpucfg@01f01c00 { + compatible = "allwinner,sun6i-a31-cpuconfig"; + reg = <0x01f01c00 0x300>; + }; }; };