From 80d4cec4cef8282e5ac3aaf98ce3e68fb299a134 Mon Sep 17 00:00:00 2001 From: Terry Zhou Date: Mon, 29 Jan 2018 15:01:31 +0800 Subject: [PATCH] clk: mvebu: a3700: fix the XTAL MODE pin to SB MPP9 There is an error in the current code that the XTAL MODE pin was set to SB MPP31 which should be SB MPP9 The latch register of SB MPP9 has different offset of 0x8 Change-Id: I73d41d0c053808fd18944ed1d191aea817b6d21a Signed-off-by: Terry Zhou --- drivers/clk/mvebu/armada-37xx-xtal.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mvebu/armada-37xx-xtal.c b/drivers/clk/mvebu/armada-37xx-xtal.c index 612d65ede10a..5370514959e1 100644 --- a/drivers/clk/mvebu/armada-37xx-xtal.c +++ b/drivers/clk/mvebu/armada-37xx-xtal.c @@ -15,8 +15,8 @@ #include #include -#define NB_GPIO1_LATCH 0xC -#define XTAL_MODE BIT(31) +#define NB_GPIO1_LATCH 0x8 +#define XTAL_MODE BIT(9) static int armada_3700_xtal_clock_probe(struct platform_device *pdev) {