From ff98a0098fd1dccf92bc42b36755a9a082d44292 Mon Sep 17 00:00:00 2001 From: zador-blood-stained Date: Tue, 21 Mar 2017 20:26:38 +0300 Subject: [PATCH] Update overlays Add PPS overlays Add overlays for A10 SoC --- patch/kernel/sun8i-dev/add-h3-overlays.patch | 93 +- .../kernel/sunxi-next/add-a20-overlays.patch | 1451 ++++++++++++++++- 2 files changed, 1514 insertions(+), 30 deletions(-) diff --git a/patch/kernel/sun8i-dev/add-h3-overlays.patch b/patch/kernel/sun8i-dev/add-h3-overlays.patch index 376c5fba97..251e997bf9 100644 --- a/patch/kernel/sun8i-dev/add-h3-overlays.patch +++ b/patch/kernel/sun8i-dev/add-h3-overlays.patch @@ -12,10 +12,10 @@ index 01d178a2..bfba239c 100644 +dts-dirs += overlay diff --git a/arch/arm/boot/dts/overlay/Makefile b/arch/arm/boot/dts/overlay/Makefile new file mode 100644 -index 00000000..e4d038d5 +index 00000000..0543d20d --- /dev/null +++ b/arch/arm/boot/dts/overlay/Makefile -@@ -0,0 +1,30 @@ +@@ -0,0 +1,31 @@ +ifeq ($(CONFIG_OF_CONFIGFS),y) + +dtbo-$(CONFIG_MACH_SUN8I) += \ @@ -25,6 +25,7 @@ index 00000000..e4d038d5 + sun8i-h3-i2c1.dtbo \ + sun8i-h3-i2c2.dtbo \ + sun8i-h3-i2c-ds1307.dtbo \ ++ sun8i-h3-pps-gpio.dtbo \ + sun8i-h3-spi-jedec-nor.dtbo \ + sun8i-h3-spi-mcp2515.dtbo \ + sun8i-h3-spi-spidev.dtbo \ @@ -48,10 +49,10 @@ index 00000000..e4d038d5 +clean-files := *.dtbo *.scr diff --git a/arch/arm/boot/dts/overlay/README.sun8i-h3-overlays b/arch/arm/boot/dts/overlay/README.sun8i-h3-overlays new file mode 100644 -index 00000000..195a25d2 +index 00000000..956be7b5 --- /dev/null +++ b/arch/arm/boot/dts/overlay/README.sun8i-h3-overlays -@@ -0,0 +1,214 @@ +@@ -0,0 +1,242 @@ +This document describes overlays provided in the kernel packages +For generic Armbian overlays documentation please see +https://docs.armbian.com/Hardware_Allwinner_overlays/ @@ -79,6 +80,7 @@ index 00000000..195a25d2 +- i2c1 +- i2c2 +- i2c-ds1307 ++- pps-gpio +- spi-jedec-nor +- spi-mcp2515 +- spi-spidev @@ -134,6 +136,24 @@ index 00000000..195a25d2 + Required + Supported values: 0, 1, 2 + ++### pps-gpio ++ ++Activates pulse-per-second GPIO client ++ ++Parameters: ++ ++param_pps_pin (pin) ++ Pin PPS source is connected to ++ Optional ++ Default: PD14 ++ ++param_pps_falling_edge (bool) ++ Assert by falling edge ++ Optional ++ Default: 0 ++ When set (to 1), assert is indicated by a falling edge ++ (instead of by a rising edge) ++ +### spi-jedec-nor + +Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus @@ -151,6 +171,7 @@ index 00000000..195a25d2 + +param_spinor_max_freq (int) + Maximum SPI frequency ++ Optional + Default: 1000000 + Range: 3000 - 100000000 + @@ -170,11 +191,13 @@ index 00000000..195a25d2 + +param_mcp2515_clk_freq (int) + Onboard oscillator clock frequency ++ Optional + Default: 8000000 + Typical values: 8000000, 16000000 + +param_mcp2515_int_pin (pin) + Interrupt pin ++ Optional + Default: PA7 + Selected pin should support interrupts (EINT) + @@ -195,6 +218,7 @@ index 00000000..195a25d2 + +param_spidev_max_freq (int) + Maximum SPIdev frequency ++ Optional + Default: 1000000 + Range: 3000 - 100000000 + @@ -208,6 +232,7 @@ index 00000000..195a25d2 + +param_uart1_rtscts (bool) + Enable RTS and CTS pins ++ Optional + Default: 0 + Set to 1 to enable + @@ -221,6 +246,7 @@ index 00000000..195a25d2 + +param_uart2_rtscts (bool) + Enable RTS and CTS pins ++ Optional + Default: 0 + Set to 1 to enable CTS and RTS pins + @@ -234,6 +260,7 @@ index 00000000..195a25d2 + +param_uart3_rtscts (bool) + Enable RTS and CTS pins ++ Optional + Default: 0 + Set to 1 to enable CTS and RTS pins + @@ -258,14 +285,16 @@ index 00000000..195a25d2 + +param_w1_pin (pin) + Data pin for 1-Wire master ++ Optional + Default: PD14 + +param_w1_pin_int_pullup (bool) + Enable internal pull-up for the data pin -+ This option should not be used with multiple devices, parasite power setup -+ or long wires - please use external pull-up resistor instead ++ Optional + Default: 0 + Set to 1 to enable the pull-up ++ This option should not be used with multiple devices, parasite power setup ++ or long wires - please use external pull-up resistor instead diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-analog-codec.dts b/arch/arm/boot/dts/overlay/sun8i-h3-analog-codec.dts new file mode 100644 index 00000000..ddcd8e84 @@ -310,10 +339,10 @@ index 00000000..f611d823 +}; diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-fixup.scr-cmd b/arch/arm/boot/dts/overlay/sun8i-h3-fixup.scr-cmd new file mode 100644 -index 00000000..9d6540ed +index 00000000..5d9b5d5d --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun8i-h3-fixup.scr-cmd -@@ -0,0 +1,137 @@ +@@ -0,0 +1,151 @@ +# overlays fixup script +# implements (or rather substitutes) overlay arguments functionality +# using u-boot scripting, environment variables and "fdt" command @@ -411,6 +440,20 @@ index 00000000..9d6540ed + env delete tmp_spi_path +fi + ++if test -n "${param_pps_pin}"; then ++ setenv tmp_bank "${param_pps_pin}" ++ setenv tmp_pin "${param_pps_pin}" ++ run decompose_pin ++ fdt set /soc/pinctrl@01c20800/pps_pins pins "${param_pps_pin}" ++ fdt get value tmp_phandle /soc/pinctrl@01c20800 phandle ++ fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_pps_falling_edge}" = "1"; then ++ fdt set /pps@0 assert-falling-edge ++fi ++ +if test -n "${param_w1_pin}"; then + setenv tmp_bank "${param_w1_pin}" + setenv tmp_pin "${param_w1_pin}" @@ -585,6 +628,40 @@ index 00000000..0e1de089 + }; + }; +}; +diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-pps-gpio.dts b/arch/arm/boot/dts/overlay/sun8i-h3-pps-gpio.dts +new file mode 100644 +index 00000000..79459304 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun8i-h3-pps-gpio.dts +@@ -0,0 +1,28 @@ ++/dts-v1/ /plugin/; ++ ++/ { ++ compatible = "allwinner,sun8i-h3"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ pps_pins: pps_pins { ++ pins = "PD14"; ++ function = "gpio_in"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ pps@0 { ++ compatible = "pps-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pps_pins>; ++ gpios = <&pio 3 14 0>; /* PD14 */ ++ status = "okay"; ++ }; ++ }; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-spi-jedec-nor.dts b/arch/arm/boot/dts/overlay/sun8i-h3-spi-jedec-nor.dts new file mode 100644 index 00000000..4df8a5ee diff --git a/patch/kernel/sunxi-next/add-a20-overlays.patch b/patch/kernel/sunxi-next/add-a20-overlays.patch index 90f8556af8..da7bab5e07 100644 --- a/patch/kernel/sunxi-next/add-a20-overlays.patch +++ b/patch/kernel/sunxi-next/add-a20-overlays.patch @@ -12,12 +12,32 @@ index 01d178a2..bfba239c 100644 +dts-dirs += overlay diff --git a/arch/arm/boot/dts/overlay/Makefile b/arch/arm/boot/dts/overlay/Makefile new file mode 100644 -index 00000000..3641753d +index 00000000..c271e599 --- /dev/null +++ b/arch/arm/boot/dts/overlay/Makefile -@@ -0,0 +1,34 @@ +@@ -0,0 +1,57 @@ +ifeq ($(CONFIG_OF_CONFIGFS),y) + ++dtbo-$(CONFIG_MACH_SUN4I) += \ ++ sun4i-a10-analog-codec.dtbo \ ++ sun4i-a10-can.dtbo \ ++ sun4i-a10-i2c1.dtbo \ ++ sun4i-a10-i2c2.dtbo \ ++ sun4i-a10-i2c-ds1307.dtbo \ ++ sun4i-a10-nand.dtbo \ ++ sun4i-a10-pps-gpio.dtbo \ ++ sun4i-a10-spdif-out.dtbo \ ++ sun4i-a10-spi-jedec-nor.dtbo \ ++ sun4i-a10-spi-mcp2515.dtbo \ ++ sun4i-a10-spi-spidev.dtbo \ ++ sun4i-a10-uart2.dtbo \ ++ sun4i-a10-uart3.dtbo \ ++ sun4i-a10-uart4.dtbo \ ++ sun4i-a10-uart5.dtbo \ ++ sun4i-a10-uart6.dtbo \ ++ sun4i-a10-uart7.dtbo \ ++ sun4i-a10-w1-gpio.dtbo ++ +dtbo-$(CONFIG_MACH_SUN7I) += \ + sun7i-a20-analog-codec.dtbo \ + sun7i-a20-can.dtbo \ @@ -28,6 +48,7 @@ index 00000000..3641753d + sun7i-a20-i2c4.dtbo \ + sun7i-a20-i2c-ds1307.dtbo \ + sun7i-a20-nand.dtbo \ ++ sun7i-a20-pps-gpio.dtbo \ + sun7i-a20-spdif-out.dtbo \ + sun7i-a20-spi-jedec-nor.dtbo \ + sun7i-a20-spi-mcp2515.dtbo \ @@ -40,8 +61,10 @@ index 00000000..3641753d + sun7i-a20-uart7.dtbo \ + sun7i-a20-w1-gpio.dtbo + ++scr-$(CONFIG_MACH_SUN4I) += sun4i-a10-fixup.scr +scr-$(CONFIG_MACH_SUN7I) += sun7i-a20-fixup.scr + ++dtbotxt-$(CONFIG_MACH_SUN4I) += README.sun4i-a10-overlays +dtbotxt-$(CONFIG_MACH_SUN7I) += README.sun7i-a20-overlays + +targets += $(dtbo-y) $(scr-y) $(dtbotxt-y) @@ -50,12 +73,294 @@ index 00000000..3641753d + +always := $(dtbo-y) $(scr-y) $(dtbotxt-y) +clean-files := *.dtbo *.scr +diff --git a/arch/arm/boot/dts/overlay/README.sun4i-a10-overlays b/arch/arm/boot/dts/overlay/README.sun4i-a10-overlays +new file mode 100644 +index 00000000..befb0a3d +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/README.sun4i-a10-overlays +@@ -0,0 +1,276 @@ ++This document describes overlays provided in the kernel packages ++For generic Armbian overlays documentation please see ++https://docs.armbian.com/Hardware_Allwinner_overlays/ ++ ++### Platform: ++ ++sun4i-a10 (Allwinner A10) ++ ++### Platform details: ++ ++Supported pin banks: PB, PC, PD, PE, PG, PH, PI ++ ++SPI controller 0 have 2 exposed hardware CS, ++other SPI controllers have only one hardware CS ++Reference: A10 User manual section 17.4.13, A10 datasheet section 5.2 ++ ++I2C bus 0 is used for the AXP209 PMIC ++ ++### Provided overlays: ++ ++- analog-codec ++- can ++- i2c1 ++- i2c2 ++- i2c-ds1307 ++- nand ++- pps-gpio ++- spdif-out ++- spi-jedec-nor ++- spi-mcp2515 ++- spi-spidev ++- uart1 ++- uart2 ++- uart3 ++- uart4 ++- uart5 ++- uart6 ++- uart7 ++- w1-gpio ++ ++### Overlay details: ++ ++### analog-codec ++ ++Activates SoC analog codec driver that provides Line Out and Mic In ++functionality ++ ++## can ++ ++Activates SoC CAN controller ++ ++CAN pins (TX, RX): PH20, PH21 ++ ++### i2c1 ++ ++Activates TWI/I2C bus 1 ++ ++I2C1 pins (SCL, SDA): PB18, PB19 ++ ++### i2c2 ++ ++Activates TWI/I2C bus 2 ++ ++I2C2 pins (SCL, SDA): PB20, PB21 ++ ++### i2c-ds1307 ++ ++Activates Maxim/Dallas DS1307 RTC support ++ ++Parameters: ++ ++param_ds1307_i2c_bus (int) ++ I2C bus RTC is connected to ++ Required ++ Supported values: 0, 1, 2 ++ ++### nand ++ ++Activates NAND controller ++ ++This overlay should not be used until mainline MLC NAND support ++allows using NAND storage reliably ++ ++### pps-gpio ++ ++Activates pulse-per-second GPIO client ++ ++Parameters: ++ ++param_pps_pin (pin) ++ Pin PPS source is connected to ++ Optional ++ Default: PI15 ++ ++param_pps_falling_edge (bool) ++ Assert by falling edge ++ Optional ++ Default: 0 ++ When set (to 1), assert is indicated by a falling edge ++ (instead of by a rising edge) ++ ++### spdif-out ++ ++Activates SPDIF/Toslink audio output ++ ++SPDIF pin: PB13 ++ ++### spi-jedec-nor ++ ++Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus ++supported by the kernel SPI NOR driver ++ ++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 ++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 ++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 ++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 ++ ++Parameters: ++ ++param_spinor_spi_bus (int) ++ SPI bus to activate SPI NOR flash support on ++ Required ++ Supported values: 0, 1, 2 ++ ++param_spi2_bus_pins (char) ++ SPI bus 2 pinmux variant ++ Optional ++ Default: a ++ Supported values: a, b ++ Determines what pins SPI bus 2 is exposed on if SPI 2 is used by any overlay ++ ++param_spinor_max_freq (int) ++ Maximum SPI frequency ++ Optional ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ ++### spi-mcp2515 ++ ++Activates mcp2515 SPI CAN controller connected to SPI bus ++ ++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 ++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 ++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 ++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 ++ ++Parameters: ++ ++param_mcp2515_spi_bus (int) ++ SPI bus to activate mcp2515 support on ++ Required ++ Supported values: 0, 1, 2 ++ ++param_spi2_bus_pins (char) ++ SPI bus 2 pinmux variant ++ Optional ++ Default: a ++ Supported values: a, b ++ Determines what pins SPI bus 2 is exposed on if SPI 2 is used by any overlay ++ ++param_mcp2515_clk_freq (int) ++ Onboard oscillator clock frequency ++ Optional ++ Default: 8000000 ++ Typical values: 8000000, 16000000 ++ ++param_mcp2515_int_pin (pin) ++ Interrupt pin ++ Optional ++ Default: PH15 ++ Selected pin should support interrupts (EINT) ++ ++### spi-spidev ++ ++Activates SPIdev device node (/dev/spidev0.0) for userspace SPI access ++ ++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 ++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 ++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 ++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 ++ ++Parameters: ++ ++param_spi2_bus_pins (char) ++ SPI bus 2 pinmux variant ++ Optional ++ Default: a ++ Supported values: a, b ++ Determines what pins SPI bus 2 is exposed on if SPI 2 is used by any overlay ++ ++param_spidev_max_freq (int) ++ Maximum SPIdev frequency ++ Optional ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ ++### uart2 ++ ++Activates serial port 2 (/dev/ttyS2) ++ ++UART 2 pins (TX, RX, RTS, CTS): PI18, PI19, PI16, PI17 ++ ++Parameters: ++ ++param_uart2_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable CTS and RTS pins ++ ++### uart3 ++ ++Activates serial port 3 (/dev/ttyS3) ++ ++UART 3 pins (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9 ++ ++Parameters: ++ ++param_uart3_rtscts (bool) ++ Enable RTS and CTS pins ++ Optional ++ Default: 0 ++ Set to 1 to enable CTS and RTS pins ++ ++### uart4 ++ ++Activates serial port 4 (/dev/ttyS4) ++ ++UART 4 pins a (TX, RX): PG10, PG11 ++UART 4 pins b (TX, RX): PH4, PH5 ++ ++Parameters: ++ ++param_uart4_pins (char) ++ Determines what pins UART 4 is exposed on ++ Optional ++ Default: a ++ Supported values: a, b ++ ++### uart 5 ++ ++Activates serial port 5 (/dev/ttyS5) ++ ++UART 5 pins (TX, RX): PH6, PH7 ++ ++### uart 6 ++ ++Activates serial port 6 (/dev/ttyS6) ++ ++UART 6 pins (TX, RX): PI12, PI13 ++ ++### uart 7 ++ ++Activates serial port 7 (/dev/ttyS7) ++ ++UART 7 pins (TX, RX): PI20, PI21 ++ ++### w1-gpio ++ ++Activates 1-Wire GPIO master ++Requires external pull-up resistor on data pin ++ ++Parameters: ++ ++param_w1_pin (pin) ++ Data pin for 1-Wire master ++ Optional ++ Default: PI15 ++ ++param_w1_pin_int_pullup (bool) ++ Enable internal pull-up for the data pin ++ Optional ++ Default: 0 ++ Set to 1 to enable the pull-up ++ This option should not be used with multiple sensors or long wires - ++ please use external pull-up resistor instead diff --git a/arch/arm/boot/dts/overlay/README.sun7i-a20-overlays b/arch/arm/boot/dts/overlay/README.sun7i-a20-overlays new file mode 100644 -index 00000000..626a520c +index 00000000..af886d93 --- /dev/null +++ b/arch/arm/boot/dts/overlay/README.sun7i-a20-overlays -@@ -0,0 +1,259 @@ +@@ -0,0 +1,290 @@ +This document describes overlays provided in the kernel packages +For generic Armbian overlays documentation please see +https://docs.armbian.com/Hardware_Allwinner_overlays/ @@ -84,6 +389,7 @@ index 00000000..626a520c +- i2c4 +- i2c-ds1307 +- nand ++- pps-gpio +- spdif-out +- spi-jedec-nor +- spi-mcp2515 @@ -152,6 +458,24 @@ index 00000000..626a520c +This overlay should not be used until mainline MLC NAND support +allows using NAND storage reliably + ++### pps-gpio ++ ++Activates pulse-per-second GPIO client ++ ++Parameters: ++ ++param_pps_pin (pin) ++ Pin PPS source is connected to ++ Optional ++ Default: PI15 ++ ++param_pps_falling_edge (bool) ++ Assert by falling edge ++ Optional ++ Default: 0 ++ When set (to 1), assert is indicated by a falling edge ++ (instead of by a rising edge) ++ +### spdif-out + +Activates SPDIF/Toslink audio output @@ -177,12 +501,14 @@ index 00000000..626a520c + +param_spi2_bus_pins (char) + SPI bus 2 pinmux variant -+ Determines what pins SPI bus 2 is exposed on if SPI 2 is used by any overlay ++ Optional + Default: a + Supported values: a, b ++ Determines what pins SPI bus 2 is exposed on if SPI 2 is used by any overlay + +param_spinor_max_freq (int) + Maximum SPI frequency ++ Optional + Default: 1000000 + Range: 3000 - 100000000 + @@ -204,17 +530,20 @@ index 00000000..626a520c + +param_spi2_bus_pins (char) + SPI bus 2 pinmux variant -+ Determines what pins SPI bus 2 is exposed on if SPI 2 is used by any overlay ++ Optional + Default: a + Supported values: a, b ++ Determines what pins SPI bus 2 is exposed on if SPI 2 is used by any overlay + +param_mcp2515_clk_freq (int) + Onboard oscillator clock frequency ++ Optional + Default: 8000000 + Typical values: 8000000, 16000000 + +param_mcp2515_int_pin (pin) + Interrupt pin ++ Optional + Default: PH15 + Selected pin should support interrupts (EINT) + @@ -231,12 +560,14 @@ index 00000000..626a520c + +param_spi2_bus_pins (char) + SPI bus 2 pinmux variant -+ Determines what pins SPI bus 2 is exposed on if SPI 2 is used by any overlay ++ Optional + Default: a + Supported values: a, b ++ Determines what pins SPI bus 2 is exposed on if SPI 2 is used by any overlay + +param_spidev_max_freq (int) + Maximum SPIdev frequency ++ Optional + Default: 1000000 + Range: 3000 - 100000000 + @@ -250,6 +581,7 @@ index 00000000..626a520c + +param_uart2_rtscts (bool) + Enable RTS and CTS pins ++ Optional + Default: 0 + Set to 1 to enable CTS and RTS pins + @@ -263,6 +595,7 @@ index 00000000..626a520c + +param_uart3_rtscts (bool) + Enable RTS and CTS pins ++ Optional + Default: 0 + Set to 1 to enable CTS and RTS pins + @@ -277,6 +610,7 @@ index 00000000..626a520c + +param_uart4_pins (char) + Determines what pins UART 4 is exposed on ++ Optional + Default: a + Supported values: a, b + @@ -307,14 +641,1028 @@ index 00000000..626a520c + +param_w1_pin (pin) + Data pin for 1-Wire master ++ Optional + Default: PI15 + +param_w1_pin_int_pullup (bool) + Enable internal pull-up for the data pin -+ This option should not be used with multiple sensors or long wires - -+ please use external pull-up resistor instead ++ Optional + Default: 0 + Set to 1 to enable the pull-up ++ This option should not be used with multiple sensors or long wires - ++ please use external pull-up resistor instead +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-analog-codec.dts b/arch/arm/boot/dts/overlay/sun4i-a10-analog-codec.dts +new file mode 100644 +index 00000000..4503f17b +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-analog-codec.dts +@@ -0,0 +1,12 @@ ++/dts-v1/ /plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target = <&codec>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-can.dts b/arch/arm/boot/dts/overlay/sun4i-a10-can.dts +new file mode 100644 +index 00000000..fef88b94 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-can.dts +@@ -0,0 +1,34 @@ ++/dts-v1/ /plugin/; ++ ++#include ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ can_pins: can_pins { ++ pins = "PH20", "PH21"; ++ function = "can"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/soc@01c00000"; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ can@01c2bc00 { ++ compatible = "allwinner,sun4i-a10-can"; ++ reg = <0x01c2bc00 0x400>; ++ interrupts = ; ++ clocks = <&apb1_gates 4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&can_pins>; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-fixup.scr-cmd b/arch/arm/boot/dts/overlay/sun4i-a10-fixup.scr-cmd +new file mode 100644 +index 00000000..4a988391 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-fixup.scr-cmd +@@ -0,0 +1,183 @@ ++# overlays fixup script ++# implements (or rather substitutes) overlay arguments functionality ++# using u-boot scripting, environment variables and "fdt" command ++ ++# setexpr test_var ${tmp_bank} - A ++# works only for hex numbers (A-F) ++ ++setenv decompose_pin 'setexpr tmp_bank sub "P(B|C|D|E|G|H|I)\\d+" "\\1"; ++setexpr tmp_pin sub "P\\S(\\d+)" "\\1"; ++test "${tmp_bank}" = "B" && setenv tmp_bank 1; ++test "${tmp_bank}" = "C" && setenv tmp_bank 2; ++test "${tmp_bank}" = "D" && setenv tmp_bank 3; ++test "${tmp_bank}" = "E" && setenv tmp_bank 4; ++test "${tmp_bank}" = "G" && setenv tmp_bank 6; ++test "${tmp_bank}" = "H" && setenv tmp_bank 7; ++test "${tmp_bank}" = "I" && setenv tmp_bank 8' ++ ++if test "${param_spinor_spi_bus}" = "0"; then ++ fdt set /soc@01c00000/spi@01c05000 status "okay" ++ fdt set /soc@01c00000/spi@01c05000/spiflash status "okay" ++fi ++ ++if test "${param_spinor_spi_bus}" = "1"; then ++ fdt set /soc@01c00000/spi@01c06000 status "okay" ++ fdt set /soc@01c00000/spi@01c06000/spiflash status "okay" ++fi ++ ++if test "${param_spinor_spi_bus}" = "2"; then ++ fdt set /soc@01c00000/spi@01c17000 status "okay" ++ fdt set /soc@01c00000/spi@01c17000/spiflash status "okay" ++fi ++ ++if test "${param_mcp2515_spi_bus}" = "0"; then ++ fdt set /soc@01c00000/spi@01c05000 status "okay" ++ fdt set /soc@01c00000/spi@01c05000/mcp2515 status "okay" ++fi ++ ++if test "${param_mcp2515_spi_bus}" = "1"; then ++ fdt set /soc@01c00000/spi@01c06000 status "okay" ++ fdt set /soc@01c00000/spi@01c06000/mcp2515 status "okay" ++fi ++ ++if test "${param_mcp2515_spi_bus}" = "2"; then ++ fdt set /soc@01c00000/spi@01c17000 status "okay" ++ fdt set /soc@01c00000/spi@01c17000/mcp2515 status "okay" ++fi ++ ++if test "${param_spidev_spi_bus}" = "0"; then ++ fdt set /soc@01c00000/spi@01c05000 status "okay" ++ fdt set /soc@01c00000/spi@01c05000/spidev status "okay" ++fi ++ ++if test "${param_spidev_spi_bus}" = "1"; then ++ fdt set /soc@01c00000/spi@01c06000 status "okay" ++ fdt set /soc@01c00000/spi@01c06000/spidev status "okay" ++fi ++ ++if test "${param_spidev_spi_bus}" = "2"; then ++ fdt set /soc@01c00000/spi@01c17000 status "okay" ++ fdt set /soc@01c00000/spi@01c17000/spidev status "okay" ++fi ++ ++if test "${param_ds1307_i2c_bus}" = "0"; then ++ fdt set /soc@01c00000/i2c@01c2ac00 status "okay" ++ fdt set /soc@01c00000/i2c@01c2ac00/ds1307@68 status "okay" ++fi ++ ++if test "${param_ds1307_i2c_bus}" = "1"; then ++ fdt set /soc@01c00000/i2c@01c2b000 status "okay" ++ fdt set /soc@01c00000/i2c@01c2b000/ds1307@68 status "okay" ++fi ++ ++if test "${param_ds1307_i2c_bus}" = "2"; then ++ fdt set /soc@01c00000/i2c@01c2b400 status "okay" ++ fdt set /soc@01c00000/i2c@01c2b400/ds1307@68 status "okay" ++fi ++ ++if test -n "${param_mcp2515_clk_freq}"; then ++ fdt set /clocks/can0_osc_fixed clock-frequency "<${param_mcp2515_clk_freq}>" ++fi ++ ++if test "${param_spi2_bus_pins}" = "b"; then ++ fdt get value tmp_phandle1 /soc@01c00000/pinctrl@01c20800/spi2@1 phandle ++ fdt get value tmp_phandle2 /soc@01c00000/pinctrl@01c20800/spi2_cs0@1 phandle ++ fdt set /soc@01c00000/spi@01c17000 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc@01c00000/spi@01c17000 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi ++ ++if test -n "${param_mcp2515_int_pin}"; then ++ setenv tmp_bank "${param_mcp2515_int_pin}" ++ setenv tmp_pin "${param_mcp2515_int_pin}" ++ run decompose_pin ++ fdt set /soc@01c00000/pinctrl@01c20800/can0_pin_irq pins "${param_mcp2515_int_pin}" ++ if test "${param_mcp2515_spi_bus}" = "0"; then ++ setenv tmp_spi_path "spi@01c05000" ++ fi ++ if test "${param_mcp2515_spi_bus}" = "1"; then ++ setenv tmp_spi_path "spi@01c06000" ++ fi ++ if test "${param_mcp2515_spi_bus}" = "2"; then ++ setenv tmp_spi_path "spi@01c17000" ++ fi ++ fdt set /soc@01c00000/${tmp_spi_path}/mcp2515 interrupts "<${tmp_bank} ${tmp_pin} 0x2>" ++ env delete tmp_pin tmp_bank tmp_spi_path ++fi ++ ++if test -n "${param_spidev_max_freq}"; then ++ if test "${param_spidev_spi_bus}" = "0"; then ++ setenv tmp_spi_path "spi@01c05000" ++ fi ++ if test "${param_spidev_spi_bus}" = "1"; then ++ setenv tmp_spi_path "spi@01c06000" ++ fi ++ if test "${param_spidev_spi_bus}" = "2"; then ++ setenv tmp_spi_path "spi@01c17000" ++ fi ++ fdt set /soc@01c00000/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>" ++ env delete tmp_spi_path ++fi ++ ++if test -n "${param_spinor_max_freq}"; then ++ if test "${param_spinor_spi_bus}" = "0"; then ++ setenv tmp_spi_path "spi@01c05000" ++ fi ++ if test "${param_spinor_spi_bus}" = "1"; then ++ setenv tmp_spi_path "spi@01c06000" ++ fi ++ if test "${param_spinor_spi_bus}" = "2"; then ++ setenv tmp_spi_path "spi@01c17000" ++ fi ++ fdt set /soc@01c00000/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>" ++ env delete tmp_spi_path ++fi ++ ++if test -n "${param_pps_pin}"; then ++ setenv tmp_bank "${param_pps_pin}" ++ setenv tmp_pin "${param_pps_pin}" ++ run decompose_pin ++ fdt set /soc@01c00000/pinctrl@01c20800/pps_pins pins "${param_pps_pin}" ++ fdt get value tmp_phandle /soc@01c00000/pinctrl@01c20800 phandle ++ fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_pps_falling_edge}" = "1"; then ++ fdt set /pps@0 assert-falling-edge ++fi ++ ++if test -n "${param_w1_pin}"; then ++ setenv tmp_bank "${param_w1_pin}" ++ setenv tmp_pin "${param_w1_pin}" ++ run decompose_pin ++ fdt set /soc@01c00000/pinctrl@01c20800/w1_pins pins "${param_w1_pin}" ++ fdt get value tmp_phandle /soc@01c00000/pinctrl@01c20800 phandle ++ fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_w1_pin_int_pullup}" = "1"; then ++ fdt set /soc@01c00000/pinctrl@01c20800/w1_pins bias-pull-up ++fi ++ ++if test "${param_uart2_rtscts}" = "1"; then ++ fdt get value tmp_phandle /soc@01c00000/pinctrl@01c20800/uart2@0 phandle ++ fdt set /soc@01c00000/serial@01c28800 pinctrl-0 "<${tmp_phandle}>" ++ env delete tmp_phandle ++fi ++ ++if test "${param_uart3_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc@01c00000/pinctrl@01c20800/uart3 phandle ++ fdt get value tmp_phandle2 /soc@01c00000/pinctrl@01c20800/uart3_rts_cts phandle ++ fdt set /soc@01c00000/serial@01c28c00 pinctrl-names "default" "default" ++ fdt set /soc@01c00000/serial@01c28c00 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc@01c00000/serial@01c28c00 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi ++ ++if test "${param_uart4_pins}" = "b"; then ++ fdt get value tmp_phandle /soc@01c00000/pinctrl@01c20800/uart4@1 phandle ++ fdt set /soc@01c00000/serial@01c29000 pinctrl-0 "<${tmp_phandle}>" ++ env delete tmp_phandle ++fi +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-i2c-ds1307.dts b/arch/arm/boot/dts/overlay/sun4i-a10-i2c-ds1307.dts +new file mode 100644 +index 00000000..dc14796e +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-i2c-ds1307.dts +@@ -0,0 +1,53 @@ ++/dts-v1/ /plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c0 = "/soc@01c00000/i2c@01c2ac00"; ++ i2c1 = "/soc@01c00000/i2c@01c2b000"; ++ i2c2 = "/soc@01c00000/i2c@01c2b400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ds1307@68 { ++ compatible = "dallas,ds1307"; ++ reg = <0x68>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ds1307@68 { ++ compatible = "dallas,ds1307"; ++ reg = <0x68>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&i2c2>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ds1307@68 { ++ compatible = "dallas,ds1307"; ++ reg = <0x68>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-i2c1.dts b/arch/arm/boot/dts/overlay/sun4i-a10-i2c1.dts +new file mode 100644 +index 00000000..4267403c +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-i2c1.dts +@@ -0,0 +1,21 @@ ++/dts-v1/ /plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c1 = "/soc@01c00000/i2c@01c2b000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins_a>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-i2c2.dts b/arch/arm/boot/dts/overlay/sun4i-a10-i2c2.dts +new file mode 100644 +index 00000000..f0a4a84a +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-i2c2.dts +@@ -0,0 +1,21 @@ ++/dts-v1/ /plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c2 = "/soc@01c00000/i2c@01c2b400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins_a>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-nand.dts b/arch/arm/boot/dts/overlay/sun4i-a10-nand.dts +new file mode 100644 +index 00000000..5d13b214 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-nand.dts +@@ -0,0 +1,102 @@ ++/dts-v1/ /plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ nand_pins_a: nand_pins@0 { ++ pins = "PC0", "PC1", "PC2", ++ "PC5", "PC8", "PC9", "PC10", ++ "PC11", "PC12", "PC13", "PC14", ++ "PC15", "PC16"; ++ function = "nand0"; ++ }; ++ ++ nand_cs0_pins_a: nand_cs@0 { ++ pins = "PC4"; ++ function = "nand0"; ++ }; ++ ++ nand_cs1_pins_a: nand_cs@1 { ++ pins = "PC3"; ++ function = "nand0"; ++ }; ++ ++ nand_cs2_pins_a: nand_cs@2 { ++ pins = "PC17"; ++ function = "nand0"; ++ }; ++ ++ nand_cs3_pins_a: nand_cs@3 { ++ pins = "PC18"; ++ function = "nand0"; ++ }; ++ ++ nand_rb0_pins_a: nand_rb@0 { ++ pins = "PC6"; ++ function = "nand0"; ++ }; ++ ++ nand_rb1_pins_a: nand_rb@1 { ++ pins = "PC7"; ++ function = "nand0"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&nfc>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&nand_pins_a>, <&nand_cs0_pins_a>, <&nand_rb0_pins_a>; ++ status = "okay"; ++ ++ nand@0 { ++ reg = <0>; ++ allwinner,rb = <0>; ++ nand-ecc-mode = "hw"; ++ nand-on-flash-bbt; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ partition@0 { ++ label = "SPL"; ++ reg = <0x0 0x0 0x0 0x400000>; ++ }; ++ ++ partition@400000 { ++ label = "SPL.backup"; ++ reg = <0x0 0x400000 0x0 0x400000>; ++ }; ++ ++ partition@800000 { ++ label = "U-Boot"; ++ reg = <0x0 0x800000 0x0 0x400000>; ++ }; ++ ++ partition@c00000 { ++ label = "U-Boot.backup"; ++ reg = <0x0 0xc00000 0x0 0x400000>; ++ }; ++ ++ partition@1000000 { ++ label = "env"; ++ reg = <0x0 0x1000000 0x0 0x400000>; ++ }; ++ ++ partition@1400000 { ++ label = "rootfs"; ++ reg = <0x0 0xa00000 0x01 0xff000000>; ++ }; ++ }; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-pps-gpio.dts b/arch/arm/boot/dts/overlay/sun4i-a10-pps-gpio.dts +new file mode 100644 +index 00000000..f6604c77 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-pps-gpio.dts +@@ -0,0 +1,28 @@ ++/dts-v1/ /plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ pps_pins: pps_pins { ++ pins = "PI15"; ++ function = "gpio_in"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ pps@0 { ++ compatible = "pps-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pps_pins>; ++ gpios = <&pio 8 15 0>; /* PI15 */ ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-spdif-out.dts b/arch/arm/boot/dts/overlay/sun4i-a10-spdif-out.dts +new file mode 100644 +index 00000000..604eca29 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-spdif-out.dts +@@ -0,0 +1,37 @@ ++/dts-v1/ /plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target = <&spdif>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spdif_tx_pins_a>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "On-board SPDIF"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&spdif>; ++ }; ++ ++ simple-audio-card,codec { ++ sound-dai = <&spdif_out>; ++ }; ++ ++ spdif_out: spdif-out { ++ #sound-dai-cells = <0>; ++ compatible = "linux,spdif-dit"; ++ }; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-spi-jedec-nor.dts b/arch/arm/boot/dts/overlay/sun4i-a10-spi-jedec-nor.dts +new file mode 100644 +index 00000000..fc4f7fc4 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-spi-jedec-nor.dts +@@ -0,0 +1,64 @@ ++/dts-v1/ /plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc/spi@01c05000"; ++ spi1 = "/soc/spi@01c06000"; ++ spi2 = "/soc/spi@01c17000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ pinctrl-names = "default", "default"; ++ pinctrl-0 = <&spi0_pins_a>; ++ pinctrl-1 = <&spi0_cs0_pins_a>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash { ++ compatible = "jedec,spi-nor"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins_a>, <&spi1_cs0_pins_a>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash { ++ compatible = "jedec,spi-nor"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&spi2>; ++ __overlay__ { ++ pinctrl-names = "default", "default"; ++ pinctrl-0 = <&spi2_pins_a>; ++ pinctrl-1 = <&spi2_cs0_pins_a>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash { ++ compatible = "jedec,spi-nor"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-spi-mcp2515.dts b/arch/arm/boot/dts/overlay/sun4i-a10-spi-mcp2515.dts +new file mode 100644 +index 00000000..def642e7 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-spi-mcp2515.dts +@@ -0,0 +1,105 @@ ++/dts-v1/ /plugin/; ++ ++#include ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi1 = "/soc/spi@01c06000"; ++ spi2 = "/soc/spi@01c17000"; ++ spi3 = "/soc/spi@01c1f000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/clocks"; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ can0_osc_fixed: can0_osc_fixed { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <8000000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&pio>; ++ __overlay__ { ++ can0_pin_irq: can0_pin_irq { ++ pins = "PH15"; ++ function = "irq"; ++ bias-pull-up; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&spi0>; ++ __overlay__ { ++ pinctrl-names = "default", "default"; ++ pinctrl-0 = <&spi0_pins_a>; ++ pinctrl-1 = <&spi0_cs0_pins_a>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ mcp2515 { ++ reg = <0>; ++ compatible = "microchip,mcp2515"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&can0_pin_irq>; ++ spi-max-frequency = <10000000>; ++ interrupt-parent = <&pio>; ++ interrupts = <7 15 IRQ_TYPE_EDGE_FALLING>; /* PH15 */ ++ clocks = <&can0_osc_fixed>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@4 { ++ target = <&spi1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins_a>, <&spi1_cs0_pins_a>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ mcp2515 { ++ reg = <0>; ++ compatible = "microchip,mcp2515"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&can0_pin_irq>; ++ spi-max-frequency = <10000000>; ++ interrupt-parent = <&pio>; ++ interrupts = <7 15 IRQ_TYPE_EDGE_FALLING>; /* PH15 */ ++ clocks = <&can0_osc_fixed>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@5 { ++ target = <&spi2>; ++ __overlay__ { ++ pinctrl-names = "default", "default"; ++ pinctrl-0 = <&spi2_pins_a>; ++ pinctrl-1 = <&spi2_cs0_pins_a>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ mcp2515 { ++ reg = <0>; ++ compatible = "microchip,mcp2515"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&can0_pin_irq>; ++ spi-max-frequency = <10000000>; ++ interrupt-parent = <&pio>; ++ interrupts = <7 15 IRQ_TYPE_EDGE_FALLING>; /* PH15 */ ++ clocks = <&can0_osc_fixed>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-spi-spidev.dts b/arch/arm/boot/dts/overlay/sun4i-a10-spi-spidev.dts +new file mode 100644 +index 00000000..af8fddf8 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-spi-spidev.dts +@@ -0,0 +1,64 @@ ++/dts-v1/ /plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi0 = "/soc/spi@01c05000"; ++ spi1 = "/soc/spi@01c06000"; ++ spi2 = "/soc/spi@01c17000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ pinctrl-names = "default", "default"; ++ pinctrl-0 = <&spi0_pins_a>; ++ pinctrl-1 = <&spi0_cs0_pins_a>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev { ++ compatible = "spidev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins_a>, <&spi1_cs0_pins_a>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev { ++ compatible = "spidev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&spi2>; ++ __overlay__ { ++ pinctrl-names = "default", "default"; ++ pinctrl-0 = <&spi2_pins_a>; ++ pinctrl-1 = <&spi2_cs0_pins_a>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev { ++ compatible = "spidev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart2.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart2.dts +new file mode 100644 +index 00000000..c21c4c2a +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart2.dts +@@ -0,0 +1,31 @@ ++/dts-v1/ /plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ uart2 = "/soc@01c00000/serial@01c28800"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart2_pins_a_2: uart2@1 { ++ pins = "PI18", "PI19"; ++ function = "uart2"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart2>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins_a_2>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart3.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart3.dts +new file mode 100644 +index 00000000..ad5eb2a0 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart3.dts +@@ -0,0 +1,31 @@ ++/dts-v1/ /plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ uart3 = "/soc@01c00000/serial@01c28c00"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart3_pins_a_2: uart3@2 { ++ pins = "PG6", "PG7"; ++ function = "uart3"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&uart3>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart3_pins_a_2>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart4.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart4.dts +new file mode 100644 +index 00000000..edfaf641 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart4.dts +@@ -0,0 +1,21 @@ ++/dts-v1/ /plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial4 = "/soc@01c00000/serial@01c29000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart4>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart4_pins_a>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart5.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart5.dts +new file mode 100644 +index 00000000..cd9fa3dc +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart5.dts +@@ -0,0 +1,21 @@ ++/dts-v1/ /plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial5 = "/soc@01c00000/serial@01c29400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart5>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart5_pins_a>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart6.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart6.dts +new file mode 100644 +index 00000000..2f873d15 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart6.dts +@@ -0,0 +1,21 @@ ++/dts-v1/ /plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial6 = "/soc@01c00000/serial@01c29800"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart6>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart6_pins_a>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-uart7.dts b/arch/arm/boot/dts/overlay/sun4i-a10-uart7.dts +new file mode 100644 +index 00000000..531951da +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-uart7.dts +@@ -0,0 +1,21 @@ ++/dts-v1/ /plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial7 = "/soc@01c00000/serial@01c29c00"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart7>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart7_pins_a>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun4i-a10-w1-gpio.dts b/arch/arm/boot/dts/overlay/sun4i-a10-w1-gpio.dts +new file mode 100644 +index 00000000..e34093eb +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun4i-a10-w1-gpio.dts +@@ -0,0 +1,28 @@ ++/dts-v1/ /plugin/; ++ ++/ { ++ compatible = "allwinner,sun4i-a10"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ w1_pins: w1_pins { ++ pins = "PI15"; ++ function = "gpio_in"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ onewire@0 { ++ compatible = "w1-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&w1_pins>; ++ gpios = <&pio 8 15 0>; /* PI15 */ ++ status = "okay"; ++ }; ++ }; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-analog-codec.dts b/arch/arm/boot/dts/overlay/sun7i-a20-analog-codec.dts new file mode 100644 index 00000000..74bb13d0 @@ -375,10 +1723,10 @@ index 00000000..8ab3fb01 +}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-fixup.scr-cmd b/arch/arm/boot/dts/overlay/sun7i-a20-fixup.scr-cmd new file mode 100644 -index 00000000..16cbe62a +index 00000000..01348d69 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-fixup.scr-cmd -@@ -0,0 +1,179 @@ +@@ -0,0 +1,193 @@ +# overlays fixup script +# implements (or rather substitutes) overlay arguments functionality +# using u-boot scripting, environment variables and "fdt" command @@ -524,6 +1872,20 @@ index 00000000..16cbe62a + env delete tmp_spi_path +fi + ++if test -n "${param_pps_pin}"; then ++ setenv tmp_bank "${param_pps_pin}" ++ setenv tmp_pin "${param_pps_pin}" ++ run decompose_pin ++ fdt set /soc@01c00000/pinctrl@01c20800/pps_pins pins "${param_pps_pin}" ++ fdt get value tmp_phandle /soc@01c00000/pinctrl@01c20800 phandle ++ fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_pps_falling_edge}" = "1"; then ++ fdt set /pps@0 assert-falling-edge ++fi ++ +if test -n "${param_w1_pin}"; then + setenv tmp_bank "${param_w1_pin}" + setenv tmp_pin "${param_w1_pin}" @@ -560,10 +1922,10 @@ index 00000000..16cbe62a +fi diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c-ds1307.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c-ds1307.dts new file mode 100644 -index 00000000..e35750b0 +index 00000000..9ac0aae3 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c-ds1307.dts -@@ -0,0 +1,67 @@ +@@ -0,0 +1,81 @@ +/dts-v1/ /plugin/; + +/ { @@ -572,6 +1934,7 @@ index 00000000..e35750b0 + fragment@0 { + target-path = "/aliases"; + __overlay__ { ++ i2c0 = "/soc@01c00000/i2c@01c2ac00"; + i2c1 = "/soc@01c00000/i2c@01c2b000"; + i2c2 = "/soc@01c00000/i2c@01c2b400"; + i2c3 = "/soc@01c00000/i2c@01c2b800"; @@ -580,7 +1943,7 @@ index 00000000..e35750b0 + }; + + fragment@1 { -+ target = <&i2c1>; ++ target = <&i2c0>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; @@ -593,7 +1956,7 @@ index 00000000..e35750b0 + }; + + fragment@2 { -+ target = <&i2c2>; ++ target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; @@ -606,7 +1969,7 @@ index 00000000..e35750b0 + }; + + fragment@3 { -+ target = <&i2c3>; ++ target = <&i2c2>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; @@ -619,6 +1982,19 @@ index 00000000..e35750b0 + }; + + fragment@4 { ++ target = <&i2c3>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ds1307@68 { ++ compatible = "dallas,ds1307"; ++ reg = <0x68>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@5 { + target = <&i2c4>; + __overlay__ { + #address-cells = <1>; @@ -906,6 +2282,40 @@ index 00000000..dec3a70c + }; + }; +}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-pps-gpio.dts b/arch/arm/boot/dts/overlay/sun7i-a20-pps-gpio.dts +new file mode 100644 +index 00000000..3a2d011d +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-pps-gpio.dts +@@ -0,0 +1,28 @@ ++/dts-v1/ /plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ pps_pins: pps_pins { ++ pins = "PI15"; ++ function = "gpio_in"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ pps@0 { ++ compatible = "pps-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pps_pins>; ++ gpios = <&pio 8 15 0>; /* PI15 */ ++ status = "okay"; ++ }; ++ }; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spdif-out.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spdif-out.dts new file mode 100644 index 00000000..0463f43c @@ -951,10 +2361,10 @@ index 00000000..0463f43c +}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi-jedec-nor.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi-jedec-nor.dts new file mode 100644 -index 00000000..e8d2e17d +index 00000000..dc0e624e --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi-jedec-nor.dts -@@ -0,0 +1,67 @@ +@@ -0,0 +1,64 @@ +/dts-v1/ /plugin/; + +/ { @@ -972,7 +2382,6 @@ index 00000000..e8d2e17d + fragment@1 { + target = <&spi0>; + __overlay__ { -+ status = "okay"; + pinctrl-names = "default", "default"; + pinctrl-0 = <&spi0_pins_a>; + pinctrl-1 = <&spi0_cs0_pins_a>; @@ -980,9 +2389,9 @@ index 00000000..e8d2e17d + #size-cells = <0>; + spiflash { + compatible = "jedec,spi-nor"; ++ status = "disabled"; + reg = <0>; + spi-max-frequency = <1000000>; -+ status = "okay"; + }; + }; + }; @@ -990,7 +2399,6 @@ index 00000000..e8d2e17d + fragment@2 { + target = <&spi1>; + __overlay__ { -+ status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>, <&spi1_cs0_pins_a>; + #address-cells = <1>; @@ -1007,7 +2415,6 @@ index 00000000..e8d2e17d + fragment@3 { + target = <&spi2>; + __overlay__ { -+ status = "disabled"; + pinctrl-names = "default", "default"; + pinctrl-0 = <&spi2_pins_a>; + pinctrl-1 = <&spi2_cs0_pins_a>;