diff --git a/patch/kernel/archive/rockchip64-6.19/media-0001-Add-rkvdec-Support-v5.patch b/patch/kernel/archive/rockchip64-6.19/media-0001-Add-rkvdec-Support-v7.patch similarity index 56% rename from patch/kernel/archive/rockchip64-6.19/media-0001-Add-rkvdec-Support-v5.patch rename to patch/kernel/archive/rockchip64-6.19/media-0001-Add-rkvdec-Support-v7.patch index 5426b5aa55..c273acd21e 100644 --- a/patch/kernel/archive/rockchip64-6.19/media-0001-Add-rkvdec-Support-v5.patch +++ b/patch/kernel/archive/rockchip64-6.19/media-0001-Add-rkvdec-Support-v7.patch @@ -1,3444 +1,47 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 10 Aug 2025 21:24:31 +0000 -Subject: media: rkvdec: Add HEVC backend - -The Rockchip VDEC supports the HEVC codec with the Main and Main10 -Profile up to Level 5.1 High tier: 4096x2304@60 fps. - -Add the backend for HEVC format to the decoder. - -Signed-off-by: Alex Bee -Signed-off-by: Nicolas Dufresne -Signed-off-by: Sebastian Fricke -Signed-off-by: Jonas Karlman ---- - drivers/media/platform/rockchip/rkvdec/Makefile | 2 +- - drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-data.c | 1848 ++++++++++ - drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c | 817 ++++ - drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h | 2 + - drivers/media/platform/rockchip/rkvdec/rkvdec.c | 76 + - drivers/media/platform/rockchip/rkvdec/rkvdec.h | 1 + - 6 files changed, 2745 insertions(+), 1 deletion(-) - -diff --git a/drivers/media/platform/rockchip/rkvdec/Makefile b/drivers/media/platform/rockchip/rkvdec/Makefile -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/Makefile -+++ b/drivers/media/platform/rockchip/rkvdec/Makefile -@@ -1,3 +1,3 @@ - obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rockchip-vdec.o - --rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-vp9.o -+rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-hevc.o rkvdec-vp9.o -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-data.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-data.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-data.c -@@ -0,0 +1,1848 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Rockchip Video Decoder driver -+ * -+ * Copyright (C) 2023 Collabora, Ltd. -+ * Sebastian Fricke -+ */ -+ -+#include -+ -+#define RKV_CABAC_TABLE_SIZE 27456 -+ -+/* -+ * This file is #include from rkvdec-hevc.c and not compiled. -+ */ -+static const u8 rkvdec_hevc_cabac_table[RKV_CABAC_TABLE_SIZE] = { -+ 0x07, 0x0f, 0x48, 0x58, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, -+ 0x68, 0x48, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40, -+ 0x40, 0x68, 0x58, 0x60, 0x40, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x60, -+ 0x60, 0x50, 0x58, 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50, 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0x08, 0x00, 0x27, 0x08, 0x37, -+ 0x27, 0x27, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+}; -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c -@@ -0,0 +1,817 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Rockchip Video Decoder HEVC backend -+ * -+ * Copyright (C) 2023 Collabora, Ltd. -+ * Sebastian Fricke -+ * -+ * Copyright (C) 2019 Collabora, Ltd. -+ * Boris Brezillon -+ * -+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd. -+ * Jeffy Chen -+ */ -+ -+#include -+ -+#include "rkvdec.h" -+#include "rkvdec-regs.h" -+#include "rkvdec-hevc-data.c" -+ -+/* Size in u8/u32 units. */ -+#define RKV_SCALING_LIST_SIZE 1360 -+#define RKV_PPS_SIZE (80 / 4) -+#define RKV_PPS_LEN 64 -+#define RKV_RPS_SIZE (32 / 4) -+#define RKV_RPS_LEN 600 -+ -+struct rkvdec_sps_pps_packet { -+ u32 info[RKV_PPS_SIZE]; -+}; -+ -+struct rkvdec_rps_packet { -+ u32 info[RKV_RPS_SIZE]; -+}; -+ -+struct rkvdec_ps_field { -+ u16 offset; -+ u8 len; -+}; -+ -+#define PS_FIELD(_offset, _len) \ -+ ((struct rkvdec_ps_field){ _offset, _len }) -+ -+/* SPS */ -+#define VIDEO_PARAMETER_SET_ID PS_FIELD(0, 4) -+#define SEQ_PARAMETER_SET_ID PS_FIELD(4, 4) -+#define CHROMA_FORMAT_IDC PS_FIELD(8, 2) -+#define PIC_WIDTH_IN_LUMA_SAMPLES PS_FIELD(10, 13) -+#define PIC_HEIGHT_IN_LUMA_SAMPLES PS_FIELD(23, 13) -+#define BIT_DEPTH_LUMA PS_FIELD(36, 4) -+#define BIT_DEPTH_CHROMA PS_FIELD(40, 4) -+#define LOG2_MAX_PIC_ORDER_CNT_LSB PS_FIELD(44, 5) -+#define LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(49, 2) -+#define LOG2_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(51, 3) -+#define LOG2_MIN_TRANSFORM_BLOCK_SIZE PS_FIELD(54, 3) -+#define LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE PS_FIELD(57, 2) -+#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTER PS_FIELD(59, 3) -+#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA PS_FIELD(62, 3) -+#define SCALING_LIST_ENABLED_FLAG PS_FIELD(65, 1) -+#define AMP_ENABLED_FLAG PS_FIELD(66, 1) -+#define SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG PS_FIELD(67, 1) -+#define PCM_ENABLED_FLAG PS_FIELD(68, 1) -+#define PCM_SAMPLE_BIT_DEPTH_LUMA PS_FIELD(69, 4) -+#define PCM_SAMPLE_BIT_DEPTH_CHROMA PS_FIELD(73, 4) -+#define PCM_LOOP_FILTER_DISABLED_FLAG PS_FIELD(77, 1) -+#define LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(78, 3) -+#define LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(81, 3) -+#define NUM_SHORT_TERM_REF_PIC_SETS PS_FIELD(84, 7) -+#define LONG_TERM_REF_PICS_PRESENT_FLAG PS_FIELD(91, 1) -+#define NUM_LONG_TERM_REF_PICS_SPS PS_FIELD(92, 6) -+#define SPS_TEMPORAL_MVP_ENABLED_FLAG PS_FIELD(98, 1) -+#define STRONG_INTRA_SMOOTHING_ENABLED_FLAG PS_FIELD(99, 1) -+/* PPS */ -+#define PIC_PARAMETER_SET_ID PS_FIELD(128, 6) -+#define PPS_SEQ_PARAMETER_SET_ID PS_FIELD(134, 4) -+#define DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG PS_FIELD(138, 1) -+#define OUTPUT_FLAG_PRESENT_FLAG PS_FIELD(139, 1) -+#define NUM_EXTRA_SLICE_HEADER_BITS PS_FIELD(140, 13) -+#define SIGN_DATA_HIDING_ENABLED_FLAG PS_FIELD(153, 1) -+#define CABAC_INIT_PRESENT_FLAG PS_FIELD(154, 1) -+#define NUM_REF_IDX_L0_DEFAULT_ACTIVE PS_FIELD(155, 4) -+#define NUM_REF_IDX_L1_DEFAULT_ACTIVE PS_FIELD(159, 4) -+#define INIT_QP_MINUS26 PS_FIELD(163, 7) -+#define CONSTRAINED_INTRA_PRED_FLAG PS_FIELD(170, 1) -+#define TRANSFORM_SKIP_ENABLED_FLAG PS_FIELD(171, 1) -+#define CU_QP_DELTA_ENABLED_FLAG PS_FIELD(172, 1) -+#define LOG2_MIN_CU_QP_DELTA_SIZE PS_FIELD(173, 3) -+#define PPS_CB_QP_OFFSET PS_FIELD(176, 5) -+#define PPS_CR_QP_OFFSET PS_FIELD(181, 5) -+#define PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG PS_FIELD(186, 1) -+#define WEIGHTED_PRED_FLAG PS_FIELD(187, 1) -+#define WEIGHTED_BIPRED_FLAG PS_FIELD(188, 1) -+#define TRANSQUANT_BYPASS_ENABLED_FLAG PS_FIELD(189, 1) -+#define TILES_ENABLED_FLAG PS_FIELD(190, 1) -+#define ENTROPY_CODING_SYNC_ENABLED_FLAG PS_FIELD(191, 1) -+#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG PS_FIELD(192, 1) -+#define LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG PS_FIELD(193, 1) -+#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG PS_FIELD(194, 1) -+#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG PS_FIELD(195, 1) -+#define PPS_BETA_OFFSET_DIV2 PS_FIELD(196, 4) -+#define PPS_TC_OFFSET_DIV2 PS_FIELD(200, 4) -+#define LISTS_MODIFICATION_PRESENT_FLAG PS_FIELD(204, 1) -+#define LOG2_PARALLEL_MERGE_LEVEL PS_FIELD(205, 3) -+#define SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG PS_FIELD(208, 1) -+#define NUM_TILE_COLUMNS PS_FIELD(212, 5) -+#define NUM_TILE_ROWS PS_FIELD(217, 5) -+#define COLUMN_WIDTH(i) PS_FIELD(256 + ((i) * 8), 8) -+#define ROW_HEIGHT(i) PS_FIELD(416 + ((i) * 8), 8) -+#define SCALING_LIST_ADDRESS PS_FIELD(592, 32) -+ -+/* Data structure describing auxiliary buffer format. */ -+struct rkvdec_hevc_priv_tbl { -+ u8 cabac_table[RKV_CABAC_TABLE_SIZE]; -+ u8 scaling_list[RKV_SCALING_LIST_SIZE]; -+ struct rkvdec_sps_pps_packet param_set[RKV_PPS_LEN]; -+ struct rkvdec_rps_packet rps[RKV_RPS_LEN]; -+}; -+ -+struct rkvdec_hevc_run { -+ struct rkvdec_run base; -+ const struct v4l2_ctrl_hevc_slice_params *slices_params; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params; -+ const struct v4l2_ctrl_hevc_sps *sps; -+ const struct v4l2_ctrl_hevc_pps *pps; -+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; -+ int num_slices; -+}; -+ -+struct rkvdec_hevc_ctx { -+ struct rkvdec_aux_buf priv_tbl; -+ struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache; -+}; -+ -+struct scaling_factor { -+ u8 scalingfactor0[1248]; -+ u8 scalingfactor1[96]; /*4X4 TU Rotate, total 16X4*/ -+ u8 scalingdc[12]; /*N1005 Vienna Meeting*/ -+ u8 reserved[4]; /*16Bytes align*/ -+}; -+ -+static void set_ps_field(u32 *buf, struct rkvdec_ps_field field, u32 value) -+{ -+ u8 bit = field.offset % 32, word = field.offset / 32; -+ u64 mask = GENMASK_ULL(bit + field.len - 1, bit); -+ u64 val = ((u64)value << bit) & mask; -+ -+ buf[word] &= ~mask; -+ buf[word] |= val; -+ if (bit + field.len > 32) { -+ buf[word + 1] &= ~(mask >> 32); -+ buf[word + 1] |= val >> 32; -+ } -+} -+ -+static void assemble_hw_pps(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ const struct v4l2_ctrl_hevc_sps *sps = run->sps; -+ const struct v4l2_ctrl_hevc_pps *pps = run->pps; -+ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; -+ struct rkvdec_sps_pps_packet *hw_ps; -+ u32 min_cb_log2_size_y, ctb_log2_size_y, ctb_size_y; -+ u32 log2_min_cu_qp_delta_size, scaling_distance; -+ dma_addr_t scaling_list_address; -+ int i; -+ -+ /* -+ * HW read the SPS/PPS information from PPS packet index by PPS id. -+ * offset from the base can be calculated by PPS_id * 80 (size per PPS -+ * packet unit). so the driver copy SPS/PPS information to the exact PPS -+ * packet unit for HW accessing. -+ */ -+ hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id]; -+ memset(hw_ps, 0, sizeof(*hw_ps)); -+ -+#define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value) -+ /* write sps */ -+ WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID); -+ WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID); -+ WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC); -+ WRITE_PPS(sps->pic_width_in_luma_samples, PIC_WIDTH_IN_LUMA_SAMPLES); -+ WRITE_PPS(sps->pic_height_in_luma_samples, PIC_HEIGHT_IN_LUMA_SAMPLES); -+ WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA); -+ WRITE_PPS(sps->bit_depth_chroma_minus8 + 8, BIT_DEPTH_CHROMA); -+ WRITE_PPS(sps->log2_max_pic_order_cnt_lsb_minus4 + 4, -+ LOG2_MAX_PIC_ORDER_CNT_LSB); -+ WRITE_PPS(sps->log2_diff_max_min_luma_coding_block_size, -+ LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE); -+ WRITE_PPS(sps->log2_min_luma_coding_block_size_minus3 + 3, -+ LOG2_MIN_LUMA_CODING_BLOCK_SIZE); -+ WRITE_PPS(sps->log2_min_luma_transform_block_size_minus2 + 2, -+ LOG2_MIN_TRANSFORM_BLOCK_SIZE); -+ WRITE_PPS(sps->log2_diff_max_min_luma_transform_block_size, -+ LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE); -+ WRITE_PPS(sps->max_transform_hierarchy_depth_inter, -+ MAX_TRANSFORM_HIERARCHY_DEPTH_INTER); -+ WRITE_PPS(sps->max_transform_hierarchy_depth_intra, -+ MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED), -+ SCALING_LIST_ENABLED_FLAG); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED), -+ AMP_ENABLED_FLAG); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET), -+ SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG); -+ if (sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED) { -+ WRITE_PPS(1, PCM_ENABLED_FLAG); -+ WRITE_PPS(sps->pcm_sample_bit_depth_luma_minus1 + 1, -+ PCM_SAMPLE_BIT_DEPTH_LUMA); -+ WRITE_PPS(sps->pcm_sample_bit_depth_chroma_minus1 + 1, -+ PCM_SAMPLE_BIT_DEPTH_CHROMA); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED), -+ PCM_LOOP_FILTER_DISABLED_FLAG); -+ WRITE_PPS(sps->log2_diff_max_min_pcm_luma_coding_block_size, -+ LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE); -+ WRITE_PPS(sps->log2_min_pcm_luma_coding_block_size_minus3 + 3, -+ LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE); -+ } -+ WRITE_PPS(sps->num_short_term_ref_pic_sets, NUM_SHORT_TERM_REF_PIC_SETS); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT), -+ LONG_TERM_REF_PICS_PRESENT_FLAG); -+ WRITE_PPS(sps->num_long_term_ref_pics_sps, NUM_LONG_TERM_REF_PICS_SPS); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED), -+ SPS_TEMPORAL_MVP_ENABLED_FLAG); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED), -+ STRONG_INTRA_SMOOTHING_ENABLED_FLAG); -+ -+ /* write pps */ -+ WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID); -+ WRITE_PPS(sps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED), -+ DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT), -+ OUTPUT_FLAG_PRESENT_FLAG); -+ WRITE_PPS(pps->num_extra_slice_header_bits, NUM_EXTRA_SLICE_HEADER_BITS); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED), -+ SIGN_DATA_HIDING_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT), -+ CABAC_INIT_PRESENT_FLAG); -+ WRITE_PPS(pps->num_ref_idx_l0_default_active_minus1 + 1, -+ NUM_REF_IDX_L0_DEFAULT_ACTIVE); -+ WRITE_PPS(pps->num_ref_idx_l1_default_active_minus1 + 1, -+ NUM_REF_IDX_L1_DEFAULT_ACTIVE); -+ WRITE_PPS(pps->init_qp_minus26, INIT_QP_MINUS26); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED), -+ CONSTRAINED_INTRA_PRED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED), -+ TRANSFORM_SKIP_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED), -+ CU_QP_DELTA_ENABLED_FLAG); -+ -+ min_cb_log2_size_y = sps->log2_min_luma_coding_block_size_minus3 + 3; -+ ctb_log2_size_y = min_cb_log2_size_y + -+ sps->log2_diff_max_min_luma_coding_block_size; -+ ctb_size_y = 1 << ctb_log2_size_y; -+ log2_min_cu_qp_delta_size = ctb_log2_size_y - pps->diff_cu_qp_delta_depth; -+ WRITE_PPS(log2_min_cu_qp_delta_size, LOG2_MIN_CU_QP_DELTA_SIZE); -+ WRITE_PPS(pps->pps_cb_qp_offset, PPS_CB_QP_OFFSET); -+ WRITE_PPS(pps->pps_cr_qp_offset, PPS_CR_QP_OFFSET); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT), -+ PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED), -+ WEIGHTED_PRED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED), -+ WEIGHTED_BIPRED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED), -+ TRANSQUANT_BYPASS_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED), -+ TILES_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED), -+ ENTROPY_CODING_SYNC_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED), -+ PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED), -+ LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED), -+ DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER), -+ PPS_DEBLOCKING_FILTER_DISABLED_FLAG); -+ WRITE_PPS(pps->pps_beta_offset_div2, PPS_BETA_OFFSET_DIV2); -+ WRITE_PPS(pps->pps_tc_offset_div2, PPS_TC_OFFSET_DIV2); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT), -+ LISTS_MODIFICATION_PRESENT_FLAG); -+ WRITE_PPS(pps->log2_parallel_merge_level_minus2 + 2, LOG2_PARALLEL_MERGE_LEVEL); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT), -+ SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG); -+ WRITE_PPS(pps->num_tile_columns_minus1 + 1, NUM_TILE_COLUMNS); -+ WRITE_PPS(pps->num_tile_rows_minus1 + 1, NUM_TILE_ROWS); -+ -+ if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) { -+ /* Userspace also provide column width and row height for uniform spacing */ -+ for (i = 0; i <= pps->num_tile_columns_minus1; i++) -+ WRITE_PPS(pps->column_width_minus1[i], COLUMN_WIDTH(i)); -+ for (i = 0; i <= pps->num_tile_rows_minus1; i++) -+ WRITE_PPS(pps->row_height_minus1[i], ROW_HEIGHT(i)); -+ } else { -+ WRITE_PPS(((sps->pic_width_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1, -+ COLUMN_WIDTH(0)); -+ WRITE_PPS(((sps->pic_height_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1, -+ ROW_HEIGHT(0)); -+ } -+ -+ scaling_distance = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list); -+ scaling_list_address = hevc_ctx->priv_tbl.dma + scaling_distance; -+ WRITE_PPS(scaling_list_address, SCALING_LIST_ADDRESS); -+} -+ -+/* -+ * Creation of the Reference Picture Set memory blob for the hardware. -+ * The layout looks like this: -+ * [0] 32 bits for L0 (6 references + 2 bits of the 7th reference) -+ * [1] 32 bits for L0 (remaining 3 bits of the 7th reference + 5 references -+ * + 4 bits of the 13th reference) -+ * [2] 11 bits for L0 (remaining bit for 13 and 2 references) and -+ * 21 bits for L1 (4 references + first bit of 5) -+ * [3] 32 bits of padding with 0s -+ * [4] 32 bits for L1 (remaining 4 bits for 5 + 5 references + 3 bits of 11) -+ * [5] 22 bits for L1 (remaining 2 bits of 11 and 4 references) -+ * lowdelay flag (bit 23), rps bit offset long term (bit 24 - 32) -+ * [6] rps bit offset long term (bit 1 - 3), rps bit offset short term (bit 4 - 12) -+ * number of references (bit 13 - 16), remaining 16 bits of padding with 0s -+ * [7] 32 bits of padding with 0s -+ * -+ * Thus we have to set up padding in between reference 5 of the L1 list. -+ */ -+static void assemble_hw_rps(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -+ const struct v4l2_ctrl_hevc_sps *sps = run->sps; -+ const struct v4l2_ctrl_hevc_slice_params *sl_params; -+ const struct v4l2_hevc_dpb_entry *dpb; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; -+ struct rkvdec_rps_packet *hw_ps; -+ int i, j; -+ unsigned int lowdelay; -+ -+#define WRITE_RPS(value, field) set_ps_field(hw_ps->info, field, value) -+ -+#define REF_PIC_LONG_TERM_L0(i) PS_FIELD((i) * 5, 1) -+#define REF_PIC_IDX_L0(i) PS_FIELD(1 + ((i) * 5), 4) -+#define REF_PIC_LONG_TERM_L1(i) PS_FIELD(((i) < 5 ? 75 : 132) + ((i) * 5), 1) -+#define REF_PIC_IDX_L1(i) PS_FIELD(((i) < 4 ? 76 : 128) + ((i) * 5), 4) -+ -+#define LOWDELAY PS_FIELD(182, 1) -+#define LONG_TERM_RPS_BIT_OFFSET PS_FIELD(183, 10) -+#define SHORT_TERM_RPS_BIT_OFFSET PS_FIELD(193, 9) -+#define NUM_RPS_POC PS_FIELD(202, 4) -+ -+ for (j = 0; j < run->num_slices; j++) { -+ uint st_bit_offset = 0; -+ uint num_l0_refs = 0; -+ uint num_l1_refs = 0; -+ -+ sl_params = &run->slices_params[j]; -+ dpb = decode_params->dpb; -+ -+ if (sl_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) { -+ num_l0_refs = sl_params->num_ref_idx_l0_active_minus1 + 1; -+ -+ if (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_B) -+ num_l1_refs = sl_params->num_ref_idx_l1_active_minus1 + 1; -+ -+ lowdelay = 1; -+ } else { -+ lowdelay = 0; -+ } -+ -+ hw_ps = &priv_tbl->rps[j]; -+ memset(hw_ps, 0, sizeof(*hw_ps)); -+ -+ for (i = 0; i < num_l0_refs; i++) { -+ const struct v4l2_hevc_dpb_entry dpb_l0 = dpb[sl_params->ref_idx_l0[i]]; -+ -+ WRITE_RPS(!!(dpb_l0.flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), -+ REF_PIC_LONG_TERM_L0(i)); -+ WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i)); -+ -+ if (dpb_l0.pic_order_cnt_val > sl_params->slice_pic_order_cnt) -+ lowdelay = 0; -+ } -+ -+ for (i = 0; i < num_l1_refs; i++) { -+ const struct v4l2_hevc_dpb_entry dpb_l1 = dpb[sl_params->ref_idx_l1[i]]; -+ int is_long_term = -+ !!(dpb_l1.flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE); -+ -+ WRITE_RPS(is_long_term, REF_PIC_LONG_TERM_L1(i)); -+ WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i)); -+ -+ if (dpb_l1.pic_order_cnt_val > sl_params->slice_pic_order_cnt) -+ lowdelay = 0; -+ } -+ -+ WRITE_RPS(lowdelay, LOWDELAY); -+ -+ if (!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC)) { -+ if (sl_params->short_term_ref_pic_set_size) -+ st_bit_offset = sl_params->short_term_ref_pic_set_size; -+ else if (sps->num_short_term_ref_pic_sets > 1) -+ st_bit_offset = fls(sps->num_short_term_ref_pic_sets - 1); -+ } -+ -+ WRITE_RPS(st_bit_offset + sl_params->long_term_ref_pic_set_size, -+ LONG_TERM_RPS_BIT_OFFSET); -+ WRITE_RPS(sl_params->short_term_ref_pic_set_size, -+ SHORT_TERM_RPS_BIT_OFFSET); -+ -+ WRITE_RPS(decode_params->num_poc_st_curr_before + -+ decode_params->num_poc_st_curr_after + -+ decode_params->num_poc_lt_curr, -+ NUM_RPS_POC); -+ } -+} -+ -+/* -+ * Flip one or more matrices along their main diagonal and flatten them -+ * before writing it to the memory. -+ * Convert: -+ * ABCD AEIM -+ * EFGH => BFJN => AEIMBFJNCGKODHLP -+ * IJKL CGKO -+ * MNOP DHLP -+ */ -+static void transpose_and_flatten_matrices(u8 *output, const u8 *input, -+ int matrices, int row_length) -+{ -+ int i, j, row, x_offset, matrix_offset, rot_index, y_offset, matrix_size, new_value; -+ -+ matrix_size = row_length * row_length; -+ for (i = 0; i < matrices; i++) { -+ row = 0; -+ x_offset = 0; -+ matrix_offset = i * matrix_size; -+ for (j = 0; j < matrix_size; j++) { -+ y_offset = j - (row * row_length); -+ rot_index = y_offset * row_length + x_offset; -+ new_value = *(input + i * matrix_size + j); -+ output[matrix_offset + rot_index] = new_value; -+ if ((j + 1) % row_length == 0) { -+ row += 1; -+ x_offset += 1; -+ } -+ } -+ } -+} -+ -+static void assemble_scalingfactor0(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input) -+{ -+ int offset = 0; -+ -+ transpose_and_flatten_matrices(output, (const u8 *)input->scaling_list_4x4, 6, 4); -+ offset = 6 * 16 * sizeof(u8); -+ transpose_and_flatten_matrices(output + offset, (const u8 *)input->scaling_list_8x8, 6, 8); -+ offset += 6 * 64 * sizeof(u8); -+ transpose_and_flatten_matrices(output + offset, -+ (const u8 *)input->scaling_list_16x16, 6, 8); -+ offset += 6 * 64 * sizeof(u8); -+ /* Add a 128 byte padding with 0s between the two 32x32 matrices */ -+ transpose_and_flatten_matrices(output + offset, -+ (const u8 *)input->scaling_list_32x32, 1, 8); -+ offset += 64 * sizeof(u8); -+ memset(output + offset, 0, 128); -+ offset += 128 * sizeof(u8); -+ transpose_and_flatten_matrices(output + offset, -+ (const u8 *)input->scaling_list_32x32 + (64 * sizeof(u8)), -+ 1, 8); -+ offset += 64 * sizeof(u8); -+ memset(output + offset, 0, 128); -+} -+ -+/* -+ * Required layout: -+ * A = scaling_list_dc_coef_16x16 -+ * B = scaling_list_dc_coef_32x32 -+ * 0 = Padding -+ * -+ * A, A, A, A, A, A, B, 0, 0, B, 0, 0 -+ */ -+static void assemble_scalingdc(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input) -+{ -+ u8 list_32x32[6] = {0}; -+ -+ memcpy(output, input->scaling_list_dc_coef_16x16, 6 * sizeof(u8)); -+ list_32x32[0] = input->scaling_list_dc_coef_32x32[0]; -+ list_32x32[3] = input->scaling_list_dc_coef_32x32[1]; -+ memcpy(output + 6 * sizeof(u8), list_32x32, 6 * sizeof(u8)); -+} -+ -+static void translate_scaling_list(struct scaling_factor *output, -+ const struct v4l2_ctrl_hevc_scaling_matrix *input) -+{ -+ assemble_scalingfactor0(output->scalingfactor0, input); -+ memcpy(output->scalingfactor1, (const u8 *)input->scaling_list_4x4, 96); -+ assemble_scalingdc(output->scalingdc, input); -+ memset(output->reserved, 0, 4 * sizeof(u8)); -+} -+ -+static void assemble_hw_scaling_list(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling = run->scaling_matrix; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu; -+ u8 *dst; -+ -+ if (!memcmp((void *)&hevc_ctx->scaling_matrix_cache, scaling, -+ sizeof(struct v4l2_ctrl_hevc_scaling_matrix))) -+ return; -+ -+ dst = tbl->scaling_list; -+ translate_scaling_list((struct scaling_factor *)dst, scaling); -+ -+ memcpy((void *)&hevc_ctx->scaling_matrix_cache, scaling, -+ sizeof(struct v4l2_ctrl_hevc_scaling_matrix)); -+} -+ -+static struct vb2_buffer * -+get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run, -+ unsigned int dpb_idx) -+{ -+ struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; -+ struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; -+ struct vb2_buffer *buf = NULL; -+ -+ if (dpb_idx < decode_params->num_active_dpb_entries) -+ buf = vb2_find_buffer(cap_q, dpb[dpb_idx].timestamp); -+ -+ /* -+ * If a DPB entry is unused or invalid, the address of current destination -+ * buffer is returned. -+ */ -+ if (!buf) -+ return &run->base.bufs.dst->vb2_buf; -+ -+ return buf; -+} -+ -+static void config_registers(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -+ const struct v4l2_ctrl_hevc_sps *sps = run->sps; -+ const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0]; -+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma; -+ const struct v4l2_pix_format_mplane *dst_fmt; -+ struct vb2_v4l2_buffer *src_buf = run->base.bufs.src; -+ struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst; -+ const struct v4l2_format *f; -+ dma_addr_t rlc_addr; -+ dma_addr_t refer_addr; -+ u32 rlc_len; -+ u32 hor_virstride; -+ u32 ver_virstride; -+ u32 y_virstride; -+ u32 yuv_virstride = 0; -+ u32 offset; -+ dma_addr_t dst_addr; -+ u32 reg, i; -+ -+ reg = RKVDEC_MODE(RKVDEC_MODE_HEVC); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_SYSCTRL); -+ -+ f = &ctx->decoded_fmt; -+ dst_fmt = &f->fmt.pix_mp; -+ hor_virstride = dst_fmt->plane_fmt[0].bytesperline; -+ ver_virstride = dst_fmt->height; -+ y_virstride = hor_virstride * ver_virstride; -+ -+ if (sps->chroma_format_idc == 0) -+ yuv_virstride = y_virstride; -+ else if (sps->chroma_format_idc == 1) -+ yuv_virstride = y_virstride + y_virstride / 2; -+ else if (sps->chroma_format_idc == 2) -+ yuv_virstride = 2 * y_virstride; -+ -+ reg = RKVDEC_Y_HOR_VIRSTRIDE(hor_virstride / 16) | -+ RKVDEC_UV_HOR_VIRSTRIDE(hor_virstride / 16) | -+ RKVDEC_SLICE_NUM_LOWBITS(run->num_slices); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_PICPAR); -+ -+ /* config rlc base address */ -+ rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); -+ writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE); -+ -+ rlc_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0); -+ reg = RKVDEC_STRM_LEN(round_up(rlc_len, 16) + 64); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_STRM_LEN); -+ -+ /* config cabac table */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table); -+ writel_relaxed(priv_start_addr + offset, -+ rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE); -+ -+ /* config output base address */ -+ dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); -+ writel_relaxed(dst_addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE); -+ -+ reg = RKVDEC_Y_VIRSTRIDE(y_virstride / 16); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE); -+ -+ reg = RKVDEC_YUV_VIRSTRIDE(yuv_virstride / 16); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE); -+ -+ /* config ref pic address */ -+ for (i = 0; i < 15; i++) { -+ struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i); -+ -+ if (i < 4 && decode_params->num_active_dpb_entries) { -+ reg = GENMASK(decode_params->num_active_dpb_entries - 1, 0); -+ reg = (reg >> (i * 4)) & 0xf; -+ } else { -+ reg = 0; -+ } -+ -+ refer_addr = vb2_dma_contig_plane_dma_addr(vb_buf, 0); -+ writel_relaxed(refer_addr | reg, -+ rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i)); -+ -+ reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ? -+ dpb[i].pic_order_cnt_val : 0); -+ writel_relaxed(reg, -+ rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i)); -+ } -+ -+ reg = RKVDEC_CUR_POC(sl_params->slice_pic_order_cnt); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0); -+ -+ /* config hw pps address */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set); -+ writel_relaxed(priv_start_addr + offset, -+ rkvdec->regs + RKVDEC_REG_PPS_BASE); -+ -+ /* config hw rps address */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, rps); -+ writel_relaxed(priv_start_addr + offset, -+ rkvdec->regs + RKVDEC_REG_RPS_BASE); -+ -+ reg = RKVDEC_AXI_DDR_RDATA(0); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_RDATA); -+ -+ reg = RKVDEC_AXI_DDR_WDATA(0); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_WDATA); -+} -+ -+#define RKVDEC_HEVC_MAX_DEPTH_IN_BYTES 2 -+ -+static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, -+ struct v4l2_format *f) -+{ -+ struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp; -+ -+ fmt->num_planes = 1; -+ if (!fmt->plane_fmt[0].sizeimage) -+ fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height * -+ RKVDEC_HEVC_MAX_DEPTH_IN_BYTES; -+ return 0; -+} -+ -+static enum rkvdec_image_fmt rkvdec_hevc_get_image_fmt(struct rkvdec_ctx *ctx, -+ struct v4l2_ctrl *ctrl) -+{ -+ const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; -+ -+ if (ctrl->id != V4L2_CID_STATELESS_HEVC_SPS) -+ return RKVDEC_IMG_FMT_ANY; -+ -+ if (sps->bit_depth_luma_minus8 == 0) { -+ if (sps->chroma_format_idc == 2) -+ return RKVDEC_IMG_FMT_422_8BIT; -+ else -+ return RKVDEC_IMG_FMT_420_8BIT; -+ } else if (sps->bit_depth_luma_minus8 == 2) { -+ if (sps->chroma_format_idc == 2) -+ return RKVDEC_IMG_FMT_422_10BIT; -+ else -+ return RKVDEC_IMG_FMT_420_10BIT; -+ } -+ -+ return RKVDEC_IMG_FMT_ANY; -+} -+ -+static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, -+ const struct v4l2_ctrl_hevc_sps *sps) -+{ -+ if (sps->chroma_format_idc > 1) -+ /* Only 4:0:0 and 4:2:0 are supported */ -+ return -EINVAL; -+ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) -+ /* Luma and chroma bit depth mismatch */ -+ return -EINVAL; -+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) -+ /* Only 8-bit and 10-bit is supported */ -+ return -EINVAL; -+ -+ if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width || -+ sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static int rkvdec_hevc_start(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_hevc_priv_tbl *priv_tbl; -+ struct rkvdec_hevc_ctx *hevc_ctx; -+ -+ hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL); -+ if (!hevc_ctx) -+ return -ENOMEM; -+ -+ priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl), -+ &hevc_ctx->priv_tbl.dma, GFP_KERNEL); -+ if (!priv_tbl) { -+ kfree(hevc_ctx); -+ return -ENOMEM; -+ } -+ -+ hevc_ctx->priv_tbl.size = sizeof(*priv_tbl); -+ hevc_ctx->priv_tbl.cpu = priv_tbl; -+ memcpy(priv_tbl->cabac_table, rkvdec_hevc_cabac_table, -+ sizeof(rkvdec_hevc_cabac_table)); -+ -+ ctx->priv = hevc_ctx; -+ return 0; -+} -+ -+static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ -+ dma_free_coherent(rkvdec->dev, hevc_ctx->priv_tbl.size, -+ hevc_ctx->priv_tbl.cpu, hevc_ctx->priv_tbl.dma); -+ kfree(hevc_ctx); -+} -+ -+static void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ struct v4l2_ctrl *ctrl; -+ -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_DECODE_PARAMS); -+ run->decode_params = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SLICE_PARAMS); -+ run->slices_params = ctrl ? ctrl->p_cur.p : NULL; -+ run->num_slices = ctrl ? ctrl->new_elems : 0; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SPS); -+ run->sps = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_PPS); -+ run->pps = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SCALING_MATRIX); -+ run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL; -+ -+ rkvdec_run_preamble(ctx, &run->base); -+} -+ -+static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_hevc_run run; -+ u32 reg; -+ -+ rkvdec_hevc_run_preamble(ctx, &run); -+ -+ assemble_hw_scaling_list(ctx, &run); -+ assemble_hw_pps(ctx, &run); -+ assemble_hw_rps(ctx, &run); -+ config_registers(ctx, &run); -+ -+ rkvdec_run_postamble(ctx, &run.base); -+ -+ schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000)); -+ -+ writel(0, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN); -+ writel(0, rkvdec->regs + RKVDEC_REG_H264_ERR_E); -+ writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND); -+ writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); -+ -+ /* Start decoding! */ -+ reg = (run.pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) ? -+ 0 : RKVDEC_WR_DDR_ALIGN_EN; -+ writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E | -+ RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E | reg, -+ rkvdec->regs + RKVDEC_REG_INTERRUPT); -+ -+ return 0; -+} -+ -+static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) -+{ -+ if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS) -+ return rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); -+ -+ return 0; -+} -+ -+const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = { -+ .adjust_fmt = rkvdec_hevc_adjust_fmt, -+ .start = rkvdec_hevc_start, -+ .stop = rkvdec_hevc_stop, -+ .run = rkvdec_hevc_run, -+ .try_ctrl = rkvdec_hevc_try_ctrl, -+ .get_image_fmt = rkvdec_hevc_get_image_fmt, -+}; -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h b/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h -@@ -28,6 +28,7 @@ - #define RKVDEC_SOFTRST_EN_P BIT(20) - #define RKVDEC_FORCE_SOFTRESET_VALID BIT(21) - #define RKVDEC_SOFTRESET_RDY BIT(22) -+#define RKVDEC_WR_DDR_ALIGN_EN BIT(23) - - #define RKVDEC_REG_SYSCTRL 0x008 - #define RKVDEC_IN_ENDIAN BIT(0) -@@ -43,6 +44,7 @@ - #define RKVDEC_RLC_MODE BIT(11) - #define RKVDEC_STRM_START_BIT(x) (((x) & 0x7f) << 12) - #define RKVDEC_MODE(x) (((x) & 0x03) << 20) -+#define RKVDEC_MODE_HEVC 0 - #define RKVDEC_MODE_H264 1 - #define RKVDEC_MODE_VP9 2 - #define RKVDEC_RPS_MODE BIT(24) -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -@@ -158,6 +158,67 @@ static const struct v4l2_ctrl_ops rkvdec_ctrl_ops = { - .s_ctrl = rkvdec_s_ctrl, - }; - -+static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_SLICE_PARAMS, -+ .cfg.flags = V4L2_CTRL_FLAG_DYNAMIC_ARRAY, -+ .cfg.type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS, -+ .cfg.dims = { 600 }, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_SPS, -+ .cfg.ops = &rkvdec_ctrl_ops, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_PPS, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE, -+ .cfg.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, -+ .cfg.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, -+ .cfg.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_START_CODE, -+ .cfg.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, -+ .cfg.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, -+ .cfg.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, -+ }, -+ { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, -+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, -+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, -+ .cfg.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, -+ }, -+ { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, -+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1, -+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, -+ }, -+}; -+ -+static const struct rkvdec_ctrls rkvdec_hevc_ctrls = { -+ .ctrls = rkvdec_hevc_ctrl_descs, -+ .num_ctrls = ARRAY_SIZE(rkvdec_hevc_ctrl_descs), -+}; -+ -+static const struct rkvdec_decoded_fmt_desc rkvdec_hevc_decoded_fmts[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_NV12, -+ .image_fmt = RKVDEC_IMG_FMT_420_8BIT, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_NV15, -+ .image_fmt = RKVDEC_IMG_FMT_420_10BIT, -+ }, -+}; -+ - static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { - { - .cfg.id = V4L2_CID_STATELESS_H264_DECODE_PARAMS, -@@ -252,6 +313,21 @@ static const struct rkvdec_decoded_fmt_desc rkvdec_vp9_decoded_fmts[] = { - }; - - static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_HEVC_SLICE, -+ .frmsize = { -+ .min_width = 64, -+ .max_width = 4096, -+ .step_width = 64, -+ .min_height = 64, -+ .max_height = 2304, -+ .step_height = 16, -+ }, -+ .ctrls = &rkvdec_hevc_ctrls, -+ .ops = &rkvdec_hevc_fmt_ops, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), -+ .decoded_fmts = rkvdec_hevc_decoded_fmts, -+ }, - { - .fourcc = V4L2_PIX_FMT_H264_SLICE, - .frmsize = { -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.h b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.h -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -@@ -139,6 +139,7 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); - void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); - - extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops; -+extern const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops; - extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops; - - #endif /* RKVDEC_H_ */ --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sun, 10 Aug 2025 21:24:32 +0000 -Subject: media: rkvdec: Add variants support - -Different versions of the Rockchip VDEC IP exists and one way they can -differ is what decoding formats are supported. - -Add a variant implementation in order to support flagging different -capabilities. - -Signed-off-by: Alex Bee -Signed-off-by: Jonas Karlman -Reviewed-by: Nicolas Dufresne ---- - drivers/media/platform/rockchip/rkvdec/rkvdec.c | 21 +++++++++- - drivers/media/platform/rockchip/rkvdec/rkvdec.h | 10 +++++ - 2 files changed, 30 insertions(+), 1 deletion(-) - -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -@@ -14,6 +14,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -327,6 +328,7 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - .ops = &rkvdec_hevc_fmt_ops, - .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), - .decoded_fmts = rkvdec_hevc_decoded_fmts, -+ .capability = RKVDEC_CAPABILITY_HEVC, - }, - { - .fourcc = V4L2_PIX_FMT_H264_SLICE, -@@ -343,6 +345,7 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), - .decoded_fmts = rkvdec_h264_decoded_fmts, - .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, -+ .capability = RKVDEC_CAPABILITY_H264, - }, - { - .fourcc = V4L2_PIX_FMT_VP9_FRAME, -@@ -358,6 +361,7 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - .ops = &rkvdec_vp9_fmt_ops, - .num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts), - .decoded_fmts = rkvdec_vp9_decoded_fmts, -+ .capability = RKVDEC_CAPABILITY_VP9, - } - }; - -@@ -1185,8 +1189,17 @@ static void rkvdec_watchdog_func(struct work_struct *work) - } - } - -+static const struct rkvdec_variant rk3399_rkvdec_variant = { -+ .capabilities = RKVDEC_CAPABILITY_HEVC | -+ RKVDEC_CAPABILITY_H264 | -+ RKVDEC_CAPABILITY_VP9, -+}; -+ - static const struct of_device_id of_rkvdec_match[] = { -- { .compatible = "rockchip,rk3399-vdec" }, -+ { -+ .compatible = "rockchip,rk3399-vdec", -+ .data = &rk3399_rkvdec_variant, -+ }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, of_rkvdec_match); -@@ -1197,16 +1210,22 @@ static const char * const rkvdec_clk_names[] = { - - static int rkvdec_probe(struct platform_device *pdev) - { -+ const struct rkvdec_variant *variant; - struct rkvdec_dev *rkvdec; - unsigned int i; - int ret, irq; - -+ variant = of_device_get_match_data(&pdev->dev); -+ if (!variant) -+ return -EINVAL; -+ - rkvdec = devm_kzalloc(&pdev->dev, sizeof(*rkvdec), GFP_KERNEL); - if (!rkvdec) - return -ENOMEM; - - platform_set_drvdata(pdev, rkvdec); - rkvdec->dev = &pdev->dev; -+ rkvdec->capabilities = variant->capabilities; - mutex_init(&rkvdec->vdev_lock); - INIT_DELAYED_WORK(&rkvdec->watchdog_work, rkvdec_watchdog_func); - -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.h b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.h -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -@@ -22,6 +22,10 @@ - #include - #include - -+#define RKVDEC_CAPABILITY_HEVC BIT(0) -+#define RKVDEC_CAPABILITY_H264 BIT(1) -+#define RKVDEC_CAPABILITY_VP9 BIT(2) -+ - struct rkvdec_ctx; - - struct rkvdec_ctrl_desc { -@@ -63,6 +67,10 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) - base.vb.vb2_buf); - } - -+struct rkvdec_variant { -+ unsigned int capabilities; -+}; -+ - struct rkvdec_coded_fmt_ops { - int (*adjust_fmt)(struct rkvdec_ctx *ctx, - struct v4l2_format *f); -@@ -98,6 +106,7 @@ struct rkvdec_coded_fmt_desc { - unsigned int num_decoded_fmts; - const struct rkvdec_decoded_fmt_desc *decoded_fmts; - u32 subsystem_flags; -+ unsigned int capability; - }; - - struct rkvdec_dev { -@@ -111,6 +120,7 @@ struct rkvdec_dev { - struct mutex vdev_lock; /* serializes ioctls */ - struct delayed_work watchdog_work; - struct iommu_domain *empty_domain; -+ unsigned int capabilities; - }; - - struct rkvdec_ctx { --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 10 Aug 2025 21:24:33 +0000 -Subject: media: rkvdec: Implement capability filtering - -Add filtering of coded formats and controls depending on a variant -capabilities. - -Signed-off-by: Alex Bee -Signed-off-by: Jonas Karlman -Reviewed-by: Nicolas Dufresne ---- - drivers/media/platform/rockchip/rkvdec/rkvdec.c | 67 +++++++--- - 1 file changed, 49 insertions(+), 18 deletions(-) - -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -@@ -365,13 +365,36 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - } - }; - -+static bool rkvdec_is_capable(struct rkvdec_ctx *ctx, unsigned int capability) -+{ -+ return (ctx->dev->capabilities & capability) == capability; -+} -+ - static const struct rkvdec_coded_fmt_desc * --rkvdec_find_coded_fmt_desc(u32 fourcc) -+rkvdec_enum_coded_fmt_desc(struct rkvdec_ctx *ctx, int index) - { -+ int fmt_idx = -1; - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { -- if (rkvdec_coded_fmts[i].fourcc == fourcc) -+ if (!rkvdec_is_capable(ctx, rkvdec_coded_fmts[i].capability)) -+ continue; -+ fmt_idx++; -+ if (index == fmt_idx) -+ return &rkvdec_coded_fmts[i]; -+ } -+ -+ return NULL; -+} -+ -+static const struct rkvdec_coded_fmt_desc * -+rkvdec_find_coded_fmt_desc(struct rkvdec_ctx *ctx, u32 fourcc) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { -+ if (rkvdec_is_capable(ctx, rkvdec_coded_fmts[i].capability) && -+ rkvdec_coded_fmts[i].fourcc == fourcc) - return &rkvdec_coded_fmts[i]; - } - -@@ -382,7 +405,7 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx) - { - struct v4l2_format *f = &ctx->coded_fmt; - -- ctx->coded_fmt_desc = &rkvdec_coded_fmts[0]; -+ ctx->coded_fmt_desc = rkvdec_enum_coded_fmt_desc(ctx, 0); - rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->fourcc); - - f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; -@@ -396,21 +419,22 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx) - static int rkvdec_enum_framesizes(struct file *file, void *priv, - struct v4l2_frmsizeenum *fsize) - { -- const struct rkvdec_coded_fmt_desc *fmt; -+ struct rkvdec_ctx *ctx = file_to_rkvdec_ctx(file); -+ const struct rkvdec_coded_fmt_desc *desc; - - if (fsize->index != 0) - return -EINVAL; - -- fmt = rkvdec_find_coded_fmt_desc(fsize->pixel_format); -- if (!fmt) -+ desc = rkvdec_find_coded_fmt_desc(ctx, fsize->pixel_format); -+ if (!desc) - return -EINVAL; - - fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS; - fsize->stepwise.min_width = 1; -- fsize->stepwise.max_width = fmt->frmsize.max_width; -+ fsize->stepwise.max_width = desc->frmsize.max_width; - fsize->stepwise.step_width = 1; - fsize->stepwise.min_height = 1; -- fsize->stepwise.max_height = fmt->frmsize.max_height; -+ fsize->stepwise.max_height = desc->frmsize.max_height; - fsize->stepwise.step_height = 1; - - return 0; -@@ -470,10 +494,10 @@ static int rkvdec_try_output_fmt(struct file *file, void *priv, - struct rkvdec_ctx *ctx = file_to_rkvdec_ctx(file); - const struct rkvdec_coded_fmt_desc *desc; - -- desc = rkvdec_find_coded_fmt_desc(pix_mp->pixelformat); -+ desc = rkvdec_find_coded_fmt_desc(ctx, pix_mp->pixelformat); - if (!desc) { -- pix_mp->pixelformat = rkvdec_coded_fmts[0].fourcc; -- desc = &rkvdec_coded_fmts[0]; -+ desc = rkvdec_enum_coded_fmt_desc(ctx, 0); -+ pix_mp->pixelformat = desc->fourcc; - } - - v4l2_apply_frmsize_constraints(&pix_mp->width, -@@ -550,7 +574,7 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv, - if (ret) - return ret; - -- desc = rkvdec_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat); -+ desc = rkvdec_find_coded_fmt_desc(ctx, f->fmt.pix_mp.pixelformat); - if (!desc) - return -EINVAL; - ctx->coded_fmt_desc = desc; -@@ -602,10 +626,14 @@ static int rkvdec_g_capture_fmt(struct file *file, void *priv, - static int rkvdec_enum_output_fmt(struct file *file, void *priv, - struct v4l2_fmtdesc *f) - { -- if (f->index >= ARRAY_SIZE(rkvdec_coded_fmts)) -+ struct rkvdec_ctx *ctx = file_to_rkvdec_ctx(file); -+ const struct rkvdec_coded_fmt_desc *desc; -+ -+ desc = rkvdec_enum_coded_fmt_desc(ctx, f->index); -+ if (!desc) - return -EINVAL; - -- f->pixelformat = rkvdec_coded_fmts[f->index].fourcc; -+ f->pixelformat = desc->fourcc; - return 0; - } - -@@ -969,14 +997,17 @@ static int rkvdec_init_ctrls(struct rkvdec_ctx *ctx) - int ret; - - for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) -- nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls; -+ if (rkvdec_is_capable(ctx, rkvdec_coded_fmts[i].capability)) -+ nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls; - - v4l2_ctrl_handler_init(&ctx->ctrl_hdl, nctrls); - - for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { -- ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls); -- if (ret) -- goto err_free_handler; -+ if (rkvdec_is_capable(ctx, rkvdec_coded_fmts[i].capability)) { -+ ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls); -+ if (ret) -+ goto err_free_handler; -+ } - } - - ret = v4l2_ctrl_handler_setup(&ctx->ctrl_hdl); --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sun, 10 Aug 2025 21:24:34 +0000 -Subject: media: rkvdec: Add RK3288 variant - -Add a RK3288 variant, a version of the Rockchip VDEC IP that only -support HEVC decoding. - -Signed-off-by: Alex Bee -Signed-off-by: Jonas Karlman -Reviewed-by: Nicolas Dufresne ---- - drivers/media/platform/rockchip/rkvdec/rkvdec.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -@@ -1220,6 +1220,10 @@ static void rkvdec_watchdog_func(struct work_struct *work) - } - } - -+static const struct rkvdec_variant rk3288_rkvdec_variant = { -+ .capabilities = RKVDEC_CAPABILITY_HEVC, -+}; -+ - static const struct rkvdec_variant rk3399_rkvdec_variant = { - .capabilities = RKVDEC_CAPABILITY_HEVC | - RKVDEC_CAPABILITY_H264 | -@@ -1227,6 +1231,10 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = { - }; - - static const struct of_device_id of_rkvdec_match[] = { -+ { -+ .compatible = "rockchip,rk3288-vdec", -+ .data = &rk3288_rkvdec_variant, -+ }, - { - .compatible = "rockchip,rk3399-vdec", - .data = &rk3399_rkvdec_variant, --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sun, 10 Aug 2025 21:24:35 +0000 -Subject: media: rkvdec: Disable QoS for HEVC and VP9 on RK3328 - -The RK3328 VDEC has a HW quirk that require QoS to be disabled when HEVC -or VP9 is decoded, otherwise the decoded picture may become corrupted. - -Add a RK3328 variant with a quirk flag to disable QoS when before -decoding is started. - -Signed-off-by: Alex Bee -Signed-off-by: Jonas Karlman ---- - drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c | 9 +++++++ - drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h | 2 ++ - drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c | 10 ++++++++ - drivers/media/platform/rockchip/rkvdec/rkvdec.c | 12 ++++++++++ - drivers/media/platform/rockchip/rkvdec/rkvdec.h | 4 ++++ - 5 files changed, 37 insertions(+) - -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c -@@ -789,6 +789,15 @@ static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) - writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND); - writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); - -+ if (rkvdec->quirks & RKVDEC_QUIRK_DISABLE_QOS) { -+ u32 reg; -+ -+ reg = readl(rkvdec->regs + RKVDEC_REG_QOS_CTRL); -+ reg |= 0xFFFF; -+ reg &= ~BIT(12); -+ writel(reg, rkvdec->regs + RKVDEC_REG_QOS_CTRL); -+ } -+ - /* Start decoding! */ - reg = (run.pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) ? - 0 : RKVDEC_WR_DDR_ALIGN_EN; -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h b/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h -@@ -219,6 +219,8 @@ - #define RKVDEC_REG_H264_ERR_E 0x134 - #define RKVDEC_H264_ERR_EN_HIGHBITS(x) ((x) & 0x3fffffff) - -+#define RKVDEC_REG_QOS_CTRL 0x18C -+ - #define RKVDEC_REG_PREF_LUMA_CACHE_COMMAND 0x410 - #define RKVDEC_REG_PREF_CHR_CACHE_COMMAND 0x450 - -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c -@@ -824,6 +824,16 @@ static int rkvdec_vp9_run(struct rkvdec_ctx *ctx) - writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); - - writel(0xe, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN); -+ -+ if (rkvdec->quirks & RKVDEC_QUIRK_DISABLE_QOS) { -+ u32 reg; -+ -+ reg = readl(rkvdec->regs + RKVDEC_REG_QOS_CTRL); -+ reg |= 0xFFFF; -+ reg &= ~BIT(12); -+ writel(reg, rkvdec->regs + RKVDEC_REG_QOS_CTRL); -+ } -+ - /* Start decoding! */ - writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E | - RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E, -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -@@ -1224,6 +1224,13 @@ static const struct rkvdec_variant rk3288_rkvdec_variant = { - .capabilities = RKVDEC_CAPABILITY_HEVC, - }; - -+static const struct rkvdec_variant rk3328_rkvdec_variant = { -+ .capabilities = RKVDEC_CAPABILITY_HEVC | -+ RKVDEC_CAPABILITY_H264 | -+ RKVDEC_CAPABILITY_VP9, -+ .quirks = RKVDEC_QUIRK_DISABLE_QOS, -+}; -+ - static const struct rkvdec_variant rk3399_rkvdec_variant = { - .capabilities = RKVDEC_CAPABILITY_HEVC | - RKVDEC_CAPABILITY_H264 | -@@ -1235,6 +1242,10 @@ static const struct of_device_id of_rkvdec_match[] = { - .compatible = "rockchip,rk3288-vdec", - .data = &rk3288_rkvdec_variant, - }, -+ { -+ .compatible = "rockchip,rk3328-vdec", -+ .data = &rk3328_rkvdec_variant, -+ }, - { - .compatible = "rockchip,rk3399-vdec", - .data = &rk3399_rkvdec_variant, -@@ -1265,6 +1276,7 @@ static int rkvdec_probe(struct platform_device *pdev) - platform_set_drvdata(pdev, rkvdec); - rkvdec->dev = &pdev->dev; - rkvdec->capabilities = variant->capabilities; -+ rkvdec->quirks = variant->quirks; - mutex_init(&rkvdec->vdev_lock); - INIT_DELAYED_WORK(&rkvdec->watchdog_work, rkvdec_watchdog_func); - -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.h b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.h -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -@@ -26,6 +26,8 @@ - #define RKVDEC_CAPABILITY_H264 BIT(1) - #define RKVDEC_CAPABILITY_VP9 BIT(2) - -+#define RKVDEC_QUIRK_DISABLE_QOS BIT(0) -+ - struct rkvdec_ctx; - - struct rkvdec_ctrl_desc { -@@ -69,6 +71,7 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) - - struct rkvdec_variant { - unsigned int capabilities; -+ unsigned int quirks; - }; - - struct rkvdec_coded_fmt_ops { -@@ -121,6 +124,7 @@ struct rkvdec_dev { - struct delayed_work watchdog_work; - struct iommu_domain *empty_domain; - unsigned int capabilities; -+ unsigned int quirks; - }; - - struct rkvdec_ctx { --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 10 Aug 2025 21:24:36 +0000 -Subject: media: dt-bindings: rockchip,vdec: Add RK3288 compatible - -Add a RK3288 compatible for a version of the Rockchip VDEC IP that only -support HEVC decoding. - -Signed-off-by: Jonas Karlman -Acked-by: Conor Dooley ---- - Documentation/devicetree/bindings/media/rockchip,vdec.yaml | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -index 111111111111..222222222222 100644 ---- a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -+++ b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -@@ -16,6 +16,7 @@ description: |- - properties: - compatible: - oneOf: -+ - const: rockchip,rk3288-vdec - - const: rockchip,rk3399-vdec - - const: rockchip,rk3576-vdec - - const: rockchip,rk3588-vdec --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sun, 10 Aug 2025 21:24:37 +0000 -Subject: ARM: dts: rockchip: Add vdec node for RK3288 - -RK3288 contains a Rockchip VDEC block that only support HEVC -decoding. Add a vdec node for this. - -Signed-off-by: Alex Bee -Signed-off-by: Jonas Karlman ---- - arch/arm/boot/dts/rockchip/rk3288.dtsi | 17 +++++++++- - 1 file changed, 16 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm/boot/dts/rockchip/rk3288.dtsi -+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi -@@ -1304,6 +1304,21 @@ vpu_mmu: iommu@ff9a0800 { - power-domains = <&power RK3288_PD_VIDEO>; - }; - -+ hevc: video-codec@ff9c0000 { -+ compatible = "rockchip,rk3288-vdec"; -+ reg = <0x0 0xff9c0000 0x0 0x440>; -+ interrupts = ; -+ clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, -+ <&cru SCLK_HEVC_CABAC>, <&cru SCLK_HEVC_CORE>; -+ clock-names = "axi", "ahb", "cabac", "core"; -+ assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, -+ <&cru SCLK_HEVC_CABAC>, <&cru SCLK_HEVC_CORE>; -+ assigned-clock-rates = <400000000>, <100000000>, -+ <300000000>, <300000000>; -+ iommus = <&hevc_mmu>; -+ power-domains = <&power RK3288_PD_HEVC>; -+ }; -+ - hevc_mmu: iommu@ff9c0440 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; -@@ -1311,7 +1326,7 @@ hevc_mmu: iommu@ff9c0440 { - clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; -- status = "disabled"; -+ power-domains = <&power RK3288_PD_HEVC>; - }; - - gpu: gpu@ffa30000 { --- -Armbian - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Detlev Casanova -Date: Thu, 24 Jul 2025 14:10:18 -0400 +Date: Thu, 18 Dec 2025 18:28:11 -0500 Subject: media: uapi: HEVC: Add v4l2_ctrl_hevc_ext_sps_[ls]t_rps controls -Some hardware (e.g.: Rockchip's rk3588 hevc decoder) need the -long and short term reference information for HEVC decoding. +Some hardware (e.g.: Rockchip's rk3588 hevc decoder) need to fully parse +the slice header, which cannot be passed with the current controls. +There is also no skip method similar as to what can be found in +verisilicon HW. -Add controls to provide it as the raw data form the stream. +The SPS is therefore extended through these 2 new controls, providing the +long and short term reference information from the slice header for HEVC +decoding. + +These now controls are similar as what is passed in the Vulkan Video API +with the StdVideoH265ShortTermRefPicSet and StdVideoH265LongTermRefPicsSps +structures embedded in the SPS struct. Signed-off-by: Detlev Casanova --- - Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst | 114 ++++++++++ + Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst | 120 ++++++++++ Documentation/userspace-api/media/v4l/videodev2.h.rst.exceptions | 2 + Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst | 12 + - 3 files changed, 128 insertions(+) + 3 files changed, 134 insertions(+) diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst b/Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst index 111111111111..222222222222 100644 --- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst +++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst -@@ -2958,6 +2958,120 @@ This structure contains all loop filter related parameters. See sections +@@ -2959,6 +2959,126 @@ This structure contains all loop filter related parameters. See sections - 0x00000004 - +``V4L2_CID_STATELESS_HEVC_EXT_SPS_LT_RPS (struct)`` -+ Specifies the list of Long-Term reference sets parameters from the SPS. ++ Subset of the :c:type:`v4l2_ctrl_hevc_sps` control. ++ It extends it with the list of Long-term reference sets parameters. + These parameters are defined according to :ref:`hevc`. + They are described in section 7.4.3.2.1 "General sequence parameter set + RBSP semantics" of the specification. -+ This control is a dynamically sized 1-dimensional array, -+ V4L2_CTRL_FLAG_DYNAMIC_ARRAY flag must be set when using it. ++ This control is a dynamically sized 1-dimensional array. ++ The values in the array should be ignored when either ++ num_long_term_ref_pics_sps is 0 or the ++ V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT flag is not set in ++ :c:type:`v4l2_ctrl_hevc_sps`. + +.. c:type:: v4l2_ctrl_hevc_ext_sps_lt_rps + @@ -3453,7 +56,7 @@ index 111111111111..222222222222 100644 + - ``lt_ref_pic_poc_lsb_sps`` + - Long term reference picture order count as described in section 7.4.3.2.1 + "General sequence parameter set RBSP semantics" of the specification. -+ * - __u8 ++ * - __u16 + - ``flags`` + - See :ref:`Extended Long-Term RPS Flags ` + @@ -3474,12 +77,14 @@ index 111111111111..222222222222 100644 + set RBSP semantics" of the specification. + +``V4L2_CID_STATELESS_HEVC_EXT_SPS_ST_RPS (struct)`` -+ Specifies the list of Short-Term reference sets parameters from the SPS. ++ Subset of the :c:type:`v4l2_ctrl_hevc_sps` control. ++ It extends it with the list of Short-term reference sets parameters. + These parameters are defined according to :ref:`hevc`. + They are described in section 7.4.8 "Short-term reference picture set + semantics" of the specification. -+ This control is a dynamically sized 1-dimensional array, -+ V4L2_CTRL_FLAG_DYNAMIC_ARRAY flag must be set when using it. ++ This control is a dynamically sized 1-dimensional array. ++ The values in the array should be ignored when ++ num_short_term_ref_pic_sets is 0. + +.. c:type:: v4l2_ctrl_hevc_ext_sps_st_rps + @@ -3498,10 +103,6 @@ index 111111111111..222222222222 100644 + - ``delta_rps_sign`` + - Sign of the delta as specified in section 7.4.8 "Short-term reference picture set + semantics" of the specification. -+ * - __u16 -+ - ``abs_delta_rps_minus1`` -+ - Absolute delta RPS as specified in section 7.4.8 "Short-term reference picture set -+ semantics" of the specification. + * - __u8 + - ``num_negative_pics`` + - Number of short-term RPS entries that have picture order count values less than the @@ -3517,6 +118,10 @@ index 111111111111..222222222222 100644 + - ``use_delta_flag`` + - Bit i specifies if short-term RPS i is included in the short-term RPS entries. + * - __u16 ++ - ``abs_delta_rps_minus1`` ++ - Absolute delta RPS as specified in section 7.4.8 "Short-term reference picture set ++ semantics" of the specification. ++ * - __u16 + - ``delta_poc_s0_minus1[16]`` + - Specifies the negative picture order count delta for the i-th entry in the short-term RPS. + See details in section 7.4.8 "Short-term reference picture set semantics" of the @@ -3526,7 +131,7 @@ index 111111111111..222222222222 100644 + - Specifies the positive picture order count delta for the i-th entry in the short-term RPS. + See details in section 7.4.8 "Short-term reference picture set semantics" of the + specification. -+ * - __u8 ++ * - __u16 + - ``flags`` + - See :ref:`Extended Short-Term RPS Flags ` + @@ -3553,20 +158,20 @@ diff --git a/Documentation/userspace-api/media/v4l/videodev2.h.rst.exceptions b/ index 111111111111..222222222222 100644 --- a/Documentation/userspace-api/media/v4l/videodev2.h.rst.exceptions +++ b/Documentation/userspace-api/media/v4l/videodev2.h.rst.exceptions -@@ -149,6 +149,8 @@ replace symbol V4L2_CTRL_TYPE_H264_DECODE_PARAMS :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_HEVC_SPS :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_HEVC_PPS :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_HEVC_EXT_SPS_ST_RPS :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_HEVC_EXT_SPS_LT_RPS :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_AREA :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_RECT :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_FWHT_PARAMS :c:type:`v4l2_ctrl_type` +@@ -150,6 +150,8 @@ replace symbol V4L2_CTRL_TYPE_H264_SCALING_MATRIX :c:type:`V4L.v4l2_ctrl_type` + replace symbol V4L2_CTRL_TYPE_H264_PRED_WEIGHTS :c:type:`V4L.v4l2_ctrl_type` + replace symbol V4L2_CTRL_TYPE_H264_SLICE_PARAMS :c:type:`V4L.v4l2_ctrl_type` + replace symbol V4L2_CTRL_TYPE_H264_DECODE_PARAMS :c:type:`V4L.v4l2_ctrl_type` ++replace symbol V4L2_CTRL_TYPE_HEVC_EXT_SPS_ST_RPS :c:type:`V4L.v4l2_ctrl_type` ++replace symbol V4L2_CTRL_TYPE_HEVC_EXT_SPS_LT_RPS :c:type:`V4L.v4l2_ctrl_type` + replace symbol V4L2_CTRL_TYPE_HEVC_SPS :c:type:`V4L.v4l2_ctrl_type` + replace symbol V4L2_CTRL_TYPE_HEVC_PPS :c:type:`V4L.v4l2_ctrl_type` + replace symbol V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS :c:type:`V4L.v4l2_ctrl_type` diff --git a/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst b/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst index 111111111111..222222222222 100644 --- a/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst +++ b/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst -@@ -523,6 +523,18 @@ See also the examples in :ref:`control`. +@@ -531,6 +531,18 @@ See also the examples in :ref:`control`. - n/a - A struct :c:type:`v4l2_ctrl_hevc_decode_params`, containing HEVC decoding parameters for stateless video decoders. @@ -3590,7 +195,7 @@ Armbian From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Detlev Casanova -Date: Thu, 24 Jul 2025 14:10:19 -0400 +Date: Thu, 18 Dec 2025 18:28:12 -0500 Subject: media: v4l2-ctrls: Add hevc_ext_sps_[ls]t_rps controls The vdpu381 decoder found on newer Rockchip SoC need the information @@ -3607,17 +212,17 @@ It is the role of the drivers to calculate the reference sets values. Signed-off-by: Detlev Casanova --- - drivers/media/v4l2-core/v4l2-ctrls-core.c | 18 +++ + drivers/media/v4l2-core/v4l2-ctrls-core.c | 28 +++++ drivers/media/v4l2-core/v4l2-ctrls-defs.c | 10 ++ include/uapi/linux/v4l2-controls.h | 61 ++++++++++ include/uapi/linux/videodev2.h | 2 + - 4 files changed, 91 insertions(+) + 4 files changed, 101 insertions(+) diff --git a/drivers/media/v4l2-core/v4l2-ctrls-core.c b/drivers/media/v4l2-core/v4l2-ctrls-core.c index 111111111111..222222222222 100644 --- a/drivers/media/v4l2-core/v4l2-ctrls-core.c +++ b/drivers/media/v4l2-core/v4l2-ctrls-core.c -@@ -418,6 +418,12 @@ void v4l2_ctrl_type_op_log(const struct v4l2_ctrl *ctrl) +@@ -424,6 +424,12 @@ void v4l2_ctrl_type_op_log(const struct v4l2_ctrl *ctrl) case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS: pr_cont("HEVC_SLICE_PARAMS"); break; @@ -3630,20 +235,37 @@ index 111111111111..222222222222 100644 case V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX: pr_cont("HEVC_SCALING_MATRIX"); break; -@@ -1173,6 +1179,12 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx, +@@ -961,6 +967,8 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx, + struct v4l2_ctrl_h264_pred_weights *p_h264_pred_weights; + struct v4l2_ctrl_h264_slice_params *p_h264_slice_params; + struct v4l2_ctrl_h264_decode_params *p_h264_dec_params; ++ struct v4l2_ctrl_hevc_ext_sps_lt_rps *p_hevc_lt_rps; ++ struct v4l2_ctrl_hevc_ext_sps_st_rps *p_hevc_st_rps; + struct v4l2_ctrl_hevc_sps *p_hevc_sps; + struct v4l2_ctrl_hevc_pps *p_hevc_pps; + struct v4l2_ctrl_hdr10_mastering_display *p_hdr10_mastering; +@@ -1254,6 +1262,20 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx, case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS: break; + case V4L2_CTRL_TYPE_HEVC_EXT_SPS_ST_RPS: ++ p_hevc_st_rps = p; ++ ++ if (p_hevc_st_rps->flags & ~V4L2_HEVC_EXT_SPS_ST_RPS_FLAG_INTER_REF_PIC_SET_PRED) ++ return -EINVAL; + break; + + case V4L2_CTRL_TYPE_HEVC_EXT_SPS_LT_RPS: ++ p_hevc_lt_rps = p; ++ ++ if (p_hevc_lt_rps->flags & ~V4L2_HEVC_EXT_SPS_LT_RPS_FLAG_USED_LT) ++ return -EINVAL; + break; + case V4L2_CTRL_TYPE_HDR10_CLL_INFO: break; -@@ -1925,6 +1937,12 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, +@@ -2006,6 +2028,12 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS: elem_size = sizeof(struct v4l2_ctrl_hevc_slice_params); break; @@ -3688,7 +310,7 @@ diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-contro index 111111111111..222222222222 100644 --- a/include/uapi/linux/v4l2-controls.h +++ b/include/uapi/linux/v4l2-controls.h -@@ -2093,6 +2093,8 @@ struct v4l2_ctrl_mpeg2_quantisation { +@@ -2099,6 +2099,8 @@ struct v4l2_ctrl_mpeg2_quantisation { #define V4L2_CID_STATELESS_HEVC_DECODE_MODE (V4L2_CID_CODEC_STATELESS_BASE + 405) #define V4L2_CID_STATELESS_HEVC_START_CODE (V4L2_CID_CODEC_STATELESS_BASE + 406) #define V4L2_CID_STATELESS_HEVC_ENTRY_POINT_OFFSETS (V4L2_CID_CODEC_STATELESS_BASE + 407) @@ -3697,9 +319,9 @@ index 111111111111..222222222222 100644 enum v4l2_stateless_hevc_decode_mode { V4L2_STATELESS_HEVC_DECODE_MODE_SLICE_BASED, -@@ -3480,6 +3482,65 @@ struct v4l2_ctrl_av1_film_grain { - #define V4L2_CID_MPEG_MFC51_BASE V4L2_CID_CODEC_MFC51_BASE - #endif +@@ -2554,6 +2556,65 @@ struct v4l2_ctrl_hevc_scaling_matrix { + __u8 scaling_list_dc_coef_32x32[2]; + }; +#define V4L2_HEVC_EXT_SPS_ST_RPS_FLAG_INTER_REF_PIC_SET_PRED 0x1 + @@ -3733,14 +355,14 @@ index 111111111111..222222222222 100644 +struct v4l2_ctrl_hevc_ext_sps_st_rps { + __u8 delta_idx_minus1; + __u8 delta_rps_sign; -+ __u16 abs_delta_rps_minus1; + __u8 num_negative_pics; + __u8 num_positive_pics; + __u32 used_by_curr_pic; + __u32 use_delta_flag; ++ __u16 abs_delta_rps_minus1; + __u16 delta_poc_s0_minus1[16]; + __u16 delta_poc_s1_minus1[16]; -+ __u8 flags; ++ __u16 flags; +}; + +#define V4L2_HEVC_EXT_SPS_LT_RPS_FLAG_USED_LT 0x1 @@ -3757,17 +379,17 @@ index 111111111111..222222222222 100644 + */ +struct v4l2_ctrl_hevc_ext_sps_lt_rps { + __u16 lt_ref_pic_poc_lsb_sps; -+ __u8 flags; ++ __u16 flags; +}; + - #define V4L2_CID_COLORIMETRY_CLASS_BASE (V4L2_CTRL_CLASS_COLORIMETRY | 0x900) - #define V4L2_CID_COLORIMETRY_CLASS (V4L2_CTRL_CLASS_COLORIMETRY | 1) + /* Stateless VP9 controls */ + #define V4L2_VP9_LOOP_FILTER_FLAG_DELTA_ENABLED 0x1 diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index 111111111111..222222222222 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h -@@ -1981,6 +1981,8 @@ enum v4l2_ctrl_type { +@@ -1985,6 +1985,8 @@ enum v4l2_ctrl_type { V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS = 0x0272, V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX = 0x0273, V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS = 0x0274, @@ -3781,218 +403,153 @@ Armbian From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Detlev Casanova -Date: Fri, 14 Jun 2024 19:56:19 -0400 -Subject: arm64: dts: rockchip: Add the vdpu381 Video Decoders on RK3588 +Date: Thu, 18 Dec 2025 18:28:13 -0500 +Subject: media: visl: Add HEVC short and long term RPS sets -Add the vdpu381 Video Decoders to the rk3588-base devicetree. - -The RK3588 based SoCs all embed 2 vdpu381 decoders. -This also adds the dedicated IOMMU controllers. +Log the recently added v4l2 controls to set HEVC short and long term RPS +sets with 2 new ftrace entries. Signed-off-by: Detlev Casanova --- - arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 74 ++++++++++ - 1 file changed, 74 insertions(+) + drivers/media/test-drivers/visl/visl-dec.c | 7 ++ + drivers/media/test-drivers/visl/visl-dec.h | 3 + + drivers/media/test-drivers/visl/visl-trace-hevc.h | 59 ++++++++++ + 3 files changed, 69 insertions(+) -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +diff --git a/drivers/media/test-drivers/visl/visl-dec.c b/drivers/media/test-drivers/visl/visl-dec.c index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -1353,6 +1353,70 @@ vepu121_3_mmu: iommu@fdbac800 { - #iommu-cells = <0>; - }; +--- a/drivers/media/test-drivers/visl/visl-dec.c ++++ b/drivers/media/test-drivers/visl/visl-dec.c +@@ -547,6 +547,9 @@ static void visl_trace_ctrls(struct visl_ctx *ctx, struct visl_run *run) + trace_v4l2_hevc_dpb_entry(&run->hevc.dpram->dpb[i]); -+ vdec0: video-codec@fdc38000 { -+ compatible = "rockchip,rk3588-vdec"; -+ reg = <0x0 0xfdc38100 0x0 0x500>, -+ <0x0 0xfdc38000 0x0 0x100>, -+ <0x0 0xfdc38600 0x0 0x100>; -+ reg-names = "function", "link", "cache"; -+ interrupts = ; -+ clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CA>, -+ <&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>; -+ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; -+ assigned-clocks = <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>, -+ <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>; -+ assigned-clock-rates = <800000000>, <600000000>, -+ <600000000>, <1000000000>; -+ iommus = <&vdec0_mmu>; -+ power-domains = <&power RK3588_PD_RKVDEC0>; -+ resets = <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVDEC0_CA>, -+ <&cru SRST_RKVDEC0_CORE>, <&cru SRST_RKVDEC0_HEVC_CA>; -+ reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; -+ sram = <&vdec0_sram>; -+ }; + trace_v4l2_hevc_pred_weight_table(&run->hevc.spram->pred_weight_table); ++ trace_v4l2_ctrl_hevc_ext_sps_lt_rps(run->hevc.rps_lt); ++ trace_v4l2_ctrl_hevc_ext_sps_st_rps(run->hevc.rps_st); + -+ vdec0_mmu: iommu@fdc38700 { -+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; -+ reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>; -+ interrupts = ; -+ clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>; -+ clock-names = "aclk", "iface"; -+ power-domains = <&power RK3588_PD_RKVDEC0>; -+ #iommu-cells = <0>; -+ }; -+ -+ vdec1: video-codec@fdc40000 { -+ compatible = "rockchip,rk3588-vdec"; -+ reg = <0x0 0xfdc40100 0x0 0x500>, -+ <0x0 0xfdc40000 0x0 0x100>, -+ <0x0 0xfdc40600 0x0 0x100>; -+ reg-names = "function", "link", "cache"; -+ interrupts = ; -+ clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CA>, -+ <&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>; -+ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; -+ assigned-clocks = <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>, -+ <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>; -+ assigned-clock-rates = <800000000>, <600000000>, -+ <600000000>, <1000000000>; -+ iommus = <&vdec1_mmu>; -+ power-domains = <&power RK3588_PD_RKVDEC1>; -+ resets = <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVDEC1_CA>, -+ <&cru SRST_RKVDEC1_CORE>, <&cru SRST_RKVDEC1_HEVC_CA>; -+ reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; -+ sram = <&vdec1_sram>; -+ }; -+ -+ vdec1_mmu: iommu@fdc40700 { -+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; -+ reg = <0x0 0xfdc40700 0x0 0x40>, <0x0 0xfdc40740 0x0 0x40>; -+ interrupts = ; -+ clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>; -+ clock-names = "aclk", "iface"; -+ power-domains = <&power RK3588_PD_RKVDEC1>; -+ #iommu-cells = <0>; -+ }; -+ - av1d: video-codec@fdc70000 { - compatible = "rockchip,rk3588-av1-vpu"; - reg = <0x0 0xfdc70000 0x0 0x800>; -@@ -3248,6 +3312,16 @@ system_sram2: sram@ff001000 { - ranges = <0x0 0x0 0xff001000 0xef000>; - #address-cells = <1>; - #size-cells = <1>; -+ -+ vdec0_sram: codec-sram@0 { -+ reg = <0x0 0x78000>; -+ pool; -+ }; -+ -+ vdec1_sram: codec-sram@78000 { -+ reg = <0x78000 0x77000>; -+ pool; -+ }; - }; + break; + case VISL_CODEC_AV1: + trace_v4l2_ctrl_av1_sequence(run->av1.seq); +@@ -611,6 +614,10 @@ void visl_device_run(void *priv) + run.hevc.spram = visl_find_control_data(ctx, V4L2_CID_STATELESS_HEVC_SLICE_PARAMS); + run.hevc.sm = visl_find_control_data(ctx, V4L2_CID_STATELESS_HEVC_SCALING_MATRIX); + run.hevc.dpram = visl_find_control_data(ctx, V4L2_CID_STATELESS_HEVC_DECODE_PARAMS); ++ run.hevc.rps_lt = visl_find_control_data(ctx, ++ V4L2_CID_STATELESS_HEVC_EXT_SPS_LT_RPS); ++ run.hevc.rps_st = visl_find_control_data(ctx, ++ V4L2_CID_STATELESS_HEVC_EXT_SPS_ST_RPS); + break; + case VISL_CODEC_AV1: + run.av1.seq = visl_find_control_data(ctx, V4L2_CID_STATELESS_AV1_SEQUENCE); +diff --git a/drivers/media/test-drivers/visl/visl-dec.h b/drivers/media/test-drivers/visl/visl-dec.h +index 111111111111..222222222222 100644 +--- a/drivers/media/test-drivers/visl/visl-dec.h ++++ b/drivers/media/test-drivers/visl/visl-dec.h +@@ -7,6 +7,7 @@ + #ifndef _VISL_DEC_H_ + #define _VISL_DEC_H_ - pinctrl: pinctrl { ++#include "linux/v4l2-controls.h" + #include "visl.h" + + struct visl_fwht_run { +@@ -43,6 +44,8 @@ struct visl_hevc_run { + const struct v4l2_ctrl_hevc_slice_params *spram; + const struct v4l2_ctrl_hevc_scaling_matrix *sm; + const struct v4l2_ctrl_hevc_decode_params *dpram; ++ const struct v4l2_ctrl_hevc_ext_sps_lt_rps *rps_lt; ++ const struct v4l2_ctrl_hevc_ext_sps_st_rps *rps_st; + }; + + struct visl_av1_run { +diff --git a/drivers/media/test-drivers/visl/visl-trace-hevc.h b/drivers/media/test-drivers/visl/visl-trace-hevc.h +index 111111111111..222222222222 100644 +--- a/drivers/media/test-drivers/visl/visl-trace-hevc.h ++++ b/drivers/media/test-drivers/visl/visl-trace-hevc.h +@@ -1,4 +1,5 @@ + /* SPDX-License-Identifier: GPL-2.0+ */ ++#include "linux/v4l2-controls.h" + #if !defined(_VISL_TRACE_HEVC_H_) || defined(TRACE_HEADER_MULTI_READ) + #define _VISL_TRACE_HEVC_H_ + +@@ -343,6 +344,54 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_decode_params_tmpl, + )) + ); + ++DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_ext_sps_lt_rps_tmpl, ++ TP_PROTO(const struct v4l2_ctrl_hevc_ext_sps_lt_rps *lt), ++ TP_ARGS(lt), ++ TP_STRUCT__entry(__field_struct(struct v4l2_ctrl_hevc_ext_sps_lt_rps, lt)), ++ TP_fast_assign(__entry->lt = *lt), ++ TP_printk("\nflags %s\n" ++ "lt_ref_pic_poc_lsb_sps %x\n", ++ __print_flags(__entry->lt.flags, "|", ++ {V4L2_HEVC_EXT_SPS_LT_RPS_FLAG_USED_LT, "USED_LT"} ++ ), ++ __entry->lt.lt_ref_pic_poc_lsb_sps ++ ) ++) ++ ++DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_ext_sps_st_rps_tmpl, ++ TP_PROTO(const struct v4l2_ctrl_hevc_ext_sps_st_rps *st), ++ TP_ARGS(st), ++ TP_STRUCT__entry(__field_struct(struct v4l2_ctrl_hevc_ext_sps_st_rps, st)), ++ TP_fast_assign(__entry->st = *st), ++ TP_printk("\nflags %s\n" ++ "delta_idx_minus1: %u\n" ++ "delta_rps_sign: %u\n" ++ "abs_delta_rps_minus1: %u\n" ++ "num_negative_pics: %u\n" ++ "num_positive_pics: %u\n" ++ "used_by_curr_pic: %08x\n" ++ "use_delta_flag: %08x\n" ++ "delta_poc_s0_minus1: %s\n" ++ "delta_poc_s1_minus1: %s\n", ++ __print_flags(__entry->st.flags, "|", ++ {V4L2_HEVC_EXT_SPS_ST_RPS_FLAG_INTER_REF_PIC_SET_PRED, "INTER_REF_PIC_SET_PRED"} ++ ), ++ __entry->st.delta_idx_minus1, ++ __entry->st.delta_rps_sign, ++ __entry->st.abs_delta_rps_minus1, ++ __entry->st.num_negative_pics, ++ __entry->st.num_positive_pics, ++ __entry->st.used_by_curr_pic, ++ __entry->st.use_delta_flag, ++ __print_array(__entry->st.delta_poc_s0_minus1, ++ ARRAY_SIZE(__entry->st.delta_poc_s0_minus1), ++ sizeof(__entry->st.delta_poc_s0_minus1[0])), ++ __print_array(__entry->st.delta_poc_s1_minus1, ++ ARRAY_SIZE(__entry->st.delta_poc_s1_minus1), ++ sizeof(__entry->st.delta_poc_s1_minus1[0])) ++ ) ++) ++ + + DECLARE_EVENT_CLASS(v4l2_hevc_dpb_entry_tmpl, + TP_PROTO(const struct v4l2_hevc_dpb_entry *e), +@@ -391,6 +440,16 @@ DEFINE_EVENT(v4l2_ctrl_hevc_decode_params_tmpl, v4l2_ctrl_hevc_decode_params, + TP_ARGS(d) + ); + ++DEFINE_EVENT(v4l2_ctrl_hevc_ext_sps_lt_rps_tmpl, v4l2_ctrl_hevc_ext_sps_lt_rps, ++ TP_PROTO(const struct v4l2_ctrl_hevc_ext_sps_lt_rps *lt), ++ TP_ARGS(lt) ++); ++ ++DEFINE_EVENT(v4l2_ctrl_hevc_ext_sps_st_rps_tmpl, v4l2_ctrl_hevc_ext_sps_st_rps, ++ TP_PROTO(const struct v4l2_ctrl_hevc_ext_sps_st_rps *st), ++ TP_ARGS(st) ++); ++ + DEFINE_EVENT(v4l2_hevc_dpb_entry_tmpl, v4l2_hevc_dpb_entry, + TP_PROTO(const struct v4l2_hevc_dpb_entry *e), + TP_ARGS(e) -- Armbian From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Detlev Casanova -Date: Wed, 11 Jun 2025 10:49:48 -0400 -Subject: arm64: dts: rockchip: Add the vdpu383 Video Decoder on rk3576 - -Add the vdpu383 Video Decoder variant to the RK3576 device tree. - -Also allow using the dedicated SRAM as a pool. - -Signed-off-by: Detlev Casanova ---- - arch/arm64/boot/dts/rockchip/rk3576.dtsi | 36 ++++++++++ - 1 file changed, 36 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi -@@ -1277,6 +1277,41 @@ gpu: gpu@27800000 { - status = "disabled"; - }; - -+ vdec: video-codec@27b00000 { -+ compatible = "rockchip,rk3576-vdec"; -+ reg = <0x0 0x27b00100 0x0 0x500>, -+ <0x0 0x27b00000 0x0 0x100>, -+ <0x0 0x27b00600 0x0 0x100>; -+ reg-names = "function", "link", "cache"; -+ interrupts = ; -+ clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC>, -+ <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_CORE>, -+ <&cru CLK_RKVDEC_HEVC_CA>; -+ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; -+ assigned-clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru CLK_RKVDEC_CORE>, -+ <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_HEVC_CA>; -+ assigned-clock-rates = <600000000>, <600000000>, -+ <500000000>, <1000000000>; -+ iommus = <&vdec_mmu>; -+ power-domains = <&power RK3576_PD_VDEC>; -+ resets = <&cru SRST_A_RKVDEC_BIU>, <&cru SRST_H_RKVDEC_BIU>, -+ <&cru SRST_H_RKVDEC>, <&cru SRST_RKVDEC_CORE>, -+ <&cru SRST_RKVDEC_HEVC_CA>; -+ reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; -+ sram = <&rkvdec_sram>; -+ }; -+ -+ vdec_mmu: iommu@27b00800 { -+ compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu"; -+ reg = <0x0 0x27b00800 0x0 0x40>, <0x0 0x27b00900 0x0 0x40>; -+ interrupts = ; -+ clocks = <&cru CLK_RKVDEC_CORE>, <&cru HCLK_RKVDEC>; -+ clock-names = "aclk", "iface"; -+ power-domains = <&power RK3576_PD_VDEC>; -+ rockchip,disable-mmu-reset; -+ #iommu-cells = <0>; -+ }; -+ - vop: vop@27d00000 { - compatible = "rockchip,rk3576-vop"; - reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>; -@@ -2680,6 +2715,7 @@ sram: sram@3ff88000 { - /* start address and size should be 4k align */ - rkvdec_sram: rkvdec-sram@0 { - reg = <0x0 0x78000>; -+ pool; - }; - }; - --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Thu, 26 Jun 2025 08:53:07 -0400 -Subject: drm/bridge: synopsys: Do not warn about audio params computation - -There is no need to warn about non pre-computed values, just change it to -dbg. - -Signed-off-by: Detlev Casanova ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c -index 111111111111..222222222222 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c -@@ -277,8 +277,7 @@ static unsigned int dw_hdmi_qp_find_n(struct dw_hdmi_qp *hdmi, unsigned long pix - if (n > 0) - return n; - -- dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n", -- pixel_clk); -+ dev_dbg(hdmi->dev, "Rate %lu missing; compute N dynamically\n", pixel_clk); - - return dw_hdmi_qp_compute_n(hdmi, pixel_clk, sample_rate); - } --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Tue, 27 May 2025 11:00:22 -0400 +Date: Thu, 18 Dec 2025 18:28:14 -0500 Subject: media: rkvdec: Switch to using structs instead of writel In an effort to merge the rkvdec2 driver [1] with this one, switch from @@ -4029,15 +586,17 @@ This also shows that the fluster score hasn't changed. [1]: https://lore.kernel.org/all/20250325213303.826925-1-detlev.casanova@collabora.com/ [2]: https://lore.kernel.org/all/20200127143009.15677-5-andrzej.p@collabora.com/ +Tested-by: Diederik de Haas # Rock 5B +Reviewed-by: Nicolas Dufresne Signed-off-by: Detlev Casanova --- - drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c | 165 ++- - drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c | 66 +- - drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h | 571 +++++++--- - drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c | 231 ++-- + drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c | 166 ++- + drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c | 64 +- + drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h | 586 +++++++--- + drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c | 232 ++-- drivers/media/platform/rockchip/rkvdec/rkvdec.c | 10 +- drivers/media/platform/rockchip/rkvdec/rkvdec.h | 1 + - 6 files changed, 589 insertions(+), 455 deletions(-) + 6 files changed, 604 insertions(+), 455 deletions(-) diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c index 111111111111..222222222222 100644 @@ -4105,25 +664,25 @@ index 111111111111..222222222222 100644 + if (!bottom) { + switch (id) { + case 0 ... 7: -+ regs->h264.ref0_14_poc[id * 2] = poc; ++ regs->h26x.ref0_14_poc[id * 2] = poc; + break; + case 8 ... 14: -+ regs->h264.ref15_29_poc[(id - 8) * 2 + 1] = poc; ++ regs->h26x.ref15_29_poc[(id - 8) * 2 + 1] = poc; + break; + case 15: -+ regs->h264.ref30_poc = poc; ++ regs->h26x.ref30_poc = poc; + break; + } + } else { + switch (id) { + case 0 ... 6: -+ regs->h264.ref0_14_poc[id * 2 + 1] = poc; ++ regs->h26x.ref0_14_poc[id * 2 + 1] = poc; + break; + case 7 ... 14: -+ regs->h264.ref15_29_poc[(id - 7) * 2] = poc; ++ regs->h26x.ref15_29_poc[(id - 7) * 2] = poc; + break; + case 15: -+ regs->h264.ref31_poc = poc; ++ regs->h26x.ref31_poc = poc; + break; + } + } @@ -4173,7 +732,7 @@ index 111111111111..222222222222 100644 - writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE); - writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_RLCWRITE_BASE); + regs->common.strm_rlc_base = rlc_addr; -+ regs->h264.rlcwrite_base = rlc_addr; ++ regs->h26x.rlcwrite_base = rlc_addr; rlc_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0); - reg = RKVDEC_STRM_LEN(rlc_len); @@ -4206,7 +765,7 @@ index 111111111111..222222222222 100644 /* * If a DPB entry is unused or invalid, address of current destination -@@ -963,54 +958,36 @@ static void config_registers(struct rkvdec_ctx *ctx, +@@ -963,54 +958,37 @@ static void config_registers(struct rkvdec_ctx *ctx, vb_buf = &dst_buf->vb2_buf; refer_addr = vb2_dma_contig_plane_dma_addr(vb_buf, 0); @@ -4228,20 +787,20 @@ index 111111111111..222222222222 100644 if (i < V4L2_H264_NUM_DPB_ENTRIES - 1) - writel_relaxed(refer_addr, - rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i)); -+ base = ®s->h264.ref0_14_base[i]; ++ base = ®s->h26x.ref0_14_base[i]; else - writel_relaxed(refer_addr, - rkvdec->regs + RKVDEC_REG_H264_BASE_REFER15); - } -+ base = ®s->h264.ref15_base; ++ base = ®s->h26x.ref15_base; - reg = RKVDEC_CUR_POC(dec_params->top_field_order_cnt); - writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0); ++ base->base_addr = refer_addr >> 4; + base->field_ref = !!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_FIELD); -+ base->colmv_used_flag_ref = !!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE); ++ base->colmv_use_flag_ref = !!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE); + base->topfield_used_ref = !!(dpb[i].fields & V4L2_H264_TOP_FIELD_REF); + base->botfield_used_ref = !!(dpb[i].fields & V4L2_H264_BOTTOM_FIELD_REF); -+ base->base_addr = refer_addr >> 4; - reg = RKVDEC_CUR_POC(dec_params->bottom_field_order_cnt); - writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC1); @@ -4249,14 +808,14 @@ index 111111111111..222222222222 100644 + set_poc_reg(regs, dpb[i].bottom_field_order_cnt, i, true); + } + -+ regs->h264.cur_poc = dec_params->top_field_order_cnt; -+ regs->h264.cur_poc1 = dec_params->bottom_field_order_cnt; ++ regs->h26x.cur_poc = dec_params->top_field_order_cnt; ++ regs->h26x.cur_poc1 = dec_params->bottom_field_order_cnt; /* config hw pps address */ offset = offsetof(struct rkvdec_h264_priv_tbl, param_set); - writel_relaxed(priv_start_addr + offset, - rkvdec->regs + RKVDEC_REG_PPS_BASE); -+ regs->h264.pps_base = priv_start_addr + offset; ++ regs->h26x.pps_base = priv_start_addr + offset; /* config hw rps address */ offset = offsetof(struct rkvdec_h264_priv_tbl, rps); @@ -4268,18 +827,19 @@ index 111111111111..222222222222 100644 - - reg = RKVDEC_AXI_DDR_WDATA(0); - writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_WDATA); -+ regs->h264.rps_base = priv_start_addr + offset; ++ regs->h26x.rps_base = priv_start_addr + offset; offset = offsetof(struct rkvdec_h264_priv_tbl, err_info); - writel_relaxed(priv_start_addr + offset, - rkvdec->regs + RKVDEC_REG_H264_ERRINFO_BASE); -+ regs->h264.errorinfo_base = priv_start_addr + offset; ++ regs->h26x.errorinfo_base = priv_start_addr + offset; + -+ rkvdec_memcpy_toio(rkvdec->regs, regs, sizeof(*regs)); ++ rkvdec_memcpy_toio(rkvdec->regs, regs, ++ MIN(sizeof(*regs), sizeof(u32) * rkvdec->variant->num_regs)); } #define RKVDEC_H264_MAX_DEPTH_IN_BYTES 2 -@@ -1181,8 +1158,6 @@ static int rkvdec_h264_run(struct rkvdec_ctx *ctx) +@@ -1181,8 +1159,6 @@ static int rkvdec_h264_run(struct rkvdec_ctx *ctx) schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000)); @@ -4369,33 +929,31 @@ index 111111111111..222222222222 100644 refer_addr = vb2_dma_contig_plane_dma_addr(vb_buf, 0); - writel_relaxed(refer_addr | reg, - rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i)); -- + - reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ? - dpb[i].pic_order_cnt_val : 0); - writel_relaxed(reg, - rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i)); -+ //writel_relaxed(refer_addr | reg, -+ // rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i)); -+ regs->h264.ref0_14_base[i].base_addr = refer_addr >> 4; -+ regs->h264.ref0_14_base[i].field_ref = !!(reg & 1); -+ regs->h264.ref0_14_base[i].topfield_used_ref = !!(reg & 2); -+ regs->h264.ref0_14_base[i].botfield_used_ref = !!(reg & 4); -+ regs->h264.ref0_14_base[i].colmv_used_flag_ref = !!(reg & 8); ++ regs->h26x.ref0_14_base[i].base_addr = refer_addr >> 4; ++ regs->h26x.ref0_14_base[i].field_ref = !!(reg & 1); ++ regs->h26x.ref0_14_base[i].topfield_used_ref = !!(reg & 2); ++ regs->h26x.ref0_14_base[i].botfield_used_ref = !!(reg & 4); ++ regs->h26x.ref0_14_base[i].colmv_use_flag_ref = !!(reg & 8); + -+ regs->h264.ref0_14_poc[i] = i < decode_params->num_active_dpb_entries ++ regs->h26x.ref0_14_poc[i] = i < decode_params->num_active_dpb_entries + ? dpb[i].pic_order_cnt_val + : 0; } - reg = RKVDEC_CUR_POC(sl_params->slice_pic_order_cnt); - writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0); -+ regs->h264.cur_poc = sl_params->slice_pic_order_cnt; ++ regs->h26x.cur_poc = sl_params->slice_pic_order_cnt; /* config hw pps address */ offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set); - writel_relaxed(priv_start_addr + offset, - rkvdec->regs + RKVDEC_REG_PPS_BASE); -+ regs->h264.pps_base = priv_start_addr + offset; ++ regs->h26x.pps_base = priv_start_addr + offset; /* config hw rps address */ offset = offsetof(struct rkvdec_hevc_priv_tbl, rps); @@ -4404,11 +962,12 @@ index 111111111111..222222222222 100644 - - reg = RKVDEC_AXI_DDR_RDATA(0); - writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_RDATA); -+ regs->h264.rps_base = priv_start_addr + offset; ++ regs->h26x.rps_base = priv_start_addr + offset; - reg = RKVDEC_AXI_DDR_WDATA(0); - writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_WDATA); -+ rkvdec_memcpy_toio(rkvdec->regs, regs, sizeof(*regs)); ++ rkvdec_memcpy_toio(rkvdec->regs, regs, ++ MIN(sizeof(*regs), sizeof(u32) * rkvdec->variant->num_regs)); } #define RKVDEC_HEVC_MAX_DEPTH_IN_BYTES 2 @@ -4439,7 +998,7 @@ index 111111111111..222222222222 100644 #define RKVDEC_REG_INTERRUPT 0x004 #define RKVDEC_INTERRUPT_DEC_E BIT(0) #define RKVDEC_CONFIG_DEC_CLK_GATE_E BIT(1) -@@ -30,198 +35,384 @@ +@@ -30,198 +35,399 @@ #define RKVDEC_SOFTRESET_RDY BIT(22) #define RKVDEC_WR_DDR_ALIGN_EN BIT(23) @@ -4663,7 +1222,7 @@ index 111111111111..222222222222 100644 + struct rkvdec_int { + u32 dec_e : 1; + u32 dec_clkgate_e : 1; -+ u32 reserved0 : 1; ++ u32 dec_e_strmd_clkgate_dis : 1; + u32 timeout_mode : 1; + u32 dec_irq_dis : 1; + u32 dec_timeout_e : 1; @@ -4683,7 +1242,10 @@ index 111111111111..222222222222 100644 + u32 softrst_en_p : 1; + u32 force_softreset_valid : 1; + u32 softreset_rdy : 1; -+ u32 reserved1 : 9; ++ u32 wr_ddr_align_en : 1; ++ u32 scl_down_en : 1; ++ u32 allow_not_wr_unref_bframe : 1; ++ u32 reserved1 : 6; + } reg01; + + struct rkvdec_sysctrl { @@ -4709,7 +1271,8 @@ index 111111111111..222222222222 100644 + u32 firstslice_flag : 1; + u32 frame_orslice : 1; + u32 buspr_slot_disable : 1; -+ u32 reserved3 : 2; ++ u32 colmv_mode : 1; ++ u32 ycacherd_prior : 1; + } reg02; + + struct rkvdec_picpar { @@ -4740,11 +1303,11 @@ index 111111111111..222222222222 100644 + u32 field_ref : 1; + u32 topfield_used_ref : 1; + u32 botfield_used_ref : 1; -+ u32 colmv_used_flag_ref : 1; ++ u32 colmv_use_flag_ref : 1; + u32 base_addr : 28; +}; + -+struct rkvdec_h264_regs { ++struct rkvdec_h26x_regs { + struct ref_base ref0_14_base[15]; + u32 ref0_14_poc[15]; + @@ -4822,9 +1385,20 @@ index 111111111111..222222222222 100644 + } reg76; + + struct { -+ u32 error_en_highbits : 30; -+ u32 reserved : 2; ++ u32 error_en_highbits : 30; ++ u32 strmd_error_slice_en : 1; ++ u32 strmd_error_frame_en : 1; + } reg77; ++ ++ u32 colmv_cur_base; ++ u32 colmv_ref_base[16]; ++ u32 scanlist_addr; ++ u32 reg96_sd_decout_base; ++ u32 sd_y_virstride; ++ u32 sd_hor_stride; ++ u32 qos_ctrl; ++ u32 perf[8]; ++ u32 qos1; +} __packed; + +struct rkvdec_vp9_regs { @@ -5007,7 +1581,7 @@ index 111111111111..222222222222 100644 +struct rkvdec_regs { + struct rkvdec_common_regs common; + union { -+ struct rkvdec_h264_regs h264; //TODO: rename to h26x ++ struct rkvdec_h26x_regs h26x; + struct rkvdec_vp9_regs vp9; + }; +} __packed; @@ -5165,17 +1739,16 @@ index 111111111111..222222222222 100644 } static void update_dec_buf_info(struct rkvdec_decoded_buffer *buf, -@@ -521,7 +480,8 @@ static void config_registers(struct rkvdec_ctx *ctx, +@@ -521,7 +480,7 @@ static void config_registers(struct rkvdec_ctx *ctx, struct rkvdec_decoded_buffer *ref_bufs[3]; struct rkvdec_decoded_buffer *dst, *last, *mv_ref; struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv; - u32 val, last_frame_info = 0; + struct rkvdec_regs *regs = &vp9_ctx->regs; -+ u32 val; const struct v4l2_vp9_segmentation *seg; struct rkvdec_dev *rkvdec = ctx->dev; dma_addr_t addr; -@@ -547,8 +507,7 @@ static void config_registers(struct rkvdec_ctx *ctx, +@@ -547,8 +506,7 @@ static void config_registers(struct rkvdec_ctx *ctx, (V4L2_VP9_FRAME_FLAG_KEY_FRAME | V4L2_VP9_FRAME_FLAG_INTRA_ONLY)); @@ -5185,7 +1758,7 @@ index 111111111111..222222222222 100644 bit_depth = dec_params->bit_depth; aligned_height = round_up(ctx->decoded_fmt.fmt.pix_mp.height, 64); -@@ -560,17 +519,14 @@ static void config_registers(struct rkvdec_ctx *ctx, +@@ -560,17 +518,14 @@ static void config_registers(struct rkvdec_ctx *ctx, uv_len = y_len / 2; yuv_len = y_len + uv_len; @@ -5209,7 +1782,7 @@ index 111111111111..222222222222 100644 /* * Reset count buffer, because decoder only output intra related syntax -@@ -588,14 +544,13 @@ static void config_registers(struct rkvdec_ctx *ctx, +@@ -588,14 +543,13 @@ static void config_registers(struct rkvdec_ctx *ctx, vp9_ctx->cur.segmapid++; for (i = 0; i < ARRAY_SIZE(ref_bufs); i++) @@ -5227,8 +1800,11 @@ index 111111111111..222222222222 100644 if (!intra_only) { const struct v4l2_vp9_loop_filter *lf; -@@ -609,43 +564,56 @@ static void config_registers(struct rkvdec_ctx *ctx, - val = 0; +@@ -606,46 +560,58 @@ static void config_registers(struct rkvdec_ctx *ctx, + else + lf = &vp9_ctx->cur.lf; + +- val = 0; for (i = 0; i < ARRAY_SIZE(lf->ref_deltas); i++) { delta = lf->ref_deltas[i]; - val |= RKVDEC_REF_DELTAS_LASTFRAME(i, delta); @@ -5310,7 +1886,7 @@ index 111111111111..222222222222 100644 for (i = 0; !intra_only && i < ARRAY_SIZE(ref_bufs); i++) { unsigned int refw = ref_bufs[i]->vp9.width; -@@ -654,29 +622,28 @@ static void config_registers(struct rkvdec_ctx *ctx, +@@ -654,29 +620,28 @@ static void config_registers(struct rkvdec_ctx *ctx, hscale = (refw << 14) / dst->vp9.width; vscale = (refh << 14) / dst->vp9.height; @@ -5358,7 +1934,7 @@ index 111111111111..222222222222 100644 if (!intra_only && !(dec_params->flags & V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT) && -@@ -685,12 +652,14 @@ static void config_registers(struct rkvdec_ctx *ctx, +@@ -685,12 +650,15 @@ static void config_registers(struct rkvdec_ctx *ctx, else mv_ref = dst; @@ -5374,25 +1950,26 @@ index 111111111111..222222222222 100644 + + regs->vp9.reg44.strmd_error_e = 0xe; + -+ rkvdec_memcpy_toio(rkvdec->regs, regs, sizeof(*regs)); ++ rkvdec_memcpy_toio(rkvdec->regs, regs, ++ MIN(sizeof(*regs), sizeof(u32) * rkvdec->variant->num_regs)); } static int validate_dec_params(struct rkvdec_ctx *ctx, -@@ -823,8 +792,6 @@ static int rkvdec_vp9_run(struct rkvdec_ctx *ctx) +@@ -823,8 +791,6 @@ static int rkvdec_vp9_run(struct rkvdec_ctx *ctx) writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND); writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); - writel(0xe, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN); - - if (rkvdec->quirks & RKVDEC_QUIRK_DISABLE_QOS) { - u32 reg; + if (rkvdec->variant->quirks & RKVDEC_QUIRK_DISABLE_QOS) + rkvdec_quirks_disable_qos(ctx); diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c index 111111111111..222222222222 100644 --- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -@@ -902,6 +902,15 @@ void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run) - v4l2_ctrl_request_complete(src_req, &ctx->ctrl_hdl); +@@ -914,6 +914,15 @@ void rkvdec_quirks_disable_qos(struct rkvdec_ctx *ctx) + writel(reg, rkvdec->regs + RKVDEC_REG_QOS_CTRL); } +void rkvdec_memcpy_toio(void __iomem *dst, void *src, size_t len) @@ -5407,7 +1984,7 @@ index 111111111111..222222222222 100644 static void rkvdec_device_run(void *priv) { struct rkvdec_ctx *ctx = priv; -@@ -1215,7 +1224,6 @@ static void rkvdec_watchdog_func(struct work_struct *work) +@@ -1227,7 +1236,6 @@ static void rkvdec_watchdog_func(struct work_struct *work) if (ctx) { dev_err(rkvdec->dev, "Frame processing timed out!\n"); writel(RKVDEC_IRQ_DIS, rkvdec->regs + RKVDEC_REG_INTERRUPT); @@ -5425,19 +2002,21 @@ index 111111111111..222222222222 100644 void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); +void rkvdec_memcpy_toio(void __iomem *dst, void *src, size_t len); - extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops; - extern const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops; + void rkvdec_quirks_disable_qos(struct rkvdec_ctx *ctx); + -- Armbian From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Detlev Casanova -Date: Tue, 10 Jun 2025 10:34:55 -0400 +Date: Thu, 18 Dec 2025 18:28:15 -0500 Subject: media: rkvdec: Move cabac tables to their own source file This is in preparation to add support for new variants that will use the same tables. +Tested-by: Diederik de Haas # Rock 5B +Reviewed-by: Nicolas Dufresne Signed-off-by: Detlev Casanova --- drivers/media/platform/rockchip/rkvdec/Makefile | 7 +- @@ -6544,7 +3123,7 @@ Armbian From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Detlev Casanova -Date: Wed, 11 Jun 2025 12:28:56 -0400 +Date: Thu, 18 Dec 2025 18:28:16 -0500 Subject: media: rkvdec: Use structs to represent the HW RPS This is in preparation to add support for other variants of the decoder. @@ -6552,10 +3131,12 @@ This is in preparation to add support for other variants of the decoder. Moving to struct representation is mainly to prepare for multicore support that is present in e.g. rk3588. +Tested-by: Diederik de Haas # Rock 5B +Reviewed-by: Nicolas Dufresne Signed-off-by: Detlev Casanova --- - drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c | 97 ++++++++-- - 1 file changed, 86 insertions(+), 11 deletions(-) + drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c | 93 +++++++++- + 1 file changed, 84 insertions(+), 9 deletions(-) diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c index 111111111111..222222222222 100644 @@ -6619,7 +3200,7 @@ index 111111111111..222222222222 100644 struct rkvdec_sps_pps_packet param_set[256]; u8 err_info[RKV_ERROR_INFO_SIZE]; }; -@@ -260,20 +293,64 @@ static void lookup_ref_buf_idx(struct rkvdec_ctx *ctx, +@@ -260,6 +293,51 @@ static void lookup_ref_buf_idx(struct rkvdec_ctx *ctx, } } @@ -6669,13 +3250,9 @@ index 111111111111..222222222222 100644 +} + static void assemble_hw_rps(struct rkvdec_ctx *ctx, -- struct v4l2_h264_reflist_builder *builder, -- struct rkvdec_h264_run *run) -+ struct v4l2_h264_reflist_builder *builder, -+ struct rkvdec_h264_run *run) - { - const struct v4l2_ctrl_h264_decode_params *dec_params = run->decode_params; - const struct v4l2_h264_dpb_entry *dpb = dec_params->dpb; + struct v4l2_h264_reflist_builder *builder, + struct rkvdec_h264_run *run) +@@ -269,11 +347,10 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, struct rkvdec_h264_ctx *h264_ctx = ctx->priv; struct rkvdec_h264_priv_tbl *priv_tbl = h264_ctx->priv_tbl.cpu; @@ -6714,7 +3291,7 @@ Armbian From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Detlev Casanova -Date: Tue, 10 Jun 2025 13:16:24 -0400 +Date: Thu, 18 Dec 2025 18:28:17 -0500 Subject: media: rkvdec: Move h264 functions to common file This is a preparation commit to add support for new variants of the @@ -6723,13 +3300,15 @@ decoder. The functions will later be shared with vdpu381 (rk3588) and vdpu383 (rk3576). +Tested-by: Diederik de Haas # Rock 5B +Reviewed-by: Nicolas Dufresne Signed-off-by: Detlev Casanova --- drivers/media/platform/rockchip/rkvdec/Makefile | 1 + - drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.c | 253 ++++++++ - drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.h | 79 +++ - drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c | 308 +--------- - 4 files changed, 337 insertions(+), 304 deletions(-) + drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.c | 258 ++++++++ + drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.h | 87 +++ + drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c | 310 +--------- + 4 files changed, 350 insertions(+), 306 deletions(-) diff --git a/drivers/media/platform/rockchip/rkvdec/Makefile b/drivers/media/platform/rockchip/rkvdec/Makefile index 111111111111..222222222222 100644 @@ -6747,13 +3326,19 @@ new file mode 100644 index 000000000000..111111111111 --- /dev/null +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.c -@@ -0,0 +1,253 @@ +@@ -0,0 +1,258 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip video decoder h264 common functions + * + * Copyright (C) 2025 Collabora, Ltd. -+ * Detlev Casanova ++ * Detlev Casanova ++ * ++ * Copyright (C) 2019 Collabora, Ltd. ++ * Boris Brezillon ++ * ++ * Copyright (C) 2016 Rockchip Electronics Co., Ltd. ++ * Jeffy Chen + */ + +#include @@ -7000,19 +3585,24 @@ index 000000000000..111111111111 + + rkvdec_run_preamble(ctx, &run->base); +} -+ diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.h b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.h new file mode 100644 index 000000000000..111111111111 --- /dev/null +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.h -@@ -0,0 +1,79 @@ +@@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Rockchip video decoder h264 common functions + * + * Copyright (C) 2025 Collabora, Ltd. -+ * Detlev Casanova ++ * Detlev Casanova ++ * ++ * Copyright (C) 2019 Collabora, Ltd. ++ * Boris Brezillon ++ * ++ * Copyright (C) 2016 Rockchip Electronics Co., Ltd. ++ * Jeffy Chen + */ + +#include @@ -7020,6 +3610,8 @@ index 000000000000..111111111111 + +#include "rkvdec.h" + ++extern const s8 rkvdec_h264_cabac_table[4][464][2]; ++ +struct rkvdec_h264_scaling_list { + u8 scaling_list_4x4[6][16]; + u8 scaling_list_8x8[6][64]; @@ -7090,15 +3682,15 @@ diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c b/drivers/medi index 111111111111..222222222222 100644 --- a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c -@@ -14,6 +14,7 @@ +@@ -14,59 +14,16 @@ #include "rkvdec.h" #include "rkvdec-regs.h" +- +-extern const s8 rkvdec_h264_cabac_table[4][464][2]; +#include "rkvdec-h264-common.h" - extern const s8 rkvdec_h264_cabac_table[4][464][2]; - -@@ -21,52 +22,10 @@ extern const s8 rkvdec_h264_cabac_table[4][464][2]; + /* Size with u32 units. */ #define RKV_CABAC_INIT_BUFFER_SIZE (3680 + 128) #define RKV_ERROR_INFO_SIZE (256 * 144 * 4) @@ -7151,7 +3743,7 @@ index 111111111111..222222222222 100644 struct rkvdec_ps_field { u16 offset; u8 len; -@@ -118,11 +77,6 @@ struct rkvdec_ps_field { +@@ -118,11 +75,6 @@ struct rkvdec_ps_field { #define SCALING_LIST_ADDRESS PS_FIELD(184, 32) #define IS_LONG_TERM(i) PS_FIELD(216 + (i), 1) @@ -7163,7 +3755,7 @@ index 111111111111..222222222222 100644 /* Data structure describing auxiliary buffer format. */ struct rkvdec_h264_priv_tbl { s8 cabac_table[4][464][2]; -@@ -132,21 +86,6 @@ struct rkvdec_h264_priv_tbl { +@@ -132,21 +84,6 @@ struct rkvdec_h264_priv_tbl { u8 err_info[RKV_ERROR_INFO_SIZE]; }; @@ -7185,7 +3777,7 @@ index 111111111111..222222222222 100644 struct rkvdec_h264_ctx { struct rkvdec_aux_buf priv_tbl; struct rkvdec_h264_reflists reflists; -@@ -270,155 +209,6 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, +@@ -270,155 +207,6 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, } } @@ -7258,8 +3850,8 @@ index 111111111111..222222222222 100644 -} - -static void assemble_hw_rps(struct rkvdec_ctx *ctx, -- struct v4l2_h264_reflist_builder *builder, -- struct rkvdec_h264_run *run) +- struct v4l2_h264_reflist_builder *builder, +- struct rkvdec_h264_run *run) -{ - const struct v4l2_ctrl_h264_decode_params *dec_params = run->decode_params; - const struct v4l2_h264_dpb_entry *dpb = dec_params->dpb; @@ -7341,8 +3933,8 @@ index 111111111111..222222222222 100644 /* * Set the ref POC in the correct register. * -@@ -568,76 +358,6 @@ static void config_registers(struct rkvdec_ctx *ctx, - rkvdec_memcpy_toio(rkvdec->regs, regs, sizeof(*regs)); +@@ -569,76 +357,6 @@ static void config_registers(struct rkvdec_ctx *ctx, + MIN(sizeof(*regs), sizeof(u32) * rkvdec->variant->num_regs)); } -#define RKVDEC_H264_MAX_DEPTH_IN_BYTES 2 @@ -7418,7 +4010,7 @@ index 111111111111..222222222222 100644 static int rkvdec_h264_start(struct rkvdec_ctx *ctx) { struct rkvdec_dev *rkvdec = ctx->dev; -@@ -689,33 +409,13 @@ static void rkvdec_h264_stop(struct rkvdec_ctx *ctx) +@@ -690,33 +408,13 @@ static void rkvdec_h264_stop(struct rkvdec_ctx *ctx) kfree(h264_ctx); } @@ -7453,7 +4045,7 @@ index 111111111111..222222222222 100644 rkvdec_h264_run_preamble(ctx, &run); -@@ -726,10 +426,10 @@ static int rkvdec_h264_run(struct rkvdec_ctx *ctx) +@@ -727,10 +425,10 @@ static int rkvdec_h264_run(struct rkvdec_ctx *ctx) v4l2_h264_build_b_ref_lists(&reflist_builder, h264_ctx->reflists.b0, h264_ctx->reflists.b1); @@ -7471,7 +4063,7 @@ Armbian From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Detlev Casanova -Date: Fri, 15 Aug 2025 17:24:37 -0400 +Date: Thu, 18 Dec 2025 18:28:18 -0500 Subject: media: rkvdec: Move hevc functions to common file This is a preparation commit to add support for new variants of the @@ -7480,19 +4072,32 @@ decoder. The functions will later be shared with vdpu381 (rk3588) and vdpu383 (rk3576). +Tested-by: Diederik de Haas # Rock 5B +Reviewed-by: Nicolas Dufresne Signed-off-by: Detlev Casanova --- - drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c | 230 +++++++++ - drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h | 46 ++ - drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c | 240 +--------- - 3 files changed, 282 insertions(+), 234 deletions(-) + drivers/media/platform/rockchip/rkvdec/Makefile | 1 + + drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c | 206 +++++++++ + drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h | 49 +++ + drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c | 217 +--------- + 4 files changed, 263 insertions(+), 210 deletions(-) +diff --git a/drivers/media/platform/rockchip/rkvdec/Makefile b/drivers/media/platform/rockchip/rkvdec/Makefile +index 111111111111..222222222222 100644 +--- a/drivers/media/platform/rockchip/rkvdec/Makefile ++++ b/drivers/media/platform/rockchip/rkvdec/Makefile +@@ -6,4 +6,5 @@ rockchip-vdec-y += \ + rkvdec-h264.o \ + rkvdec-h264-common.o \ + rkvdec-hevc.o \ ++ rkvdec-hevc-common.o \ + rkvdec-vp9.o diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c new file mode 100644 index 000000000000..111111111111 --- /dev/null +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c -@@ -0,0 +1,230 @@ +@@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip video decoder hevc common functions @@ -7510,6 +4115,9 @@ index 000000000000..111111111111 + * Jeffy Chen + */ + ++#include ++#include ++ +#include "rkvdec.h" +#include "rkvdec-hevc-common.h" + @@ -7596,9 +4204,9 @@ index 000000000000..111111111111 + memset(output->reserved, 0, 4 * sizeof(u8)); +} + -+void assemble_hw_scaling_list(struct rkvdec_hevc_run *run, -+ struct scaling_factor *scaling_factor, -+ struct v4l2_ctrl_hevc_scaling_matrix *cache) ++void rkvdec_hevc_assemble_hw_scaling_list(struct rkvdec_hevc_run *run, ++ struct scaling_factor *scaling_factor, ++ struct v4l2_ctrl_hevc_scaling_matrix *cache) +{ + const struct v4l2_ctrl_hevc_scaling_matrix *scaling = run->scaling_matrix; + @@ -7671,28 +4279,9 @@ index 000000000000..111111111111 + return RKVDEC_IMG_FMT_ANY; +} + -+static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, -+ const struct v4l2_ctrl_hevc_sps *sps) -+{ -+ if (sps->chroma_format_idc > 1) -+ /* Only 4:0:0 and 4:2:0 are supported */ -+ return -EINVAL; -+ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) -+ /* Luma and chroma bit depth mismatch */ -+ return -EINVAL; -+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) -+ /* Only 8-bit and 10-bit is supported */ -+ return -EINVAL; -+ -+ if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width || -+ sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height) -+ return -EINVAL; -+ -+ return 0; -+} + +void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) ++ struct rkvdec_hevc_run *run) +{ + struct v4l2_ctrl *ctrl; + @@ -7715,20 +4304,12 @@ index 000000000000..111111111111 + + rkvdec_run_preamble(ctx, &run->base); +} -+ -+int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) -+{ -+ if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS) -+ return rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); -+ -+ return 0; -+} diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h new file mode 100644 index 000000000000..111111111111 --- /dev/null +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h -@@ -0,0 +1,46 @@ +@@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Rockchip video decoder hevc common functions @@ -7746,6 +4327,12 @@ index 000000000000..111111111111 + * Jeffy Chen + */ + ++#include ++#include "rkvdec.h" ++ ++#define RKV_HEVC_CABAC_TABLE_SIZE 27456 ++extern const u8 rkvdec_hevc_cabac_table[RKV_HEVC_CABAC_TABLE_SIZE]; ++ +struct rkvdec_hevc_run { + struct rkvdec_run base; + const struct v4l2_ctrl_hevc_slice_params *slices_params; @@ -7763,8 +4350,6 @@ index 000000000000..111111111111 + u8 reserved[4]; /*16Bytes align*/ +}; + -+enum rkvdec_image_fmt rkvdec_hevc_get_image_fmt(struct rkvdec_ctx *ctx, -+ struct v4l2_ctrl *ctrl); +void rkvdec_hevc_assemble_hw_scaling_list(struct rkvdec_hevc_run *run, + struct scaling_factor *scaling_factor, + struct v4l2_ctrl_hevc_scaling_matrix *cache); @@ -7772,8 +4357,7 @@ index 000000000000..111111111111 + struct rkvdec_hevc_run *run, + unsigned int dpb_idx); +int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, struct v4l2_format *f); -+//int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, const struct v4l2_ctrl_hevc_sps *sps); -+int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl); ++enum rkvdec_image_fmt rkvdec_hevc_get_image_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl); +void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run); diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c index 111111111111..222222222222 100644 @@ -7787,7 +4371,17 @@ index 111111111111..222222222222 100644 /* Size in u8/u32 units. */ #define RKV_SCALING_LIST_SIZE 1360 -@@ -113,34 +114,17 @@ struct rkvdec_ps_field { +@@ -24,9 +25,6 @@ + #define RKV_RPS_SIZE (32 / 4) + #define RKV_RPS_LEN 600 + +-#define RKV_HEVC_CABAC_TABLE_SIZE 27456 +-extern const u8 rkvdec_hevc_cabac_table[RKV_HEVC_CABAC_TABLE_SIZE]; +- + struct rkvdec_sps_pps_packet { + u32 info[RKV_PPS_SIZE]; + }; +@@ -113,34 +111,17 @@ struct rkvdec_ps_field { /* Data structure describing auxiliary buffer format. */ struct rkvdec_hevc_priv_tbl { u8 cabac_table[RKV_HEVC_CABAC_TABLE_SIZE]; @@ -7823,7 +4417,7 @@ index 111111111111..222222222222 100644 static void set_ps_field(u32 *buf, struct rkvdec_ps_field field, u32 value) { u8 bit = field.offset % 32, word = field.offset / 32; -@@ -417,131 +401,6 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, +@@ -417,131 +398,6 @@ static void assemble_sw_rps(struct rkvdec_ctx *ctx, } } @@ -7955,8 +4549,8 @@ index 111111111111..222222222222 100644 static void config_registers(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run) { -@@ -645,63 +504,6 @@ static void config_registers(struct rkvdec_ctx *ctx, - rkvdec_memcpy_toio(rkvdec->regs, regs, sizeof(*regs)); +@@ -645,43 +501,6 @@ static void config_registers(struct rkvdec_ctx *ctx, + MIN(sizeof(*regs), sizeof(u32) * rkvdec->variant->num_regs)); } -#define RKVDEC_HEVC_MAX_DEPTH_IN_BYTES 2 @@ -7996,30 +4590,19 @@ index 111111111111..222222222222 100644 - return RKVDEC_IMG_FMT_ANY; -} - --static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, -- const struct v4l2_ctrl_hevc_sps *sps) --{ -- if (sps->chroma_format_idc > 1) -- /* Only 4:0:0 and 4:2:0 are supported */ -- return -EINVAL; -- if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) -- /* Luma and chroma bit depth mismatch */ -- return -EINVAL; -- if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) -- /* Only 8-bit and 10-bit is supported */ -- return -EINVAL; -- -- if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width || -- sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height) -- return -EINVAL; -- -- return 0; --} -- - static int rkvdec_hevc_start(struct rkvdec_ctx *ctx) + static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, + const struct v4l2_ctrl_hevc_sps *sps) { - struct rkvdec_dev *rkvdec = ctx->dev; -@@ -738,40 +540,18 @@ static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx) +@@ -692,7 +511,7 @@ static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, + /* Luma and chroma bit depth mismatch */ + return -EINVAL; + if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) +- /* Only 8-bit and 10-bit is supported */ ++ /* Only 8-bit and 10-bit are supported */ + return -EINVAL; + + if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width || +@@ -738,40 +557,18 @@ static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx) kfree(hevc_ctx); } @@ -8062,161 +4645,210 @@ index 111111111111..222222222222 100644 + rkvdec_hevc_assemble_hw_scaling_list(&run, &tbl->scaling_list, + &hevc_ctx->scaling_matrix_cache); assemble_hw_pps(ctx, &run); - assemble_hw_rps(ctx, &run); + assemble_sw_rps(ctx, &run); config_registers(ctx, &run); -@@ -802,14 +582,6 @@ static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) - return 0; - } - --static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) --{ -- if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS) -- return rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); -- -- return 0; --} -- - const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = { - .adjust_fmt = rkvdec_hevc_adjust_fmt, - .start = rkvdec_hevc_start, -- Armbian From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Detlev Casanova -Date: Tue, 10 Jun 2025 14:05:08 -0400 -Subject: media: rkvdec: Add per variant configuration +Date: Thu, 18 Dec 2025 18:28:19 -0500 +Subject: media: rkvdec: Add variant specific coded formats list -This is to prepare for adding different variants of the decoder and -support specific formats and ops. +Prepare for adding new variants of the decoder and support specific +formats and format ops per variant. +This removes the need of capability flags for variants, so remove them. + +Tested-by: Diederik de Haas # Rock 5B Signed-off-by: Detlev Casanova --- - drivers/media/platform/rockchip/rkvdec/rkvdec.c | 31 +++++++--- - drivers/media/platform/rockchip/rkvdec/rkvdec.h | 7 +++ - 2 files changed, 28 insertions(+), 10 deletions(-) + drivers/media/platform/rockchip/rkvdec/rkvdec.c | 68 +++++----- + drivers/media/platform/rockchip/rkvdec/rkvdec.h | 8 +- + 2 files changed, 39 insertions(+), 37 deletions(-) diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c index 111111111111..222222222222 100644 --- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -@@ -390,12 +390,13 @@ rkvdec_enum_coded_fmt_desc(struct rkvdec_ctx *ctx, int index) +@@ -328,7 +328,6 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { + .ops = &rkvdec_hevc_fmt_ops, + .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), + .decoded_fmts = rkvdec_hevc_decoded_fmts, +- .capability = RKVDEC_CAPABILITY_HEVC, + }, + { + .fourcc = V4L2_PIX_FMT_H264_SLICE, +@@ -345,7 +344,6 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { + .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), + .decoded_fmts = rkvdec_h264_decoded_fmts, + .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, +- .capability = RKVDEC_CAPABILITY_H264, + }, + { + .fourcc = V4L2_PIX_FMT_VP9_FRAME, +@@ -361,27 +359,38 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { + .ops = &rkvdec_vp9_fmt_ops, + .num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts), + .decoded_fmts = rkvdec_vp9_decoded_fmts, +- .capability = RKVDEC_CAPABILITY_VP9, + } + }; + +-static bool rkvdec_is_capable(struct rkvdec_ctx *ctx, unsigned int capability) +-{ +- return (ctx->dev->variant->capabilities & capability) == capability; +-} ++static const struct rkvdec_coded_fmt_desc rk3288_coded_fmts[] = { ++ { ++ .fourcc = V4L2_PIX_FMT_HEVC_SLICE, ++ .frmsize = { ++ .min_width = 64, ++ .max_width = 4096, ++ .step_width = 64, ++ .min_height = 64, ++ .max_height = 2304, ++ .step_height = 16, ++ }, ++ .ctrls = &rkvdec_hevc_ctrls, ++ .ops = &rkvdec_hevc_fmt_ops, ++ .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), ++ .decoded_fmts = rkvdec_hevc_decoded_fmts, ++ } ++}; + + static const struct rkvdec_coded_fmt_desc * + rkvdec_enum_coded_fmt_desc(struct rkvdec_ctx *ctx, int index) + { ++ const struct rkvdec_variant *variant = ctx->dev->variant; + int fmt_idx = -1; + unsigned int i; + +- for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { +- if (!rkvdec_is_capable(ctx, rkvdec_coded_fmts[i].capability)) +- continue; ++ for (i = 0; i < variant->num_coded_fmts; i++) { + fmt_idx++; + if (index == fmt_idx) +- return &rkvdec_coded_fmts[i]; ++ return &variant->coded_fmts[i]; + } + + return NULL; +@@ -390,12 +399,12 @@ rkvdec_enum_coded_fmt_desc(struct rkvdec_ctx *ctx, int index) static const struct rkvdec_coded_fmt_desc * rkvdec_find_coded_fmt_desc(struct rkvdec_ctx *ctx, u32 fourcc) { -+ const struct rkvdec_config *cfg = ctx->dev->config; ++ const struct rkvdec_variant *variant = ctx->dev->variant; unsigned int i; - for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { - if (rkvdec_is_capable(ctx, rkvdec_coded_fmts[i].capability) && - rkvdec_coded_fmts[i].fourcc == fourcc) - return &rkvdec_coded_fmts[i]; -+ for (i = 0; i < cfg->coded_fmts_num; i++) { -+ if (rkvdec_is_capable(ctx, cfg->coded_fmts[i].capability) && -+ cfg->coded_fmts[i].fourcc == fourcc) -+ return &cfg->coded_fmts[i]; ++ for (i = 0; i < variant->num_coded_fmts; i++) { ++ if (variant->coded_fmts[i].fourcc == fourcc) ++ return &variant->coded_fmts[i]; } return NULL; -@@ -1002,18 +1003,19 @@ static int rkvdec_add_ctrls(struct rkvdec_ctx *ctx, +@@ -1014,21 +1023,19 @@ static int rkvdec_add_ctrls(struct rkvdec_ctx *ctx, static int rkvdec_init_ctrls(struct rkvdec_ctx *ctx) { -+ const struct rkvdec_config *cfg = ctx->dev->config; ++ const struct rkvdec_variant *variant = ctx->dev->variant; unsigned int i, nctrls = 0; int ret; - for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) - if (rkvdec_is_capable(ctx, rkvdec_coded_fmts[i].capability)) - nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls; -+ for (i = 0; i < cfg->coded_fmts_num; i++) -+ if (rkvdec_is_capable(ctx, cfg->coded_fmts[i].capability)) -+ nctrls += cfg->coded_fmts[i].ctrls->num_ctrls; ++ for (i = 0; i < variant->num_coded_fmts; i++) ++ nctrls += variant->coded_fmts[i].ctrls->num_ctrls; v4l2_ctrl_handler_init(&ctx->ctrl_hdl, nctrls); - for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { - if (rkvdec_is_capable(ctx, rkvdec_coded_fmts[i].capability)) { - ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls); -+ for (i = 0; i < cfg->coded_fmts_num; i++) { -+ if (rkvdec_is_capable(ctx, cfg->coded_fmts[i].capability)) { -+ ret = rkvdec_add_ctrls(ctx, cfg->coded_fmts[i].ctrls); - if (ret) - goto err_free_handler; - } -@@ -1228,11 +1230,18 @@ static void rkvdec_watchdog_func(struct work_struct *work) +- if (ret) +- goto err_free_handler; +- } ++ for (i = 0; i < variant->num_coded_fmts; i++) { ++ ret = rkvdec_add_ctrls(ctx, variant->coded_fmts[i].ctrls); ++ if (ret) ++ goto err_free_handler; } - } -+static const struct rkvdec_config config_rkvdec = { -+ .coded_fmts = (struct rkvdec_coded_fmt_desc *)rkvdec_coded_fmts, -+ .coded_fmts_num = ARRAY_SIZE(rkvdec_coded_fmts), -+}; -+ + ret = v4l2_ctrl_handler_setup(&ctx->ctrl_hdl); +@@ -1242,22 +1249,21 @@ static void rkvdec_watchdog_func(struct work_struct *work) + static const struct rkvdec_variant rk3288_rkvdec_variant = { -+ .config = &config_rkvdec, - .capabilities = RKVDEC_CAPABILITY_HEVC, + .num_regs = 68, +- .capabilities = RKVDEC_CAPABILITY_HEVC, ++ .coded_fmts = rk3288_coded_fmts, ++ .num_coded_fmts = ARRAY_SIZE(rk3288_coded_fmts), }; static const struct rkvdec_variant rk3328_rkvdec_variant = { -+ .config = &config_rkvdec, - .capabilities = RKVDEC_CAPABILITY_HEVC | - RKVDEC_CAPABILITY_H264 | - RKVDEC_CAPABILITY_VP9, -@@ -1240,6 +1249,7 @@ static const struct rkvdec_variant rk3328_rkvdec_variant = { + .num_regs = 109, +- .capabilities = RKVDEC_CAPABILITY_HEVC | +- RKVDEC_CAPABILITY_H264 | +- RKVDEC_CAPABILITY_VP9, ++ .coded_fmts = rkvdec_coded_fmts, ++ .num_coded_fmts = ARRAY_SIZE(rkvdec_coded_fmts), + .quirks = RKVDEC_QUIRK_DISABLE_QOS, }; static const struct rkvdec_variant rk3399_rkvdec_variant = { -+ .config = &config_rkvdec, - .capabilities = RKVDEC_CAPABILITY_HEVC | - RKVDEC_CAPABILITY_H264 | - RKVDEC_CAPABILITY_VP9, -@@ -1283,6 +1293,7 @@ static int rkvdec_probe(struct platform_device *pdev) + .num_regs = 78, +- .capabilities = RKVDEC_CAPABILITY_HEVC | +- RKVDEC_CAPABILITY_H264 | +- RKVDEC_CAPABILITY_VP9, ++ .coded_fmts = rkvdec_coded_fmts, ++ .num_coded_fmts = ARRAY_SIZE(rkvdec_coded_fmts), + }; - platform_set_drvdata(pdev, rkvdec); - rkvdec->dev = &pdev->dev; -+ rkvdec->config = variant->config; - rkvdec->capabilities = variant->capabilities; - rkvdec->quirks = variant->quirks; - mutex_init(&rkvdec->vdev_lock); + static const struct of_device_id of_rkvdec_match[] = { diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.h b/drivers/media/platform/rockchip/rkvdec/rkvdec.h index 111111111111..222222222222 100644 --- a/drivers/media/platform/rockchip/rkvdec/rkvdec.h +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -@@ -70,6 +70,7 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) - } +@@ -22,10 +22,6 @@ + #include + #include + +-#define RKVDEC_CAPABILITY_HEVC BIT(0) +-#define RKVDEC_CAPABILITY_H264 BIT(1) +-#define RKVDEC_CAPABILITY_VP9 BIT(2) +- + #define RKVDEC_QUIRK_DISABLE_QOS BIT(0) + + struct rkvdec_ctx; +@@ -71,7 +67,8 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) struct rkvdec_variant { -+ const struct rkvdec_config *config; - unsigned int capabilities; + unsigned int num_regs; +- unsigned int capabilities; ++ const struct rkvdec_coded_fmt_desc *coded_fmts; ++ size_t num_coded_fmts; unsigned int quirks; }; -@@ -112,6 +113,11 @@ struct rkvdec_coded_fmt_desc { - unsigned int capability; + +@@ -110,7 +107,6 @@ struct rkvdec_coded_fmt_desc { + unsigned int num_decoded_fmts; + const struct rkvdec_decoded_fmt_desc *decoded_fmts; + u32 subsystem_flags; +- unsigned int capability; }; -+struct rkvdec_config { -+ struct rkvdec_coded_fmt_desc *coded_fmts; -+ size_t coded_fmts_num; -+}; -+ struct rkvdec_dev { - struct v4l2_device v4l2_dev; - struct media_device mdev; -@@ -125,6 +131,7 @@ struct rkvdec_dev { - struct iommu_domain *empty_domain; - unsigned int capabilities; - unsigned int quirks; -+ const struct rkvdec_config *config; - }; - - struct rkvdec_ctx { -- Armbian From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Detlev Casanova -Date: Tue, 10 Jun 2025 14:53:27 -0400 +Date: Thu, 18 Dec 2025 18:28:20 -0500 Subject: media: rkvdec: Add RCB and SRAM support The RCB (Rows and Cols Buffers) are a set of buffers used by other @@ -8237,23 +4869,24 @@ so, how to free it. This commit is in preparation of other variants support. +Tested-by: Diederik de Haas # Rock 5B Signed-off-by: Detlev Casanova --- drivers/media/platform/rockchip/rkvdec/Makefile | 1 + - drivers/media/platform/rockchip/rkvdec/rkvdec-rcb.c | 174 ++++++++++ + drivers/media/platform/rockchip/rkvdec/rkvdec-rcb.c | 179 ++++++++++ drivers/media/platform/rockchip/rkvdec/rkvdec-rcb.h | 29 ++ - drivers/media/platform/rockchip/rkvdec/rkvdec.c | 29 +- + drivers/media/platform/rockchip/rkvdec/rkvdec.c | 27 +- drivers/media/platform/rockchip/rkvdec/rkvdec.h | 13 + - 5 files changed, 242 insertions(+), 4 deletions(-) + 5 files changed, 247 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/rockchip/rkvdec/Makefile b/drivers/media/platform/rockchip/rkvdec/Makefile index 111111111111..222222222222 100644 --- a/drivers/media/platform/rockchip/rkvdec/Makefile +++ b/drivers/media/platform/rockchip/rkvdec/Makefile -@@ -6,4 +6,5 @@ rockchip-vdec-y += \ - rkvdec-h264.o \ +@@ -7,4 +7,5 @@ rockchip-vdec-y += \ rkvdec-h264-common.o \ rkvdec-hevc.o \ + rkvdec-hevc-common.o \ + rkvdec-rcb.o \ rkvdec-vp9.o diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-rcb.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-rcb.c @@ -8261,7 +4894,7 @@ new file mode 100644 index 000000000000..111111111111 --- /dev/null +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-rcb.c -@@ -0,0 +1,174 @@ +@@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip video decoder Rows and Cols Buffers manager @@ -8273,9 +4906,10 @@ index 000000000000..111111111111 +#include "rkvdec.h" +#include "rkvdec-rcb.h" + -+#include +#include +#include ++#include ++#include + +struct rkvdec_rcb_config { + struct rkvdec_aux_buf *rcb_bufs; @@ -8320,14 +4954,14 @@ index 000000000000..111111111111 + continue; + + switch (cfg->rcb_bufs[i].type) { -+ case RKVDEC2_ALLOC_SRAM: ++ case RKVDEC_ALLOC_SRAM: + virt_addr = (unsigned long)cfg->rcb_bufs[i].cpu; + + if (dev->iommu_domain) + iommu_unmap(dev->iommu_domain, virt_addr, rcb_size); + gen_pool_free(dev->sram_pool, virt_addr, rcb_size); + break; -+ case RKVDEC2_ALLOC_DMA: ++ case RKVDEC_ALLOC_DMA: + dma_free_coherent(dev->dev, + rcb_size, + cfg->rcb_bufs[i].cpu, @@ -8351,6 +4985,11 @@ index 000000000000..111111111111 + struct rkvdec_dev *rkvdec = ctx->dev; + struct rkvdec_rcb_config *cfg; + ++ if (!size_info || !rcb_count) { ++ ctx->rcb_config = NULL; ++ return 0; ++ } ++ + ctx->rcb_config = devm_kzalloc(rkvdec->dev, sizeof(*ctx->rcb_config), GFP_KERNEL); + if (!ctx->rcb_config) + return -ENOMEM; @@ -8370,17 +5009,17 @@ index 000000000000..111111111111 + void *cpu = NULL; + dma_addr_t dma; + size_t rcb_size = rkvdec_rcb_size(&size_info[i], width, height); -+ enum rkvdec_alloc_type alloc_type = RKVDEC2_ALLOC_SRAM; ++ enum rkvdec_alloc_type alloc_type = RKVDEC_ALLOC_SRAM; + + /* Try allocating an SRAM buffer */ + if (ctx->dev->sram_pool) { + if (rkvdec->iommu_domain) -+ rcb_size = ALIGN(rcb_size, 0x1000); ++ rcb_size = ALIGN(rcb_size, SZ_4K); + + cpu = gen_pool_dma_zalloc_align(ctx->dev->sram_pool, + rcb_size, + &dma, -+ 0x1000); ++ SZ_4K); + } + + /* If an IOMMU is used, map the SRAM address through it */ @@ -8412,7 +5051,7 @@ index 000000000000..111111111111 + rcb_size, + &dma, + GFP_KERNEL); -+ alloc_type = RKVDEC2_ALLOC_DMA; ++ alloc_type = RKVDEC_ALLOC_DMA; + } + + if (!cpu) { @@ -8435,7 +5074,6 @@ index 000000000000..111111111111 + + return ret; +} -+ diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-rcb.h b/drivers/media/platform/rockchip/rkvdec/rkvdec-rcb.h new file mode 100644 index 000000000000..111111111111 @@ -8491,19 +5129,19 @@ index 111111111111..222222222222 100644 static bool rkvdec_image_fmt_match(enum rkvdec_image_fmt fmt1, enum rkvdec_image_fmt fmt2) -@@ -770,6 +772,7 @@ static int rkvdec_start_streaming(struct vb2_queue *q, unsigned int count) +@@ -778,6 +780,7 @@ static int rkvdec_start_streaming(struct vb2_queue *q, unsigned int count) { struct rkvdec_ctx *ctx = vb2_get_drv_priv(q); const struct rkvdec_coded_fmt_desc *desc; -+ const struct rkvdec_config *cfg = ctx->dev->config; ++ const struct rkvdec_variant *variant = ctx->dev->variant; int ret; if (V4L2_TYPE_IS_CAPTURE(q->type)) -@@ -779,13 +782,22 @@ static int rkvdec_start_streaming(struct vb2_queue *q, unsigned int count) +@@ -787,13 +790,22 @@ static int rkvdec_start_streaming(struct vb2_queue *q, unsigned int count) if (WARN_ON(!desc)) return -EINVAL; -+ ret = rkvdec_allocate_rcb(ctx, cfg->rcb_size_info, cfg->rcb_num); ++ ret = rkvdec_allocate_rcb(ctx, variant->rcb_sizes, variant->num_rcb_sizes); + if (ret) + return ret; + @@ -8523,7 +5161,7 @@ index 111111111111..222222222222 100644 } static void rkvdec_queue_cleanup(struct vb2_queue *vq, u32 state) -@@ -821,6 +833,8 @@ static void rkvdec_stop_streaming(struct vb2_queue *q) +@@ -829,6 +841,8 @@ static void rkvdec_stop_streaming(struct vb2_queue *q) if (desc->ops->stop) desc->ops->stop(ctx); @@ -8532,27 +5170,18 @@ index 111111111111..222222222222 100644 } rkvdec_queue_cleanup(q, VB2_BUF_STATE_ERROR); -@@ -1322,8 +1336,6 @@ static int rkvdec_probe(struct platform_device *pdev) - return ret; - } - -- vb2_dma_contig_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32)); -- - irq = platform_get_irq(pdev, 0); - if (irq <= 0) - return -ENXIO; -@@ -1336,6 +1348,10 @@ static int rkvdec_probe(struct platform_device *pdev) +@@ -1345,6 +1359,10 @@ static int rkvdec_probe(struct platform_device *pdev) return ret; } + rkvdec->sram_pool = of_gen_pool_get(pdev->dev.of_node, "sram", 0); -+ if (!rkvdec->sram_pool && rkvdec->config->rcb_num > 0) ++ if (!rkvdec->sram_pool && rkvdec->variant->num_rcb_sizes > 0) + dev_info(&pdev->dev, "No sram node, RCB will be stored in RAM\n"); + pm_runtime_set_autosuspend_delay(&pdev->dev, 100); pm_runtime_use_autosuspend(&pdev->dev); pm_runtime_enable(&pdev->dev); -@@ -1344,7 +1360,8 @@ static int rkvdec_probe(struct platform_device *pdev) +@@ -1353,7 +1371,8 @@ static int rkvdec_probe(struct platform_device *pdev) if (ret) goto err_disable_runtime_pm; @@ -8562,7 +5191,7 @@ index 111111111111..222222222222 100644 rkvdec->empty_domain = iommu_paging_domain_alloc(rkvdec->dev); if (IS_ERR(rkvdec->empty_domain)) { -@@ -1358,6 +1375,10 @@ static int rkvdec_probe(struct platform_device *pdev) +@@ -1367,6 +1386,10 @@ static int rkvdec_probe(struct platform_device *pdev) err_disable_runtime_pm: pm_runtime_dont_use_autosuspend(&pdev->dev); pm_runtime_disable(&pdev->dev); @@ -8577,7 +5206,7 @@ diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.h b/drivers/media/pla index 111111111111..222222222222 100644 --- a/drivers/media/platform/rockchip/rkvdec/rkvdec.h +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -@@ -19,6 +19,7 @@ +@@ -19,12 +19,14 @@ #include #include #include @@ -8585,7 +5214,6 @@ index 111111111111..222222222222 100644 #include #include -@@ -29,6 +30,7 @@ #define RKVDEC_QUIRK_DISABLE_QOS BIT(0) struct rkvdec_ctx; @@ -8593,25 +5221,25 @@ index 111111111111..222222222222 100644 struct rkvdec_ctrl_desc { struct v4l2_ctrl_config cfg; -@@ -116,6 +118,8 @@ struct rkvdec_coded_fmt_desc { - struct rkvdec_config { - struct rkvdec_coded_fmt_desc *coded_fmts; - size_t coded_fmts_num; -+ struct rcb_size_info *rcb_size_info; -+ size_t rcb_num; +@@ -69,6 +71,8 @@ struct rkvdec_variant { + unsigned int num_regs; + const struct rkvdec_coded_fmt_desc *coded_fmts; + size_t num_coded_fmts; ++ const struct rcb_size_info *rcb_sizes; ++ size_t num_rcb_sizes; + unsigned int quirks; }; - struct rkvdec_dev { -@@ -128,6 +132,8 @@ struct rkvdec_dev { +@@ -119,6 +123,8 @@ struct rkvdec_dev { void __iomem *regs; struct mutex vdev_lock; /* serializes ioctls */ struct delayed_work watchdog_work; + struct gen_pool *sram_pool; + struct iommu_domain *iommu_domain; struct iommu_domain *empty_domain; - unsigned int capabilities; - unsigned int quirks; -@@ -142,6 +148,7 @@ struct rkvdec_ctx { + const struct rkvdec_variant *variant; + }; +@@ -131,6 +137,7 @@ struct rkvdec_ctx { struct v4l2_ctrl_handler ctrl_hdl; struct rkvdec_dev *dev; enum rkvdec_image_fmt image_fmt; @@ -8619,13 +5247,13 @@ index 111111111111..222222222222 100644 void *priv; }; -@@ -150,10 +157,16 @@ static inline struct rkvdec_ctx *file_to_rkvdec_ctx(struct file *filp) +@@ -139,10 +146,16 @@ static inline struct rkvdec_ctx *file_to_rkvdec_ctx(struct file *filp) return container_of(file_to_v4l2_fh(filp), struct rkvdec_ctx, fh); } +enum rkvdec_alloc_type { -+ RKVDEC2_ALLOC_DMA = 0, -+ RKVDEC2_ALLOC_SRAM = 1, ++ RKVDEC_ALLOC_DMA = 0, ++ RKVDEC_ALLOC_SRAM = 1, +}; + struct rkvdec_aux_buf { @@ -8641,23 +5269,27 @@ Armbian From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Detlev Casanova -Date: Tue, 10 Jun 2025 15:13:46 -0400 +Date: Thu, 18 Dec 2025 18:28:21 -0500 Subject: media: rkvdec: Support per-variant interrupt handler -Preparation commit for supporting different variants with different -interrupt management. +Prepare for supporting different variants with different interrupt +managers. +To support other variants specific function type later, introduce the +rkvdec_variant_ops struct. + +Tested-by: Diederik de Haas # Rock 5B Signed-off-by: Detlev Casanova --- - drivers/media/platform/rockchip/rkvdec/rkvdec.c | 15 ++++++++-- - drivers/media/platform/rockchip/rkvdec/rkvdec.h | 1 + - 2 files changed, 13 insertions(+), 3 deletions(-) + drivers/media/platform/rockchip/rkvdec/rkvdec.c | 21 ++++++++-- + drivers/media/platform/rockchip/rkvdec/rkvdec.h | 5 +++ + 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c index 111111111111..222222222222 100644 --- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -@@ -1205,10 +1205,9 @@ static void rkvdec_iommu_restore(struct rkvdec_dev *rkvdec) +@@ -1222,10 +1222,9 @@ static void rkvdec_iommu_restore(struct rkvdec_dev *rkvdec) } } @@ -8670,7 +5302,7 @@ index 111111111111..222222222222 100644 enum vb2_buffer_state state; u32 status; -@@ -1229,6 +1228,15 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) +@@ -1246,6 +1245,15 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) return IRQ_HANDLED; } @@ -8678,40 +5310,73 @@ index 111111111111..222222222222 100644 +{ + struct rkvdec_dev *rkvdec = priv; + struct rkvdec_ctx *ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); -+ const struct rkvdec_config *cfg = rkvdec->config; ++ const struct rkvdec_variant *variant = rkvdec->variant; + -+ return cfg->irq_handler(ctx); ++ return variant->ops->irq_handler(ctx); +} + static void rkvdec_watchdog_func(struct work_struct *work) { struct rkvdec_dev *rkvdec; -@@ -1247,6 +1255,7 @@ static void rkvdec_watchdog_func(struct work_struct *work) - static const struct rkvdec_config config_rkvdec = { - .coded_fmts = (struct rkvdec_coded_fmt_desc *)rkvdec_coded_fmts, - .coded_fmts_num = ARRAY_SIZE(rkvdec_coded_fmts), +@@ -1261,16 +1269,22 @@ static void rkvdec_watchdog_func(struct work_struct *work) + } + } + ++static const struct rkvdec_variant_ops rk3399_variant_ops = { + .irq_handler = rk3399_irq_handler, ++}; ++ + static const struct rkvdec_variant rk3288_rkvdec_variant = { + .num_regs = 68, + .coded_fmts = rk3288_coded_fmts, + .num_coded_fmts = ARRAY_SIZE(rk3288_coded_fmts), ++ .ops = &rk3399_variant_ops, }; - static const struct rkvdec_variant rk3288_rkvdec_variant = { + static const struct rkvdec_variant rk3328_rkvdec_variant = { + .num_regs = 109, + .coded_fmts = rkvdec_coded_fmts, + .num_coded_fmts = ARRAY_SIZE(rkvdec_coded_fmts), ++ .ops = &rk3399_variant_ops, + .quirks = RKVDEC_QUIRK_DISABLE_QOS, + }; + +@@ -1278,6 +1292,7 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = { + .num_regs = 78, + .coded_fmts = rkvdec_coded_fmts, + .num_coded_fmts = ARRAY_SIZE(rkvdec_coded_fmts), ++ .ops = &rk3399_variant_ops, + }; + + static const struct of_device_id of_rkvdec_match[] = { diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.h b/drivers/media/platform/rockchip/rkvdec/rkvdec.h index 111111111111..222222222222 100644 --- a/drivers/media/platform/rockchip/rkvdec/rkvdec.h +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -@@ -120,6 +120,7 @@ struct rkvdec_config { - size_t coded_fmts_num; - struct rcb_size_info *rcb_size_info; - size_t rcb_num; +@@ -67,12 +67,17 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) + base.vb.vb2_buf); + } + ++struct rkvdec_variant_ops { + irqreturn_t (*irq_handler)(struct rkvdec_ctx *ctx); ++}; ++ + struct rkvdec_variant { + unsigned int num_regs; + const struct rkvdec_coded_fmt_desc *coded_fmts; + size_t num_coded_fmts; + const struct rcb_size_info *rcb_sizes; + size_t num_rcb_sizes; ++ const struct rkvdec_variant_ops *ops; + unsigned int quirks; }; - struct rkvdec_dev { -- Armbian From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Detlev Casanova -Date: Tue, 10 Jun 2025 16:40:09 -0400 +Date: Thu, 18 Dec 2025 18:28:22 -0500 Subject: media: rkvdec: Enable all clocks without naming them For other variants, the clock names and number will differ. @@ -8719,17 +5384,19 @@ For other variants, the clock names and number will differ. There is no need to keep track of the clock names in the driver so drop them to avoid having a list for each variant. +Tested-by: Diederik de Haas # Rock 5B +Reviewed-by: Nicolas Dufresne Signed-off-by: Detlev Casanova --- - drivers/media/platform/rockchip/rkvdec/rkvdec.c | 24 +++------- + drivers/media/platform/rockchip/rkvdec/rkvdec.c | 26 +++------- drivers/media/platform/rockchip/rkvdec/rkvdec.h | 1 + - 2 files changed, 7 insertions(+), 18 deletions(-) + 2 files changed, 7 insertions(+), 20 deletions(-) diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c index 111111111111..222222222222 100644 --- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -@@ -1295,15 +1295,10 @@ static const struct of_device_id of_rkvdec_match[] = { +@@ -1312,15 +1312,10 @@ static const struct of_device_id of_rkvdec_match[] = { }; MODULE_DEVICE_TABLE(of, of_rkvdec_match); @@ -8745,7 +5412,7 @@ index 111111111111..222222222222 100644 int ret, irq; variant = of_device_get_match_data(&pdev->dev); -@@ -1322,19 +1317,12 @@ static int rkvdec_probe(struct platform_device *pdev) +@@ -1337,19 +1332,12 @@ static int rkvdec_probe(struct platform_device *pdev) mutex_init(&rkvdec->vdev_lock); INIT_DELAYED_WORK(&rkvdec->watchdog_work, rkvdec_watchdog_func); @@ -8764,38 +5431,39 @@ index 111111111111..222222222222 100644 + if (ret < 0) return ret; -+ rkvdec->clk_count = ret; ++ rkvdec->num_clocks = ret; + rkvdec->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(rkvdec->regs)) return PTR_ERR(rkvdec->regs); -@@ -1410,7 +1398,7 @@ static int rkvdec_runtime_resume(struct device *dev) +@@ -1427,16 +1415,14 @@ static int rkvdec_runtime_resume(struct device *dev) { struct rkvdec_dev *rkvdec = dev_get_drvdata(dev); - return clk_bulk_prepare_enable(ARRAY_SIZE(rkvdec_clk_names), -+ return clk_bulk_prepare_enable(rkvdec->clk_count, - rkvdec->clocks); +- rkvdec->clocks); ++ return clk_bulk_prepare_enable(rkvdec->num_clocks, rkvdec->clocks); } -@@ -1418,7 +1406,7 @@ static int rkvdec_runtime_suspend(struct device *dev) + static int rkvdec_runtime_suspend(struct device *dev) { struct rkvdec_dev *rkvdec = dev_get_drvdata(dev); - clk_bulk_disable_unprepare(ARRAY_SIZE(rkvdec_clk_names), -+ clk_bulk_disable_unprepare(rkvdec->clk_count, - rkvdec->clocks); +- rkvdec->clocks); ++ clk_bulk_disable_unprepare(rkvdec->num_clocks, rkvdec->clocks); return 0; } + #endif diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.h b/drivers/media/platform/rockchip/rkvdec/rkvdec.h index 111111111111..222222222222 100644 --- a/drivers/media/platform/rockchip/rkvdec/rkvdec.h +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -@@ -130,6 +130,7 @@ struct rkvdec_dev { +@@ -125,6 +125,7 @@ struct rkvdec_dev { struct v4l2_m2m_dev *m2m_dev; struct device *dev; struct clk_bulk_data *clocks; -+ unsigned int clk_count; ++ unsigned int num_clocks; void __iomem *regs; struct mutex vdev_lock; /* serializes ioctls */ struct delayed_work watchdog_work; @@ -8804,7 +5472,96 @@ Armbian From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Detlev Casanova -Date: Tue, 10 Jun 2025 15:53:52 -0400 +Date: Thu, 18 Dec 2025 18:28:23 -0500 +Subject: media: rkvdec: Disable multicore support + +Similarly to what is done in Hantro, avoid exposing equal video codecs to +userspace. Equal video codecs allow scheduling work between the cores. +For that kernel support is required, which does not yet exist. +Until that is implemented, avoid exposing each core separately to +userspace so that multicore can be added in the future without breaking +userspace ABI. + +This currently applies only to RK3588 which has 2 equal VDPU381 decoders, +but will be applied for all SoC supported by rkvdec that has multiple DTS +nodes with the same compatible. + +Signed-off-by: Detlev Casanova +--- + drivers/media/platform/rockchip/rkvdec/rkvdec.c | 47 ++++++++++ + 1 file changed, 47 insertions(+) + +diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c +index 111111111111..222222222222 100644 +--- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c ++++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c +@@ -1269,6 +1269,49 @@ static void rkvdec_watchdog_func(struct work_struct *work) + } + } + ++/* ++ * Some SoCs, like RK3588 have multiple identical VDPU cores, but the ++ * kernel is currently missing support for multi-core handling. Exposing ++ * separate devices for each core to userspace is bad, since that does ++ * not allow scheduling tasks properly (and creates ABI). With this workaround ++ * the driver will only probe for the first core and early exit for the other ++ * cores. Once the driver gains multi-core support, the same technique ++ * for detecting the first core can be used to cluster all cores together. ++ */ ++static int rkvdec_disable_multicore(struct rkvdec_dev *rkvdec) ++{ ++ struct device_node *node = NULL; ++ const char *compatible; ++ bool is_first_core; ++ int ret; ++ ++ /* Intentionally ignores the fallback strings */ ++ ret = of_property_read_string(rkvdec->dev->of_node, "compatible", &compatible); ++ if (ret) ++ return ret; ++ ++ /* The first compatible and available node found is considered the main core */ ++ do { ++ node = of_find_compatible_node(node, NULL, compatible); ++ if (of_device_is_available(node)) ++ break; ++ } while (node); ++ ++ if (!node) ++ return -EINVAL; ++ ++ is_first_core = (rkvdec->dev->of_node == node); ++ ++ of_node_put(node); ++ ++ if (!is_first_core) { ++ dev_info(rkvdec->dev, "missing multi-core support, ignoring this instance\n"); ++ return -ENODEV; ++ } ++ ++ return 0; ++} ++ + static const struct rkvdec_variant_ops rk3399_variant_ops = { + .irq_handler = rk3399_irq_handler, + }; +@@ -1332,6 +1375,10 @@ static int rkvdec_probe(struct platform_device *pdev) + mutex_init(&rkvdec->vdev_lock); + INIT_DELAYED_WORK(&rkvdec->watchdog_work, rkvdec_watchdog_func); + ++ ret = rkvdec_disable_multicore(rkvdec); ++ if (ret) ++ return ret; ++ + ret = devm_clk_bulk_get_all_enabled(&pdev->dev, &rkvdec->clocks); + if (ret < 0) + return ret; +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Detlev Casanova +Date: Thu, 18 Dec 2025 18:28:24 -0500 Subject: media: rkvdec: Add H264 support for the VDPU381 variant This decoder variant is found in Rockchip RK3588 SoC family. @@ -8815,29 +5572,29 @@ output formats and level up to 5.1. The maximum width and height have been significantly increased supporting up to 65520 pixels for both. -Also make sure to only expose the first core and ignore the other -until mutli-core is supported. +Support for named register sections is added for this variant and future +ones. Fluster score for JVT-AVC_V1 is 129/135. +Tested-by: Diederik de Haas # Rock 5B Signed-off-by: Detlev Casanova --- drivers/media/platform/rockchip/rkvdec/Makefile | 1 + drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.h | 2 + - drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c | 2 - - drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c | 469 ++++++++++ - drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-regs.h | 427 +++++++++ - drivers/media/platform/rockchip/rkvdec/rkvdec.c | 173 +++- - drivers/media/platform/rockchip/rkvdec/rkvdec.h | 6 + - 7 files changed, 1076 insertions(+), 4 deletions(-) + drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c | 465 ++++++++++ + drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-regs.h | 424 +++++++++ + drivers/media/platform/rockchip/rkvdec/rkvdec.c | 97 +- + drivers/media/platform/rockchip/rkvdec/rkvdec.h | 11 + + 6 files changed, 997 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/rockchip/rkvdec/Makefile b/drivers/media/platform/rockchip/rkvdec/Makefile index 111111111111..222222222222 100644 --- a/drivers/media/platform/rockchip/rkvdec/Makefile +++ b/drivers/media/platform/rockchip/rkvdec/Makefile -@@ -7,4 +7,5 @@ rockchip-vdec-y += \ - rkvdec-h264-common.o \ +@@ -8,4 +8,5 @@ rockchip-vdec-y += \ rkvdec-hevc.o \ + rkvdec-hevc-common.o \ rkvdec-rcb.o \ + rkvdec-vdpu381-h264.o \ rkvdec-vp9.o @@ -8845,7 +5602,7 @@ diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.h b/drive index 111111111111..222222222222 100644 --- a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.h +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.h -@@ -66,6 +66,8 @@ struct rkvdec_rps { +@@ -74,6 +74,8 @@ struct rkvdec_rps { u32 reserved1[66]; } __packed; @@ -8854,25 +5611,12 @@ index 111111111111..222222222222 100644 void lookup_ref_buf_idx(struct rkvdec_ctx *ctx, struct rkvdec_h264_run *run); void assemble_hw_rps(struct v4l2_h264_reflist_builder *builder, struct rkvdec_h264_run *run, -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c -@@ -16,8 +16,6 @@ - #include "rkvdec-regs.h" - #include "rkvdec-h264-common.h" - --extern const s8 rkvdec_h264_cabac_table[4][464][2]; -- - /* Size with u32 units. */ - #define RKV_CABAC_INIT_BUFFER_SIZE (3680 + 128) - #define RKV_ERROR_INFO_SIZE (256 * 144 * 4) diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c new file mode 100644 index 000000000000..111111111111 --- /dev/null +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c -@@ -0,0 +1,469 @@ +@@ -0,0 +1,465 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip VDPU381 Video Decoder H264 backend @@ -9244,10 +5988,6 @@ index 000000000000..111111111111 + if (!ctrl) + return -EINVAL; + -+ ret = rkvdec_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps); -+ if (ret) -+ return ret; -+ + h264_ctx = kzalloc(sizeof(*h264_ctx), GFP_KERNEL); + if (!h264_ctx) + return -ENOMEM; @@ -9347,7 +6087,7 @@ new file mode 100644 index 000000000000..111111111111 --- /dev/null +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-regs.h -@@ -0,0 +1,427 @@ +@@ -0,0 +1,424 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Rockchip VDPU381 Video Decoder driver registers description @@ -9374,9 +6114,6 @@ index 000000000000..111111111111 + +#define MAX_SLICE_NUMBER 0x3fff + -+#define RKVDEC_1080P_PIXELS (1920 * 1080) -+#define RKVDEC_4K_PIXELS (4096 * 2304) -+#define RKVDEC_8K_PIXELS (7680 * 4320) +#define RKVDEC_TIMEOUT_1080p (0xefffff) +#define RKVDEC_TIMEOUT_4K (0x2cfffff) +#define RKVDEC_TIMEOUT_8K (0x4ffffff) @@ -9440,7 +6177,7 @@ index 000000000000..111111111111 + u32 reserved4 : 7; + } reg011; + -+ struct rkvdec_vdpu381_sencodary_en { ++ struct rkvdec_vdpu381_secondary_en { + u32 wr_ddr_align_en : 1; + u32 colmv_compress_en : 1; + u32 fbc_e : 1; @@ -9787,60 +6524,17 @@ index 111111111111..222222222222 100644 #include "rkvdec-rcb.h" static bool rkvdec_image_fmt_match(enum rkvdec_image_fmt fmt1, -@@ -85,11 +86,50 @@ static bool rkvdec_is_valid_fmt(struct rkvdec_ctx *ctx, u32 fourcc, - return false; - } - -+#define VDPU38X_STRIDE_ALIGN 16 -+ -+/** -+ * The default v4l2_fill_pixfmt_mp() function doesn't allow for specific alignment values. -+ * As the VDPU381 and VDPU383 need lines to be aligned on 16, use our own implementation here. -+ */ -+static int vdpu38x_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pix_mp, u32 pixelformat, -+ u32 width, u32 height) -+{ -+ const struct v4l2_format_info *info = v4l2_format_info(pix_mp->pixelformat); -+ struct v4l2_plane_pix_format *plane = &pix_mp->plane_fmt[0]; -+ -+ if (!info) -+ return -EINVAL; -+ -+ pix_mp->num_planes = 1; -+ -+ memset(plane, 0, sizeof(*plane)); -+ -+ plane->bytesperline = pix_mp->width * info->bpp[0] / info->bpp_div[0]; -+ plane->bytesperline = ALIGN(plane->bytesperline, VDPU38X_STRIDE_ALIGN); -+ -+ for (int i = 0; i < info->comp_planes; i++) { -+ unsigned int vdiv = i ? info->vdiv : 1; -+ unsigned int hdiv = i ? info->hdiv : 1; -+ unsigned int stride = DIV_ROUND_UP(pix_mp->width, hdiv) -+ * info->bpp[i] / info->bpp_div[i]; -+ unsigned int height = DIV_ROUND_UP(pix_mp->height, vdiv); -+ -+ plane->sizeimage += ALIGN(stride, VDPU38X_STRIDE_ALIGN) * height; -+ } -+ -+ return 0; -+} -+ - static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, - struct v4l2_pix_format_mplane *pix_mp) +@@ -90,6 +91,9 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, { -- v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, -- pix_mp->width, pix_mp->height); -+ const struct rkvdec_config *cfg = ctx->dev->config; -+ -+ cfg->fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, pix_mp->width, pix_mp->height); + v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, + pix_mp->width, pix_mp->height); + + ctx->colmv_offset = pix_mp->plane_fmt[0].sizeimage; + pix_mp->plane_fmt[0].sizeimage += 128 * DIV_ROUND_UP(pix_mp->width, 16) * DIV_ROUND_UP(pix_mp->height, 16); -@@ -367,6 +407,26 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { +@@ -382,6 +386,25 @@ static const struct rkvdec_coded_fmt_desc rk3288_coded_fmts[] = { } }; @@ -9851,7 +6545,7 @@ index 111111111111..222222222222 100644 + .min_width = 64, + .max_width = 65520, + .step_width = 64, -+ .min_height = 16, ++ .min_height = 64, + .max_height = 65520, + .step_height = 16, + }, @@ -9860,14 +6554,13 @@ index 111111111111..222222222222 100644 + .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), + .decoded_fmts = rkvdec_h264_decoded_fmts, + .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, -+ .capability = RKVDEC_CAPABILITY_H264, + }, +}; + - static bool rkvdec_is_capable(struct rkvdec_ctx *ctx, unsigned int capability) + static const struct rkvdec_coded_fmt_desc * + rkvdec_enum_coded_fmt_desc(struct rkvdec_ctx *ctx, int index) { - return (ctx->dev->capabilities & capability) == capability; -@@ -1228,6 +1288,35 @@ static irqreturn_t rk3399_irq_handler(struct rkvdec_ctx *ctx) +@@ -1245,6 +1268,35 @@ static irqreturn_t rk3399_irq_handler(struct rkvdec_ctx *ctx) return IRQ_HANDLED; } @@ -9903,61 +6596,30 @@ index 111111111111..222222222222 100644 static irqreturn_t rkvdec_irq_handler(int irq, void *priv) { struct rkvdec_dev *rkvdec = priv; -@@ -1252,10 +1341,76 @@ static void rkvdec_watchdog_func(struct work_struct *work) - } - } +@@ -1321,6 +1373,7 @@ static const struct rkvdec_variant rk3288_rkvdec_variant = { + .coded_fmts = rk3288_coded_fmts, + .num_coded_fmts = ARRAY_SIZE(rk3288_coded_fmts), + .ops = &rk3399_variant_ops, ++ .has_single_reg_region = true, + }; -+/* -+ * Some SoCs, like RK3588 have multiple identical VDPU cores, but the -+ * kernel is currently missing support for multi-core handling. Exposing -+ * separate devices for each core to userspace is bad, since that does -+ * not allow scheduling tasks properly (and creates ABI). With this workaround -+ * the driver will only probe for the first core and early exit for the other -+ * cores. Once the driver gains multi-core support, the same technique -+ * for detecting the first core can be used to cluster all cores together. -+ */ -+static int rkvdec_disable_multicore(struct rkvdec_dev *rkvdec) -+{ -+ struct device_node *node = NULL; -+ const char *compatible; -+ bool is_first_core; -+ int ret; -+ -+ /* Intentionally ignores the fallback strings */ -+ ret = of_property_read_string(rkvdec->dev->of_node, "compatible", &compatible); -+ if (ret) -+ return ret; -+ -+ /* The first compatible and available node found is considered the main core */ -+ do { -+ node = of_find_compatible_node(node, NULL, compatible); -+ if (of_device_is_available(node)) -+ break; -+ } while (node); -+ -+ if (!node) -+ return -EINVAL; -+ -+ is_first_core = (rkvdec->dev->of_node == node); -+ -+ of_node_put(node); -+ -+ if (!is_first_core) { -+ dev_info(rkvdec->dev, "missing multi-core support, ignoring this instance\n"); -+ return -ENODEV; -+ } -+ -+ return 0; -+} -+ - static const struct rkvdec_config config_rkvdec = { - .coded_fmts = (struct rkvdec_coded_fmt_desc *)rkvdec_coded_fmts, - .coded_fmts_num = ARRAY_SIZE(rkvdec_coded_fmts), - .irq_handler = rk3399_irq_handler, -+ .fill_pixfmt_mp = v4l2_fill_pixfmt_mp, + static const struct rkvdec_variant rk3328_rkvdec_variant = { +@@ -1328,6 +1381,7 @@ static const struct rkvdec_variant rk3328_rkvdec_variant = { + .coded_fmts = rkvdec_coded_fmts, + .num_coded_fmts = ARRAY_SIZE(rkvdec_coded_fmts), + .ops = &rk3399_variant_ops, ++ .has_single_reg_region = true, + .quirks = RKVDEC_QUIRK_DISABLE_QOS, + }; + +@@ -1336,6 +1390,32 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = { + .coded_fmts = rkvdec_coded_fmts, + .num_coded_fmts = ARRAY_SIZE(rkvdec_coded_fmts), + .ops = &rk3399_variant_ops, ++ .has_single_reg_region = true, +}; + -+static struct rcb_size_info vdpu381_rcb_sizes[] = { ++static const struct rcb_size_info vdpu381_rcb_sizes[] = { + {6, PIC_WIDTH}, // intrar + {1, PIC_WIDTH}, // transdr (Is actually 0.4*pic_width) + {1, PIC_HEIGHT}, // transdc (Is actually 0.1*pic_height) @@ -9970,78 +6632,83 @@ index 111111111111..222222222222 100644 + {67, PIC_HEIGHT}, // filtc col +}; + -+static const struct rkvdec_config config_vdpu381 = { -+ .coded_fmts = (struct rkvdec_coded_fmt_desc *)vdpu381_coded_fmts, -+ .coded_fmts_num = ARRAY_SIZE(vdpu381_coded_fmts), -+ .rcb_size_info = vdpu381_rcb_sizes, -+ .rcb_num = ARRAY_SIZE(vdpu381_rcb_sizes), ++static const struct rkvdec_variant_ops vdpu381_variant_ops = { + .irq_handler = vdpu381_irq_handler, -+ .fill_pixfmt_mp = vdpu38x_fill_pixfmt_mp, - }; - - static const struct rkvdec_variant rk3288_rkvdec_variant = { -@@ -1278,6 +1433,11 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = { - RKVDEC_CAPABILITY_VP9, - }; - -+static const struct rkvdec_variant rk3588_vdpu381_variant = { -+ .config = &config_vdpu381, -+ .capabilities = RKVDEC_CAPABILITY_H264, +}; + ++static const struct rkvdec_variant vdpu381_variant = { ++ .coded_fmts = vdpu381_coded_fmts, ++ .num_coded_fmts = ARRAY_SIZE(vdpu381_coded_fmts), ++ .rcb_sizes = vdpu381_rcb_sizes, ++ .num_rcb_sizes = ARRAY_SIZE(vdpu381_rcb_sizes), ++ .ops = &vdpu381_variant_ops, + }; + static const struct of_device_id of_rkvdec_match[] = { - { - .compatible = "rockchip,rk3288-vdec", -@@ -1291,6 +1451,10 @@ static const struct of_device_id of_rkvdec_match[] = { +@@ -1351,6 +1431,10 @@ static const struct of_device_id of_rkvdec_match[] = { .compatible = "rockchip,rk3399-vdec", .data = &rk3399_rkvdec_variant, }, + { + .compatible = "rockchip,rk3588-vdec", -+ .data = &rk3588_vdpu381_variant, ++ .data = &vdpu381_variant, + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, of_rkvdec_match); -@@ -1317,11 +1481,16 @@ static int rkvdec_probe(struct platform_device *pdev) - mutex_init(&rkvdec->vdev_lock); - INIT_DELAYED_WORK(&rkvdec->watchdog_work, rkvdec_watchdog_func); - -+ ret = rkvdec_disable_multicore(rkvdec); -+ if (ret) -+ return ret; -+ - ret = devm_clk_bulk_get_all_enabled(&pdev->dev, &rkvdec->clocks); - if (ret < 0) +@@ -1384,10 +1468,17 @@ static int rkvdec_probe(struct platform_device *pdev) return ret; - rkvdec->clk_count = ret; + rkvdec->num_clocks = ret; + rkvdec->axi_clk = devm_clk_get(&pdev->dev, "axi"); - rkvdec->regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(rkvdec->regs)) +- rkvdec->regs = devm_platform_ioremap_resource(pdev, 0); +- if (IS_ERR(rkvdec->regs)) +- return PTR_ERR(rkvdec->regs); ++ if (rkvdec->variant->has_single_reg_region) { ++ rkvdec->regs = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(rkvdec->regs)) ++ return PTR_ERR(rkvdec->regs); ++ } else { ++ rkvdec->regs = devm_platform_ioremap_resource_byname(pdev, "function"); ++ if (IS_ERR(rkvdec->regs)) ++ return PTR_ERR(rkvdec->regs); ++ } + + ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); + if (ret) { diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.h b/drivers/media/platform/rockchip/rkvdec/rkvdec.h index 111111111111..222222222222 100644 --- a/drivers/media/platform/rockchip/rkvdec/rkvdec.h +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -@@ -121,6 +121,8 @@ struct rkvdec_config { - struct rcb_size_info *rcb_size_info; - size_t rcb_num; - irqreturn_t (*irq_handler)(struct rkvdec_ctx *ctx); -+ int (*fill_pixfmt_mp)(struct v4l2_pix_format_mplane *pix_mp, u32 pixelformat, -+ u32 width, u32 height); +@@ -25,6 +25,10 @@ + + #define RKVDEC_QUIRK_DISABLE_QOS BIT(0) + ++#define RKVDEC_1080P_PIXELS (1920 * 1088) ++#define RKVDEC_4K_PIXELS (4096 * 2304) ++#define RKVDEC_8K_PIXELS (7680 * 4320) ++ + struct rkvdec_ctx; + struct rkvdec_rcb_config; + +@@ -78,6 +82,7 @@ struct rkvdec_variant { + const struct rcb_size_info *rcb_sizes; + size_t num_rcb_sizes; + const struct rkvdec_variant_ops *ops; ++ bool has_single_reg_region; + unsigned int quirks; }; - struct rkvdec_dev { -@@ -131,6 +133,7 @@ struct rkvdec_dev { +@@ -126,6 +131,7 @@ struct rkvdec_dev { struct device *dev; struct clk_bulk_data *clocks; - unsigned int clk_count; + unsigned int num_clocks; + struct clk *axi_clk; void __iomem *regs; struct mutex vdev_lock; /* serializes ioctls */ struct delayed_work watchdog_work; -@@ -151,6 +154,7 @@ struct rkvdec_ctx { +@@ -144,6 +150,7 @@ struct rkvdec_ctx { struct rkvdec_dev *dev; enum rkvdec_image_fmt image_fmt; struct rkvdec_rcb_config *rcb_config; @@ -10049,10 +6716,16 @@ index 111111111111..222222222222 100644 void *priv; }; -@@ -179,4 +183,6 @@ extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops; +@@ -170,8 +177,12 @@ void rkvdec_memcpy_toio(void __iomem *dst, void *src, size_t len); + + void rkvdec_quirks_disable_qos(struct rkvdec_ctx *ctx); + ++/* RKVDEC ops */ + extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops; extern const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops; extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops; ++/* VDPU381 ops */ +extern const struct rkvdec_coded_fmt_ops rkvdec_vdpu381_h264_fmt_ops; + #endif /* RKVDEC_H_ */ @@ -10061,7 +6734,7 @@ Armbian From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Detlev Casanova -Date: Tue, 10 Jun 2025 17:45:17 -0400 +Date: Thu, 18 Dec 2025 18:28:25 -0500 Subject: media: rkvdec: Add H264 support for the VDPU383 variant This variant is used on the RK3576 SoC. @@ -10070,1281 +6743,37 @@ The moving vectors size requirements are slightly different so support for a colmv_size function per variant is added. Also, the link registers are used to start the decoder and read IRQ status. -Per variant support for named register sections is added. -The fluster score is 128/135 for JVT-AVC_V1. +The fluster score is 128/135 for JVT-AVC_V1, with MPS_MW_A failing in +addition to the usual ones. The other test suites are not supported yet. +Reviewed-by: Nicolas Dufresne Signed-off-by: Detlev Casanova --- - drivers/media/platform/rockchip/rkvdec/Kconfig | 1 + - drivers/media/platform/rockchip/rkvdec/Makefile | 3 + - drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c | 413 ++++++- - drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h | 84 +- - drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c | 5 +- - drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c | 588 ++++++++++ - drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c | 582 +++++++++ - drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-regs.h | 284 +++++ - drivers/media/platform/rockchip/rkvdec/rkvdec.c | 212 +++- - drivers/media/platform/rockchip/rkvdec/rkvdec.h | 9 + - 10 files changed, 2109 insertions(+), 72 deletions(-) + drivers/media/platform/rockchip/rkvdec/Makefile | 1 + + drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c | 578 ++++++++++ + drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-regs.h | 281 +++++ + drivers/media/platform/rockchip/rkvdec/rkvdec.c | 105 +- + drivers/media/platform/rockchip/rkvdec/rkvdec.h | 5 + + 5 files changed, 965 insertions(+), 5 deletions(-) -diff --git a/drivers/media/platform/rockchip/rkvdec/Kconfig b/drivers/media/platform/rockchip/rkvdec/Kconfig -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/Kconfig -+++ b/drivers/media/platform/rockchip/rkvdec/Kconfig -@@ -8,6 +8,7 @@ config VIDEO_ROCKCHIP_VDEC - select VIDEOBUF2_VMALLOC - select V4L2_MEM2MEM_DEV - select V4L2_H264 -+ select V4L2_HEVC - select V4L2_VP9 - help - Support for the Rockchip Video Decoder IP present on Rockchip SoCs, diff --git a/drivers/media/platform/rockchip/rkvdec/Makefile b/drivers/media/platform/rockchip/rkvdec/Makefile index 111111111111..222222222222 100644 --- a/drivers/media/platform/rockchip/rkvdec/Makefile +++ b/drivers/media/platform/rockchip/rkvdec/Makefile -@@ -6,6 +6,9 @@ rockchip-vdec-y += \ - rkvdec-h264.o \ - rkvdec-h264-common.o \ - rkvdec-hevc.o \ -+ rkvdec-hevc-common.o \ +@@ -9,4 +9,5 @@ rockchip-vdec-y += \ + rkvdec-hevc-common.o \ rkvdec-rcb.o \ rkvdec-vdpu381-h264.o \ -+ rkvdec-vdpu381-hevc.o \ + rkvdec-vdpu383-h264.o \ rkvdec-vp9.o -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c -@@ -18,6 +18,143 @@ - #include "rkvdec.h" - #include "rkvdec-hevc-common.h" - -+#define RKVDEC_HEVC_MAX_DEPTH_IN_BYTES 2 -+ -+/* Store the Short term ref pic set calculated values */ -+struct calculated_rps_st_set { -+ u8 num_delta_pocs; -+ u8 num_negative_pics; -+ u8 num_positive_pics; -+ u8 used_by_curr_pic_s0[16]; -+ u8 used_by_curr_pic_s1[16]; -+ s32 delta_poc_s0[16]; -+ s32 delta_poc_s1[16]; -+}; -+ -+enum rkvdec_image_fmt rkvdec_hevc_get_image_fmt(struct rkvdec_ctx *ctx, -+ struct v4l2_ctrl *ctrl) -+{ -+ const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; -+ -+ if (ctrl->id != V4L2_CID_STATELESS_HEVC_SPS) -+ return RKVDEC_IMG_FMT_ANY; -+ -+ if (sps->bit_depth_luma_minus8 == 0) -+ return RKVDEC_IMG_FMT_420_8BIT; -+ else if (sps->bit_depth_luma_minus8 == 2) -+ return RKVDEC_IMG_FMT_420_10BIT; -+ -+ return RKVDEC_IMG_FMT_ANY; -+} -+ -+void compute_tiles_uniform(struct rkvdec_hevc_run *run, u16 log2_min_cb_size, -+ u16 width, u16 height, s32 pic_in_cts_width, -+ s32 pic_in_cts_height, u16 *column_width, u16 *row_height) -+{ -+ const struct v4l2_ctrl_hevc_pps *pps = run->pps; -+ int i; -+ -+ for (i = 0; i < pps->num_tile_columns_minus1 + 1; i++) -+ column_width[i] = ((i + 1) * pic_in_cts_width) / -+ (pps->num_tile_columns_minus1 + 1) - -+ (i * pic_in_cts_width) / -+ (pps->num_tile_columns_minus1 + 1); -+ -+ for (i = 0; i < pps->num_tile_rows_minus1 + 1; i++) -+ row_height[i] = ((i + 1) * pic_in_cts_height) / -+ (pps->num_tile_rows_minus1 + 1) - -+ (i * pic_in_cts_height) / -+ (pps->num_tile_rows_minus1 + 1); -+} -+ -+void compute_tiles_non_uniform(struct rkvdec_hevc_run *run, u16 log2_min_cb_size, -+ u16 width, u16 height, s32 pic_in_cts_width, -+ s32 pic_in_cts_height, u16 *column_width, u16 *row_height) -+{ -+ const struct v4l2_ctrl_hevc_pps *pps = run->pps; -+ s32 sum = 0; -+ int i; -+ -+ for (i = 0; i < pps->num_tile_columns_minus1; i++) { -+ column_width[i] = pps->column_width_minus1[i] + 1; -+ sum += column_width[i]; -+ } -+ column_width[i] = pic_in_cts_width - sum; -+ -+ sum = 0; -+ for (i = 0; i < pps->num_tile_rows_minus1; i++) { -+ row_height[i] = pps->row_height_minus1[i] + 1; -+ sum += row_height[i]; -+ } -+ row_height[i] = pic_in_cts_height - sum; -+} -+ -+static void set_ref_poc(struct rkvdec_rps_short_term_ref_set *set, int poc, int value, int flag) -+{ -+ switch (poc) { -+ case 0: -+ set->delta_poc0 = value; -+ set->used_flag0 = flag; -+ break; -+ case 1: -+ set->delta_poc1 = value; -+ set->used_flag1 = flag; -+ break; -+ case 2: -+ set->delta_poc2 = value; -+ set->used_flag2 = flag; -+ break; -+ case 3: -+ set->delta_poc3 = value; -+ set->used_flag3 = flag; -+ break; -+ case 4: -+ set->delta_poc4 = value; -+ set->used_flag4 = flag; -+ break; -+ case 5: -+ set->delta_poc5 = value; -+ set->used_flag5 = flag; -+ break; -+ case 6: -+ set->delta_poc6 = value; -+ set->used_flag6 = flag; -+ break; -+ case 7: -+ set->delta_poc7 = value; -+ set->used_flag7 = flag; -+ break; -+ case 8: -+ set->delta_poc8 = value; -+ set->used_flag8 = flag; -+ break; -+ case 9: -+ set->delta_poc9 = value; -+ set->used_flag9 = flag; -+ break; -+ case 10: -+ set->delta_poc10 = value; -+ set->used_flag10 = flag; -+ break; -+ case 11: -+ set->delta_poc11 = value; -+ set->used_flag11 = flag; -+ break; -+ case 12: -+ set->delta_poc12 = value; -+ set->used_flag12 = flag; -+ break; -+ case 13: -+ set->delta_poc13 = value; -+ set->used_flag13 = flag; -+ break; -+ case 14: -+ set->delta_poc14 = value; -+ set->used_flag14 = flag; -+ break; -+ } -+} -+ - /* - * Flip one or more matrices along their main diagonal and flatten them - * before writing it to the memory. -@@ -50,13 +187,15 @@ static void transpose_and_flatten_matrices(u8 *output, const u8 *input, - } - } - --static void assemble_scalingfactor0(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input) -+static void assemble_scalingfactor0(struct rkvdec_dev *rkvdec, u8 *output, -+ const struct v4l2_ctrl_hevc_scaling_matrix *input) - { - int offset = 0; - - transpose_and_flatten_matrices(output, (const u8 *)input->scaling_list_4x4, 6, 4); - offset = 6 * 16 * sizeof(u8); -- transpose_and_flatten_matrices(output + offset, (const u8 *)input->scaling_list_8x8, 6, 8); -+ transpose_and_flatten_matrices(output + offset, -+ (const u8 *)input->scaling_list_8x8, 6, 8); - offset += 6 * 64 * sizeof(u8); - transpose_and_flatten_matrices(output + offset, - (const u8 *)input->scaling_list_16x16, 6, 8); -@@ -92,18 +231,19 @@ static void assemble_scalingdc(u8 *output, const struct v4l2_ctrl_hevc_scaling_m - memcpy(output + 6 * sizeof(u8), list_32x32, 6 * sizeof(u8)); - } - --static void translate_scaling_list(struct scaling_factor *output, -+static void translate_scaling_list(struct rkvdec_dev *rkvdec, struct scaling_factor *output, - const struct v4l2_ctrl_hevc_scaling_matrix *input) - { -- assemble_scalingfactor0(output->scalingfactor0, input); -+ assemble_scalingfactor0(rkvdec, output->scalingfactor0, input); - memcpy(output->scalingfactor1, (const u8 *)input->scaling_list_4x4, 96); - assemble_scalingdc(output->scalingdc, input); - memset(output->reserved, 0, 4 * sizeof(u8)); - } - --void assemble_hw_scaling_list(struct rkvdec_hevc_run *run, -- struct scaling_factor *scaling_factor, -- struct v4l2_ctrl_hevc_scaling_matrix *cache) -+void rkvdec_hevc_assemble_hw_scaling_list(struct rkvdec_dev *rkvdec, -+ struct rkvdec_hevc_run *run, -+ struct scaling_factor *scaling_list, -+ struct v4l2_ctrl_hevc_scaling_matrix *cache) - { - const struct v4l2_ctrl_hevc_scaling_matrix *scaling = run->scaling_matrix; - -@@ -111,15 +251,220 @@ void assemble_hw_scaling_list(struct rkvdec_hevc_run *run, - sizeof(struct v4l2_ctrl_hevc_scaling_matrix))) - return; - -- translate_scaling_list(scaling_factor, scaling); -+ translate_scaling_list(rkvdec, scaling_list, scaling); - - memcpy(cache, scaling, - sizeof(struct v4l2_ctrl_hevc_scaling_matrix)); - } - --struct vb2_buffer * --get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run, -- unsigned int dpb_idx) -+static void rkvdec_hevc_assemble_hw_lt_rps(struct rkvdec_hevc_run *run, struct rkvdec_rps *rps) -+{ -+ const struct v4l2_ctrl_hevc_sps *sps = run->sps; -+ -+ if (!run->ext_sps_lt_rps) -+ return; -+ -+ for (int i = 0; i < sps->num_long_term_ref_pics_sps; i++) { -+ rps->refs[i].lt_ref_pic_poc_lsb = -+ run->ext_sps_lt_rps[i].lt_ref_pic_poc_lsb_sps; -+ rps->refs[i].used_by_curr_pic_lt_flag = -+ !!(run->ext_sps_lt_rps[i].flags & V4L2_HEVC_EXT_SPS_LT_RPS_FLAG_USED_LT); -+ } -+} -+ -+static void rkvdec_hevc_assemble_hw_st_rps(struct rkvdec_hevc_run *run, struct rkvdec_rps *rps, -+ struct calculated_rps_st_set *calculated_rps_st_sets) -+{ -+ const struct v4l2_ctrl_hevc_sps *sps = run->sps; -+ -+ for (int i = 0; i < sps->num_short_term_ref_pic_sets; i++) { -+ int poc = 0; -+ int j = 0; -+ const struct calculated_rps_st_set *set = &calculated_rps_st_sets[i]; -+ -+ rps->short_term_ref_sets[i].num_negative = set->num_negative_pics; -+ rps->short_term_ref_sets[i].num_positive = set->num_positive_pics; -+ -+ for (; j < set->num_negative_pics; j++) { -+ set_ref_poc(&rps->short_term_ref_sets[i], j, -+ set->delta_poc_s0[j], set->used_by_curr_pic_s0[j]); -+ } -+ poc = j; -+ -+ for (j = 0; j < set->num_positive_pics; j++) { -+ set_ref_poc(&rps->short_term_ref_sets[i], poc + j, -+ set->delta_poc_s1[j], set->used_by_curr_pic_s1[j]); -+ } -+ } -+} -+ -+/* -+ * Compute the short term ref pic set parameters based on its reference short term ref pic -+ */ -+static void st_ref_pic_set_prediction(struct rkvdec_hevc_run *run, int idx, -+ struct calculated_rps_st_set *calculated_rps_st_sets) -+{ -+ const struct v4l2_ctrl_hevc_ext_sps_st_rps *rps_data = &run->ext_sps_st_rps[idx]; -+ struct calculated_rps_st_set *st_rps = &calculated_rps_st_sets[idx]; -+ struct calculated_rps_st_set *ref_rps; -+ u8 st_rps_idx = idx; -+ u8 ref_rps_idx = 0; -+ s16 delta_rps = 0; -+ u8 use_delta_flag[16] = { 0 }; -+ u8 used_by_curr_pic_flag[16] = { 0 }; -+ int i, j; -+ int dPoc; -+ -+ ref_rps_idx = st_rps_idx - (rps_data->delta_idx_minus1 + 1); /* 7-59 */ -+ delta_rps = (1 - 2 * rps_data->delta_rps_sign) * -+ (rps_data->abs_delta_rps_minus1 + 1); /* 7-60 */ -+ -+ ref_rps = &calculated_rps_st_sets[ref_rps_idx]; -+ -+ for (j = 0; j <= ref_rps->num_delta_pocs; j++) { -+ used_by_curr_pic_flag[j] = !!(rps_data->used_by_curr_pic & (1 << j)); -+ use_delta_flag[j] = !!(rps_data->use_delta_flag & (1 << j)); -+ } -+ -+ /* 7-61: calculate num_negative_pics, delta_poc_s0 and used_by_curr_pic_s0 */ -+ i = 0; -+ for (j = (ref_rps->num_positive_pics - 1); j >= 0; j--) { -+ dPoc = ref_rps->delta_poc_s1[j] + delta_rps; -+ if (dPoc < 0 && use_delta_flag[ref_rps->num_negative_pics + j]) { -+ st_rps->delta_poc_s0[i] = dPoc; -+ st_rps->used_by_curr_pic_s0[i++] = -+ used_by_curr_pic_flag[ref_rps->num_negative_pics + j]; -+ } -+ } -+ if (delta_rps < 0 && use_delta_flag[ref_rps->num_delta_pocs]) { -+ st_rps->delta_poc_s0[i] = delta_rps; -+ st_rps->used_by_curr_pic_s0[i++] = used_by_curr_pic_flag[ref_rps->num_delta_pocs]; -+ } -+ for (j = 0; j < ref_rps->num_negative_pics; j++) { -+ dPoc = ref_rps->delta_poc_s0[j] + delta_rps; -+ if (dPoc < 0 && use_delta_flag[j]) { -+ st_rps->delta_poc_s0[i] = dPoc; -+ st_rps->used_by_curr_pic_s0[i++] = used_by_curr_pic_flag[j]; -+ } -+ } -+ st_rps->num_negative_pics = i; -+ -+ /* 7-62: calculate num_positive_pics, delta_poc_s1 and used_by_curr_pic_s1 */ -+ i = 0; -+ for (j = (ref_rps->num_negative_pics - 1); j >= 0; j--) { -+ dPoc = ref_rps->delta_poc_s0[j] + delta_rps; -+ if (dPoc > 0 && use_delta_flag[j]) { -+ st_rps->delta_poc_s1[i] = dPoc; -+ st_rps->used_by_curr_pic_s1[i++] = used_by_curr_pic_flag[j]; -+ } -+ } -+ if (delta_rps > 0 && use_delta_flag[ref_rps->num_delta_pocs]) { -+ st_rps->delta_poc_s1[i] = delta_rps; -+ st_rps->used_by_curr_pic_s1[i++] = used_by_curr_pic_flag[ref_rps->num_delta_pocs]; -+ } -+ for (j = 0; j < ref_rps->num_positive_pics; j++) { -+ dPoc = ref_rps->delta_poc_s1[j] + delta_rps; -+ if (dPoc > 0 && use_delta_flag[ref_rps->num_negative_pics + j]) { -+ st_rps->delta_poc_s1[i] = dPoc; -+ st_rps->used_by_curr_pic_s1[i++] = -+ used_by_curr_pic_flag[ref_rps->num_negative_pics + j]; -+ } -+ } -+ st_rps->num_positive_pics = i; -+ -+ st_rps->num_delta_pocs = st_rps->num_positive_pics + st_rps->num_negative_pics; -+} -+ -+/* -+ * Compute the short term ref pic set parameters based on the control's data. -+ */ -+static void st_ref_pic_set_calculate(struct rkvdec_hevc_run *run, int idx, -+ struct calculated_rps_st_set *calculated_rps_st_sets) -+{ -+ const struct v4l2_ctrl_hevc_ext_sps_st_rps *rps_data = &run->ext_sps_st_rps[idx]; -+ struct calculated_rps_st_set *st_rps = &calculated_rps_st_sets[idx]; -+ int j, i = 0; -+ -+ /* 7-63 */ -+ st_rps->num_negative_pics = rps_data->num_negative_pics; -+ /* 7-64 */ -+ st_rps->num_positive_pics = rps_data->num_positive_pics; -+ -+ for (i = 0; i < st_rps->num_negative_pics; i++) { -+ /* 7-65 */ -+ st_rps->used_by_curr_pic_s0[i] = !!(rps_data->used_by_curr_pic & (1 << i)); -+ -+ if (i == 0) { -+ /* 7-67 */ -+ st_rps->delta_poc_s0[i] = -(rps_data->delta_poc_s0_minus1[i] + 1); -+ } else { -+ /* 7-69 */ -+ st_rps->delta_poc_s0[i] = -+ st_rps->delta_poc_s0[i - 1] - -+ (rps_data->delta_poc_s0_minus1[i] + 1); -+ } -+ } -+ -+ for (j = 0; j < st_rps->num_positive_pics; j++) { -+ /* 7-66 */ -+ st_rps->used_by_curr_pic_s1[j] = !!(rps_data->used_by_curr_pic & (1 << (i + j))); -+ -+ if (j == 0) { -+ /* 7-68 */ -+ st_rps->delta_poc_s1[j] = rps_data->delta_poc_s1_minus1[j] + 1; -+ } else { -+ /* 7-70 */ -+ st_rps->delta_poc_s1[j] = -+ st_rps->delta_poc_s1[j - 1] + -+ (rps_data->delta_poc_s1_minus1[j] + 1); -+ } -+ } -+ -+ /* 7-71 */ -+ st_rps->num_delta_pocs = st_rps->num_positive_pics + st_rps->num_negative_pics; -+} -+ -+static void rkvdec_hevc_prepare_hw_st_rps(struct rkvdec_hevc_run *run, struct rkvdec_rps *rps, -+ struct v4l2_ctrl_hevc_ext_sps_st_rps *cache) -+{ -+ int idx; -+ -+ if (!run->ext_sps_st_rps) -+ return; -+ -+ if (!memcmp(cache, run->ext_sps_st_rps, sizeof(struct v4l2_ctrl_hevc_ext_sps_st_rps))) -+ return; -+ -+ struct calculated_rps_st_set *calculated_rps_st_sets = -+ kzalloc(sizeof(struct calculated_rps_st_set) * -+ run->sps->num_short_term_ref_pic_sets, GFP_KERNEL); -+ -+ for (idx = 0; idx < run->sps->num_short_term_ref_pic_sets; idx++) { -+ const struct v4l2_ctrl_hevc_ext_sps_st_rps *rps_data = &run->ext_sps_st_rps[idx]; -+ -+ if (rps_data->flags & V4L2_HEVC_EXT_SPS_ST_RPS_FLAG_INTER_REF_PIC_SET_PRED) -+ st_ref_pic_set_prediction(run, idx, calculated_rps_st_sets); -+ else -+ st_ref_pic_set_calculate(run, idx, calculated_rps_st_sets); -+ } -+ -+ rkvdec_hevc_assemble_hw_st_rps(run, rps, calculated_rps_st_sets); -+ -+ kfree(calculated_rps_st_sets); -+ -+ memcpy(cache, run->ext_sps_st_rps, sizeof(struct v4l2_ctrl_hevc_ext_sps_st_rps)); -+} -+ -+void rkvdec_hevc_assemble_hw_rps(struct rkvdec_hevc_run *run, struct rkvdec_rps *rps, -+ struct v4l2_ctrl_hevc_ext_sps_st_rps *st_cache) -+{ -+ rkvdec_hevc_prepare_hw_st_rps(run, rps, st_cache); -+ rkvdec_hevc_assemble_hw_lt_rps(run, rps); -+} -+ -+struct vb2_buffer *get_ref_buf(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run, -+ unsigned int dpb_idx) - { - struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; - const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -@@ -140,9 +485,8 @@ get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run, - return buf; - } - --#define RKVDEC_HEVC_MAX_DEPTH_IN_BYTES 2 -- --int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, struct v4l2_format *f) -+int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, -+ struct v4l2_format *f) - { - struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp; - -@@ -153,40 +497,19 @@ int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, struct v4l2_format *f) - return 0; - } - --enum rkvdec_image_fmt rkvdec_hevc_get_image_fmt(struct rkvdec_ctx *ctx, -- struct v4l2_ctrl *ctrl) --{ -- const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; -- -- if (ctrl->id != V4L2_CID_STATELESS_HEVC_SPS) -- return RKVDEC_IMG_FMT_ANY; -- -- if (sps->bit_depth_luma_minus8 == 0) { -- if (sps->chroma_format_idc == 2) -- return RKVDEC_IMG_FMT_422_8BIT; -- else -- return RKVDEC_IMG_FMT_420_8BIT; -- } else if (sps->bit_depth_luma_minus8 == 2) { -- if (sps->chroma_format_idc == 2) -- return RKVDEC_IMG_FMT_422_10BIT; -- else -- return RKVDEC_IMG_FMT_420_10BIT; -- } -- -- return RKVDEC_IMG_FMT_ANY; --} -- --static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, -+int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, - const struct v4l2_ctrl_hevc_sps *sps) - { -+ /* Only 4:0:0 and 4:2:0 is supported */ - if (sps->chroma_format_idc > 1) -- /* Only 4:0:0 and 4:2:0 are supported */ - return -EINVAL; -+ -+ /* Luma and chroma bit depth mismatch */ - if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) -- /* Luma and chroma bit depth mismatch */ - return -EINVAL; -+ -+ /* Only 8-bit and 10-bit are supported */ - if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) -- /* Only 8-bit and 10-bit is supported */ - return -EINVAL; - - if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width || -@@ -197,7 +520,7 @@ static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, - } - - void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, -- struct rkvdec_hevc_run *run) -+ struct rkvdec_hevc_run *run) - { - struct v4l2_ctrl *ctrl; - -@@ -217,6 +540,12 @@ void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, - ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, - V4L2_CID_STATELESS_HEVC_SCALING_MATRIX); - run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_EXT_SPS_ST_RPS); -+ run->ext_sps_st_rps = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_EXT_SPS_LT_RPS); -+ run->ext_sps_lt_rps = ctrl ? ctrl->p_cur.p : NULL; - - rkvdec_run_preamble(ctx, &run->base); - } -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h -@@ -15,14 +15,68 @@ - * Jeffy Chen - */ - -+#include -+ -+#include "rkvdec.h" -+ -+struct rkvdec_rps_refs { -+ u16 lt_ref_pic_poc_lsb; -+ u16 used_by_curr_pic_lt_flag : 1; -+ u16 reserved : 15; -+} __packed; -+ -+struct rkvdec_rps_short_term_ref_set { -+ u32 num_negative : 4; -+ u32 num_positive : 4; -+ u32 delta_poc0 : 16; -+ u32 used_flag0 : 1; -+ u32 delta_poc1 : 16; -+ u32 used_flag1 : 1; -+ u32 delta_poc2 : 16; -+ u32 used_flag2 : 1; -+ u32 delta_poc3 : 16; -+ u32 used_flag3 : 1; -+ u32 delta_poc4 : 16; -+ u32 used_flag4 : 1; -+ u32 delta_poc5 : 16; -+ u32 used_flag5 : 1; -+ u32 delta_poc6 : 16; -+ u32 used_flag6 : 1; -+ u32 delta_poc7 : 16; -+ u32 used_flag7 : 1; -+ u32 delta_poc8 : 16; -+ u32 used_flag8 : 1; -+ u32 delta_poc9 : 16; -+ u32 used_flag9 : 1; -+ u32 delta_poc10 : 16; -+ u32 used_flag10 : 1; -+ u32 delta_poc11 : 16; -+ u32 used_flag11 : 1; -+ u32 delta_poc12 : 16; -+ u32 used_flag12 : 1; -+ u32 delta_poc13 : 16; -+ u32 used_flag13 : 1; -+ u32 delta_poc14 : 16; -+ u32 used_flag14 : 1; -+ u32 reserved_bits : 25; -+ u32 reserved[3]; -+} __packed; -+ -+struct rkvdec_rps { -+ struct rkvdec_rps_refs refs[32]; -+ struct rkvdec_rps_short_term_ref_set short_term_ref_sets[64]; -+} __packed; -+ - struct rkvdec_hevc_run { -- struct rkvdec_run base; -- const struct v4l2_ctrl_hevc_slice_params *slices_params; -- const struct v4l2_ctrl_hevc_decode_params *decode_params; -- const struct v4l2_ctrl_hevc_sps *sps; -- const struct v4l2_ctrl_hevc_pps *pps; -- const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; -- int num_slices; -+ struct rkvdec_run base; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params; -+ const struct v4l2_ctrl_hevc_slice_params *slices_params; -+ const struct v4l2_ctrl_hevc_sps *sps; -+ const struct v4l2_ctrl_hevc_pps *pps; -+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; -+ const struct v4l2_ctrl_hevc_ext_sps_st_rps *ext_sps_st_rps; -+ const struct v4l2_ctrl_hevc_ext_sps_lt_rps *ext_sps_lt_rps; -+ int num_slices; - }; - - struct scaling_factor { -@@ -32,15 +86,27 @@ struct scaling_factor { - u8 reserved[4]; /*16Bytes align*/ - }; - -+#define RKV_HEVC_CABAC_TABLE_SIZE 27456 -+extern const u8 rkvdec_hevc_cabac_table[RKV_HEVC_CABAC_TABLE_SIZE]; -+ - enum rkvdec_image_fmt rkvdec_hevc_get_image_fmt(struct rkvdec_ctx *ctx, - struct v4l2_ctrl *ctrl); --void rkvdec_hevc_assemble_hw_scaling_list(struct rkvdec_hevc_run *run, -+void compute_tiles_uniform(struct rkvdec_hevc_run *run, u16 log2_min_cb_size, -+ u16 width, u16 height, s32 pic_in_cts_width, -+ s32 pic_in_cts_height, u16 *column_width, u16 *row_height); -+void compute_tiles_non_uniform(struct rkvdec_hevc_run *run, u16 log2_min_cb_size, -+ u16 width, u16 height, s32 pic_in_cts_width, -+ s32 pic_in_cts_height, u16 *column_width, u16 *row_height); -+void rkvdec_hevc_assemble_hw_rps(struct rkvdec_hevc_run *run, struct rkvdec_rps *rps, -+ struct v4l2_ctrl_hevc_ext_sps_st_rps *st_cache); -+void rkvdec_hevc_assemble_hw_scaling_list(struct rkvdec_dev *rkvdec, -+ struct rkvdec_hevc_run *run, - struct scaling_factor *scaling_factor, - struct v4l2_ctrl_hevc_scaling_matrix *cache); - struct vb2_buffer *get_ref_buf(struct rkvdec_ctx *ctx, - struct rkvdec_hevc_run *run, - unsigned int dpb_idx); - int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, struct v4l2_format *f); --//int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, const struct v4l2_ctrl_hevc_sps *sps); -+int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, const struct v4l2_ctrl_hevc_sps *sps); - int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl); - void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run); -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c -@@ -25,9 +25,6 @@ - #define RKV_RPS_SIZE (32 / 4) - #define RKV_RPS_LEN 600 - --#define RKV_HEVC_CABAC_TABLE_SIZE 27456 --extern const u8 rkvdec_hevc_cabac_table[RKV_HEVC_CABAC_TABLE_SIZE]; -- - struct rkvdec_sps_pps_packet { - u32 info[RKV_PPS_SIZE]; - }; -@@ -550,7 +547,7 @@ static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) - - rkvdec_hevc_run_preamble(ctx, &run); - -- rkvdec_hevc_assemble_hw_scaling_list(&run, &tbl->scaling_list, -+ rkvdec_hevc_assemble_hw_scaling_list(rkvdec, &run, &tbl->scaling_list, - &hevc_ctx->scaling_matrix_cache); - assemble_hw_pps(ctx, &run); - assemble_hw_rps(ctx, &run); -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c -@@ -0,0 +1,588 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Rockchip VDPU381 HEVC backend -+ * -+ * Copyright (C) 2025 Collabora, Ltd. -+ * Detlev Casanova -+ */ -+ -+#include -+ -+#include "rkvdec.h" -+#include "rkvdec-rcb.h" -+#include "rkvdec-hevc-common.h" -+#include "rkvdec-vdpu381-regs.h" -+ -+// SPS -+struct rkvdec_hevc_sps { -+ u16 video_parameters_set_id : 4; -+ u16 seq_parameters_set_id_sps : 4; -+ u16 chroma_format_idc : 2; -+ u16 width : 16; -+ u16 height : 16; -+ u16 bit_depth_luma : 4; -+ u16 bit_depth_chroma : 4; -+ u16 max_pic_order_count_lsb : 5; -+ u16 diff_max_min_luma_coding_block_size : 2; -+ u16 min_luma_coding_block_size : 3; -+ u16 min_transform_block_size : 3; -+ u16 diff_max_min_transform_block_size : 2; -+ u16 max_transform_hierarchy_depth_inter : 3; -+ u16 max_transform_hierarchy_depth_intra : 3; -+ u16 scaling_list_enabled_flag : 1; -+ u16 amp_enabled_flag : 1; -+ u16 sample_adaptive_offset_enabled_flag : 1; -+ u16 pcm_enabled_flag : 1; -+ u16 pcm_sample_bit_depth_luma : 4; -+ u16 pcm_sample_bit_depth_chroma : 4; -+ u16 pcm_loop_filter_disabled_flag : 1; -+ u16 diff_max_min_pcm_luma_coding_block_size : 3; -+ u16 min_pcm_luma_coding_block_size : 3; -+ u16 num_short_term_ref_pic_sets : 7; -+ u16 long_term_ref_pics_present_flag : 1; -+ u16 num_long_term_ref_pics_sps : 6; -+ u16 sps_temporal_mvp_enabled_flag : 1; -+ u16 strong_intra_smoothing_enabled_flag : 1; -+ u16 reserved_0 : 7; -+ u16 sps_max_dec_pic_buffering_minus1 : 4; -+ u16 reserved_0_2 : 3; -+ u16 reserved_f : 8; -+} __packed; -+ -+//PPS -+struct rkvdec_hevc_pps { -+ u16 picture_parameters_set_id : 6; -+ u16 seq_parameters_set_id_pps : 4; -+ u16 dependent_slice_segments_enabled_flag : 1; -+ u16 output_flag_present_flag : 1; -+ u16 num_extra_slice_header_bits : 13; -+ u16 sign_data_hiding_enabled_flag : 1; -+ u16 cabac_init_present_flag : 1; -+ u16 num_ref_idx_l0_default_active : 4; -+ u16 num_ref_idx_l1_default_active : 4; -+ u16 init_qp_minus26 : 7; -+ u16 constrained_intra_pred_flag : 1; -+ u16 transform_skip_enabled_flag : 1; -+ u16 cu_qp_delta_enabled_flag : 1; -+ u16 log2_min_cb_size : 3; -+ u16 pps_cb_qp_offset : 5; -+ u16 pps_cr_qp_offset : 5; -+ u16 pps_slice_chroma_qp_offsets_present_flag : 1; -+ u16 weighted_pred_flag : 1; -+ u16 weighted_bipred_flag : 1; -+ u16 transquant_bypass_enabled_flag : 1; -+ u16 tiles_enabled_flag : 1; -+ u16 entropy_coding_sync_enabled_flag : 1; -+ u16 pps_loop_filter_across_slices_enabled_flag : 1; -+ u16 loop_filter_across_tiles_enabled_flag : 1; -+ u16 deblocking_filter_override_enabled_flag : 1; -+ u16 pps_deblocking_filter_disabled_flag : 1; -+ u16 pps_beta_offset_div2 : 4; -+ u16 pps_tc_offset_div2 : 4; -+ u16 lists_modification_present_flag : 1; -+ u16 log2_parallel_merge_level : 3; -+ u16 slice_segment_header_extension_present_flag : 1; -+ u16 zeroes : 3; -+ u16 num_tile_columns : 5; -+ u16 num_tile_rows : 5; -+ u16 sps_pps_mode : 4; -+ u16 reserved_bits : 14; -+ u16 reserved; -+} __packed; -+ -+struct rkvdec_hevc_tile { -+ u16 value0 : 12; -+ u16 value1 : 12; -+} __packed; -+ -+struct rkvdec_sps_pps_packet { -+ struct rkvdec_hevc_sps sps; -+ struct rkvdec_hevc_pps pps; -+ struct rkvdec_hevc_tile column_width[10]; -+ struct rkvdec_hevc_tile row_height[11]; -+ u32 zeroes[3]; -+ u32 zeroes_bits : 6; -+ u32 padding_bits : 2; -+ u32 padding; -+} __packed; -+ -+struct rkvdec_hevc_priv_tbl { -+ struct rkvdec_sps_pps_packet param_set[64]; -+ struct rkvdec_rps rps; -+ struct scaling_factor scaling_list; -+ u8 cabac_table[27456]; -+}; -+ -+struct rkvdec_hevc_ctx { -+ struct rkvdec_aux_buf priv_tbl; -+ struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache; -+ struct v4l2_ctrl_hevc_ext_sps_st_rps st_cache; -+ struct rkvdec_vdpu381_regs_hevc regs; -+}; -+ -+static void assemble_hw_pps(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ struct rkvdec_hevc_ctx *h264_ctx = ctx->priv; -+ const struct v4l2_ctrl_hevc_sps *sps = run->sps; -+ const struct v4l2_ctrl_hevc_pps *pps = run->pps; -+ struct rkvdec_hevc_priv_tbl *priv_tbl = h264_ctx->priv_tbl.cpu; -+ struct rkvdec_sps_pps_packet *hw_ps; -+ bool tiles_enabled; -+ s32 max_cu_width; -+ s32 pic_in_cts_width; -+ s32 pic_in_cts_height; -+ u16 log2_min_cb_size, width, height; -+ u16 column_width[20]; -+ u16 row_height[22]; -+ u8 pcm_enabled; -+ u32 i; -+ -+ /* -+ * HW read the SPS/PPS information from PPS packet index by PPS id. -+ * offset from the base can be calculated by PPS_id * 32 (size per PPS -+ * packet unit). so the driver copy SPS/PPS information to the exact PPS -+ * packet unit for HW accessing. -+ */ -+ hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id]; -+ memset(hw_ps, 0, sizeof(*hw_ps)); -+ -+ /* write sps */ -+ hw_ps->sps.video_parameters_set_id = sps->video_parameter_set_id; -+ hw_ps->sps.seq_parameters_set_id_sps = sps->seq_parameter_set_id; -+ hw_ps->sps.chroma_format_idc = sps->chroma_format_idc; -+ -+ log2_min_cb_size = sps->log2_min_luma_coding_block_size_minus3 + 3; -+ width = sps->pic_width_in_luma_samples; -+ height = sps->pic_height_in_luma_samples; -+ hw_ps->sps.width = width; -+ hw_ps->sps.height = height; -+ hw_ps->sps.bit_depth_luma = sps->bit_depth_luma_minus8 + 8; -+ hw_ps->sps.bit_depth_chroma = sps->bit_depth_chroma_minus8 + 8; -+ hw_ps->sps.max_pic_order_count_lsb = sps->log2_max_pic_order_cnt_lsb_minus4 + 4; -+ hw_ps->sps.diff_max_min_luma_coding_block_size = -+ sps->log2_diff_max_min_luma_coding_block_size; -+ hw_ps->sps.min_luma_coding_block_size = sps->log2_min_luma_coding_block_size_minus3 + 3; -+ hw_ps->sps.min_transform_block_size = sps->log2_min_luma_transform_block_size_minus2 + 2; -+ hw_ps->sps.diff_max_min_transform_block_size = -+ sps->log2_diff_max_min_luma_transform_block_size; -+ hw_ps->sps.max_transform_hierarchy_depth_inter = sps->max_transform_hierarchy_depth_inter; -+ hw_ps->sps.max_transform_hierarchy_depth_intra = sps->max_transform_hierarchy_depth_intra; -+ hw_ps->sps.scaling_list_enabled_flag = -+ !!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED); -+ hw_ps->sps.amp_enabled_flag = !!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED); -+ hw_ps->sps.sample_adaptive_offset_enabled_flag = -+ !!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET); -+ -+ pcm_enabled = !!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED); -+ hw_ps->sps.pcm_enabled_flag = pcm_enabled; -+ hw_ps->sps.pcm_sample_bit_depth_luma = -+ pcm_enabled ? sps->pcm_sample_bit_depth_luma_minus1 + 1 : 0; -+ hw_ps->sps.pcm_sample_bit_depth_chroma = -+ pcm_enabled ? sps->pcm_sample_bit_depth_chroma_minus1 + 1 : 0; -+ hw_ps->sps.pcm_loop_filter_disabled_flag = -+ !!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED); -+ hw_ps->sps.diff_max_min_pcm_luma_coding_block_size = -+ sps->log2_diff_max_min_pcm_luma_coding_block_size; -+ hw_ps->sps.min_pcm_luma_coding_block_size = -+ pcm_enabled ? sps->log2_min_pcm_luma_coding_block_size_minus3 + 3 : 0; -+ hw_ps->sps.num_short_term_ref_pic_sets = sps->num_short_term_ref_pic_sets; -+ hw_ps->sps.long_term_ref_pics_present_flag = -+ !!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT); -+ hw_ps->sps.num_long_term_ref_pics_sps = sps->num_long_term_ref_pics_sps; -+ hw_ps->sps.sps_temporal_mvp_enabled_flag = -+ !!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED); -+ hw_ps->sps.strong_intra_smoothing_enabled_flag = -+ !!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED); -+ hw_ps->sps.sps_max_dec_pic_buffering_minus1 = sps->sps_max_dec_pic_buffering_minus1; -+ hw_ps->sps.reserved_f = 0xff; -+ -+ /* write pps */ -+ hw_ps->pps.picture_parameters_set_id = pps->pic_parameter_set_id; -+ hw_ps->pps.seq_parameters_set_id_pps = sps->seq_parameter_set_id; -+ hw_ps->pps.dependent_slice_segments_enabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED); -+ hw_ps->pps.output_flag_present_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT); -+ hw_ps->pps.num_extra_slice_header_bits = pps->num_extra_slice_header_bits; -+ hw_ps->pps.sign_data_hiding_enabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED); -+ hw_ps->pps.cabac_init_present_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT); -+ hw_ps->pps.num_ref_idx_l0_default_active = pps->num_ref_idx_l0_default_active_minus1 + 1; -+ hw_ps->pps.num_ref_idx_l1_default_active = pps->num_ref_idx_l1_default_active_minus1 + 1; -+ hw_ps->pps.init_qp_minus26 = pps->init_qp_minus26; -+ hw_ps->pps.constrained_intra_pred_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED); -+ hw_ps->pps.transform_skip_enabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED); -+ hw_ps->pps.cu_qp_delta_enabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED); -+ hw_ps->pps.log2_min_cb_size = log2_min_cb_size + -+ sps->log2_diff_max_min_luma_coding_block_size - -+ pps->diff_cu_qp_delta_depth; -+ hw_ps->pps.pps_cb_qp_offset = pps->pps_cb_qp_offset; -+ hw_ps->pps.pps_cr_qp_offset = pps->pps_cr_qp_offset; -+ hw_ps->pps.pps_slice_chroma_qp_offsets_present_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT); -+ hw_ps->pps.weighted_pred_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED); -+ hw_ps->pps.weighted_bipred_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED); -+ hw_ps->pps.transquant_bypass_enabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED); -+ -+ tiles_enabled = !!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED); -+ hw_ps->pps.tiles_enabled_flag = tiles_enabled; -+ hw_ps->pps.entropy_coding_sync_enabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED); -+ hw_ps->pps.pps_loop_filter_across_slices_enabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED); -+ hw_ps->pps.loop_filter_across_tiles_enabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED); -+ hw_ps->pps.deblocking_filter_override_enabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED); -+ hw_ps->pps.pps_deblocking_filter_disabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER); -+ hw_ps->pps.pps_beta_offset_div2 = pps->pps_beta_offset_div2; -+ hw_ps->pps.pps_tc_offset_div2 = pps->pps_tc_offset_div2; -+ hw_ps->pps.lists_modification_present_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT); -+ hw_ps->pps.log2_parallel_merge_level = pps->log2_parallel_merge_level_minus2 + 2; -+ hw_ps->pps.slice_segment_header_extension_present_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT); -+ hw_ps->pps.num_tile_columns = tiles_enabled ? pps->num_tile_columns_minus1 + 1 : 0; -+ hw_ps->pps.num_tile_rows = tiles_enabled ? pps->num_tile_rows_minus1 + 1 : 0; -+ hw_ps->pps.sps_pps_mode = 0; -+ hw_ps->pps.reserved_bits = 0x3fff; -+ hw_ps->pps.reserved = 0xffff; -+ -+ // Setup tiles information -+ memset(column_width, 0, sizeof(column_width)); -+ memset(row_height, 0, sizeof(row_height)); -+ -+ max_cu_width = 1 << (sps->log2_diff_max_min_luma_coding_block_size + log2_min_cb_size); -+ pic_in_cts_width = (width + max_cu_width - 1) / max_cu_width; -+ pic_in_cts_height = (height + max_cu_width - 1) / max_cu_width; -+ -+ if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) { -+ if (pps->flags & V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING) { -+ compute_tiles_uniform(run, log2_min_cb_size, width, height, -+ pic_in_cts_width, pic_in_cts_height, -+ column_width, row_height); -+ } else { -+ compute_tiles_non_uniform(run, log2_min_cb_size, width, height, -+ pic_in_cts_width, pic_in_cts_height, -+ column_width, row_height); -+ } -+ } else { -+ column_width[0] = (width + max_cu_width - 1) / max_cu_width; -+ row_height[0] = (height + max_cu_width - 1) / max_cu_width; -+ } -+ -+ for (i = 0; i < 20; i++) { -+ if (column_width[i] > 0) -+ column_width[i]--; -+ -+ if (i & 1) -+ hw_ps->column_width[i / 2].value1 = column_width[i]; -+ else -+ hw_ps->column_width[i / 2].value0 = column_width[i]; -+ } -+ -+ for (i = 0; i < 22; i++) { -+ if (row_height[i] > 0) -+ row_height[i]--; -+ -+ if (i & 1) -+ hw_ps->row_height[i / 2].value1 = row_height[i]; -+ else -+ hw_ps->row_height[i / 2].value0 = row_height[i]; -+ } -+ -+ hw_ps->padding = 0xffffffff; -+ hw_ps->padding_bits = 0x3; -+} -+ -+static void set_ref_valid(struct rkvdec_vdpu381_regs_hevc *regs, int id, u32 valid) -+{ -+ switch (id) { -+ case 0: -+ regs->hevc_param.reg099.hevc_ref_valid_0 = valid; -+ break; -+ case 1: -+ regs->hevc_param.reg099.hevc_ref_valid_1 = valid; -+ break; -+ case 2: -+ regs->hevc_param.reg099.hevc_ref_valid_2 = valid; -+ break; -+ case 3: -+ regs->hevc_param.reg099.hevc_ref_valid_3 = valid; -+ break; -+ case 4: -+ regs->hevc_param.reg099.hevc_ref_valid_4 = valid; -+ break; -+ case 5: -+ regs->hevc_param.reg099.hevc_ref_valid_5 = valid; -+ break; -+ case 6: -+ regs->hevc_param.reg099.hevc_ref_valid_6 = valid; -+ break; -+ case 7: -+ regs->hevc_param.reg099.hevc_ref_valid_7 = valid; -+ break; -+ case 8: -+ regs->hevc_param.reg099.hevc_ref_valid_8 = valid; -+ break; -+ case 9: -+ regs->hevc_param.reg099.hevc_ref_valid_9 = valid; -+ break; -+ case 10: -+ regs->hevc_param.reg099.hevc_ref_valid_10 = valid; -+ break; -+ case 11: -+ regs->hevc_param.reg099.hevc_ref_valid_11 = valid; -+ break; -+ case 12: -+ regs->hevc_param.reg099.hevc_ref_valid_12 = valid; -+ break; -+ case 13: -+ regs->hevc_param.reg099.hevc_ref_valid_13 = valid; -+ break; -+ case 14: -+ regs->hevc_param.reg099.hevc_ref_valid_14 = valid; -+ break; -+ } -+} -+ -+static void rkvdec_write_regs(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ -+ rkvdec_memcpy_toio(rkvdec->regs + OFFSET_COMMON_REGS, -+ &hevc_ctx->regs.common, -+ sizeof(hevc_ctx->regs.common)); -+ rkvdec_memcpy_toio(rkvdec->regs + OFFSET_CODEC_PARAMS_REGS, -+ &hevc_ctx->regs.hevc_param, -+ sizeof(hevc_ctx->regs.hevc_param)); -+ rkvdec_memcpy_toio(rkvdec->regs + OFFSET_COMMON_ADDR_REGS, -+ &hevc_ctx->regs.common_addr, -+ sizeof(hevc_ctx->regs.common_addr)); -+ rkvdec_memcpy_toio(rkvdec->regs + OFFSET_CODEC_ADDR_REGS, -+ &hevc_ctx->regs.hevc_addr, -+ sizeof(hevc_ctx->regs.hevc_addr)); -+ rkvdec_memcpy_toio(rkvdec->regs + OFFSET_POC_HIGHBIT_REGS, -+ &hevc_ctx->regs.hevc_highpoc, -+ sizeof(hevc_ctx->regs.hevc_highpoc)); -+} -+ -+static void config_registers(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ const struct v4l2_ctrl_hevc_decode_params *dec_params = run->decode_params; -+ const struct v4l2_hevc_dpb_entry *dpb = dec_params->dpb; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_vdpu381_regs_hevc *regs = &hevc_ctx->regs; -+ dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma; -+ const struct v4l2_pix_format_mplane *dst_fmt; -+ struct vb2_v4l2_buffer *src_buf = run->base.bufs.src; -+ struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst; -+ const struct v4l2_format *f; -+ dma_addr_t rlc_addr; -+ u32 hor_virstride = 0; -+ u32 ver_virstride = 0; -+ u32 y_virstride = 0; -+ u32 offset; -+ u32 pixels; -+ dma_addr_t dst_addr; -+ u32 i; -+ -+ memset(regs, 0, sizeof(*regs)); -+ -+ /* Set HEVC mode */ -+ regs->common.reg009.dec_mode = VDPU381_MODE_HEVC; -+ -+ /* Set config */ -+ regs->common.reg011.buf_empty_en = 1; -+ regs->common.reg011.dec_clkgate_e = 1; -+ regs->common.reg011.dec_timeout_e = 1; -+ regs->common.reg011.pix_range_detection_e = 1; -+ -+ /* Set IDR flag */ -+ regs->common.reg013.cur_pic_is_idr = -+ !!(dec_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC); -+ -+ /* Set input stream length */ -+ regs->common.stream_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0); -+ -+ /* Set max slice number */ -+ regs->common.reg017.slice_num = 1; -+ -+ /* Set strides */ -+ f = &ctx->decoded_fmt; -+ dst_fmt = &f->fmt.pix_mp; -+ hor_virstride = dst_fmt->plane_fmt[0].bytesperline; -+ ver_virstride = dst_fmt->height; -+ y_virstride = hor_virstride * ver_virstride; -+ pixels = dst_fmt->height * dst_fmt->width; -+ -+ regs->common.reg018.y_hor_virstride = hor_virstride / 16; -+ regs->common.reg019.uv_hor_virstride = hor_virstride / 16; -+ regs->common.reg020.y_virstride = y_virstride / 16; -+ -+ /* Activate block gating */ -+ regs->common.reg026.swreg_block_gating_e = 0xfffef; -+ regs->common.reg026.reg_cfg_gating_en = 1; -+ -+ /* Set timeout threshold */ -+ if (pixels < RKVDEC_1080P_PIXELS) -+ regs->common.timeout_threshold = RKVDEC_TIMEOUT_1080p; -+ else if (pixels < RKVDEC_4K_PIXELS) -+ regs->common.timeout_threshold = RKVDEC_TIMEOUT_4K; -+ else if (pixels < RKVDEC_8K_PIXELS) -+ regs->common.timeout_threshold = RKVDEC_TIMEOUT_8K; -+ -+ /* Set POC val */ -+ regs->hevc_param.cur_top_poc = dec_params->pic_order_cnt_val; -+ -+ /* Set ref pic address & poc */ -+ for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) { -+ struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i); -+ dma_addr_t buf_dma = vb2_dma_contig_plane_dma_addr(vb_buf, 0); -+ u32 valid = !!(dec_params->num_active_dpb_entries > i); -+ -+ /* Set reference addresses */ -+ regs->hevc_addr.ref_base[i] = buf_dma; -+ -+ /* Set COLMV addresses */ -+ regs->hevc_addr.colmv_base[i] = buf_dma + ctx->colmv_offset; -+ -+ regs->hevc_param.reg067_082_ref_poc[i] = -+ dpb[i].pic_order_cnt_val; -+ -+ set_ref_valid(regs, i, valid); -+ regs->hevc_param.reg103.ref_pic_layer_same_with_cur |= 1 << i; -+ } -+ -+ /* Set rlc base address (input stream) */ -+ rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); -+ regs->common_addr.rlc_base = rlc_addr; -+ regs->common_addr.rlcwrite_base = rlc_addr; -+ -+ /* Set output base address */ -+ dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); -+ regs->common_addr.decout_base = dst_addr; -+ regs->common_addr.error_ref_base = dst_addr; -+ -+ /* Set colmv address */ -+ regs->common_addr.colmv_cur_base = dst_addr + ctx->colmv_offset; -+ -+ /* Set RCB addresses */ -+ for (i = 0; i < rkvdec_rcb_buf_count(ctx); i++) -+ regs->common_addr.rcb_base[i] = rkvdec_rcb_buf_dma_addr(ctx, i); -+ -+ /* Set hw pps address */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set); -+ regs->hevc_addr.pps_base = priv_start_addr + offset; -+ -+ /* Set hw rps address */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, rps); -+ regs->hevc_addr.rps_base = priv_start_addr + offset; -+ -+ /* Set cabac table */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table); -+ regs->hevc_addr.cabactbl_base = priv_start_addr + offset; -+ -+ /* Set scaling matrix */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list); -+ regs->hevc_addr.scanlist_addr = priv_start_addr + offset; -+ -+ rkvdec_write_regs(ctx); -+} -+ -+static int rkvdec_hevc_start(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_hevc_priv_tbl *priv_tbl; -+ struct rkvdec_hevc_ctx *hevc_ctx; -+ struct v4l2_ctrl *ctrl; -+ int ret; -+ -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SPS); -+ if (!ctrl) -+ return -EINVAL; -+ -+ ret = rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); -+ if (ret) -+ return ret; -+ -+ hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL); -+ if (!hevc_ctx) -+ return -ENOMEM; -+ -+ priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl), -+ &hevc_ctx->priv_tbl.dma, GFP_KERNEL); -+ if (!priv_tbl) { -+ ret = -ENOMEM; -+ goto err_free_ctx; -+ } -+ -+ hevc_ctx->priv_tbl.size = sizeof(*priv_tbl); -+ hevc_ctx->priv_tbl.cpu = priv_tbl; -+ memcpy(priv_tbl->cabac_table, rkvdec_hevc_cabac_table, -+ sizeof(rkvdec_hevc_cabac_table)); -+ -+ ctx->priv = hevc_ctx; -+ return 0; -+ -+err_free_ctx: -+ kfree(hevc_ctx); -+ return ret; -+} -+ -+static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ -+ dma_free_coherent(rkvdec->dev, hevc_ctx->priv_tbl.size, -+ hevc_ctx->priv_tbl.cpu, hevc_ctx->priv_tbl.dma); -+ kfree(hevc_ctx); -+} -+ -+static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_hevc_run run; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu; -+ -+ rkvdec_hevc_run_preamble(ctx, &run); -+ -+ rkvdec_hevc_assemble_hw_scaling_list(rkvdec, -+ &run, -+ &tbl->scaling_list, -+ &hevc_ctx->scaling_matrix_cache); -+ assemble_hw_pps(ctx, &run); -+ rkvdec_hevc_assemble_hw_rps(&run, &tbl->rps, &hevc_ctx->st_cache); -+ -+ config_registers(ctx, &run); -+ -+ rkvdec_run_postamble(ctx, &run.base); -+ -+ schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000)); -+ -+ /* Start decoding! */ -+ writel(VDPU381_DEC_E_BIT, rkvdec->regs + VDPU381_REG_DEC_E); -+ -+ return 0; -+} -+ -+const struct rkvdec_coded_fmt_ops rkvdec_vdpu381_hevc_fmt_ops = { -+ .adjust_fmt = rkvdec_hevc_adjust_fmt, -+ .start = rkvdec_hevc_start, -+ .stop = rkvdec_hevc_stop, -+ .run = rkvdec_hevc_run, -+ .try_ctrl = rkvdec_hevc_try_ctrl, -+ .get_image_fmt = rkvdec_hevc_get_image_fmt, -+}; diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c new file mode 100644 index 000000000000..111111111111 --- /dev/null +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c -@@ -0,0 +1,582 @@ +@@ -0,0 +1,578 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip Video Decoder VDPU383 H264 backend @@ -11739,11 +7168,11 @@ index 000000000000..111111111111 + regs->common.reg010.err_prc_auto_gating_e = 1; + + /* Set timeout threshold */ -+ if (pixels < VDPU383_1080P_PIXELS) ++ if (pixels < RKVDEC_1080P_PIXELS) + regs->common.reg013_core_timeout_threshold = VDPU383_TIMEOUT_1080p; -+ else if (pixels < VDPU383_4K_PIXELS) ++ else if (pixels < RKVDEC_4K_PIXELS) + regs->common.reg013_core_timeout_threshold = VDPU383_TIMEOUT_4K; -+ else if (pixels < VDPU383_8K_PIXELS) ++ else if (pixels < RKVDEC_8K_PIXELS) + regs->common.reg013_core_timeout_threshold = VDPU383_TIMEOUT_8K; + else + regs->common.reg013_core_timeout_threshold = VDPU383_TIMEOUT_MAX; @@ -11824,10 +7253,6 @@ index 000000000000..111111111111 + if (!ctrl) + return -EINVAL; + -+ ret = rkvdec_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps); -+ if (ret) -+ return ret; -+ + h264_ctx = kzalloc(sizeof(*h264_ctx), GFP_KERNEL); + if (!h264_ctx) + return -ENOMEM; @@ -11932,7 +7357,7 @@ new file mode 100644 index 000000000000..111111111111 --- /dev/null +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-regs.h -@@ -0,0 +1,284 @@ +@@ -0,0 +1,281 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Rockchip Video Decoder VDPU383 driver registers description @@ -11955,9 +7380,6 @@ index 000000000000..111111111111 +#define VDPU383_MODE_HEVC 0 +#define VDPU383_MODE_H264 1 + -+#define VDPU383_1080P_PIXELS (1920 * 1080) -+#define VDPU383_4K_PIXELS (4096 * 2304) -+#define VDPU383_8K_PIXELS (7680 * 4320) +#define VDPU383_TIMEOUT_1080p (0xffffff) +#define VDPU383_TIMEOUT_4K (0x2cfffff) +#define VDPU383_TIMEOUT_8K (0x4ffffff) @@ -12237,8 +7659,8 @@ index 111111111111..222222222222 100644 #include "rkvdec-rcb.h" static bool rkvdec_image_fmt_match(enum rkvdec_image_fmt fmt1, -@@ -121,6 +123,16 @@ static int vdpu38x_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pix_mp, u32 pix - return 0; +@@ -86,17 +88,26 @@ static bool rkvdec_is_valid_fmt(struct rkvdec_ctx *ctx, u32 fourcc, + return false; } +static u32 rkvdec_colmv_size(u16 width, u16 height) @@ -12246,7 +7668,7 @@ index 111111111111..222222222222 100644 + return 128 * DIV_ROUND_UP(width, 16) * DIV_ROUND_UP(height, 16); +} + -+static u32 rkvdec_vdpu383_colmv_size(u16 width, u16 height) ++static u32 vdpu383_colmv_size(u16 width, u16 height) +{ + return ALIGN(width, 64) * ALIGN(height, 16); +} @@ -12254,37 +7676,1321 @@ index 111111111111..222222222222 100644 static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, struct v4l2_pix_format_mplane *pix_mp) { -@@ -130,9 +142,7 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, +- v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, +- pix_mp->width, pix_mp->height); ++ const struct rkvdec_variant *variant = ctx->dev->variant; ++ ++ v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, pix_mp->width, pix_mp->height); ctx->colmv_offset = pix_mp->plane_fmt[0].sizeimage; - pix_mp->plane_fmt[0].sizeimage += 128 * - DIV_ROUND_UP(pix_mp->width, 16) * - DIV_ROUND_UP(pix_mp->height, 16); -+ pix_mp->plane_fmt[0].sizeimage += cfg->colmv_size(pix_mp->width, pix_mp->height); ++ pix_mp->plane_fmt[0].sizeimage += variant->ops->colmv_size(pix_mp->width, pix_mp->height); } static void rkvdec_reset_fmt(struct rkvdec_ctx *ctx, struct v4l2_format *f, -@@ -251,17 +261,6 @@ static const struct rkvdec_ctrls rkvdec_hevc_ctrls = { - .num_ctrls = ARRAY_SIZE(rkvdec_hevc_ctrl_descs), +@@ -405,6 +416,25 @@ static const struct rkvdec_coded_fmt_desc vdpu381_coded_fmts[] = { + }, }; --static const struct rkvdec_decoded_fmt_desc rkvdec_hevc_decoded_fmts[] = { -- { -- .fourcc = V4L2_PIX_FMT_NV12, -- .image_fmt = RKVDEC_IMG_FMT_420_8BIT, -- }, -- { -- .fourcc = V4L2_PIX_FMT_NV15, -- .image_fmt = RKVDEC_IMG_FMT_420_10BIT, -- }, --}; -- - static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { ++static const struct rkvdec_coded_fmt_desc vdpu383_coded_fmts[] = { ++ { ++ .fourcc = V4L2_PIX_FMT_H264_SLICE, ++ .frmsize = { ++ .min_width = 64, ++ .max_width = 65520, ++ .step_width = 64, ++ .min_height = 64, ++ .max_height = 65520, ++ .step_height = 16, ++ }, ++ .ctrls = &rkvdec_h264_ctrls, ++ .ops = &rkvdec_vdpu383_h264_fmt_ops, ++ .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), ++ .decoded_fmts = rkvdec_h264_decoded_fmts, ++ .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, ++ }, ++}; ++ + static const struct rkvdec_coded_fmt_desc * + rkvdec_enum_coded_fmt_desc(struct rkvdec_ctx *ctx, int index) + { +@@ -1297,6 +1327,35 @@ static irqreturn_t vdpu381_irq_handler(struct rkvdec_ctx *ctx) + return IRQ_HANDLED; + } + ++static irqreturn_t vdpu383_irq_handler(struct rkvdec_ctx *ctx) ++{ ++ struct rkvdec_dev *rkvdec = ctx->dev; ++ enum vb2_buffer_state state; ++ bool need_reset = 0; ++ u32 status; ++ ++ status = readl(rkvdec->link + VDPU383_LINK_STA_INT); ++ writel(FIELD_PREP_WM16(VDPU383_STA_INT_ALL, 0), rkvdec->link + VDPU383_LINK_STA_INT); ++ /* On vdpu383, the interrupts must be disabled */ ++ writel(FIELD_PREP_WM16(VDPU383_INT_EN_IRQ | VDPU383_INT_EN_LINE_IRQ, 0), ++ rkvdec->link + VDPU383_LINK_INT_EN); ++ ++ if (status & VDPU383_STA_INT_DEC_RDY_STA) { ++ state = VB2_BUF_STATE_DONE; ++ } else { ++ state = VB2_BUF_STATE_ERROR; ++ rkvdec_iommu_restore(rkvdec); ++ } ++ ++ if (need_reset) ++ rkvdec_iommu_restore(rkvdec); ++ ++ if (cancel_delayed_work(&rkvdec->watchdog_work)) ++ rkvdec_job_finish(ctx, state); ++ ++ return IRQ_HANDLED; ++} ++ + static irqreturn_t rkvdec_irq_handler(int irq, void *priv) + { + struct rkvdec_dev *rkvdec = priv; +@@ -1366,6 +1425,7 @@ static int rkvdec_disable_multicore(struct rkvdec_dev *rkvdec) + + static const struct rkvdec_variant_ops rk3399_variant_ops = { + .irq_handler = rk3399_irq_handler, ++ .colmv_size = rkvdec_colmv_size, + }; + + static const struct rkvdec_variant rk3288_rkvdec_variant = { +@@ -1408,6 +1468,7 @@ static const struct rcb_size_info vdpu381_rcb_sizes[] = { + + static const struct rkvdec_variant_ops vdpu381_variant_ops = { + .irq_handler = vdpu381_irq_handler, ++ .colmv_size = rkvdec_colmv_size, + }; + + static const struct rkvdec_variant vdpu381_variant = { +@@ -1418,6 +1479,32 @@ static const struct rkvdec_variant vdpu381_variant = { + .ops = &vdpu381_variant_ops, + }; + ++static const struct rcb_size_info vdpu383_rcb_sizes[] = { ++ {6, PIC_WIDTH}, // streamd ++ {6, PIC_WIDTH}, // streamd_tile ++ {12, PIC_WIDTH}, // inter ++ {12, PIC_WIDTH}, // inter_tile ++ {16, PIC_WIDTH}, // intra ++ {10, PIC_WIDTH}, // intra_tile ++ {120, PIC_WIDTH}, // filterd ++ {120, PIC_WIDTH}, // filterd_protect ++ {120, PIC_WIDTH}, // filterd_tile_row ++ {180, PIC_HEIGHT}, // filterd_tile_col ++}; ++ ++static const struct rkvdec_variant_ops vdpu383_variant_ops = { ++ .irq_handler = vdpu383_irq_handler, ++ .colmv_size = vdpu383_colmv_size, ++}; ++ ++static const struct rkvdec_variant vdpu383_variant = { ++ .coded_fmts = vdpu383_coded_fmts, ++ .num_coded_fmts = ARRAY_SIZE(vdpu383_coded_fmts), ++ .rcb_sizes = vdpu383_rcb_sizes, ++ .num_rcb_sizes = ARRAY_SIZE(vdpu383_rcb_sizes), ++ .ops = &vdpu383_variant_ops, ++}; ++ + static const struct of_device_id of_rkvdec_match[] = { { - .cfg.id = V4L2_CID_STATELESS_H264_DECODE_PARAMS, -@@ -309,6 +308,60 @@ static const struct rkvdec_ctrls rkvdec_h264_ctrls = { - .num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs), + .compatible = "rockchip,rk3288-vdec", +@@ -1435,6 +1522,10 @@ static const struct of_device_id of_rkvdec_match[] = { + .compatible = "rockchip,rk3588-vdec", + .data = &vdpu381_variant, + }, ++ { ++ .compatible = "rockchip,rk3576-vdec", ++ .data = &vdpu383_variant, ++ }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, of_rkvdec_match); +@@ -1478,6 +1569,10 @@ static int rkvdec_probe(struct platform_device *pdev) + rkvdec->regs = devm_platform_ioremap_resource_byname(pdev, "function"); + if (IS_ERR(rkvdec->regs)) + return PTR_ERR(rkvdec->regs); ++ ++ rkvdec->link = devm_platform_ioremap_resource_byname(pdev, "link"); ++ if (IS_ERR(rkvdec->link)) ++ return PTR_ERR(rkvdec->link); + } + + ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); +diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.h b/drivers/media/platform/rockchip/rkvdec/rkvdec.h +index 111111111111..222222222222 100644 +--- a/drivers/media/platform/rockchip/rkvdec/rkvdec.h ++++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.h +@@ -73,6 +73,7 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) + + struct rkvdec_variant_ops { + irqreturn_t (*irq_handler)(struct rkvdec_ctx *ctx); ++ u32 (*colmv_size)(u16 width, u16 height); + }; + + struct rkvdec_variant { +@@ -133,6 +134,7 @@ struct rkvdec_dev { + unsigned int num_clocks; + struct clk *axi_clk; + void __iomem *regs; ++ void __iomem *link; + struct mutex vdev_lock; /* serializes ioctls */ + struct delayed_work watchdog_work; + struct gen_pool *sram_pool; +@@ -185,4 +187,7 @@ extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops; + /* VDPU381 ops */ + extern const struct rkvdec_coded_fmt_ops rkvdec_vdpu381_h264_fmt_ops; + ++/* VDPU383 ops */ ++extern const struct rkvdec_coded_fmt_ops rkvdec_vdpu383_h264_fmt_ops; ++ + #endif /* RKVDEC_H_ */ +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Detlev Casanova +Date: Thu, 18 Dec 2025 18:28:26 -0500 +Subject: media: rkvdec: Add HEVC support for the VDPU381 variant + +The VDPU381 supports HEVC decoding up to 7680x4320@30fps. +It could double that when using both decoder cores. + +It support YUV420 (8 and 10 bits) as well as AFBC (not implemented +here) + +The fluster score is 146/147 for JCT-VC-HEVC_V1, tested on ROCK 5B. +None of the other test suites works. + +Tested-by: Diederik de Haas # Rock 5B +Reviewed-by: Nicolas Dufresne +Signed-off-by: Detlev Casanova +--- + drivers/media/platform/rockchip/rkvdec/Makefile | 1 + + drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c | 335 +++++ + drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h | 59 + + drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c | 622 ++++++++++ + drivers/media/platform/rockchip/rkvdec/rkvdec.c | 82 ++ + drivers/media/platform/rockchip/rkvdec/rkvdec.h | 3 + + 6 files changed, 1102 insertions(+) + +diff --git a/drivers/media/platform/rockchip/rkvdec/Makefile b/drivers/media/platform/rockchip/rkvdec/Makefile +index 111111111111..222222222222 100644 +--- a/drivers/media/platform/rockchip/rkvdec/Makefile ++++ b/drivers/media/platform/rockchip/rkvdec/Makefile +@@ -9,5 +9,6 @@ rockchip-vdec-y += \ + rkvdec-hevc-common.o \ + rkvdec-rcb.o \ + rkvdec-vdpu381-h264.o \ ++ rkvdec-vdpu381-hevc.o \ + rkvdec-vdpu383-h264.o \ + rkvdec-vp9.o +diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c +index 111111111111..222222222222 100644 +--- a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c ++++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c +@@ -21,6 +21,125 @@ + #include "rkvdec.h" + #include "rkvdec-hevc-common.h" + ++/* Store the Short term ref pic set calculated values */ ++struct calculated_rps_st_set { ++ u8 num_delta_pocs; ++ u8 num_negative_pics; ++ u8 num_positive_pics; ++ u8 used_by_curr_pic_s0[16]; ++ u8 used_by_curr_pic_s1[16]; ++ s32 delta_poc_s0[16]; ++ s32 delta_poc_s1[16]; ++}; ++ ++void compute_tiles_uniform(struct rkvdec_hevc_run *run, u16 log2_min_cb_size, ++ u16 width, u16 height, s32 pic_in_cts_width, ++ s32 pic_in_cts_height, u16 *column_width, u16 *row_height) ++{ ++ const struct v4l2_ctrl_hevc_pps *pps = run->pps; ++ int i; ++ ++ for (i = 0; i < pps->num_tile_columns_minus1 + 1; i++) ++ column_width[i] = ((i + 1) * pic_in_cts_width) / ++ (pps->num_tile_columns_minus1 + 1) - ++ (i * pic_in_cts_width) / ++ (pps->num_tile_columns_minus1 + 1); ++ ++ for (i = 0; i < pps->num_tile_rows_minus1 + 1; i++) ++ row_height[i] = ((i + 1) * pic_in_cts_height) / ++ (pps->num_tile_rows_minus1 + 1) - ++ (i * pic_in_cts_height) / ++ (pps->num_tile_rows_minus1 + 1); ++} ++ ++void compute_tiles_non_uniform(struct rkvdec_hevc_run *run, u16 log2_min_cb_size, ++ u16 width, u16 height, s32 pic_in_cts_width, ++ s32 pic_in_cts_height, u16 *column_width, u16 *row_height) ++{ ++ const struct v4l2_ctrl_hevc_pps *pps = run->pps; ++ s32 sum = 0; ++ int i; ++ ++ for (i = 0; i < pps->num_tile_columns_minus1; i++) { ++ column_width[i] = pps->column_width_minus1[i] + 1; ++ sum += column_width[i]; ++ } ++ column_width[i] = pic_in_cts_width - sum; ++ ++ sum = 0; ++ for (i = 0; i < pps->num_tile_rows_minus1; i++) { ++ row_height[i] = pps->row_height_minus1[i] + 1; ++ sum += row_height[i]; ++ } ++ row_height[i] = pic_in_cts_height - sum; ++} ++ ++static void set_ref_poc(struct rkvdec_rps_short_term_ref_set *set, int poc, int value, int flag) ++{ ++ switch (poc) { ++ case 0: ++ set->delta_poc0 = value; ++ set->used_flag0 = flag; ++ break; ++ case 1: ++ set->delta_poc1 = value; ++ set->used_flag1 = flag; ++ break; ++ case 2: ++ set->delta_poc2 = value; ++ set->used_flag2 = flag; ++ break; ++ case 3: ++ set->delta_poc3 = value; ++ set->used_flag3 = flag; ++ break; ++ case 4: ++ set->delta_poc4 = value; ++ set->used_flag4 = flag; ++ break; ++ case 5: ++ set->delta_poc5 = value; ++ set->used_flag5 = flag; ++ break; ++ case 6: ++ set->delta_poc6 = value; ++ set->used_flag6 = flag; ++ break; ++ case 7: ++ set->delta_poc7 = value; ++ set->used_flag7 = flag; ++ break; ++ case 8: ++ set->delta_poc8 = value; ++ set->used_flag8 = flag; ++ break; ++ case 9: ++ set->delta_poc9 = value; ++ set->used_flag9 = flag; ++ break; ++ case 10: ++ set->delta_poc10 = value; ++ set->used_flag10 = flag; ++ break; ++ case 11: ++ set->delta_poc11 = value; ++ set->used_flag11 = flag; ++ break; ++ case 12: ++ set->delta_poc12 = value; ++ set->used_flag12 = flag; ++ break; ++ case 13: ++ set->delta_poc13 = value; ++ set->used_flag13 = flag; ++ break; ++ case 14: ++ set->delta_poc14 = value; ++ set->used_flag14 = flag; ++ break; ++ } ++} ++ + /* + * Flip one or more matrices along their main diagonal and flatten them + * before writing it to the memory. +@@ -120,6 +239,211 @@ void rkvdec_hevc_assemble_hw_scaling_list(struct rkvdec_hevc_run *run, + sizeof(struct v4l2_ctrl_hevc_scaling_matrix)); + } + ++static void rkvdec_hevc_assemble_hw_lt_rps(struct rkvdec_hevc_run *run, struct rkvdec_rps *rps) ++{ ++ const struct v4l2_ctrl_hevc_sps *sps = run->sps; ++ ++ if (!run->ext_sps_lt_rps) ++ return; ++ ++ for (int i = 0; i < sps->num_long_term_ref_pics_sps; i++) { ++ rps->refs[i].lt_ref_pic_poc_lsb = ++ run->ext_sps_lt_rps[i].lt_ref_pic_poc_lsb_sps; ++ rps->refs[i].used_by_curr_pic_lt_flag = ++ !!(run->ext_sps_lt_rps[i].flags & V4L2_HEVC_EXT_SPS_LT_RPS_FLAG_USED_LT); ++ } ++} ++ ++static void rkvdec_hevc_assemble_hw_st_rps(struct rkvdec_hevc_run *run, struct rkvdec_rps *rps, ++ struct calculated_rps_st_set *calculated_rps_st_sets) ++{ ++ const struct v4l2_ctrl_hevc_sps *sps = run->sps; ++ ++ for (int i = 0; i < sps->num_short_term_ref_pic_sets; i++) { ++ int poc = 0; ++ int j = 0; ++ const struct calculated_rps_st_set *set = &calculated_rps_st_sets[i]; ++ ++ rps->short_term_ref_sets[i].num_negative = set->num_negative_pics; ++ rps->short_term_ref_sets[i].num_positive = set->num_positive_pics; ++ ++ for (; j < set->num_negative_pics; j++) { ++ set_ref_poc(&rps->short_term_ref_sets[i], j, ++ set->delta_poc_s0[j], set->used_by_curr_pic_s0[j]); ++ } ++ poc = j; ++ ++ for (j = 0; j < set->num_positive_pics; j++) { ++ set_ref_poc(&rps->short_term_ref_sets[i], poc + j, ++ set->delta_poc_s1[j], set->used_by_curr_pic_s1[j]); ++ } ++ } ++} ++ ++/* ++ * Compute the short term ref pic set parameters based on its reference short term ref pic ++ */ ++static void st_ref_pic_set_prediction(struct rkvdec_hevc_run *run, int idx, ++ struct calculated_rps_st_set *calculated_rps_st_sets) ++{ ++ const struct v4l2_ctrl_hevc_ext_sps_st_rps *rps_data = &run->ext_sps_st_rps[idx]; ++ struct calculated_rps_st_set *st_rps = &calculated_rps_st_sets[idx]; ++ struct calculated_rps_st_set *ref_rps; ++ u8 st_rps_idx = idx; ++ u8 ref_rps_idx = 0; ++ s16 delta_rps = 0; ++ u8 use_delta_flag[16] = { 0 }; ++ u8 used_by_curr_pic_flag[16] = { 0 }; ++ int i, j; ++ int dPoc; ++ ++ ref_rps_idx = st_rps_idx - (rps_data->delta_idx_minus1 + 1); /* 7-59 */ ++ delta_rps = (1 - 2 * rps_data->delta_rps_sign) * ++ (rps_data->abs_delta_rps_minus1 + 1); /* 7-60 */ ++ ++ ref_rps = &calculated_rps_st_sets[ref_rps_idx]; ++ ++ for (j = 0; j <= ref_rps->num_delta_pocs; j++) { ++ used_by_curr_pic_flag[j] = !!(rps_data->used_by_curr_pic & (1 << j)); ++ use_delta_flag[j] = !!(rps_data->use_delta_flag & (1 << j)); ++ } ++ ++ /* 7-61: calculate num_negative_pics, delta_poc_s0 and used_by_curr_pic_s0 */ ++ i = 0; ++ for (j = (ref_rps->num_positive_pics - 1); j >= 0; j--) { ++ dPoc = ref_rps->delta_poc_s1[j] + delta_rps; ++ if (dPoc < 0 && use_delta_flag[ref_rps->num_negative_pics + j]) { ++ st_rps->delta_poc_s0[i] = dPoc; ++ st_rps->used_by_curr_pic_s0[i++] = ++ used_by_curr_pic_flag[ref_rps->num_negative_pics + j]; ++ } ++ } ++ if (delta_rps < 0 && use_delta_flag[ref_rps->num_delta_pocs]) { ++ st_rps->delta_poc_s0[i] = delta_rps; ++ st_rps->used_by_curr_pic_s0[i++] = used_by_curr_pic_flag[ref_rps->num_delta_pocs]; ++ } ++ for (j = 0; j < ref_rps->num_negative_pics; j++) { ++ dPoc = ref_rps->delta_poc_s0[j] + delta_rps; ++ if (dPoc < 0 && use_delta_flag[j]) { ++ st_rps->delta_poc_s0[i] = dPoc; ++ st_rps->used_by_curr_pic_s0[i++] = used_by_curr_pic_flag[j]; ++ } ++ } ++ st_rps->num_negative_pics = i; ++ ++ /* 7-62: calculate num_positive_pics, delta_poc_s1 and used_by_curr_pic_s1 */ ++ i = 0; ++ for (j = (ref_rps->num_negative_pics - 1); j >= 0; j--) { ++ dPoc = ref_rps->delta_poc_s0[j] + delta_rps; ++ if (dPoc > 0 && use_delta_flag[j]) { ++ st_rps->delta_poc_s1[i] = dPoc; ++ st_rps->used_by_curr_pic_s1[i++] = used_by_curr_pic_flag[j]; ++ } ++ } ++ if (delta_rps > 0 && use_delta_flag[ref_rps->num_delta_pocs]) { ++ st_rps->delta_poc_s1[i] = delta_rps; ++ st_rps->used_by_curr_pic_s1[i++] = used_by_curr_pic_flag[ref_rps->num_delta_pocs]; ++ } ++ for (j = 0; j < ref_rps->num_positive_pics; j++) { ++ dPoc = ref_rps->delta_poc_s1[j] + delta_rps; ++ if (dPoc > 0 && use_delta_flag[ref_rps->num_negative_pics + j]) { ++ st_rps->delta_poc_s1[i] = dPoc; ++ st_rps->used_by_curr_pic_s1[i++] = ++ used_by_curr_pic_flag[ref_rps->num_negative_pics + j]; ++ } ++ } ++ st_rps->num_positive_pics = i; ++ ++ st_rps->num_delta_pocs = st_rps->num_positive_pics + st_rps->num_negative_pics; ++} ++ ++/* ++ * Compute the short term ref pic set parameters based on the control's data. ++ */ ++static void st_ref_pic_set_calculate(struct rkvdec_hevc_run *run, int idx, ++ struct calculated_rps_st_set *calculated_rps_st_sets) ++{ ++ const struct v4l2_ctrl_hevc_ext_sps_st_rps *rps_data = &run->ext_sps_st_rps[idx]; ++ struct calculated_rps_st_set *st_rps = &calculated_rps_st_sets[idx]; ++ int j, i = 0; ++ ++ /* 7-63 */ ++ st_rps->num_negative_pics = rps_data->num_negative_pics; ++ /* 7-64 */ ++ st_rps->num_positive_pics = rps_data->num_positive_pics; ++ ++ for (i = 0; i < st_rps->num_negative_pics; i++) { ++ /* 7-65 */ ++ st_rps->used_by_curr_pic_s0[i] = !!(rps_data->used_by_curr_pic & (1 << i)); ++ ++ if (i == 0) { ++ /* 7-67 */ ++ st_rps->delta_poc_s0[i] = -(rps_data->delta_poc_s0_minus1[i] + 1); ++ } else { ++ /* 7-69 */ ++ st_rps->delta_poc_s0[i] = ++ st_rps->delta_poc_s0[i - 1] - ++ (rps_data->delta_poc_s0_minus1[i] + 1); ++ } ++ } ++ ++ for (j = 0; j < st_rps->num_positive_pics; j++) { ++ /* 7-66 */ ++ st_rps->used_by_curr_pic_s1[j] = !!(rps_data->used_by_curr_pic & (1 << (i + j))); ++ ++ if (j == 0) { ++ /* 7-68 */ ++ st_rps->delta_poc_s1[j] = rps_data->delta_poc_s1_minus1[j] + 1; ++ } else { ++ /* 7-70 */ ++ st_rps->delta_poc_s1[j] = ++ st_rps->delta_poc_s1[j - 1] + ++ (rps_data->delta_poc_s1_minus1[j] + 1); ++ } ++ } ++ ++ /* 7-71 */ ++ st_rps->num_delta_pocs = st_rps->num_positive_pics + st_rps->num_negative_pics; ++} ++ ++static void rkvdec_hevc_prepare_hw_st_rps(struct rkvdec_hevc_run *run, struct rkvdec_rps *rps, ++ struct v4l2_ctrl_hevc_ext_sps_st_rps *cache) ++{ ++ int idx; ++ ++ if (!run->ext_sps_st_rps) ++ return; ++ ++ if (!memcmp(cache, run->ext_sps_st_rps, sizeof(struct v4l2_ctrl_hevc_ext_sps_st_rps))) ++ return; ++ ++ struct calculated_rps_st_set *calculated_rps_st_sets = ++ kzalloc(sizeof(struct calculated_rps_st_set) * ++ run->sps->num_short_term_ref_pic_sets, GFP_KERNEL); ++ ++ for (idx = 0; idx < run->sps->num_short_term_ref_pic_sets; idx++) { ++ const struct v4l2_ctrl_hevc_ext_sps_st_rps *rps_data = &run->ext_sps_st_rps[idx]; ++ ++ if (rps_data->flags & V4L2_HEVC_EXT_SPS_ST_RPS_FLAG_INTER_REF_PIC_SET_PRED) ++ st_ref_pic_set_prediction(run, idx, calculated_rps_st_sets); ++ else ++ st_ref_pic_set_calculate(run, idx, calculated_rps_st_sets); ++ } ++ ++ rkvdec_hevc_assemble_hw_st_rps(run, rps, calculated_rps_st_sets); ++ ++ kfree(calculated_rps_st_sets); ++ ++ memcpy(cache, run->ext_sps_st_rps, sizeof(struct v4l2_ctrl_hevc_ext_sps_st_rps)); ++} ++ ++void rkvdec_hevc_assemble_hw_rps(struct rkvdec_hevc_run *run, struct rkvdec_rps *rps, ++ struct v4l2_ctrl_hevc_ext_sps_st_rps *st_cache) ++{ ++ rkvdec_hevc_prepare_hw_st_rps(run, rps, st_cache); ++ rkvdec_hevc_assemble_hw_lt_rps(run, rps); ++} ++ + struct vb2_buffer * + get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run, + unsigned int dpb_idx) +@@ -202,5 +526,16 @@ void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, + V4L2_CID_STATELESS_HEVC_SCALING_MATRIX); + run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL; + ++ if (ctx->has_sps_st_rps) { ++ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, ++ V4L2_CID_STATELESS_HEVC_EXT_SPS_ST_RPS); ++ run->ext_sps_st_rps = ctrl ? ctrl->p_cur.p : NULL; ++ } ++ if (ctx->has_sps_lt_rps) { ++ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, ++ V4L2_CID_STATELESS_HEVC_EXT_SPS_LT_RPS); ++ run->ext_sps_lt_rps = ctrl ? ctrl->p_cur.p : NULL; ++ } ++ + rkvdec_run_preamble(ctx, &run->base); + } +diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h +index 111111111111..222222222222 100644 +--- a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h ++++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h +@@ -16,11 +16,60 @@ + */ + + #include ++#include + #include "rkvdec.h" + + #define RKV_HEVC_CABAC_TABLE_SIZE 27456 + extern const u8 rkvdec_hevc_cabac_table[RKV_HEVC_CABAC_TABLE_SIZE]; + ++struct rkvdec_rps_refs { ++ u16 lt_ref_pic_poc_lsb; ++ u16 used_by_curr_pic_lt_flag : 1; ++ u16 reserved : 15; ++} __packed; ++ ++struct rkvdec_rps_short_term_ref_set { ++ u32 num_negative : 4; ++ u32 num_positive : 4; ++ u32 delta_poc0 : 16; ++ u32 used_flag0 : 1; ++ u32 delta_poc1 : 16; ++ u32 used_flag1 : 1; ++ u32 delta_poc2 : 16; ++ u32 used_flag2 : 1; ++ u32 delta_poc3 : 16; ++ u32 used_flag3 : 1; ++ u32 delta_poc4 : 16; ++ u32 used_flag4 : 1; ++ u32 delta_poc5 : 16; ++ u32 used_flag5 : 1; ++ u32 delta_poc6 : 16; ++ u32 used_flag6 : 1; ++ u32 delta_poc7 : 16; ++ u32 used_flag7 : 1; ++ u32 delta_poc8 : 16; ++ u32 used_flag8 : 1; ++ u32 delta_poc9 : 16; ++ u32 used_flag9 : 1; ++ u32 delta_poc10 : 16; ++ u32 used_flag10 : 1; ++ u32 delta_poc11 : 16; ++ u32 used_flag11 : 1; ++ u32 delta_poc12 : 16; ++ u32 used_flag12 : 1; ++ u32 delta_poc13 : 16; ++ u32 used_flag13 : 1; ++ u32 delta_poc14 : 16; ++ u32 used_flag14 : 1; ++ u32 reserved_bits : 25; ++ u32 reserved[3]; ++} __packed; ++ ++struct rkvdec_rps { ++ struct rkvdec_rps_refs refs[32]; ++ struct rkvdec_rps_short_term_ref_set short_term_ref_sets[64]; ++} __packed; ++ + struct rkvdec_hevc_run { + struct rkvdec_run base; + const struct v4l2_ctrl_hevc_slice_params *slices_params; +@@ -28,6 +77,8 @@ struct rkvdec_hevc_run { + const struct v4l2_ctrl_hevc_sps *sps; + const struct v4l2_ctrl_hevc_pps *pps; + const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; ++ const struct v4l2_ctrl_hevc_ext_sps_st_rps *ext_sps_st_rps; ++ const struct v4l2_ctrl_hevc_ext_sps_lt_rps *ext_sps_lt_rps; + int num_slices; + }; + +@@ -38,6 +89,14 @@ struct scaling_factor { + u8 reserved[4]; /*16Bytes align*/ + }; + ++void compute_tiles_uniform(struct rkvdec_hevc_run *run, u16 log2_min_cb_size, ++ u16 width, u16 height, s32 pic_in_cts_width, ++ s32 pic_in_cts_height, u16 *column_width, u16 *row_height); ++void compute_tiles_non_uniform(struct rkvdec_hevc_run *run, u16 log2_min_cb_size, ++ u16 width, u16 height, s32 pic_in_cts_width, ++ s32 pic_in_cts_height, u16 *column_width, u16 *row_height); ++void rkvdec_hevc_assemble_hw_rps(struct rkvdec_hevc_run *run, struct rkvdec_rps *rps, ++ struct v4l2_ctrl_hevc_ext_sps_st_rps *st_cache); + void rkvdec_hevc_assemble_hw_scaling_list(struct rkvdec_hevc_run *run, + struct scaling_factor *scaling_factor, + struct v4l2_ctrl_hevc_scaling_matrix *cache); +diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c +new file mode 100644 +index 000000000000..111111111111 +--- /dev/null ++++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c +@@ -0,0 +1,622 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Rockchip VDPU381 HEVC backend ++ * ++ * Copyright (C) 2025 Collabora, Ltd. ++ * Detlev Casanova ++ */ ++ ++#include ++ ++#include "rkvdec.h" ++#include "rkvdec-rcb.h" ++#include "rkvdec-hevc-common.h" ++#include "rkvdec-vdpu381-regs.h" ++ ++// SPS ++struct rkvdec_hevc_sps { ++ u16 video_parameters_set_id : 4; ++ u16 seq_parameters_set_id_sps : 4; ++ u16 chroma_format_idc : 2; ++ u16 width : 16; ++ u16 height : 16; ++ u16 bit_depth_luma : 4; ++ u16 bit_depth_chroma : 4; ++ u16 max_pic_order_count_lsb : 5; ++ u16 diff_max_min_luma_coding_block_size : 2; ++ u16 min_luma_coding_block_size : 3; ++ u16 min_transform_block_size : 3; ++ u16 diff_max_min_transform_block_size : 2; ++ u16 max_transform_hierarchy_depth_inter : 3; ++ u16 max_transform_hierarchy_depth_intra : 3; ++ u16 scaling_list_enabled_flag : 1; ++ u16 amp_enabled_flag : 1; ++ u16 sample_adaptive_offset_enabled_flag : 1; ++ u16 pcm_enabled_flag : 1; ++ u16 pcm_sample_bit_depth_luma : 4; ++ u16 pcm_sample_bit_depth_chroma : 4; ++ u16 pcm_loop_filter_disabled_flag : 1; ++ u16 diff_max_min_pcm_luma_coding_block_size : 3; ++ u16 min_pcm_luma_coding_block_size : 3; ++ u16 num_short_term_ref_pic_sets : 7; ++ u16 long_term_ref_pics_present_flag : 1; ++ u16 num_long_term_ref_pics_sps : 6; ++ u16 sps_temporal_mvp_enabled_flag : 1; ++ u16 strong_intra_smoothing_enabled_flag : 1; ++ u16 reserved_0 : 7; ++ u16 sps_max_dec_pic_buffering_minus1 : 4; ++ u16 reserved_0_2 : 3; ++ u16 reserved_f : 8; ++} __packed; ++ ++//PPS ++struct rkvdec_hevc_pps { ++ u16 picture_parameters_set_id : 6; ++ u16 seq_parameters_set_id_pps : 4; ++ u16 dependent_slice_segments_enabled_flag : 1; ++ u16 output_flag_present_flag : 1; ++ u16 num_extra_slice_header_bits : 13; ++ u16 sign_data_hiding_enabled_flag : 1; ++ u16 cabac_init_present_flag : 1; ++ u16 num_ref_idx_l0_default_active : 4; ++ u16 num_ref_idx_l1_default_active : 4; ++ u16 init_qp_minus26 : 7; ++ u16 constrained_intra_pred_flag : 1; ++ u16 transform_skip_enabled_flag : 1; ++ u16 cu_qp_delta_enabled_flag : 1; ++ u16 log2_min_cb_size : 3; ++ u16 pps_cb_qp_offset : 5; ++ u16 pps_cr_qp_offset : 5; ++ u16 pps_slice_chroma_qp_offsets_present_flag : 1; ++ u16 weighted_pred_flag : 1; ++ u16 weighted_bipred_flag : 1; ++ u16 transquant_bypass_enabled_flag : 1; ++ u16 tiles_enabled_flag : 1; ++ u16 entropy_coding_sync_enabled_flag : 1; ++ u16 pps_loop_filter_across_slices_enabled_flag : 1; ++ u16 loop_filter_across_tiles_enabled_flag : 1; ++ u16 deblocking_filter_override_enabled_flag : 1; ++ u16 pps_deblocking_filter_disabled_flag : 1; ++ u16 pps_beta_offset_div2 : 4; ++ u16 pps_tc_offset_div2 : 4; ++ u16 lists_modification_present_flag : 1; ++ u16 log2_parallel_merge_level : 3; ++ u16 slice_segment_header_extension_present_flag : 1; ++ u16 zeroes : 3; ++ u16 num_tile_columns : 5; ++ u16 num_tile_rows : 5; ++ u16 sps_pps_mode : 4; ++ u16 reserved_bits : 14; ++ u16 reserved; ++} __packed; ++ ++struct rkvdec_hevc_tile { ++ u16 value0 : 12; ++ u16 value1 : 12; ++} __packed; ++ ++struct rkvdec_sps_pps_packet { ++ struct rkvdec_hevc_sps sps; ++ struct rkvdec_hevc_pps pps; ++ struct rkvdec_hevc_tile column_width[10]; ++ struct rkvdec_hevc_tile row_height[11]; ++ u32 zeroes[3]; ++ u32 zeroes_bits : 6; ++ u32 padding_bits : 2; ++ u32 padding; ++} __packed; ++ ++struct rkvdec_hevc_priv_tbl { ++ struct rkvdec_sps_pps_packet param_set[64]; ++ struct rkvdec_rps rps; ++ struct scaling_factor scaling_list; ++ u8 cabac_table[27456]; ++}; ++ ++struct rkvdec_hevc_ctx { ++ struct rkvdec_aux_buf priv_tbl; ++ struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache; ++ struct v4l2_ctrl_hevc_ext_sps_st_rps st_cache; ++ struct rkvdec_vdpu381_regs_hevc regs; ++}; ++ ++static void assemble_hw_pps(struct rkvdec_ctx *ctx, ++ struct rkvdec_hevc_run *run) ++{ ++ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; ++ const struct v4l2_ctrl_hevc_sps *sps = run->sps; ++ const struct v4l2_ctrl_hevc_pps *pps = run->pps; ++ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; ++ struct rkvdec_sps_pps_packet *hw_ps; ++ bool tiles_enabled; ++ s32 max_cu_width; ++ s32 pic_in_cts_width; ++ s32 pic_in_cts_height; ++ u16 log2_min_cb_size, width, height; ++ u16 column_width[20]; ++ u16 row_height[22]; ++ u8 pcm_enabled; ++ u32 i; ++ ++ /* ++ * HW read the SPS/PPS information from PPS packet index by PPS id. ++ * offset from the base can be calculated by PPS_id * 32 (size per PPS ++ * packet unit). so the driver copy SPS/PPS information to the exact PPS ++ * packet unit for HW accessing. ++ */ ++ hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id]; ++ memset(hw_ps, 0, sizeof(*hw_ps)); ++ ++ /* write sps */ ++ hw_ps->sps.video_parameters_set_id = sps->video_parameter_set_id; ++ hw_ps->sps.seq_parameters_set_id_sps = sps->seq_parameter_set_id; ++ hw_ps->sps.chroma_format_idc = sps->chroma_format_idc; ++ ++ log2_min_cb_size = sps->log2_min_luma_coding_block_size_minus3 + 3; ++ width = sps->pic_width_in_luma_samples; ++ height = sps->pic_height_in_luma_samples; ++ hw_ps->sps.width = width; ++ hw_ps->sps.height = height; ++ hw_ps->sps.bit_depth_luma = sps->bit_depth_luma_minus8 + 8; ++ hw_ps->sps.bit_depth_chroma = sps->bit_depth_chroma_minus8 + 8; ++ hw_ps->sps.max_pic_order_count_lsb = sps->log2_max_pic_order_cnt_lsb_minus4 + 4; ++ hw_ps->sps.diff_max_min_luma_coding_block_size = ++ sps->log2_diff_max_min_luma_coding_block_size; ++ hw_ps->sps.min_luma_coding_block_size = sps->log2_min_luma_coding_block_size_minus3 + 3; ++ hw_ps->sps.min_transform_block_size = sps->log2_min_luma_transform_block_size_minus2 + 2; ++ hw_ps->sps.diff_max_min_transform_block_size = ++ sps->log2_diff_max_min_luma_transform_block_size; ++ hw_ps->sps.max_transform_hierarchy_depth_inter = sps->max_transform_hierarchy_depth_inter; ++ hw_ps->sps.max_transform_hierarchy_depth_intra = sps->max_transform_hierarchy_depth_intra; ++ hw_ps->sps.scaling_list_enabled_flag = ++ !!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED); ++ hw_ps->sps.amp_enabled_flag = !!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED); ++ hw_ps->sps.sample_adaptive_offset_enabled_flag = ++ !!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET); ++ ++ pcm_enabled = !!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED); ++ hw_ps->sps.pcm_enabled_flag = pcm_enabled; ++ hw_ps->sps.pcm_sample_bit_depth_luma = ++ pcm_enabled ? sps->pcm_sample_bit_depth_luma_minus1 + 1 : 0; ++ hw_ps->sps.pcm_sample_bit_depth_chroma = ++ pcm_enabled ? sps->pcm_sample_bit_depth_chroma_minus1 + 1 : 0; ++ hw_ps->sps.pcm_loop_filter_disabled_flag = ++ !!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED); ++ hw_ps->sps.diff_max_min_pcm_luma_coding_block_size = ++ sps->log2_diff_max_min_pcm_luma_coding_block_size; ++ hw_ps->sps.min_pcm_luma_coding_block_size = ++ pcm_enabled ? sps->log2_min_pcm_luma_coding_block_size_minus3 + 3 : 0; ++ hw_ps->sps.num_short_term_ref_pic_sets = sps->num_short_term_ref_pic_sets; ++ hw_ps->sps.long_term_ref_pics_present_flag = ++ !!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT); ++ hw_ps->sps.num_long_term_ref_pics_sps = sps->num_long_term_ref_pics_sps; ++ hw_ps->sps.sps_temporal_mvp_enabled_flag = ++ !!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED); ++ hw_ps->sps.strong_intra_smoothing_enabled_flag = ++ !!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED); ++ hw_ps->sps.sps_max_dec_pic_buffering_minus1 = sps->sps_max_dec_pic_buffering_minus1; ++ hw_ps->sps.reserved_f = 0xff; ++ ++ /* write pps */ ++ hw_ps->pps.picture_parameters_set_id = pps->pic_parameter_set_id; ++ hw_ps->pps.seq_parameters_set_id_pps = sps->seq_parameter_set_id; ++ hw_ps->pps.dependent_slice_segments_enabled_flag = ++ !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED); ++ hw_ps->pps.output_flag_present_flag = ++ !!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT); ++ hw_ps->pps.num_extra_slice_header_bits = pps->num_extra_slice_header_bits; ++ hw_ps->pps.sign_data_hiding_enabled_flag = ++ !!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED); ++ hw_ps->pps.cabac_init_present_flag = ++ !!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT); ++ hw_ps->pps.num_ref_idx_l0_default_active = pps->num_ref_idx_l0_default_active_minus1 + 1; ++ hw_ps->pps.num_ref_idx_l1_default_active = pps->num_ref_idx_l1_default_active_minus1 + 1; ++ hw_ps->pps.init_qp_minus26 = pps->init_qp_minus26; ++ hw_ps->pps.constrained_intra_pred_flag = ++ !!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED); ++ hw_ps->pps.transform_skip_enabled_flag = ++ !!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED); ++ hw_ps->pps.cu_qp_delta_enabled_flag = ++ !!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED); ++ hw_ps->pps.log2_min_cb_size = log2_min_cb_size + ++ sps->log2_diff_max_min_luma_coding_block_size - ++ pps->diff_cu_qp_delta_depth; ++ hw_ps->pps.pps_cb_qp_offset = pps->pps_cb_qp_offset; ++ hw_ps->pps.pps_cr_qp_offset = pps->pps_cr_qp_offset; ++ hw_ps->pps.pps_slice_chroma_qp_offsets_present_flag = ++ !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT); ++ hw_ps->pps.weighted_pred_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED); ++ hw_ps->pps.weighted_bipred_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED); ++ hw_ps->pps.transquant_bypass_enabled_flag = ++ !!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED); ++ ++ tiles_enabled = !!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED); ++ hw_ps->pps.tiles_enabled_flag = tiles_enabled; ++ hw_ps->pps.entropy_coding_sync_enabled_flag = ++ !!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED); ++ hw_ps->pps.pps_loop_filter_across_slices_enabled_flag = ++ !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED); ++ hw_ps->pps.loop_filter_across_tiles_enabled_flag = ++ !!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED); ++ hw_ps->pps.deblocking_filter_override_enabled_flag = ++ !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED); ++ hw_ps->pps.pps_deblocking_filter_disabled_flag = ++ !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER); ++ hw_ps->pps.pps_beta_offset_div2 = pps->pps_beta_offset_div2; ++ hw_ps->pps.pps_tc_offset_div2 = pps->pps_tc_offset_div2; ++ hw_ps->pps.lists_modification_present_flag = ++ !!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT); ++ hw_ps->pps.log2_parallel_merge_level = pps->log2_parallel_merge_level_minus2 + 2; ++ hw_ps->pps.slice_segment_header_extension_present_flag = ++ !!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT); ++ hw_ps->pps.num_tile_columns = tiles_enabled ? pps->num_tile_columns_minus1 + 1 : 0; ++ hw_ps->pps.num_tile_rows = tiles_enabled ? pps->num_tile_rows_minus1 + 1 : 0; ++ hw_ps->pps.sps_pps_mode = 0; ++ hw_ps->pps.reserved_bits = 0x3fff; ++ hw_ps->pps.reserved = 0xffff; ++ ++ // Setup tiles information ++ memset(column_width, 0, sizeof(column_width)); ++ memset(row_height, 0, sizeof(row_height)); ++ ++ max_cu_width = 1 << (sps->log2_diff_max_min_luma_coding_block_size + log2_min_cb_size); ++ pic_in_cts_width = (width + max_cu_width - 1) / max_cu_width; ++ pic_in_cts_height = (height + max_cu_width - 1) / max_cu_width; ++ ++ if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) { ++ if (pps->flags & V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING) { ++ compute_tiles_uniform(run, log2_min_cb_size, width, height, ++ pic_in_cts_width, pic_in_cts_height, ++ column_width, row_height); ++ } else { ++ compute_tiles_non_uniform(run, log2_min_cb_size, width, height, ++ pic_in_cts_width, pic_in_cts_height, ++ column_width, row_height); ++ } ++ } else { ++ column_width[0] = (width + max_cu_width - 1) / max_cu_width; ++ row_height[0] = (height + max_cu_width - 1) / max_cu_width; ++ } ++ ++ for (i = 0; i < 20; i++) { ++ if (column_width[i] > 0) ++ column_width[i]--; ++ ++ if (i & 1) ++ hw_ps->column_width[i / 2].value1 = column_width[i]; ++ else ++ hw_ps->column_width[i / 2].value0 = column_width[i]; ++ } ++ ++ for (i = 0; i < 22; i++) { ++ if (row_height[i] > 0) ++ row_height[i]--; ++ ++ if (i & 1) ++ hw_ps->row_height[i / 2].value1 = row_height[i]; ++ else ++ hw_ps->row_height[i / 2].value0 = row_height[i]; ++ } ++ ++ hw_ps->padding = 0xffffffff; ++ hw_ps->padding_bits = 0x3; ++} ++ ++static void set_ref_valid(struct rkvdec_vdpu381_regs_hevc *regs, int id, u32 valid) ++{ ++ switch (id) { ++ case 0: ++ regs->hevc_param.reg099.hevc_ref_valid_0 = valid; ++ break; ++ case 1: ++ regs->hevc_param.reg099.hevc_ref_valid_1 = valid; ++ break; ++ case 2: ++ regs->hevc_param.reg099.hevc_ref_valid_2 = valid; ++ break; ++ case 3: ++ regs->hevc_param.reg099.hevc_ref_valid_3 = valid; ++ break; ++ case 4: ++ regs->hevc_param.reg099.hevc_ref_valid_4 = valid; ++ break; ++ case 5: ++ regs->hevc_param.reg099.hevc_ref_valid_5 = valid; ++ break; ++ case 6: ++ regs->hevc_param.reg099.hevc_ref_valid_6 = valid; ++ break; ++ case 7: ++ regs->hevc_param.reg099.hevc_ref_valid_7 = valid; ++ break; ++ case 8: ++ regs->hevc_param.reg099.hevc_ref_valid_8 = valid; ++ break; ++ case 9: ++ regs->hevc_param.reg099.hevc_ref_valid_9 = valid; ++ break; ++ case 10: ++ regs->hevc_param.reg099.hevc_ref_valid_10 = valid; ++ break; ++ case 11: ++ regs->hevc_param.reg099.hevc_ref_valid_11 = valid; ++ break; ++ case 12: ++ regs->hevc_param.reg099.hevc_ref_valid_12 = valid; ++ break; ++ case 13: ++ regs->hevc_param.reg099.hevc_ref_valid_13 = valid; ++ break; ++ case 14: ++ regs->hevc_param.reg099.hevc_ref_valid_14 = valid; ++ break; ++ } ++} ++ ++static void rkvdec_write_regs(struct rkvdec_ctx *ctx) ++{ ++ struct rkvdec_dev *rkvdec = ctx->dev; ++ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; ++ ++ rkvdec_memcpy_toio(rkvdec->regs + OFFSET_COMMON_REGS, ++ &hevc_ctx->regs.common, ++ sizeof(hevc_ctx->regs.common)); ++ rkvdec_memcpy_toio(rkvdec->regs + OFFSET_CODEC_PARAMS_REGS, ++ &hevc_ctx->regs.hevc_param, ++ sizeof(hevc_ctx->regs.hevc_param)); ++ rkvdec_memcpy_toio(rkvdec->regs + OFFSET_COMMON_ADDR_REGS, ++ &hevc_ctx->regs.common_addr, ++ sizeof(hevc_ctx->regs.common_addr)); ++ rkvdec_memcpy_toio(rkvdec->regs + OFFSET_CODEC_ADDR_REGS, ++ &hevc_ctx->regs.hevc_addr, ++ sizeof(hevc_ctx->regs.hevc_addr)); ++ rkvdec_memcpy_toio(rkvdec->regs + OFFSET_POC_HIGHBIT_REGS, ++ &hevc_ctx->regs.hevc_highpoc, ++ sizeof(hevc_ctx->regs.hevc_highpoc)); ++} ++ ++static void config_registers(struct rkvdec_ctx *ctx, ++ struct rkvdec_hevc_run *run) ++{ ++ const struct v4l2_ctrl_hevc_decode_params *dec_params = run->decode_params; ++ const struct v4l2_hevc_dpb_entry *dpb = dec_params->dpb; ++ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; ++ struct rkvdec_vdpu381_regs_hevc *regs = &hevc_ctx->regs; ++ dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma; ++ const struct v4l2_pix_format_mplane *dst_fmt; ++ struct vb2_v4l2_buffer *src_buf = run->base.bufs.src; ++ struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst; ++ const struct v4l2_format *f; ++ dma_addr_t rlc_addr; ++ u32 hor_virstride = 0; ++ u32 ver_virstride = 0; ++ u32 y_virstride = 0; ++ u32 offset; ++ u32 pixels; ++ dma_addr_t dst_addr; ++ u32 i; ++ ++ memset(regs, 0, sizeof(*regs)); ++ ++ /* Set HEVC mode */ ++ regs->common.reg009.dec_mode = VDPU381_MODE_HEVC; ++ ++ /* Set config */ ++ regs->common.reg011.buf_empty_en = 1; ++ regs->common.reg011.dec_clkgate_e = 1; ++ regs->common.reg011.dec_timeout_e = 1; ++ regs->common.reg011.pix_range_detection_e = 1; ++ ++ /* Set IDR flag */ ++ regs->common.reg013.cur_pic_is_idr = ++ !!(dec_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC); ++ ++ /* Set input stream length */ ++ regs->common.stream_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0); ++ ++ /* Set max slice number */ ++ regs->common.reg017.slice_num = 1; ++ ++ /* Set strides */ ++ f = &ctx->decoded_fmt; ++ dst_fmt = &f->fmt.pix_mp; ++ hor_virstride = dst_fmt->plane_fmt[0].bytesperline; ++ ver_virstride = dst_fmt->height; ++ y_virstride = hor_virstride * ver_virstride; ++ pixels = dst_fmt->height * dst_fmt->width; ++ ++ regs->common.reg018.y_hor_virstride = hor_virstride / 16; ++ regs->common.reg019.uv_hor_virstride = hor_virstride / 16; ++ regs->common.reg020.y_virstride = y_virstride / 16; ++ ++ /* Activate block gating */ ++ regs->common.reg026.swreg_block_gating_e = 0xfffef; ++ regs->common.reg026.reg_cfg_gating_en = 1; ++ ++ /* Set timeout threshold */ ++ if (pixels < RKVDEC_1080P_PIXELS) ++ regs->common.timeout_threshold = RKVDEC_TIMEOUT_1080p; ++ else if (pixels < RKVDEC_4K_PIXELS) ++ regs->common.timeout_threshold = RKVDEC_TIMEOUT_4K; ++ else if (pixels < RKVDEC_8K_PIXELS) ++ regs->common.timeout_threshold = RKVDEC_TIMEOUT_8K; ++ ++ /* Set POC val */ ++ regs->hevc_param.cur_top_poc = dec_params->pic_order_cnt_val; ++ ++ /* Set ref pic address & poc */ ++ for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) { ++ struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i); ++ dma_addr_t buf_dma = vb2_dma_contig_plane_dma_addr(vb_buf, 0); ++ u32 valid = !!(dec_params->num_active_dpb_entries > i); ++ ++ /* Set reference addresses */ ++ regs->hevc_addr.ref_base[i] = buf_dma; ++ ++ /* Set COLMV addresses */ ++ regs->hevc_addr.colmv_base[i] = buf_dma + ctx->colmv_offset; ++ ++ regs->hevc_param.reg067_082_ref_poc[i] = ++ dpb[i].pic_order_cnt_val; ++ ++ set_ref_valid(regs, i, valid); ++ regs->hevc_param.reg103.ref_pic_layer_same_with_cur |= 1 << i; ++ } ++ ++ /* Set rlc base address (input stream) */ ++ rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); ++ regs->common_addr.rlc_base = rlc_addr; ++ regs->common_addr.rlcwrite_base = rlc_addr; ++ ++ /* Set output base address */ ++ dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); ++ regs->common_addr.decout_base = dst_addr; ++ regs->common_addr.error_ref_base = dst_addr; ++ ++ /* Set colmv address */ ++ regs->common_addr.colmv_cur_base = dst_addr + ctx->colmv_offset; ++ ++ /* Set RCB addresses */ ++ for (i = 0; i < rkvdec_rcb_buf_count(ctx); i++) ++ regs->common_addr.rcb_base[i] = rkvdec_rcb_buf_dma_addr(ctx, i); ++ ++ /* Set hw pps address */ ++ offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set); ++ regs->hevc_addr.pps_base = priv_start_addr + offset; ++ ++ /* Set hw rps address */ ++ offset = offsetof(struct rkvdec_hevc_priv_tbl, rps); ++ regs->hevc_addr.rps_base = priv_start_addr + offset; ++ ++ /* Set cabac table */ ++ offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table); ++ regs->hevc_addr.cabactbl_base = priv_start_addr + offset; ++ ++ /* Set scaling matrix */ ++ offset = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list); ++ regs->hevc_addr.scanlist_addr = priv_start_addr + offset; ++ ++ rkvdec_write_regs(ctx); ++} ++ ++static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, ++ const struct v4l2_ctrl_hevc_sps *sps) ++{ ++ if (sps->chroma_format_idc != 1) ++ /* Only 4:2:0 is supported */ ++ return -EINVAL; ++ ++ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) ++ /* Luma and chroma bit depth mismatch */ ++ return -EINVAL; ++ ++ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) ++ /* Only 8-bit and 10-bit are supported */ ++ return -EINVAL; ++ ++ if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width || ++ sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static int rkvdec_hevc_start(struct rkvdec_ctx *ctx) ++{ ++ struct rkvdec_dev *rkvdec = ctx->dev; ++ struct rkvdec_hevc_priv_tbl *priv_tbl; ++ struct rkvdec_hevc_ctx *hevc_ctx; ++ struct v4l2_ctrl *ctrl; ++ int ret; ++ ++ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, ++ V4L2_CID_STATELESS_HEVC_SPS); ++ if (!ctrl) ++ return -EINVAL; ++ ++ hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL); ++ if (!hevc_ctx) ++ return -ENOMEM; ++ ++ priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl), ++ &hevc_ctx->priv_tbl.dma, GFP_KERNEL); ++ if (!priv_tbl) { ++ ret = -ENOMEM; ++ goto err_free_ctx; ++ } ++ ++ hevc_ctx->priv_tbl.size = sizeof(*priv_tbl); ++ hevc_ctx->priv_tbl.cpu = priv_tbl; ++ memcpy(priv_tbl->cabac_table, rkvdec_hevc_cabac_table, ++ sizeof(rkvdec_hevc_cabac_table)); ++ ++ ctx->priv = hevc_ctx; ++ return 0; ++ ++err_free_ctx: ++ kfree(hevc_ctx); ++ return ret; ++} ++ ++static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx) ++{ ++ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; ++ struct rkvdec_dev *rkvdec = ctx->dev; ++ ++ dma_free_coherent(rkvdec->dev, hevc_ctx->priv_tbl.size, ++ hevc_ctx->priv_tbl.cpu, hevc_ctx->priv_tbl.dma); ++ kfree(hevc_ctx); ++} ++ ++static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) ++{ ++ struct rkvdec_dev *rkvdec = ctx->dev; ++ struct rkvdec_hevc_run run; ++ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; ++ struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu; ++ ++ rkvdec_hevc_run_preamble(ctx, &run); ++ ++ /* ++ * On vdpu381, not setting the long and short term ref sets will just output wrong frames. ++ * Let's just warn about it and let the decoder run anyway. ++ */ ++ if ((!ctx->has_sps_lt_rps && run.sps->num_long_term_ref_pics_sps) || ++ (!ctx->has_sps_st_rps && run.sps->num_short_term_ref_pic_sets)) { ++ dev_warn_ratelimited(rkvdec->dev, "Long and short term RPS not set\n"); ++ } ++ ++ rkvdec_hevc_assemble_hw_scaling_list(&run, ++ &tbl->scaling_list, ++ &hevc_ctx->scaling_matrix_cache); ++ assemble_hw_pps(ctx, &run); ++ rkvdec_hevc_assemble_hw_rps(&run, &tbl->rps, &hevc_ctx->st_cache); ++ ++ config_registers(ctx, &run); ++ ++ rkvdec_run_postamble(ctx, &run.base); ++ ++ schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000)); ++ ++ /* Start decoding! */ ++ writel(VDPU381_DEC_E_BIT, rkvdec->regs + VDPU381_REG_DEC_E); ++ ++ return 0; ++} ++ ++static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) ++{ ++ if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS) ++ return rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); ++ ++ return 0; ++} ++ ++const struct rkvdec_coded_fmt_ops rkvdec_vdpu381_hevc_fmt_ops = { ++ .adjust_fmt = rkvdec_hevc_adjust_fmt, ++ .start = rkvdec_hevc_start, ++ .stop = rkvdec_hevc_stop, ++ .run = rkvdec_hevc_run, ++ .try_ctrl = rkvdec_hevc_try_ctrl, ++ .get_image_fmt = rkvdec_hevc_get_image_fmt, ++}; +diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c +index 111111111111..222222222222 100644 +--- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c ++++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c +@@ -153,6 +153,16 @@ static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl) + enum rkvdec_image_fmt image_fmt; + struct vb2_queue *vq; + ++ if (ctrl->id == V4L2_CID_STATELESS_HEVC_EXT_SPS_ST_RPS) { ++ ctx->has_sps_st_rps |= !!(ctrl->has_changed); ++ return 0; ++ } ++ ++ if (ctrl->id == V4L2_CID_STATELESS_HEVC_EXT_SPS_LT_RPS) { ++ ctx->has_sps_lt_rps |= !!(ctrl->has_changed); ++ return 0; ++ } ++ + /* Check if this change requires a capture format reset */ + if (!desc->ops->get_image_fmt) + return 0; +@@ -226,6 +236,62 @@ static const struct rkvdec_ctrls rkvdec_hevc_ctrls = { + .num_ctrls = ARRAY_SIZE(rkvdec_hevc_ctrl_descs), }; +static const struct rkvdec_ctrl_desc vdpu38x_hevc_ctrl_descs[] = { @@ -12328,10 +9034,12 @@ index 111111111111..222222222222 100644 + }, + { + .cfg.id = V4L2_CID_STATELESS_HEVC_EXT_SPS_ST_RPS, ++ .cfg.ops = &rkvdec_ctrl_ops, + .cfg.dims = { 65 }, + }, + { + .cfg.id = V4L2_CID_STATELESS_HEVC_EXT_SPS_LT_RPS, ++ .cfg.ops = &rkvdec_ctrl_ops, + .cfg.dims = { 65 }, + }, +}; @@ -12341,38 +9049,20 @@ index 111111111111..222222222222 100644 + .num_ctrls = ARRAY_SIZE(vdpu38x_hevc_ctrl_descs), +}; + - static const struct rkvdec_decoded_fmt_desc rkvdec_h264_decoded_fmts[] = { + static const struct rkvdec_decoded_fmt_desc rkvdec_hevc_decoded_fmts[] = { { .fourcc = V4L2_PIX_FMT_NV12, -@@ -328,6 +381,17 @@ static const struct rkvdec_decoded_fmt_desc rkvdec_h264_decoded_fmts[] = { - }, +@@ -398,6 +464,22 @@ static const struct rkvdec_coded_fmt_desc rk3288_coded_fmts[] = { }; -+static const struct rkvdec_decoded_fmt_desc rkvdec_hevc_decoded_fmts[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_NV12, -+ .image_fmt = RKVDEC_IMG_FMT_420_8BIT, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_NV15, -+ .image_fmt = RKVDEC_IMG_FMT_420_10BIT, -+ }, -+}; -+ - static const struct rkvdec_ctrl_desc rkvdec_vp9_ctrl_descs[] = { - { - .cfg.id = V4L2_CID_STATELESS_VP9_FRAME, -@@ -425,6 +489,43 @@ static const struct rkvdec_coded_fmt_desc vdpu381_coded_fmts[] = { - .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, - .capability = RKVDEC_CAPABILITY_H264, - }, + static const struct rkvdec_coded_fmt_desc vdpu381_coded_fmts[] = { + { + .fourcc = V4L2_PIX_FMT_HEVC_SLICE, + .frmsize = { -+ .min_width = 16, ++ .min_width = 64, + .max_width = 65472, -+ .step_width = 16, -+ .min_height = 16, ++ .step_width = 64, ++ .min_height = 64, + .max_height = 65472, + .step_height = 16, + }, @@ -12381,200 +9071,37 @@ index 111111111111..222222222222 100644 + .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), + .decoded_fmts = rkvdec_hevc_decoded_fmts, + .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, -+ .capability = RKVDEC_CAPABILITY_HEVC, + }, -+}; -+ -+static const struct rkvdec_coded_fmt_desc vdpu383_coded_fmts[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_H264_SLICE, -+ .frmsize = { -+ .min_width = 64, -+ .max_width = 65520, -+ .step_width = 64, -+ .min_height = 16, -+ .max_height = 65520, -+ .step_height = 16, -+ }, -+ .ctrls = &rkvdec_h264_ctrls, -+ .ops = &rkvdec_vdpu383_h264_fmt_ops, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), -+ .decoded_fmts = rkvdec_h264_decoded_fmts, -+ .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, -+ .capability = RKVDEC_CAPABILITY_H264, -+ }, - }; - - static bool rkvdec_is_capable(struct rkvdec_ctx *ctx, unsigned int capability) -@@ -1317,6 +1418,35 @@ static irqreturn_t vdpu381_irq_handler(struct rkvdec_ctx *ctx) - return IRQ_HANDLED; - } - -+static irqreturn_t vdpu383_irq_handler(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ enum vb2_buffer_state state; -+ bool need_reset = 0; -+ u32 status; -+ -+ status = readl(rkvdec->link + VDPU383_LINK_STA_INT); -+ writel(FIELD_PREP_WM16(VDPU383_STA_INT_ALL, 0), rkvdec->link + VDPU383_LINK_STA_INT); -+ /* On vdpu383, the interrupts must be disabled */ -+ writel(FIELD_PREP_WM16(VDPU383_INT_EN_IRQ | VDPU383_INT_EN_LINE_IRQ, 0), -+ rkvdec->link + VDPU383_LINK_INT_EN); -+ -+ if (status & VDPU383_STA_INT_DEC_RDY_STA) { -+ state = VB2_BUF_STATE_DONE; -+ } else { -+ state = VB2_BUF_STATE_ERROR; -+ rkvdec_iommu_restore(rkvdec); -+ } -+ -+ if (need_reset) -+ rkvdec_iommu_restore(rkvdec); -+ -+ if (cancel_delayed_work(&rkvdec->watchdog_work)) -+ rkvdec_job_finish(ctx, state); -+ -+ return IRQ_HANDLED; -+} -+ - static irqreturn_t rkvdec_irq_handler(int irq, void *priv) - { - struct rkvdec_dev *rkvdec = priv; -@@ -1389,6 +1519,7 @@ static const struct rkvdec_config config_rkvdec = { - .coded_fmts_num = ARRAY_SIZE(rkvdec_coded_fmts), - .irq_handler = rk3399_irq_handler, - .fill_pixfmt_mp = v4l2_fill_pixfmt_mp, -+ .colmv_size = rkvdec_colmv_size, - }; - - static struct rcb_size_info vdpu381_rcb_sizes[] = { -@@ -1411,6 +1542,33 @@ static const struct rkvdec_config config_vdpu381 = { - .rcb_num = ARRAY_SIZE(vdpu381_rcb_sizes), - .irq_handler = vdpu381_irq_handler, - .fill_pixfmt_mp = vdpu38x_fill_pixfmt_mp, -+ .colmv_size = rkvdec_colmv_size, -+ .named_regs = true, -+}; -+ -+static struct rcb_size_info vdpu383_rcb_sizes[] = { -+ {6, PIC_WIDTH}, // streamd -+ {6, PIC_WIDTH}, // streamd_tile -+ {12, PIC_WIDTH}, // inter -+ {12, PIC_WIDTH}, // inter_tile -+ {16, PIC_WIDTH}, // intra -+ {10, PIC_WIDTH}, // intra_tile -+ {120, PIC_WIDTH}, // filterd -+ {120, PIC_WIDTH}, // filterd_protect -+ {120, PIC_WIDTH}, // filterd_tile_row -+ {180, PIC_HEIGHT}, // filterd_tile_col -+}; -+ -+const struct rkvdec_config config_vdpu383 = { -+ .coded_fmts = (struct rkvdec_coded_fmt_desc *)vdpu383_coded_fmts, -+ .coded_fmts_num = ARRAY_SIZE(vdpu383_coded_fmts), -+ .rcb_size_info = vdpu383_rcb_sizes, -+ .rcb_num = ARRAY_SIZE(vdpu383_rcb_sizes), -+ .irq_handler = vdpu383_irq_handler, -+ .fill_pixfmt_mp = vdpu38x_fill_pixfmt_mp, -+ .colmv_size = rkvdec_vdpu383_colmv_size, -+ .fill_pixfmt_mp = vdpu38x_fill_pixfmt_mp, -+ .named_regs = true, - }; - - static const struct rkvdec_variant rk3288_rkvdec_variant = { -@@ -1435,6 +1593,12 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = { - - static const struct rkvdec_variant rk3588_vdpu381_variant = { - .config = &config_vdpu381, -+ .capabilities = RKVDEC_CAPABILITY_H264 | -+ RKVDEC_CAPABILITY_HEVC, -+}; -+ -+static const struct rkvdec_variant rk3576_vdpu383_variant = { -+ .config = &config_vdpu383, - .capabilities = RKVDEC_CAPABILITY_H264, - }; - -@@ -1455,6 +1619,10 @@ static const struct of_device_id of_rkvdec_match[] = { - .compatible = "rockchip,rk3588-vdec", - .data = &rk3588_vdpu381_variant, - }, -+ { -+ .compatible = "rockchip,rk3576-vdec", -+ .data = &rk3576_vdpu383_variant -+ }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, of_rkvdec_match); -@@ -1492,9 +1660,19 @@ static int rkvdec_probe(struct platform_device *pdev) - rkvdec->clk_count = ret; - rkvdec->axi_clk = devm_clk_get(&pdev->dev, "axi"); - -- rkvdec->regs = devm_platform_ioremap_resource(pdev, 0); -- if (IS_ERR(rkvdec->regs)) -- return PTR_ERR(rkvdec->regs); -+ if (rkvdec->config->named_regs) { -+ rkvdec->regs = devm_platform_ioremap_resource_byname(pdev, "function"); -+ if (IS_ERR(rkvdec->regs)) -+ return PTR_ERR(rkvdec->regs); -+ -+ rkvdec->link = devm_platform_ioremap_resource_byname(pdev, "link"); -+ if (IS_ERR(rkvdec->link)) -+ return PTR_ERR(rkvdec->link); -+ } else { -+ rkvdec->regs = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(rkvdec->regs)) -+ return PTR_ERR(rkvdec->regs); -+ } - - ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); - if (ret) { + { + .fourcc = V4L2_PIX_FMT_H264_SLICE, + .frmsize = { diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.h b/drivers/media/platform/rockchip/rkvdec/rkvdec.h index 111111111111..222222222222 100644 --- a/drivers/media/platform/rockchip/rkvdec/rkvdec.h +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -@@ -123,6 +123,8 @@ struct rkvdec_config { - irqreturn_t (*irq_handler)(struct rkvdec_ctx *ctx); - int (*fill_pixfmt_mp)(struct v4l2_pix_format_mplane *pix_mp, u32 pixelformat, - u32 width, u32 height); -+ u32 (*colmv_size)(u16 width, u16 height); -+ bool named_regs; +@@ -154,6 +154,8 @@ struct rkvdec_ctx { + struct rkvdec_rcb_config *rcb_config; + u32 colmv_offset; + void *priv; ++ u8 has_sps_st_rps: 1; ++ u8 has_sps_lt_rps: 1; }; - struct rkvdec_dev { -@@ -135,6 +137,7 @@ struct rkvdec_dev { - unsigned int clk_count; - struct clk *axi_clk; - void __iomem *regs; -+ void __iomem *link; - struct mutex vdev_lock; /* serializes ioctls */ - struct delayed_work watchdog_work; - struct gen_pool *sram_pool; -@@ -179,10 +182,16 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); - void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); - void rkvdec_memcpy_toio(void __iomem *dst, void *src, size_t len); + static inline struct rkvdec_ctx *file_to_rkvdec_ctx(struct file *filp) +@@ -186,6 +188,7 @@ extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops; -+/* RKVDEC ops */ - extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops; - extern const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops; - extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops; - -+/* VDPU381 ops */ + /* VDPU381 ops */ extern const struct rkvdec_coded_fmt_ops rkvdec_vdpu381_h264_fmt_ops; +extern const struct rkvdec_coded_fmt_ops rkvdec_vdpu381_hevc_fmt_ops; -+ -+/* VDPU383 ops */ -+extern const struct rkvdec_coded_fmt_ops rkvdec_vdpu383_h264_fmt_ops; - #endif /* RKVDEC_H_ */ + /* VDPU383 ops */ + extern const struct rkvdec_coded_fmt_ops rkvdec_vdpu383_h264_fmt_ops; -- Armbian From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Detlev Casanova -Date: Wed, 11 Jun 2025 17:04:28 -0400 +Date: Thu, 18 Dec 2025 18:28:27 -0500 Subject: media: rkvdec: Add HEVC support for the VDPU383 variant The VDPU383 decoder is used on the RK3576 SoC and has support for HEVC. @@ -12584,14 +9111,18 @@ file and adds a specific scaling matrix flatten function. The fluster score for JCT-VC-HEVC_V1 is 146/147. +Reviewed-by: Nicolas Dufresne Signed-off-by: Detlev Casanova --- drivers/media/platform/rockchip/rkvdec/Makefile | 1 + - drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c | 49 +- - drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c | 680 ++++++++++ - drivers/media/platform/rockchip/rkvdec/rkvdec.c | 94 +- + drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c | 59 +- + drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h | 3 +- + drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c | 2 +- + drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c | 3 +- + drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c | 720 ++++++++++ + drivers/media/platform/rockchip/rkvdec/rkvdec.c | 91 ++ drivers/media/platform/rockchip/rkvdec/rkvdec.h | 2 + - 5 files changed, 783 insertions(+), 43 deletions(-) + 8 files changed, 833 insertions(+), 48 deletions(-) diff --git a/drivers/media/platform/rockchip/rkvdec/Makefile b/drivers/media/platform/rockchip/rkvdec/Makefile index 111111111111..222222222222 100644 @@ -12607,7 +9138,7 @@ diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c b/drive index 111111111111..222222222222 100644 --- a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c -@@ -155,60 +155,25 @@ static void set_ref_poc(struct rkvdec_rps_short_term_ref_set *set, int poc, int +@@ -140,56 +140,26 @@ static void set_ref_poc(struct rkvdec_rps_short_term_ref_set *set, int poc, int } } @@ -12643,44 +9174,114 @@ index 111111111111..222222222222 100644 - } -} - - static void assemble_scalingfactor0(struct rkvdec_dev *rkvdec, u8 *output, - const struct v4l2_ctrl_hevc_scaling_matrix *input) +-static void assemble_scalingfactor0(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input) ++static void assemble_scalingfactor0(struct rkvdec_ctx *ctx, u8 *output, ++ const struct v4l2_ctrl_hevc_scaling_matrix *input) { -+ const struct rkvdec_config *cfg = rkvdec->config; ++ const struct rkvdec_variant *variant = ctx->dev->variant; int offset = 0; - transpose_and_flatten_matrices(output, (const u8 *)input->scaling_list_4x4, 6, 4); -+ cfg->flatten_matrices(output, (const u8 *)input->scaling_list_4x4, 6, 4); ++ variant->ops->flatten_matrices(output, (const u8 *)input->scaling_list_4x4, 6, 4); offset = 6 * 16 * sizeof(u8); -- transpose_and_flatten_matrices(output + offset, -- (const u8 *)input->scaling_list_8x8, 6, 8); -+ cfg->flatten_matrices(output + offset, (const u8 *)input->scaling_list_8x8, 6, 8); +- transpose_and_flatten_matrices(output + offset, (const u8 *)input->scaling_list_8x8, 6, 8); ++ variant->ops->flatten_matrices(output + offset, (const u8 *)input->scaling_list_8x8, 6, 8); offset += 6 * 64 * sizeof(u8); - transpose_and_flatten_matrices(output + offset, - (const u8 *)input->scaling_list_16x16, 6, 8); -+ cfg->flatten_matrices(output + offset, (const u8 *)input->scaling_list_16x16, 6, 8); ++ variant->ops->flatten_matrices(output + offset, (const u8 *)input->scaling_list_16x16, ++ 6, 8); offset += 6 * 64 * sizeof(u8); /* Add a 128 byte padding with 0s between the two 32x32 matrices */ - transpose_and_flatten_matrices(output + offset, - (const u8 *)input->scaling_list_32x32, 1, 8); -+ cfg->flatten_matrices(output + offset, (const u8 *)input->scaling_list_32x32, 1, 8); ++ variant->ops->flatten_matrices(output + offset, (const u8 *)input->scaling_list_32x32, ++ 1, 8); offset += 64 * sizeof(u8); memset(output + offset, 0, 128); offset += 128 * sizeof(u8); - transpose_and_flatten_matrices(output + offset, -- (const u8 *)input->scaling_list_32x32 + (64 * sizeof(u8)), -- 1, 8); -+ cfg->flatten_matrices(output + offset, -+ (const u8 *)input->scaling_list_32x32 + (64 * sizeof(u8)), 1, 8); ++ variant->ops->flatten_matrices(output + offset, + (const u8 *)input->scaling_list_32x32 + (64 * sizeof(u8)), + 1, 8); offset += 64 * sizeof(u8); - memset(output + offset, 0, 128); +@@ -214,16 +184,17 @@ static void assemble_scalingdc(u8 *output, const struct v4l2_ctrl_hevc_scaling_m + memcpy(output + 6 * sizeof(u8), list_32x32, 6 * sizeof(u8)); } + +-static void translate_scaling_list(struct scaling_factor *output, ++static void translate_scaling_list(struct rkvdec_ctx *ctx, struct scaling_factor *output, + const struct v4l2_ctrl_hevc_scaling_matrix *input) + { +- assemble_scalingfactor0(output->scalingfactor0, input); ++ assemble_scalingfactor0(ctx, output->scalingfactor0, input); + memcpy(output->scalingfactor1, (const u8 *)input->scaling_list_4x4, 96); + assemble_scalingdc(output->scalingdc, input); + memset(output->reserved, 0, 4 * sizeof(u8)); + } + +-void rkvdec_hevc_assemble_hw_scaling_list(struct rkvdec_hevc_run *run, ++void rkvdec_hevc_assemble_hw_scaling_list(struct rkvdec_ctx *ctx, ++ struct rkvdec_hevc_run *run, + struct scaling_factor *scaling_factor, + struct v4l2_ctrl_hevc_scaling_matrix *cache) + { +@@ -233,7 +204,7 @@ void rkvdec_hevc_assemble_hw_scaling_list(struct rkvdec_hevc_run *run, + sizeof(struct v4l2_ctrl_hevc_scaling_matrix))) + return; + +- translate_scaling_list(scaling_factor, scaling); ++ translate_scaling_list(ctx, scaling_factor, scaling); + + memcpy(cache, scaling, + sizeof(struct v4l2_ctrl_hevc_scaling_matrix)); +diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h +index 111111111111..222222222222 100644 +--- a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h ++++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h +@@ -97,7 +97,8 @@ void compute_tiles_non_uniform(struct rkvdec_hevc_run *run, u16 log2_min_cb_size + s32 pic_in_cts_height, u16 *column_width, u16 *row_height); + void rkvdec_hevc_assemble_hw_rps(struct rkvdec_hevc_run *run, struct rkvdec_rps *rps, + struct v4l2_ctrl_hevc_ext_sps_st_rps *st_cache); +-void rkvdec_hevc_assemble_hw_scaling_list(struct rkvdec_hevc_run *run, ++void rkvdec_hevc_assemble_hw_scaling_list(struct rkvdec_ctx *ctx, ++ struct rkvdec_hevc_run *run, + struct scaling_factor *scaling_factor, + struct v4l2_ctrl_hevc_scaling_matrix *cache); + struct vb2_buffer *get_ref_buf(struct rkvdec_ctx *ctx, +diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c +index 111111111111..222222222222 100644 +--- a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c ++++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c +@@ -567,7 +567,7 @@ static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) + + rkvdec_hevc_run_preamble(ctx, &run); + +- rkvdec_hevc_assemble_hw_scaling_list(&run, &tbl->scaling_list, ++ rkvdec_hevc_assemble_hw_scaling_list(ctx, &run, &tbl->scaling_list, + &hevc_ctx->scaling_matrix_cache); + assemble_hw_pps(ctx, &run); + assemble_sw_rps(ctx, &run); +diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c +index 111111111111..222222222222 100644 +--- a/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c ++++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c +@@ -586,8 +586,7 @@ static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) + dev_warn_ratelimited(rkvdec->dev, "Long and short term RPS not set\n"); + } + +- rkvdec_hevc_assemble_hw_scaling_list(&run, +- &tbl->scaling_list, ++ rkvdec_hevc_assemble_hw_scaling_list(ctx, &run, &tbl->scaling_list, + &hevc_ctx->scaling_matrix_cache); + assemble_hw_pps(ctx, &run); + rkvdec_hevc_assemble_hw_rps(&run, &tbl->rps, &hevc_ctx->st_cache); diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c new file mode 100644 index 000000000000..111111111111 --- /dev/null +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c -@@ -0,0 +1,680 @@ +@@ -0,0 +1,720 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip VDPU383 HEVC backend @@ -13162,7 +9763,7 @@ index 000000000000..111111111111 + + memset(regs, 0, sizeof(*regs)); + -+ /* Set H264 mode */ ++ /* Set HEVC mode */ + regs->common.reg008_dec_mode = VDPU383_MODE_HEVC; + + /* Set input stream length */ @@ -13194,11 +9795,11 @@ index 000000000000..111111111111 + regs->common.reg010.err_prc_auto_gating_e = 1; + + /* Set timeout threshold */ -+ if (pixels < VDPU383_1080P_PIXELS) ++ if (pixels < RKVDEC_1080P_PIXELS) + regs->common.reg013_core_timeout_threshold = VDPU383_TIMEOUT_1080p; -+ else if (pixels < VDPU383_4K_PIXELS) ++ else if (pixels < RKVDEC_4K_PIXELS) + regs->common.reg013_core_timeout_threshold = VDPU383_TIMEOUT_4K; -+ else if (pixels < VDPU383_8K_PIXELS) ++ else if (pixels < RKVDEC_8K_PIXELS) + regs->common.reg013_core_timeout_threshold = VDPU383_TIMEOUT_8K; + else + regs->common.reg013_core_timeout_threshold = VDPU383_TIMEOUT_MAX; @@ -13261,6 +9862,28 @@ index 000000000000..111111111111 + rkvdec_write_regs(ctx); +} + ++static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, ++ const struct v4l2_ctrl_hevc_sps *sps) ++{ ++ if (sps->chroma_format_idc != 1) ++ /* Only 4:2:0 is supported */ ++ return -EINVAL; ++ ++ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) ++ /* Luma and chroma bit depth mismatch */ ++ return -EINVAL; ++ ++ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) ++ /* Only 8-bit and 10-bit are supported */ ++ return -EINVAL; ++ ++ if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width || ++ sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height) ++ return -EINVAL; ++ ++ return 0; ++} ++ +static int rkvdec_hevc_start(struct rkvdec_ctx *ctx) +{ + struct rkvdec_dev *rkvdec = ctx->dev; @@ -13324,8 +9947,18 @@ index 000000000000..111111111111 + + rkvdec_hevc_run_preamble(ctx, &run); + -+ rkvdec_hevc_assemble_hw_scaling_list(rkvdec, &run, -+ &tbl->scaling_list, ++ /* ++ * On vdpu383, not setting the long and short term ref sets leads to IOMMU page faults. ++ * To be on the safe side for this new v4l2 control, write an error in the log and mark ++ * the buffer as failed by returning an error here. ++ */ ++ if ((!ctx->has_sps_lt_rps && run.sps->num_long_term_ref_pics_sps) || ++ (!ctx->has_sps_st_rps && run.sps->num_short_term_ref_pic_sets)) { ++ dev_err_ratelimited(rkvdec->dev, "Long and short term RPS not set\n"); ++ return -EINVAL; ++ } ++ ++ rkvdec_hevc_assemble_hw_scaling_list(ctx, &run, &tbl->scaling_list, + &hevc_ctx->scaling_matrix_cache); + assemble_hw_pps(ctx, &run); + rkvdec_hevc_assemble_hw_rps(&run, &tbl->rps, &hevc_ctx->st_cache); @@ -13353,6 +9986,14 @@ index 000000000000..111111111111 + return 0; +} + ++static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) ++{ ++ if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS) ++ return rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); ++ ++ return 0; ++} ++ +const struct rkvdec_coded_fmt_ops rkvdec_vdpu383_hevc_fmt_ops = { + .adjust_fmt = rkvdec_hevc_adjust_fmt, + .start = rkvdec_hevc_start, @@ -13365,17 +10006,17 @@ diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/pla index 111111111111..222222222222 100644 --- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -@@ -526,6 +526,22 @@ static const struct rkvdec_coded_fmt_desc vdpu383_coded_fmts[] = { - .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, - .capability = RKVDEC_CAPABILITY_H264, - }, +@@ -499,6 +499,22 @@ static const struct rkvdec_coded_fmt_desc vdpu381_coded_fmts[] = { + }; + + static const struct rkvdec_coded_fmt_desc vdpu383_coded_fmts[] = { + { + .fourcc = V4L2_PIX_FMT_HEVC_SLICE, + .frmsize = { -+ .min_width = 16, ++ .min_width = 64, + .max_width = 65472, -+ .step_width = 16, -+ .min_height = 16, ++ .step_width = 64, ++ .min_height = 64, + .max_height = 65472, + .step_height = 16, + }, @@ -13385,11 +10026,11 @@ index 111111111111..222222222222 100644 + .decoded_fmts = rkvdec_hevc_decoded_fmts, + .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, + }, - }; - - static bool rkvdec_is_capable(struct rkvdec_ctx *ctx, unsigned int capability) -@@ -1456,6 +1472,78 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) - return cfg->irq_handler(ctx); + { + .fourcc = V4L2_PIX_FMT_H264_SLICE, + .frmsize = { +@@ -1447,6 +1463,78 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) + return variant->ops->irq_handler(ctx); } +/* @@ -13467,53 +10108,43 @@ index 111111111111..222222222222 100644 static void rkvdec_watchdog_func(struct work_struct *work) { struct rkvdec_dev *rkvdec; -@@ -1519,6 +1607,7 @@ static const struct rkvdec_config config_rkvdec = { - .coded_fmts_num = ARRAY_SIZE(rkvdec_coded_fmts), +@@ -1508,6 +1596,7 @@ static int rkvdec_disable_multicore(struct rkvdec_dev *rkvdec) + static const struct rkvdec_variant_ops rk3399_variant_ops = { .irq_handler = rk3399_irq_handler, - .fill_pixfmt_mp = v4l2_fill_pixfmt_mp, -+ .flatten_matrices = transpose_and_flatten_matrices, .colmv_size = rkvdec_colmv_size, ++ .flatten_matrices = transpose_and_flatten_matrices, }; -@@ -1543,6 +1632,7 @@ static const struct rkvdec_config config_vdpu381 = { + static const struct rkvdec_variant rk3288_rkvdec_variant = { +@@ -1551,6 +1640,7 @@ static const struct rcb_size_info vdpu381_rcb_sizes[] = { + static const struct rkvdec_variant_ops vdpu381_variant_ops = { .irq_handler = vdpu381_irq_handler, - .fill_pixfmt_mp = vdpu38x_fill_pixfmt_mp, .colmv_size = rkvdec_colmv_size, + .flatten_matrices = transpose_and_flatten_matrices, - .named_regs = true, }; -@@ -1568,6 +1658,7 @@ const struct rkvdec_config config_vdpu383 = { - .fill_pixfmt_mp = vdpu38x_fill_pixfmt_mp, - .colmv_size = rkvdec_vdpu383_colmv_size, - .fill_pixfmt_mp = vdpu38x_fill_pixfmt_mp, + static const struct rkvdec_variant vdpu381_variant = { +@@ -1577,6 +1667,7 @@ static const struct rcb_size_info vdpu383_rcb_sizes[] = { + static const struct rkvdec_variant_ops vdpu383_variant_ops = { + .irq_handler = vdpu383_irq_handler, + .colmv_size = vdpu383_colmv_size, + .flatten_matrices = vdpu383_flatten_matrices, - .named_regs = true, }; -@@ -1599,7 +1690,8 @@ static const struct rkvdec_variant rk3588_vdpu381_variant = { - - static const struct rkvdec_variant rk3576_vdpu383_variant = { - .config = &config_vdpu383, -- .capabilities = RKVDEC_CAPABILITY_H264, -+ .capabilities = RKVDEC_CAPABILITY_H264 | -+ RKVDEC_CAPABILITY_HEVC, - }; - - static const struct of_device_id of_rkvdec_match[] = { + static const struct rkvdec_variant vdpu383_variant = { diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.h b/drivers/media/platform/rockchip/rkvdec/rkvdec.h index 111111111111..222222222222 100644 --- a/drivers/media/platform/rockchip/rkvdec/rkvdec.h +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -@@ -124,6 +124,7 @@ struct rkvdec_config { - int (*fill_pixfmt_mp)(struct v4l2_pix_format_mplane *pix_mp, u32 pixelformat, - u32 width, u32 height); +@@ -74,6 +74,7 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) + struct rkvdec_variant_ops { + irqreturn_t (*irq_handler)(struct rkvdec_ctx *ctx); u32 (*colmv_size)(u16 width, u16 height); + void (*flatten_matrices)(u8 *output, const u8 *input, int matrices, int row_length); - bool named_regs; }; -@@ -193,5 +194,6 @@ extern const struct rkvdec_coded_fmt_ops rkvdec_vdpu381_hevc_fmt_ops; + struct rkvdec_variant { +@@ -192,5 +193,6 @@ extern const struct rkvdec_coded_fmt_ops rkvdec_vdpu381_hevc_fmt_ops; /* VDPU383 ops */ extern const struct rkvdec_coded_fmt_ops rkvdec_vdpu383_h264_fmt_ops; @@ -13523,3 +10154,184 @@ index 111111111111..222222222222 100644 -- Armbian +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Detlev Casanova +Date: Mon, 20 Oct 2025 17:20:08 -0400 +Subject: arm64: dts: rockchip: Add the vdpu381 Video Decoders on RK3588 + +Add the vdpu381 Video Decoders to the rk3588-base devicetree. + +The RK3588 based SoCs all embed 2 vdpu381 decoders. +This also adds the dedicated IOMMU controllers. + +Signed-off-by: Detlev Casanova +--- + arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 74 ++++++++++ + 1 file changed, 74 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +@@ -1353,6 +1353,70 @@ vepu121_3_mmu: iommu@fdbac800 { + #iommu-cells = <0>; + }; + ++ vdec0: video-codec@fdc38000 { ++ compatible = "rockchip,rk3588-vdec"; ++ reg = <0x0 0xfdc38100 0x0 0x500>, ++ <0x0 0xfdc38000 0x0 0x100>, ++ <0x0 0xfdc38600 0x0 0x100>; ++ reg-names = "function", "link", "cache"; ++ interrupts = ; ++ clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CA>, ++ <&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>; ++ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; ++ assigned-clocks = <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>, ++ <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>; ++ assigned-clock-rates = <800000000>, <600000000>, ++ <600000000>, <1000000000>; ++ iommus = <&vdec0_mmu>; ++ power-domains = <&power RK3588_PD_RKVDEC0>; ++ resets = <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVDEC0_CA>, ++ <&cru SRST_RKVDEC0_CORE>, <&cru SRST_RKVDEC0_HEVC_CA>; ++ reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; ++ sram = <&vdec0_sram>; ++ }; ++ ++ vdec0_mmu: iommu@fdc38700 { ++ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; ++ reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>; ++ interrupts = ; ++ clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>; ++ clock-names = "aclk", "iface"; ++ power-domains = <&power RK3588_PD_RKVDEC0>; ++ #iommu-cells = <0>; ++ }; ++ ++ vdec1: video-codec@fdc40000 { ++ compatible = "rockchip,rk3588-vdec"; ++ reg = <0x0 0xfdc40100 0x0 0x500>, ++ <0x0 0xfdc40000 0x0 0x100>, ++ <0x0 0xfdc40600 0x0 0x100>; ++ reg-names = "function", "link", "cache"; ++ interrupts = ; ++ clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CA>, ++ <&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>; ++ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; ++ assigned-clocks = <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>, ++ <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>; ++ assigned-clock-rates = <800000000>, <600000000>, ++ <600000000>, <1000000000>; ++ iommus = <&vdec1_mmu>; ++ power-domains = <&power RK3588_PD_RKVDEC1>; ++ resets = <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVDEC1_CA>, ++ <&cru SRST_RKVDEC1_CORE>, <&cru SRST_RKVDEC1_HEVC_CA>; ++ reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; ++ sram = <&vdec1_sram>; ++ }; ++ ++ vdec1_mmu: iommu@fdc40700 { ++ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; ++ reg = <0x0 0xfdc40700 0x0 0x40>, <0x0 0xfdc40740 0x0 0x40>; ++ interrupts = ; ++ clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>; ++ clock-names = "aclk", "iface"; ++ power-domains = <&power RK3588_PD_RKVDEC1>; ++ #iommu-cells = <0>; ++ }; ++ + av1d: video-codec@fdc70000 { + compatible = "rockchip,rk3588-av1-vpu"; + reg = <0x0 0xfdc70000 0x0 0x800>; +@@ -3249,6 +3313,16 @@ system_sram2: sram@ff001000 { + ranges = <0x0 0x0 0xff001000 0xef000>; + #address-cells = <1>; + #size-cells = <1>; ++ ++ vdec0_sram: codec-sram@0 { ++ reg = <0x0 0x78000>; ++ pool; ++ }; ++ ++ vdec1_sram: codec-sram@78000 { ++ reg = <0x78000 0x77000>; ++ pool; ++ }; + }; + + pinctrl: pinctrl { +-- +Armbian + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Detlev Casanova +Date: Mon, 20 Oct 2025 17:20:09 -0400 +Subject: arm64: dts: rockchip: Add the vdpu383 Video Decoder on rk3576 + +Add the vdpu383 Video Decoder variant to the RK3576 device tree. + +Also allow using the dedicated SRAM as a pool. + +Signed-off-by: Detlev Casanova +--- + arch/arm64/boot/dts/rockchip/rk3576.dtsi | 36 ++++++++++ + 1 file changed, 36 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi +index 111111111111..222222222222 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi +@@ -1277,6 +1277,41 @@ gpu: gpu@27800000 { + status = "disabled"; + }; + ++ vdec: video-codec@27b00000 { ++ compatible = "rockchip,rk3576-vdec"; ++ reg = <0x0 0x27b00100 0x0 0x500>, ++ <0x0 0x27b00000 0x0 0x100>, ++ <0x0 0x27b00600 0x0 0x100>; ++ reg-names = "function", "link", "cache"; ++ interrupts = ; ++ clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC>, ++ <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_CORE>, ++ <&cru CLK_RKVDEC_HEVC_CA>; ++ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; ++ assigned-clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru CLK_RKVDEC_CORE>, ++ <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_HEVC_CA>; ++ assigned-clock-rates = <600000000>, <600000000>, ++ <500000000>, <1000000000>; ++ iommus = <&vdec_mmu>; ++ power-domains = <&power RK3576_PD_VDEC>; ++ resets = <&cru SRST_A_RKVDEC_BIU>, <&cru SRST_H_RKVDEC_BIU>, ++ <&cru SRST_H_RKVDEC>, <&cru SRST_RKVDEC_CORE>, ++ <&cru SRST_RKVDEC_HEVC_CA>; ++ reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; ++ sram = <&rkvdec_sram>; ++ }; ++ ++ vdec_mmu: iommu@27b00800 { ++ compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu"; ++ reg = <0x0 0x27b00800 0x0 0x40>, <0x0 0x27b00900 0x0 0x40>; ++ interrupts = ; ++ clocks = <&cru CLK_RKVDEC_CORE>, <&cru HCLK_RKVDEC>; ++ clock-names = "aclk", "iface"; ++ power-domains = <&power RK3576_PD_VDEC>; ++ rockchip,disable-mmu-reset; ++ #iommu-cells = <0>; ++ }; ++ + vop: vop@27d00000 { + compatible = "rockchip,rk3576-vop"; + reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>; +@@ -2680,6 +2715,7 @@ sram: sram@3ff88000 { + /* start address and size should be 4k align */ + rkvdec_sram: rkvdec-sram@0 { + reg = <0x0 0x78000>; ++ pool; + }; + }; + +-- +Armbian + diff --git a/patch/kernel/archive/rockchip64-6.19/media-0002-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch b/patch/kernel/archive/rockchip64-6.19/media-0002-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch deleted file mode 100644 index 13b5aecefc..0000000000 --- a/patch/kernel/archive/rockchip64-6.19/media-0002-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: amazingfate -Date: Fri, 21 Jun 2024 16:32:55 +0800 -Subject: media: v4l2-core: Initialize h264 frame_mbs_only_flag as 1 - ---- - drivers/media/v4l2-core/v4l2-ctrls-core.c | 13 ++++++++++ - 1 file changed, 13 insertions(+) - -diff --git a/drivers/media/v4l2-core/v4l2-ctrls-core.c b/drivers/media/v4l2-core/v4l2-ctrls-core.c -index 111111111111..222222222222 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls-core.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls-core.c -@@ -111,6 +111,7 @@ static void std_init_compound(const struct v4l2_ctrl *ctrl, u32 idx, - struct v4l2_ctrl_vp9_frame *p_vp9_frame; - struct v4l2_ctrl_fwht_params *p_fwht_params; - struct v4l2_ctrl_h264_scaling_matrix *p_h264_scaling_matrix; -+ struct v4l2_ctrl_h264_sps *p_h264_sps; - struct v4l2_ctrl_av1_sequence *p_av1_sequence; - void *p = ptr.p + idx * ctrl->elem_size; - -@@ -179,6 +180,18 @@ static void std_init_compound(const struct v4l2_ctrl *ctrl, u32 idx, - */ - memset(p_h264_scaling_matrix, 16, sizeof(*p_h264_scaling_matrix)); - break; -+ case V4L2_CTRL_TYPE_H264_SPS: -+ p_h264_sps = p; -+ /* -+ * Without V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY, -+ * frame_mbs_only_flag set to 0 will translate to a miniumum -+ * height of 32 (see H.264 specification 7-8). Some driver may -+ * have a minimum size lower then 32, which would fail -+ * validation with the SPS value. Set this flag, so that there -+ * is now doubling in the height, allowing a valid default. -+ */ -+ p_h264_sps->flags = V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY; -+ break; - } - } - --- -Armbian -