From f8a272faa4e02b45b9eafc34560a1c7ad9681ff4 Mon Sep 17 00:00:00 2001 From: Jianfeng Liu Date: Sun, 12 Mar 2023 01:31:52 +0800 Subject: [PATCH] fix rockchip64 6.1 patches (#4917) * fix rockchip64 6.1 patches * remove LINUXFAMILY rk35xx for rk35xx edge --- config/sources/families/rk35xx.conf | 3 - .../board-pbp-add-dp-alt-mode.patch | 14 ++-- .../rockchip64-6.1/board-rock3a-cec.patch | 68 ------------------- .../board-rock3a-hdmi-sound.patch | 26 ------- .../rockchip64-6.1/board-rock3a-pcie.patch | 68 +++++++------------ 5 files changed, 33 insertions(+), 146 deletions(-) delete mode 100644 patch/kernel/archive/rockchip64-6.1/board-rock3a-hdmi-sound.patch diff --git a/config/sources/families/rk35xx.conf b/config/sources/families/rk35xx.conf index 7aa1b32f40..4d0e8bc9d6 100644 --- a/config/sources/families/rk35xx.conf +++ b/config/sources/families/rk35xx.conf @@ -27,11 +27,8 @@ case $BRANCH in ;; - # temporary until kernel 5.16 is well supported for rockchip64 - # it has to be its own family too edge) SKIP_BOOTSPLASH="yes" - LINUXFAMILY=rk35xx ;; diff --git a/patch/kernel/archive/rockchip64-6.1/board-pbp-add-dp-alt-mode.patch b/patch/kernel/archive/rockchip64-6.1/board-pbp-add-dp-alt-mode.patch index 4d5f349faf..bfe3b68627 100644 --- a/patch/kernel/archive/rockchip64-6.1/board-pbp-add-dp-alt-mode.patch +++ b/patch/kernel/archive/rockchip64-6.1/board-pbp-add-dp-alt-mode.patch @@ -154,16 +154,16 @@ index ba1387ab5..4d2eaeab1 100644 default: break; @@ -520,8 +564,14 @@ int dp_altmode_probe(struct typec_altmode *alt) - if (!(DP_CAP_DFP_D_PIN_ASSIGN(port->vdo) & - DP_CAP_UFP_D_PIN_ASSIGN(alt->vdo)) && - !(DP_CAP_UFP_D_PIN_ASSIGN(port->vdo) & -- DP_CAP_DFP_D_PIN_ASSIGN(alt->vdo))) + if (!(DP_CAP_PIN_ASSIGN_DFP_D(port->vdo) & + DP_CAP_PIN_ASSIGN_UFP_D(alt->vdo)) && + !(DP_CAP_PIN_ASSIGN_UFP_D(port->vdo) & +- DP_CAP_PIN_ASSIGN_DFP_D(alt->vdo))) - return -ENODEV; -+ DP_CAP_DFP_D_PIN_ASSIGN(alt->vdo))) { ++ DP_CAP_PIN_ASSIGN_DFP_D(alt->vdo))) { + dev_err(&alt->dev, "No compatible pin configuration found:"\ + "%04lx -> %04lx, %04lx <- %04lx", -+ DP_CAP_DFP_D_PIN_ASSIGN(port->vdo), DP_CAP_UFP_D_PIN_ASSIGN(alt->vdo), -+ DP_CAP_UFP_D_PIN_ASSIGN(port->vdo), DP_CAP_DFP_D_PIN_ASSIGN(alt->vdo)); ++ DP_CAP_PIN_ASSIGN_DFP_D(port->vdo), DP_CAP_PIN_ASSIGN_DFP_D(alt->vdo), ++ DP_CAP_PIN_ASSIGN_UFP_D(port->vdo), DP_CAP_PIN_ASSIGN_UFP_D(alt->vdo)); + return -ENODEV; + } + diff --git a/patch/kernel/archive/rockchip64-6.1/board-rock3a-cec.patch b/patch/kernel/archive/rockchip64-6.1/board-rock3a-cec.patch index b6ee947f7b..707fd53b4f 100644 --- a/patch/kernel/archive/rockchip64-6.1/board-rock3a-cec.patch +++ b/patch/kernel/archive/rockchip64-6.1/board-rock3a-cec.patch @@ -61,71 +61,3 @@ index a1c5fdf7d68f..c9cded3d2f1b 100644 }; --- - drivers/pinctrl/pinctrl-rockchip.c | 20 ++++++++++---------- - 1 file changed, 10 insertions(+), 10 deletions(-) - -diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c -index da974ff2d75d..849d5fa2a362 100644 ---- a/drivers/pinctrl/pinctrl-rockchip.c -+++ b/drivers/pinctrl/pinctrl-rockchip.c -@@ -926,19 +926,19 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = { - RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */ - RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */ - RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */ -- RK_MUXROUTE_PMU(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */ -+ RK_MUXROUTE_GRF(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */ - RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */ - RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */ - RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */ - RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */ - RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */ - RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */ -- RK_MUXROUTE_PMU(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */ -+ RK_MUXROUTE_GRF(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */ - RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */ - RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */ - RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */ -- RK_MUXROUTE_PMU(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */ -- RK_MUXROUTE_PMU(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */ -+ RK_MUXROUTE_GRF(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */ -+ RK_MUXROUTE_GRF(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */ - RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */ - RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */ - RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */ -@@ -964,7 +964,7 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = { - RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */ - RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */ - RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */ -- RK_MUXROUTE_PMU(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */ -+ RK_MUXROUTE_GRF(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */ - RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */ - RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */ - RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */ -@@ -973,8 +973,8 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = { - RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */ - RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */ - RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */ -- RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */ -- RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */ -+ RK_MUXROUTE_GRF(3, RK_PD6, 4, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */ -+ RK_MUXROUTE_GRF(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */ - RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */ - RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */ - RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */ -@@ -1004,13 +1004,13 @@ static struct rockchip_mux_route_data rk3568_mux_route_data[] = { - RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */ - RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */ - RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */ -- RK_MUXROUTE_PMU(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */ -+ RK_MUXROUTE_GRF(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */ - RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */ - RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */ -- RK_MUXROUTE_PMU(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */ -+ RK_MUXROUTE_GRF(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */ - RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */ - RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */ -- RK_MUXROUTE_PMU(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */ -+ RK_MUXROUTE_GRF(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */ - RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */ - RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */ - }; diff --git a/patch/kernel/archive/rockchip64-6.1/board-rock3a-hdmi-sound.patch b/patch/kernel/archive/rockchip64-6.1/board-rock3a-hdmi-sound.patch deleted file mode 100644 index 536682e128..0000000000 --- a/patch/kernel/archive/rockchip64-6.1/board-rock3a-hdmi-sound.patch +++ /dev/null @@ -1,26 +0,0 @@ -diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -index 0813c0c5abde..d1a2d9497cac 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -@@ -161,6 +161,10 @@ - status = "okay"; - }; - -+&hdmi_sound { -+ status = "okay"; -+}; -+ - &gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -@@ -406,6 +410,10 @@ - }; - }; - -+&i2s0_8ch { -+ status = "okay"; -+}; -+ - &i2s1_8ch { - rockchip,trcm-sync-tx-only; - status = "okay"; diff --git a/patch/kernel/archive/rockchip64-6.1/board-rock3a-pcie.patch b/patch/kernel/archive/rockchip64-6.1/board-rock3a-pcie.patch index 6b2e7b9fdb..8319a826a2 100644 --- a/patch/kernel/archive/rockchip64-6.1/board-rock3a-pcie.patch +++ b/patch/kernel/archive/rockchip64-6.1/board-rock3a-pcie.patch @@ -1,13 +1,12 @@ diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -index 53cf444ecb04..36222b0e3c69 100644 +index 8adf672709e8bf..c1fa917083ba64 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts -@@ -96,6 +96,37 @@ vcc5v0_usb_host: vcc5v0-usb-host { - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; +@@ -67,6 +67,37 @@ + regulator-boot-on; }; -+ -+ pcie30_avdd0v9: pcie30-avdd0v9 { + ++ pcie30_avdd0v9: pcie30-avdd0v9-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; @@ -17,7 +16,7 @@ index 53cf444ecb04..36222b0e3c69 100644 + vin-supply = <&vcc3v3_sys>; + }; + -+ pcie30_avdd1v8: pcie30-avdd1v8 { ++ pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; @@ -27,52 +26,37 @@ index 53cf444ecb04..36222b0e3c69 100644 + vin-supply = <&vcc3v3_sys>; + }; + -+ pcie30_3v3: gpio-regulator { -+ compatible = "regulator-gpio"; -+ regulator-name = "pcie30_3v3"; -+ regulator-min-microvolt = <100000>; ++ /* pi6c pcie clock generator */ ++ vcc3v3_pi6c_03: vcc3v3-pi6c-03-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_pi6c_03"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; -+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; -+ gpios-states = <0x1>; -+ states = <100000 0x0 -+ 3300000 0x1>; ++ vin-supply = <&vcc5v0_sys>; + }; - }; - - &cpu0 { -@@ -114,6 +145,10 @@ &cpu3 { - cpu-supply = <&vdd_cpu>; - }; - -+&combphy2 { -+ status = "okay"; -+}; + - &gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; -@@ -500,3 +535,24 @@ &usb2phy1_otg { - phy-supply = <&vcc5v0_usb_host>; + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; +@@ -546,6 +577,19 @@ status = "okay"; }; -+ + +&pcie30phy { ++ phy-supply = <&vcc3v3_pi6c_03>; + status = "okay"; +}; + +&pcie3x2 { -+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&pcie30_3v3>; -+ //num-lanes = <2>; ++ pinctrl-names = "default"; + pinctrl-0 = <&pcie30x2m1_pins>; -+ bus-scan-delay-ms = <1000>; ++ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + -+&pcie2x1 { -+ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&pcie30_3v3>; -+ pinctrl-0 = <&pcie20m1_pins>; -+ bus-scan-delay-ms = <1000>; -+ status = "okay"; -+}; + &pinctrl { + cam { + vcc_cam_en: vcc_cam_en {