diff --git a/patch/kernel/archive/rockchip64-5.15/add-board-orangepi-4-lts.patch b/patch/kernel/archive/rockchip64-5.15/add-board-orangepi-4-lts.patch
index 528cc309b2..3e8da91f3c 100644
--- a/patch/kernel/archive/rockchip64-5.15/add-board-orangepi-4-lts.patch
+++ b/patch/kernel/archive/rockchip64-5.15/add-board-orangepi-4-lts.patch
@@ -3,7 +3,7 @@ new file mode 100644
 index 00000000000..e0490aaa7ba
 --- /dev/null
 +++ b/arch/arm64/boot/dts/rockchip/rk3399-orangepi-4-lts.dts
-@@ -0,0 +1,1257 @@
+@@ -0,0 +1,1258 @@
 +/*
 + * SPDX-License-Identifier: (GPL-2.0+ or MIT)
 + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
@@ -528,8 +528,8 @@ index 00000000000..e0490aaa7ba
 +	rk808: pmic@1b {
 +		compatible = "rockchip,rk808";
 +		reg = <0x1b>;
-+		interrupt-parent = <&gpio1>;
-+		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
++		interrupt-parent = <&gpio2>;
++		interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
 +		#clock-cells = <1>;
 +		clock-output-names = "xin32k", "rk808-clkout2";
 +		pinctrl-names = "default";
@@ -875,6 +875,7 @@ index 00000000000..e0490aaa7ba
 +};
 +
 +&i2s0 {
++	rockchip,i2s-broken-burst-len;
 +	assigned-clocks = <&cru SCLK_I2SOUT_SRC>;
 +	assigned-clock-parents = <&cru SCLK_I2S0_8CH>;
 +	resets = <&cru SRST_I2S0_8CH>, <&cru SRST_H_I2S0_8CH>;
@@ -956,8 +957,8 @@ index 00000000000..e0490aaa7ba
 +};
 +
 +&sdio0 {
-+	clock-frequency = <50000000>;
-+	clock-freq-min-max = <200000 50000000>;
++	clock-frequency = <150000000>;
++	max-frequency = <150000000>;
 +	supports-sdio;
 +	bus-width = <4>;
 +	disable-wp;
@@ -1128,7 +1129,7 @@ index 00000000000..e0490aaa7ba
 +
 +	pmic {
 +		pmic_int_l: pmic-int-l {
-+			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
++			rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
 +		};
 +
 +		vsel1_gpio: vsel1-gpio {
diff --git a/patch/kernel/archive/rockchip64-5.19/add-board-orangepi-4-lts.patch b/patch/kernel/archive/rockchip64-5.19/add-board-orangepi-4-lts.patch
index 528cc309b2..3e8da91f3c 100644
--- a/patch/kernel/archive/rockchip64-5.19/add-board-orangepi-4-lts.patch
+++ b/patch/kernel/archive/rockchip64-5.19/add-board-orangepi-4-lts.patch
@@ -3,7 +3,7 @@ new file mode 100644
 index 00000000000..e0490aaa7ba
 --- /dev/null
 +++ b/arch/arm64/boot/dts/rockchip/rk3399-orangepi-4-lts.dts
-@@ -0,0 +1,1257 @@
+@@ -0,0 +1,1258 @@
 +/*
 + * SPDX-License-Identifier: (GPL-2.0+ or MIT)
 + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
@@ -528,8 +528,8 @@ index 00000000000..e0490aaa7ba
 +	rk808: pmic@1b {
 +		compatible = "rockchip,rk808";
 +		reg = <0x1b>;
-+		interrupt-parent = <&gpio1>;
-+		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
++		interrupt-parent = <&gpio2>;
++		interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
 +		#clock-cells = <1>;
 +		clock-output-names = "xin32k", "rk808-clkout2";
 +		pinctrl-names = "default";
@@ -875,6 +875,7 @@ index 00000000000..e0490aaa7ba
 +};
 +
 +&i2s0 {
++	rockchip,i2s-broken-burst-len;
 +	assigned-clocks = <&cru SCLK_I2SOUT_SRC>;
 +	assigned-clock-parents = <&cru SCLK_I2S0_8CH>;
 +	resets = <&cru SRST_I2S0_8CH>, <&cru SRST_H_I2S0_8CH>;
@@ -956,8 +957,8 @@ index 00000000000..e0490aaa7ba
 +};
 +
 +&sdio0 {
-+	clock-frequency = <50000000>;
-+	clock-freq-min-max = <200000 50000000>;
++	clock-frequency = <150000000>;
++	max-frequency = <150000000>;
 +	supports-sdio;
 +	bus-width = <4>;
 +	disable-wp;
@@ -1128,7 +1129,7 @@ index 00000000000..e0490aaa7ba
 +
 +	pmic {
 +		pmic_int_l: pmic-int-l {
-+			rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
++			rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
 +		};
 +
 +		vsel1_gpio: vsel1-gpio {