diff --git a/patch/kernel/sun50i-dev/unresolved/spi-patch-for-A64-4.10.x.patch b/patch/kernel/sun50i-dev/unresolved/spi-patch-for-A64-4.10.x.patch deleted file mode 100644 index b476f18e35..0000000000 --- a/patch/kernel/sun50i-dev/unresolved/spi-patch-for-A64-4.10.x.patch +++ /dev/null @@ -1,81 +0,0 @@ -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -index 02c0385f..19a8657b 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -@@ -51,6 +51,11 @@ - #address-cells = <1>; - #size-cells = <1>; - -+ aliases { -+ spi0 = &spi0; -+ spi1 = &spi1; -+ }; -+ - cpus { - #address-cells = <1>; - #size-cells = <0>; -@@ -304,6 +309,27 @@ - function = "emac"; - drive-strength = <40>; - }; -+ -+ spi0_pins_a: spi0@0 { -+ pins = "PC0", "PC1", "PC2"; -+ function = "spi0"; -+ }; -+ -+ spi0_cs0_pins_a: spi0_cs0@0 { -+ pins = "PC3"; -+ function = "spi0"; -+ }; -+ -+ spi1_pins_a: spi1@0 { -+ pins = "PD1", "PD2", "PD3"; -+ function = "spi1"; -+ }; -+ -+ spi1_cs0_pins_a: spi1_cs0@0 { -+ pins = "PD0"; -+ function = "spi1"; -+ }; -+ - }; - - uart0: serial@1c28000 { -@@ -431,5 +457,36 @@ - interrupts = , - ; - }; -+ -+ spi0: spi@01c68000 { -+ compatible = "allwinner,sun8i-h3-spi"; -+ reg = <0x01c68000 0x1000>; -+ interrupts = ; -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&spi0_pins_a>, <&spi0_cs0_pins_a>; -+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; -+ clock-names = "ahb", "mod"; -+ clock-frequency = <0x5f5e100>; -+ resets = <&ccu RST_BUS_SPI0>; -+ status = "disabled"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ spi1: spi@01c69000 { -+ compatible = "allwinner,sun8i-h3-spi"; -+ reg = <0x01c69000 0x1000>; -+ interrupts = ; -+ pinctrl-names = "default", "sleep"; -+ pinctrl-0 = <&spi1_pins_a>, <&spi1_cs0_pins_a>; -+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; -+ clock-names = "ahb", "mod"; -+ clock-frequency = <0x5f5e100>; -+ resets = <&ccu RST_BUS_SPI1>; -+ status = "disabled"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ - }; - };