From e4add7b8fd3f809c49d8c01d6dba0d9156ebbc38 Mon Sep 17 00:00:00 2001 From: Paolo Sabatino Date: Sun, 18 Jul 2021 14:06:02 +0000 Subject: [PATCH] rk322x: update rk322x-edge kernel config, add DMC patches and overlays --- config/kernel/linux-rk322x-edge.config | 317 +-- ...-fix-ddr-clock-gate-add-SIP-v2-calls.patch | 234 ++ ...d-ddr-clock-and-SIP-related-constant.patch | 67 + .../03-0003-extend-rockchip-dfi-driver.patch | 743 +++++++ .../rk322x-5.12/03-0004-add-dmc-driver.patch | 1936 +++++++++++++++++ .../rk322x-5.12/general-add-overlays.patch | 159 +- 6 files changed, 3210 insertions(+), 246 deletions(-) create mode 100644 patch/kernel/archive/rk322x-5.12/03-0001-fix-ddr-clock-gate-add-SIP-v2-calls.patch create mode 100644 patch/kernel/archive/rk322x-5.12/03-0002-add-ddr-clock-and-SIP-related-constant.patch create mode 100644 patch/kernel/archive/rk322x-5.12/03-0003-extend-rockchip-dfi-driver.patch create mode 100644 patch/kernel/archive/rk322x-5.12/03-0004-add-dmc-driver.patch diff --git a/config/kernel/linux-rk322x-edge.config b/config/kernel/linux-rk322x-edge.config index 97078d51d0..b965800047 100644 --- a/config/kernel/linux-rk322x-edge.config +++ b/config/kernel/linux-rk322x-edge.config @@ -1,13 +1,12 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.12.17 Kernel Configuration +# Linux/arm 5.10.50 Kernel Configuration # CONFIG_CC_VERSION_TEXT="arm-linux-gnueabihf-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0" CONFIG_CC_IS_GCC=y CONFIG_GCC_VERSION=80300 +CONFIG_LD_VERSION=232000000 CONFIG_CLANG_VERSION=0 -CONFIG_LD_IS_BFD=y -CONFIG_LD_VERSION=23200 CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y @@ -227,6 +226,7 @@ CONFIG_PERF_EVENTS=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLUB_DEBUG=y +# CONFIG_SLUB_MEMCG_SYSFS_ON is not set # CONFIG_COMPAT_BRK is not set # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -265,6 +265,7 @@ CONFIG_MMU=y CONFIG_ARCH_MMAP_RND_BITS_MIN=8 CONFIG_ARCH_MMAP_RND_BITS_MAX=16 CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set # CONFIG_ARCH_FOOTBRIDGE is not set # CONFIG_ARCH_IOP32X is not set @@ -321,6 +322,7 @@ CONFIG_ARCH_MULTI_V6_V7=y # CONFIG_SOC_DRA7XX is not set # end of TI OMAP/AM/DM/DRA Family +# CONFIG_ARCH_SIRF is not set # CONFIG_ARCH_QCOM is not set # CONFIG_ARCH_RDA is not set # CONFIG_ARCH_REALTEK is not set @@ -333,11 +335,13 @@ CONFIG_ARCH_ROCKCHIP=y # CONFIG_ARCH_STI is not set # CONFIG_ARCH_STM32 is not set # CONFIG_ARCH_SUNXI is not set +# CONFIG_ARCH_TANGO is not set # CONFIG_ARCH_TEGRA is not set # CONFIG_ARCH_UNIPHIER is not set # CONFIG_ARCH_U8500 is not set # CONFIG_ARCH_VEXPRESS is not set # CONFIG_ARCH_WM8850 is not set +# CONFIG_ARCH_ZX is not set # CONFIG_ARCH_ZYNQ is not set # @@ -449,6 +453,7 @@ CONFIG_AEABI=y CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_HAVE_ARCH_PFN_VALID=y CONFIG_HIGHMEM=y # CONFIG_HIGHPTE is not set CONFIG_CPU_SW_DOMAIN_PAN=y @@ -602,8 +607,6 @@ CONFIG_CRYPTO_SHA1_ARM_CE=m CONFIG_CRYPTO_SHA2_ARM_CE=m CONFIG_CRYPTO_SHA256_ARM=m CONFIG_CRYPTO_SHA512_ARM=m -CONFIG_CRYPTO_BLAKE2S_ARM=m -CONFIG_CRYPTO_BLAKE2B_NEON=m CONFIG_CRYPTO_AES_ARM=m CONFIG_CRYPTO_AES_ARM_BS=m CONFIG_CRYPTO_AES_ARM_CE=m @@ -620,6 +623,8 @@ CONFIG_AS_VFP_VMRS_FPINST=y # General architecture-dependent options # CONFIG_SET_FS=y +# CONFIG_OPROFILE is not set +CONFIG_HAVE_OPROFILE=y # CONFIG_KPROBES is not set # CONFIG_JUMP_LABEL is not set CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y @@ -643,17 +648,14 @@ CONFIG_HAVE_HW_BREAKPOINT=y CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y CONFIG_SECCOMP=y CONFIG_SECCOMP_FILTER=y -# CONFIG_SECCOMP_CACHE_DEBUG is not set CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y -CONFIG_LTO_NONE=y CONFIG_HAVE_CONTEXT_TRACKING=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y @@ -677,7 +679,6 @@ CONFIG_STRICT_MODULE_RWX=y CONFIG_ARCH_HAS_PHYS_TO_DMA=y # CONFIG_LOCK_EVENT_COUNTS is not set CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y -CONFIG_HAVE_ARCH_PFN_VALID=y # # GCOV-based kernel profiling @@ -687,7 +688,6 @@ CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y # end of GCOV-based kernel profiling CONFIG_HAVE_GCC_PLUGINS=y -# CONFIG_GCC_PLUGINS is not set # end of General architecture-dependent options CONFIG_RT_MUTEXES=y @@ -701,6 +701,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_MODULE_SIG is not set # CONFIG_MODULE_COMPRESS is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +# CONFIG_UNUSED_SYMBOLS is not set # CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y @@ -830,9 +831,9 @@ CONFIG_ZSMALLOC=y # CONFIG_ZSMALLOC_STAT is not set CONFIG_GENERIC_EARLY_IOREMAP=y CONFIG_IDLE_PAGE_TRACKING=y +CONFIG_FRAME_VECTOR=y # CONFIG_PERCPU_STATS is not set -# CONFIG_GUP_TEST is not set -CONFIG_KMAP_LOCAL=y +# CONFIG_GUP_BENCHMARK is not set # end of Memory Management options CONFIG_NET=y @@ -1046,7 +1047,6 @@ CONFIG_NF_DUP_NETDEV=m CONFIG_NFT_DUP_NETDEV=m CONFIG_NFT_FWD_NETDEV=m CONFIG_NFT_FIB_NETDEV=m -# CONFIG_NFT_REJECT_NETDEV is not set CONFIG_NF_FLOW_TABLE_INET=m CONFIG_NF_FLOW_TABLE=m CONFIG_NETFILTER_XTABLES=y @@ -1189,7 +1189,6 @@ CONFIG_IP_VS_SH=m CONFIG_IP_VS_MH=m CONFIG_IP_VS_SED=m CONFIG_IP_VS_NQ=m -# CONFIG_IP_VS_TWOS is not set # # IPVS SH scheduler @@ -1365,7 +1364,6 @@ CONFIG_BRIDGE=y CONFIG_BRIDGE_IGMP_SNOOPING=y CONFIG_BRIDGE_VLAN_FILTERING=y # CONFIG_BRIDGE_MRP is not set -# CONFIG_BRIDGE_CFM is not set CONFIG_HAVE_NET_DSA=y CONFIG_NET_DSA=m CONFIG_NET_DSA_TAG_8021Q=m @@ -1373,21 +1371,17 @@ CONFIG_NET_DSA_TAG_8021Q=m CONFIG_NET_DSA_TAG_BRCM_COMMON=m CONFIG_NET_DSA_TAG_BRCM=m CONFIG_NET_DSA_TAG_BRCM_PREPEND=m -# CONFIG_NET_DSA_TAG_HELLCREEK is not set CONFIG_NET_DSA_TAG_GSWIP=m -CONFIG_NET_DSA_TAG_DSA_COMMON=m CONFIG_NET_DSA_TAG_DSA=m CONFIG_NET_DSA_TAG_EDSA=m CONFIG_NET_DSA_TAG_MTK=m CONFIG_NET_DSA_TAG_KSZ=m CONFIG_NET_DSA_TAG_RTL4_A=m # CONFIG_NET_DSA_TAG_OCELOT is not set -# CONFIG_NET_DSA_TAG_OCELOT_8021Q is not set CONFIG_NET_DSA_TAG_QCA=m CONFIG_NET_DSA_TAG_LAN9303=m CONFIG_NET_DSA_TAG_SJA1105=m CONFIG_NET_DSA_TAG_TRAILER=m -# CONFIG_NET_DSA_TAG_XRS700X is not set CONFIG_VLAN_8021Q=y CONFIG_VLAN_8021Q_GVRP=y CONFIG_VLAN_8021Q_MVRP=y @@ -1526,7 +1520,9 @@ CONFIG_BATMAN_ADV_BLA=y CONFIG_BATMAN_ADV_DAT=y CONFIG_BATMAN_ADV_NC=y CONFIG_BATMAN_ADV_MCAST=y +# CONFIG_BATMAN_ADV_DEBUGFS is not set # CONFIG_BATMAN_ADV_DEBUG is not set +CONFIG_BATMAN_ADV_SYSFS=y # CONFIG_BATMAN_ADV_TRACING is not set CONFIG_OPENVSWITCH=m CONFIG_OPENVSWITCH_GRE=m @@ -1545,7 +1541,6 @@ CONFIG_NET_L3_MASTER_DEV=y # CONFIG_NET_NCSI is not set CONFIG_RPS=y CONFIG_RFS_ACCEL=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y CONFIG_XPS=y CONFIG_CGROUP_NET_PRIO=y CONFIG_CGROUP_NET_CLASSID=y @@ -1724,6 +1719,7 @@ CONFIG_MAC80211_VERBOSE_DEBUG=y # CONFIG_MAC80211_TDLS_DEBUG is not set # CONFIG_MAC80211_DEBUG_COUNTERS is not set CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_WIMAX is not set CONFIG_RFKILL=y CONFIG_RFKILL_LEDS=y CONFIG_RFKILL_INPUT=y @@ -1811,120 +1807,7 @@ CONFIG_GNSS=m # CONFIG_GNSS_MTK_SERIAL is not set CONFIG_GNSS_SIRF_SERIAL=m # CONFIG_GNSS_UBX_SERIAL is not set -CONFIG_MTD=y -# CONFIG_MTD_TESTS is not set - -# -# Partition parsers -# -# CONFIG_MTD_AR7_PARTS is not set -# CONFIG_MTD_CMDLINE_PARTS is not set -CONFIG_MTD_OF_PARTS=y -# CONFIG_MTD_AFS_PARTS is not set -# CONFIG_MTD_REDBOOT_PARTS is not set -# end of Partition parsers - -# -# User Modules And Translation Layers -# -# CONFIG_MTD_BLOCK is not set -# CONFIG_MTD_BLOCK_RO is not set -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_SM_FTL is not set -# CONFIG_MTD_OOPS is not set -# CONFIG_MTD_SWAP is not set -# CONFIG_MTD_PARTITIONED_MASTER is not set - -# -# RAM/ROM/Flash chip drivers -# -# CONFIG_MTD_CFI is not set -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set -# end of RAM/ROM/Flash chip drivers - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_PLATRAM is not set -# end of Mapping drivers for chip access - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_MCHP23K256 is not set -# CONFIG_MTD_SST25L is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOCG3 is not set -# end of Self-contained MTD device drivers - -# -# NAND -# -CONFIG_MTD_NAND_CORE=y -# CONFIG_MTD_ONENAND is not set -CONFIG_MTD_RAW_NAND=y - -# -# Raw/parallel NAND flash controllers -# -# CONFIG_MTD_NAND_DENALI_DT is not set -# CONFIG_MTD_NAND_BRCMNAND is not set -# CONFIG_MTD_NAND_MXIC is not set -# CONFIG_MTD_NAND_GPIO is not set -# CONFIG_MTD_NAND_PLATFORM is not set -# CONFIG_MTD_NAND_CADENCE is not set -# CONFIG_MTD_NAND_ARASAN is not set -# CONFIG_MTD_NAND_INTEL_LGM is not set -CONFIG_MTD_NAND_ROCKCHIP=y - -# -# Misc -# -# CONFIG_MTD_NAND_NANDSIM is not set -# CONFIG_MTD_NAND_DISKONCHIP is not set -# CONFIG_MTD_SPI_NAND is not set - -# -# ECC engine support -# -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set -# CONFIG_MTD_NAND_ECC_SW_BCH is not set -# end of ECC engine support -# end of NAND - -# -# LPDDR & LPDDR2 PCM memory drivers -# -# CONFIG_MTD_LPDDR is not set -# CONFIG_MTD_LPDDR2_NVM is not set -# end of LPDDR & LPDDR2 PCM memory drivers - -# CONFIG_MTD_SPI_NOR is not set -# CONFIG_MTD_UBI is not set -# CONFIG_MTD_HYPERBUS is not set +# CONFIG_MTD is not set CONFIG_DTC=y CONFIG_OF=y # CONFIG_OF_UNITTEST is not set @@ -1945,13 +1828,6 @@ CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_NULL_BLK is not set CONFIG_CDROM=y CONFIG_ZRAM=m -CONFIG_ZRAM_DEF_COMP_LZORLE=y -# CONFIG_ZRAM_DEF_COMP_ZSTD is not set -# CONFIG_ZRAM_DEF_COMP_LZ4 is not set -# CONFIG_ZRAM_DEF_COMP_LZO is not set -# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set -# CONFIG_ZRAM_DEF_COMP_842 is not set -CONFIG_ZRAM_DEF_COMP="lzo-rle" CONFIG_ZRAM_WRITEBACK=y # CONFIG_ZRAM_MEMORY_TRACKING is not set CONFIG_BLK_DEV_LOOP=y @@ -2172,13 +2048,12 @@ CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m CONFIG_NET_DSA_MICROCHIP_KSZ8795=m CONFIG_NET_DSA_MICROCHIP_KSZ8795_SPI=m CONFIG_NET_DSA_MV88E6XXX=m +CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y # CONFIG_NET_DSA_MV88E6XXX_PTP is not set # CONFIG_NET_DSA_MSCC_SEVILLE is not set # CONFIG_NET_DSA_AR9331 is not set CONFIG_NET_DSA_SJA1105=m # CONFIG_NET_DSA_SJA1105_PTP is not set -# CONFIG_NET_DSA_XRS700X_I2C is not set -# CONFIG_NET_DSA_XRS700X_MDIO is not set # CONFIG_NET_DSA_QCA8K is not set CONFIG_NET_DSA_REALTEK_SMI=m CONFIG_NET_DSA_SMSC_LAN9303=m @@ -2197,6 +2072,7 @@ CONFIG_ETHERNET=y CONFIG_NET_VENDOR_ARC=y CONFIG_ARC_EMAC_CORE=y CONFIG_EMAC_ROCKCHIP=y +# CONFIG_NET_VENDOR_AURORA is not set # CONFIG_NET_VENDOR_BROADCOM is not set CONFIG_NET_VENDOR_CADENCE=y # CONFIG_MACB is not set @@ -2244,7 +2120,6 @@ CONFIG_DWMAC_ROCKCHIP=y # CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_WIZNET is not set CONFIG_NET_VENDOR_XILINX=y -# CONFIG_XILINX_EMACLITE is not set # CONFIG_XILINX_AXI_EMAC is not set # CONFIG_XILINX_LL_TEMAC is not set CONFIG_PHYLINK=y @@ -2385,8 +2260,8 @@ CONFIG_USB_SIERRA_NET=m CONFIG_USB_VL600=m CONFIG_USB_NET_CH9200=m CONFIG_USB_NET_AQC111=m -# CONFIG_USB_RTL8153_ECM is not set CONFIG_WLAN=y +# CONFIG_WIRELESS_WDS is not set CONFIG_WLAN_VENDOR_ADMTEK=y CONFIG_ATH_COMMON=m CONFIG_WLAN_VENDOR_ATH=y @@ -2462,7 +2337,6 @@ CONFIG_MT76_LEDS=y CONFIG_MT76_USB=m CONFIG_MT76x02_LIB=m CONFIG_MT76x02_USB=m -CONFIG_MT76_CONNAC_LIB=m CONFIG_MT76x0_COMMON=m CONFIG_MT76x0U=m CONFIG_MT76x2_COMMON=m @@ -2502,6 +2376,7 @@ CONFIG_RTLWIFI_USB=m CONFIG_RTL8192C_COMMON=m CONFIG_RTL8XXXU=y # CONFIG_RTL8XXXU_UNTESTED is not set +CONFIG_RTL8723CS=m CONFIG_RTW88=m CONFIG_WLAN_VENDOR_RSI=y # CONFIG_RSI_91X is not set @@ -2514,6 +2389,7 @@ CONFIG_WLAN_VENDOR_TI=y # CONFIG_WLCORE is not set # CONFIG_RTL8822BS is not set CONFIG_RTL8723DU=m +CONFIG_RTL8723DS=m CONFIG_RTL8822BU=m CONFIG_RTL8188EU=m CONFIG_RTL8821CU=m @@ -2529,6 +2405,10 @@ CONFIG_WLAN_VENDOR_QUANTENNA=y # CONFIG_MAC80211_HWSIM is not set CONFIG_USB_NET_RNDIS_WLAN=y CONFIG_VIRT_WIFI=m + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# # CONFIG_WAN is not set # CONFIG_NETDEVSIM is not set CONFIG_NET_FAILOVER=m @@ -2541,6 +2421,7 @@ CONFIG_NET_FAILOVER=m CONFIG_INPUT=y CONFIG_INPUT_LEDS=y CONFIG_INPUT_FF_MEMLESS=y +CONFIG_INPUT_POLLDEV=y # CONFIG_INPUT_SPARSEKMAP is not set CONFIG_INPUT_MATRIXKMAP=y @@ -2632,6 +2513,7 @@ CONFIG_JOYSTICK_FSIA6B=m CONFIG_INPUT_TABLET=y # CONFIG_TABLET_USB_ACECAD is not set # CONFIG_TABLET_USB_AIPTEK is not set +# CONFIG_TABLET_USB_GTCO is not set # CONFIG_TABLET_USB_HANWANG is not set # CONFIG_TABLET_USB_KBTAB is not set # CONFIG_TABLET_USB_PEGASUS is not set @@ -2746,7 +2628,6 @@ CONFIG_INPUT_UINPUT=y # CONFIG_INPUT_PWM_VIBRA is not set # CONFIG_INPUT_RK805_PWRKEY is not set # CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set -# CONFIG_INPUT_DA7280_HAPTICS is not set # CONFIG_INPUT_ADXL34X is not set # CONFIG_INPUT_IMS_PCU is not set # CONFIG_INPUT_IQS269A is not set @@ -2840,6 +2721,7 @@ CONFIG_SERIAL_SIFIVE=m # CONFIG_SERIAL_BCM63XX is not set # CONFIG_SERIAL_ALTERA_JTAGUART is not set # CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set # CONFIG_SERIAL_XILINX_PS_UART is not set # CONFIG_SERIAL_ARC is not set # CONFIG_SERIAL_FSL_LPUART is not set @@ -2876,7 +2758,6 @@ CONFIG_TCG_TPM=y CONFIG_HW_RANDOM_TPM=y # CONFIG_TCG_TIS is not set # CONFIG_TCG_TIS_SPI is not set -# CONFIG_TCG_TIS_I2C_CR50 is not set # CONFIG_TCG_TIS_I2C_ATMEL is not set CONFIG_TCG_TIS_I2C_INFINEON=y # CONFIG_TCG_TIS_I2C_NUVOTON is not set @@ -3037,7 +2918,6 @@ CONFIG_PINCTRL_ROCKCHIP=y # CONFIG_PINCTRL_STMFX is not set # CONFIG_PINCTRL_RK805 is not set # CONFIG_PINCTRL_OCELOT is not set -# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set # # Renesas pinctrl drivers @@ -3119,13 +2999,8 @@ CONFIG_GPIO_MAX77650=m # # end of USB GPIO expanders -# -# Virtual GPIO drivers -# # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set -# end of Virtual GPIO drivers - CONFIG_W1=m CONFIG_W1_CON=y @@ -3169,7 +3044,6 @@ CONFIG_POWER_RESET=y # CONFIG_POWER_RESET_GPIO is not set CONFIG_POWER_RESET_GPIO_RESTART=y # CONFIG_POWER_RESET_LTC2952 is not set -# CONFIG_POWER_RESET_REGULATOR is not set # CONFIG_POWER_RESET_RESTART is not set # CONFIG_POWER_RESET_VERSATILE is not set CONFIG_POWER_RESET_SYSCON=y @@ -3202,7 +3076,6 @@ CONFIG_BATTERY_SBS=y CONFIG_CHARGER_GPIO=m # CONFIG_CHARGER_MANAGER is not set # CONFIG_CHARGER_LT3651 is not set -# CONFIG_CHARGER_LTC4162L is not set # CONFIG_CHARGER_DETECTOR_MAX14656 is not set # CONFIG_CHARGER_MAX77650 is not set # CONFIG_CHARGER_BQ2415X is not set @@ -3212,7 +3085,6 @@ CONFIG_CHARGER_GPIO=m # CONFIG_CHARGER_BQ2515X is not set # CONFIG_CHARGER_BQ25890 is not set # CONFIG_CHARGER_BQ25980 is not set -# CONFIG_CHARGER_BQ256XX is not set # CONFIG_CHARGER_SMB347 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set # CONFIG_CHARGER_RT9455 is not set @@ -3240,14 +3112,12 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set -# CONFIG_SENSORS_AHT10 is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set # CONFIG_SENSORS_ASPEED is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_CORSAIR_CPRO is not set -# CONFIG_SENSORS_CORSAIR_PSU is not set # CONFIG_SENSORS_DS620 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_F71805F is not set @@ -3269,7 +3139,6 @@ CONFIG_SENSORS_GPIO_FAN=y # CONFIG_SENSORS_LTC2947_I2C is not set # CONFIG_SENSORS_LTC2947_SPI is not set # CONFIG_SENSORS_LTC2990 is not set -# CONFIG_SENSORS_LTC2992 is not set # CONFIG_SENSORS_LTC4151 is not set # CONFIG_SENSORS_LTC4215 is not set # CONFIG_SENSORS_LTC4222 is not set @@ -3277,7 +3146,6 @@ CONFIG_SENSORS_GPIO_FAN=y # CONFIG_SENSORS_LTC4260 is not set # CONFIG_SENSORS_LTC4261 is not set # CONFIG_SENSORS_MAX1111 is not set -# CONFIG_SENSORS_MAX127 is not set # CONFIG_SENSORS_MAX16065 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX1668 is not set @@ -3292,7 +3160,6 @@ CONFIG_SENSORS_GPIO_FAN=y # CONFIG_SENSORS_MAX31790 is not set # CONFIG_SENSORS_MCP3021 is not set # CONFIG_SENSORS_TC654 is not set -# CONFIG_SENSORS_TPS23861 is not set # CONFIG_SENSORS_MR75203 is not set # CONFIG_SENSORS_ADCXX is not set # CONFIG_SENSORS_LM63 is not set @@ -3323,7 +3190,6 @@ CONFIG_SENSORS_GPIO_FAN=y # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set CONFIG_SENSORS_PWM_FAN=y -# CONFIG_SENSORS_SBTSI is not set # CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set @@ -3554,7 +3420,6 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_REGULATOR_ARIZONA_MICSUPP is not set # CONFIG_REGULATOR_BD718XX is not set # CONFIG_REGULATOR_CPCAP is not set -# CONFIG_REGULATOR_DA9121 is not set # CONFIG_REGULATOR_DA9210 is not set # CONFIG_REGULATOR_DA9211 is not set # CONFIG_REGULATOR_FAN53555 is not set @@ -3582,7 +3447,6 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_PCA9450 is not set -# CONFIG_REGULATOR_PF8X00 is not set # CONFIG_REGULATOR_PFUZE100 is not set # CONFIG_REGULATOR_PV88060 is not set # CONFIG_REGULATOR_PV88080 is not set @@ -3889,13 +3753,13 @@ CONFIG_V4L_PLATFORM_DRIVERS=y # CONFIG_VIDEO_CADENCE is not set # CONFIG_VIDEO_ASPEED is not set CONFIG_VIDEO_MUX=m -# CONFIG_VIDEO_ROCKCHIP_ISP1 is not set CONFIG_VIDEO_XILINX=m # CONFIG_VIDEO_XILINX_CSI2RXSS is not set CONFIG_VIDEO_XILINX_TPG=m CONFIG_VIDEO_XILINX_VTC=m CONFIG_V4L_MEM2MEM_DRIVERS=y # CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set +CONFIG_VIDEO_ROCKCHIP_IEP=m CONFIG_VIDEO_ROCKCHIP_RGA=m CONFIG_DVB_PLATFORM_DRIVERS=y CONFIG_DVB_C8SECTPFE=m @@ -4026,9 +3890,7 @@ CONFIG_VIDEO_CX25840=m # CONFIG_VIDEO_IMX274 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX319 is not set -# CONFIG_VIDEO_IMX334 is not set # CONFIG_VIDEO_IMX355 is not set -# CONFIG_VIDEO_OV02A10 is not set # CONFIG_VIDEO_OV2640 is not set # CONFIG_VIDEO_OV2659 is not set # CONFIG_VIDEO_OV2680 is not set @@ -4036,7 +3898,6 @@ CONFIG_VIDEO_CX25840=m # CONFIG_VIDEO_OV5640 is not set # CONFIG_VIDEO_OV5645 is not set # CONFIG_VIDEO_OV5647 is not set -# CONFIG_VIDEO_OV5648 is not set # CONFIG_VIDEO_OV6650 is not set # CONFIG_VIDEO_OV5670 is not set # CONFIG_VIDEO_OV5675 is not set @@ -4047,7 +3908,6 @@ CONFIG_VIDEO_CX25840=m # CONFIG_VIDEO_OV7670 is not set # CONFIG_VIDEO_OV7740 is not set # CONFIG_VIDEO_OV8856 is not set -# CONFIG_VIDEO_OV8865 is not set # CONFIG_VIDEO_OV9640 is not set # CONFIG_VIDEO_OV9650 is not set # CONFIG_VIDEO_OV13858 is not set @@ -4065,13 +3925,12 @@ CONFIG_VIDEO_CX25840=m # CONFIG_VIDEO_NOON010PC30 is not set # CONFIG_VIDEO_M5MOLS is not set # CONFIG_VIDEO_RDACM20 is not set -# CONFIG_VIDEO_RDACM21 is not set # CONFIG_VIDEO_RJ54N1 is not set # CONFIG_VIDEO_S5K6AA is not set # CONFIG_VIDEO_S5K6A3 is not set # CONFIG_VIDEO_S5K4ECGX is not set # CONFIG_VIDEO_S5K5BAF is not set -# CONFIG_VIDEO_CCS is not set +# CONFIG_VIDEO_SMIAPP is not set # CONFIG_VIDEO_ET8EK8 is not set # CONFIG_VIDEO_S5C73M3 is not set # end of Camera sensor devices @@ -4263,7 +4122,6 @@ CONFIG_DVB_GP8PSK_FE=m # CONFIG_DVB_AU8522_DTV is not set # CONFIG_DVB_AU8522_V4L is not set # CONFIG_DVB_S5H1411 is not set -# CONFIG_DVB_MXL692 is not set # # ISDB-T (terrestrial) frontends @@ -4378,7 +4236,6 @@ CONFIG_DRM_PANEL=y # # Display Panels # -# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set # CONFIG_DRM_PANEL_ARM_VERSATILE is not set # CONFIG_DRM_PANEL_LVDS is not set CONFIG_DRM_PANEL_SIMPLE=m @@ -4411,7 +4268,6 @@ CONFIG_DRM_PANEL_BRIDGE=y # CONFIG_DRM_CHRONTEL_CH7033 is not set CONFIG_DRM_DISPLAY_CONNECTOR=m # CONFIG_DRM_LONTIUM_LT9611 is not set -# CONFIG_DRM_LONTIUM_LT9611UXC is not set # CONFIG_DRM_ITE_IT66121 is not set # CONFIG_DRM_LVDS_CODEC is not set # CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set @@ -4434,7 +4290,6 @@ CONFIG_DRM_SIMPLE_BRIDGE=m # CONFIG_DRM_TI_TPD12S015 is not set # CONFIG_DRM_ANALOGIX_ANX6345 is not set # CONFIG_DRM_ANALOGIX_ANX78XX is not set -# CONFIG_DRM_ANALOGIX_ANX7625 is not set # CONFIG_DRM_I2C_ADV7511 is not set # CONFIG_DRM_CDNS_MHDP8546 is not set CONFIG_DRM_DW_HDMI=y @@ -4598,7 +4453,6 @@ CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y # CONFIG_SND_USB_VARIAX is not set CONFIG_SND_SOC=m CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y -# CONFIG_SND_SOC_ADI is not set # CONFIG_SND_SOC_AMD_ACP is not set # CONFIG_SND_ATMEL_SOC is not set # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set @@ -4618,7 +4472,6 @@ CONFIG_SND_SOC_FSL_AUDMIX=m # CONFIG_SND_SOC_FSL_SPDIF is not set # CONFIG_SND_SOC_FSL_ESAI is not set # CONFIG_SND_SOC_FSL_MICFIL is not set -# CONFIG_SND_SOC_FSL_XCVR is not set # CONFIG_SND_SOC_IMX_AUDMUX is not set # end of SoC Audio for Freescale CPUs @@ -4644,14 +4497,13 @@ CONFIG_SND_SOC_RK3288_HDMI_ANALOG=m CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=m CONFIG_SND_SOC_XILINX_SPDIF=m # CONFIG_SND_SOC_XTFPGA_I2S is not set +# CONFIG_ZX_TDM is not set CONFIG_SND_SOC_I2C_AND_SPI=m # # CODEC drivers # # CONFIG_SND_SOC_AC97_CODEC is not set -# CONFIG_SND_SOC_ADAU1372_I2C is not set -# CONFIG_SND_SOC_ADAU1372_SPI is not set # CONFIG_SND_SOC_ADAU1701 is not set # CONFIG_SND_SOC_ADAU1761_I2C is not set # CONFIG_SND_SOC_ADAU1761_SPI is not set @@ -4723,7 +4575,6 @@ CONFIG_SND_SOC_PCM1789_I2C=m # CONFIG_SND_SOC_PCM3060_SPI is not set # CONFIG_SND_SOC_PCM3168A_I2C is not set # CONFIG_SND_SOC_PCM3168A_SPI is not set -# CONFIG_SND_SOC_PCM5102A is not set # CONFIG_SND_SOC_PCM512x_I2C is not set # CONFIG_SND_SOC_PCM512x_SPI is not set CONFIG_SND_SOC_RK3328=m @@ -4731,10 +4582,9 @@ CONFIG_SND_SOC_RL6231=m CONFIG_SND_SOC_RT5616=m # CONFIG_SND_SOC_RT5631 is not set CONFIG_SND_SOC_RT5645=m -# CONFIG_SND_SOC_RT5659 is not set # CONFIG_SND_SOC_SGTL5000 is not set CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m -# CONFIG_SND_SOC_SIMPLE_MUX is not set +# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set CONFIG_SND_SOC_SPDIF=m CONFIG_SND_SOC_SSM2305=m # CONFIG_SND_SOC_SSM2602_SPI is not set @@ -4793,16 +4643,11 @@ CONFIG_SND_SOC_MAX9759=m CONFIG_SND_SOC_MT6351=m CONFIG_SND_SOC_MT6358=m # CONFIG_SND_SOC_MT6660 is not set -# CONFIG_SND_SOC_NAU8315 is not set CONFIG_SND_SOC_NAU8540=m # CONFIG_SND_SOC_NAU8810 is not set # CONFIG_SND_SOC_NAU8822 is not set # CONFIG_SND_SOC_NAU8824 is not set # CONFIG_SND_SOC_TPA6130A2 is not set -# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set -# CONFIG_SND_SOC_LPASS_VA_MACRO is not set -# CONFIG_SND_SOC_LPASS_RX_MACRO is not set -# CONFIG_SND_SOC_LPASS_TX_MACRO is not set # end of CODEC drivers CONFIG_SND_SIMPLE_CARD_UTILS=m @@ -4897,7 +4742,6 @@ CONFIG_HID_PICOLCD_BACKLIGHT=y CONFIG_HID_PICOLCD_LEDS=y CONFIG_HID_PICOLCD_CIR=y CONFIG_HID_PLANTRONICS=m -# CONFIG_HID_PLAYSTATION is not set CONFIG_HID_PRIMAX=m # CONFIG_HID_RETRODE is not set CONFIG_HID_ROCCAT=m @@ -4944,8 +4788,7 @@ CONFIG_USB_HIDDEV=y # # I2C HID support # -# CONFIG_I2C_HID_OF is not set -# CONFIG_I2C_HID_OF_GOODIX is not set +CONFIG_I2C_HID=y # end of I2C HID support # end of HID support @@ -5037,7 +4880,7 @@ CONFIG_USBIP_VHCI_NR_HCS=1 CONFIG_USBIP_HOST=m CONFIG_USBIP_VUDC=m # CONFIG_USBIP_DEBUG is not set -# CONFIG_USB_CDNS_SUPPORT is not set +# CONFIG_USB_CDNS3 is not set # CONFIG_USB_MUSB_HDRC is not set # CONFIG_USB_DWC3 is not set CONFIG_USB_DWC2=y @@ -5100,6 +4943,7 @@ CONFIG_USB_SERIAL_SIERRAWIRELESS=m CONFIG_USB_SERIAL_SYMBOL=m CONFIG_USB_SERIAL_TI=m CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_XIRCOM=m CONFIG_USB_SERIAL_WWAN=m CONFIG_USB_SERIAL_OPTION=m CONFIG_USB_SERIAL_OMNINET=m @@ -5109,7 +4953,6 @@ CONFIG_USB_SERIAL_WISHBONE=m CONFIG_USB_SERIAL_SSU100=m CONFIG_USB_SERIAL_QT2=m CONFIG_USB_SERIAL_UPD78F0730=m -# CONFIG_USB_SERIAL_XR is not set CONFIG_USB_SERIAL_DEBUG=m # @@ -5319,17 +5162,12 @@ CONFIG_LEDS_USER=m # CONFIG_LEDS_SPI_BYTE is not set # CONFIG_LEDS_TI_LMU_COMMON is not set -# -# Flash and Torch LED drivers -# - # # LED Triggers # CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_ONESHOT=y -# CONFIG_LEDS_TRIGGER_MTD is not set CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_BACKLIGHT=y CONFIG_LEDS_TRIGGER_CPU=y @@ -5346,13 +5184,6 @@ CONFIG_LEDS_TRIGGER_TRANSIENT=y # CONFIG_LEDS_TRIGGER_NETDEV is not set # CONFIG_LEDS_TRIGGER_PATTERN is not set # CONFIG_LEDS_TRIGGER_AUDIO is not set -CONFIG_LEDS_TRIGGER_TTY=m - -# -# LED Blink -# -CONFIG_LEDS_BLINK=y -# CONFIG_LEDS_BLINK_LGM is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC_ATOMIC_SCRUB=y @@ -5427,6 +5258,7 @@ CONFIG_RTC_DRV_DS1390=m CONFIG_RTC_DRV_MAX6916=m CONFIG_RTC_DRV_R9701=m CONFIG_RTC_DRV_RX4581=m +CONFIG_RTC_DRV_RX6110=m CONFIG_RTC_DRV_RS5C348=m CONFIG_RTC_DRV_MAX6902=m CONFIG_RTC_DRV_PCF2123=m @@ -5441,7 +5273,6 @@ CONFIG_RTC_DRV_DS3232_HWMON=y CONFIG_RTC_DRV_PCF2127=m CONFIG_RTC_DRV_RV3029C2=m CONFIG_RTC_DRV_RV3029_HWMON=y -CONFIG_RTC_DRV_RX6110=m # # Platform RTC drivers @@ -5477,7 +5308,6 @@ CONFIG_RTC_DRV_CADENCE=m # HID Sensor RTC drivers # # CONFIG_RTC_DRV_HID_SENSOR_TIME is not set -# CONFIG_RTC_DRV_GOLDFISH is not set CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set @@ -5517,7 +5347,6 @@ CONFIG_SYNC_FILE=y # CONFIG_SW_SYNC is not set # CONFIG_UDMABUF is not set # CONFIG_DMABUF_MOVE_NOTIFY is not set -# CONFIG_DMABUF_DEBUG is not set CONFIG_DMABUF_SELFTESTS=m # CONFIG_DMABUF_HEAPS is not set # end of DMABUF options @@ -5611,11 +5440,13 @@ CONFIG_STAGING_MEDIA=y CONFIG_VIDEO_HANTRO=m CONFIG_VIDEO_HANTRO_ROCKCHIP=y CONFIG_VIDEO_ROCKCHIP_VDEC=m +# CONFIG_VIDEO_ROCKCHIP_ISP1 is not set # # Android # CONFIG_ASHMEM=y +# CONFIG_ION is not set # end of Android # CONFIG_STAGING_BOARD is not set @@ -5669,7 +5500,6 @@ CONFIG_FIELDBUS_DEV=m CONFIG_HMS_ANYBUSS_BUS=m CONFIG_ARCX_ANYBUS_CONTROLLER=m CONFIG_HMS_PROFINET=m -# CONFIG_WIMAX is not set # CONFIG_WFX is not set # CONFIG_GOLDFISH is not set # CONFIG_CHROME_PLATFORMS is not set @@ -5688,7 +5518,7 @@ CONFIG_COMMON_CLK_SI544=m # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CDCE925 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set -# CONFIG_COMMON_CLK_AXI_CLKGEN is not set +# CONFIG_CLK_QORIQ is not set # CONFIG_COMMON_CLK_PWM is not set CONFIG_COMMON_CLK_VC5=m # CONFIG_COMMON_CLK_BD718XX is not set @@ -5700,7 +5530,6 @@ CONFIG_COMMON_CLK_ROCKCHIP=y # CONFIG_CLK_RK3188 is not set CONFIG_CLK_RK322X=y # CONFIG_CLK_RK3288 is not set -# CONFIG_XILINX_VCU is not set # CONFIG_HWSPINLOCK is not set # @@ -5721,7 +5550,6 @@ CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y CONFIG_MAILBOX=y # CONFIG_ARM_MHU is not set -# CONFIG_ARM_MHU_V2 is not set # CONFIG_PLATFORM_MHU is not set # CONFIG_PL320_MBOX is not set CONFIG_ROCKCHIP_MBOX=y @@ -5769,6 +5597,11 @@ CONFIG_ROCKCHIP_IOMMU=y # # end of Amlogic SoC drivers +# +# Aspeed SoC drivers +# +# end of Aspeed SoC drivers + # # Broadcom SoC drivers # @@ -5787,12 +5620,6 @@ CONFIG_ROCKCHIP_IOMMU=y # # end of i.MX SoC drivers -# -# Enable LiteX SoC Builder specific drivers -# -# CONFIG_LITEX_SOC_CONTROLLER is not set -# end of Enable LiteX SoC Builder specific drivers - # # Qualcomm SoC drivers # @@ -5806,6 +5633,7 @@ CONFIG_ROCKCHIP_PM_DOMAINS=y # # Xilinx SoC drivers # +# CONFIG_XILINX_VCU is not set # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers @@ -5823,8 +5651,11 @@ CONFIG_DEVFREQ_GOV_USERSPACE=y # # DEVFREQ Drivers # +# CONFIG_ARM_RK3328_DMC_DEVFREQ is not set +CONFIG_ARM_RK3228_DMC_DEVFREQ=y # CONFIG_ARM_RK3399_DMC_DEVFREQ is not set -# CONFIG_PM_DEVFREQ_EVENT is not set +CONFIG_PM_DEVFREQ_EVENT=y +CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y CONFIG_EXTCON=y # @@ -5838,7 +5669,6 @@ CONFIG_EXTCON=y # CONFIG_EXTCON_RT8973A is not set # CONFIG_EXTCON_SM5502 is not set # CONFIG_EXTCON_USB_GPIO is not set -# CONFIG_EXTCON_USBC_TUSB320 is not set CONFIG_MEMORY=y # CONFIG_ARM_PL172_MPMC is not set CONFIG_PL353_SMC=y @@ -6020,7 +5850,6 @@ CONFIG_AD5696_I2C=m CONFIG_AD5758=m # CONFIG_AD5761 is not set # CONFIG_AD5764 is not set -# CONFIG_AD5766 is not set # CONFIG_AD5770R is not set # CONFIG_AD5791 is not set # CONFIG_AD7303 is not set @@ -6201,7 +6030,6 @@ CONFIG_HID_SENSOR_MAGNETOMETER_3D=m # CONFIG_SENSORS_HMC5843_SPI is not set # CONFIG_SENSORS_RM3100_I2C is not set # CONFIG_SENSORS_RM3100_SPI is not set -# CONFIG_YAMAHA_YAS530 is not set # end of Magnetometer sensors # @@ -6227,7 +6055,6 @@ CONFIG_IIO_SYSFS_TRIGGER=y # # Linear and angular position sensors # -# CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE is not set # end of Linear and angular position sensors # @@ -6319,7 +6146,6 @@ CONFIG_MAX31856=m CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set -# CONFIG_PWM_ATMEL_TCB is not set # CONFIG_PWM_FSL_FTM is not set # CONFIG_PWM_PCA9685 is not set CONFIG_PWM_ROCKCHIP=y @@ -6396,7 +6222,6 @@ CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y CONFIG_ROCKCHIP_EFUSE=y CONFIG_ROCKCHIP_OTP=m -# CONFIG_NVMEM_RMEM is not set # # HW tracing support @@ -6489,6 +6314,7 @@ CONFIG_F2FS_FS_XATTR=y CONFIG_F2FS_FS_POSIX_ACL=y # CONFIG_F2FS_FS_SECURITY is not set # CONFIG_F2FS_CHECK_FS is not set +# CONFIG_F2FS_IO_TRACE is not set # CONFIG_F2FS_FAULT_INJECTION is not set # CONFIG_F2FS_FS_COMPRESSION is not set CONFIG_FS_POSIX_ACL=y @@ -6587,7 +6413,6 @@ CONFIG_HFSPLUS_FS=m # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set -# CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set CONFIG_SQUASHFS=m CONFIG_SQUASHFS_FILE_CACHE=y @@ -6612,7 +6437,6 @@ CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 # CONFIG_QNX6FS_FS is not set # CONFIG_ROMFS_FS is not set CONFIG_PSTORE=y -CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 CONFIG_PSTORE_DEFLATE_COMPRESS=m # CONFIG_PSTORE_LZO_COMPRESS is not set # CONFIG_PSTORE_LZ4_COMPRESS is not set @@ -6630,6 +6454,24 @@ CONFIG_PSTORE_RAM=y # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set # CONFIG_EROFS_FS is not set +CONFIG_AUFS_FS=m +CONFIG_AUFS_BRANCH_MAX_127=y +# CONFIG_AUFS_BRANCH_MAX_511 is not set +# CONFIG_AUFS_BRANCH_MAX_1023 is not set +# CONFIG_AUFS_BRANCH_MAX_32767 is not set +CONFIG_AUFS_SBILIST=y +# CONFIG_AUFS_HNOTIFY is not set +# CONFIG_AUFS_EXPORT is not set +# CONFIG_AUFS_XATTR is not set +# CONFIG_AUFS_FHSM is not set +# CONFIG_AUFS_RDU is not set +# CONFIG_AUFS_DIRREN is not set +# CONFIG_AUFS_SHWH is not set +# CONFIG_AUFS_BR_RAMFS is not set +# CONFIG_AUFS_BR_FUSE is not set +CONFIG_AUFS_BR_HFSPLUS=y +CONFIG_AUFS_BDEV_LOOP=y +# CONFIG_AUFS_DEBUG is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V2=y @@ -6666,7 +6508,6 @@ CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_ACL_SUPPORT=y CONFIG_NFS_COMMON=y -CONFIG_NFS_V4_2_SSC_HELPER=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y CONFIG_SUNRPC_BACKCHANNEL=y @@ -6687,7 +6528,6 @@ CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y # CONFIG_CIFS_DEBUG is not set # CONFIG_CIFS_DFS_UPCALL is not set -# CONFIG_CIFS_SWN_UPCALL is not set CONFIG_CIFS_FSCACHE=y # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set @@ -6898,13 +6738,17 @@ CONFIG_CRYPTO_POLY1305=m CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_RMD128=m CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_SHA3=m CONFIG_CRYPTO_SM3=m CONFIG_CRYPTO_STREEBOG=m +CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_WP512=m # @@ -6923,6 +6767,7 @@ CONFIG_CRYPTO_CAST6=m CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_FCRYPT=m CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m CONFIG_CRYPTO_CHACHA20=m CONFIG_CRYPTO_SEED=m CONFIG_CRYPTO_SERPENT=m @@ -6966,7 +6811,6 @@ CONFIG_CRYPTO_HASH_INFO=y # CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_LIB_ARC4=y -CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=m CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m CONFIG_CRYPTO_LIB_BLAKE2S=m CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m @@ -7105,7 +6949,6 @@ CONFIG_CMA_SIZE_SEL_MBYTES=y # CONFIG_CMA_SIZE_SEL_MAX is not set CONFIG_CMA_ALIGNMENT=8 # CONFIG_DMA_API_DEBUG is not set -# CONFIG_DMA_MAP_BENCHMARK is not set CONFIG_SGL_ALLOC=y CONFIG_CPU_RMAP=y CONFIG_DQL=y @@ -7130,8 +6973,6 @@ CONFIG_SBITMAP=y # CONFIG_STRING_SELFTEST is not set # end of Library routines -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y - # # Kernel hacking # @@ -7155,6 +6996,7 @@ CONFIG_DEBUG_BUGVERBOSE=y # Compile-time checks and compiler options # # CONFIG_DEBUG_INFO is not set +CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=1024 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set @@ -7208,12 +7050,9 @@ CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y # CONFIG_DEBUG_VIRTUAL is not set # CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_DEBUG_PER_CPU_MAPS is not set -# CONFIG_DEBUG_KMAP_LOCAL is not set # CONFIG_DEBUG_HIGHMEM is not set -CONFIG_HAVE_ARCH_KASAN=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y -# CONFIG_KASAN is not set # end of Memory Debugging # CONFIG_DEBUG_SHIRQ is not set @@ -7263,7 +7102,6 @@ CONFIG_DEBUG_SPINLOCK=y # CONFIG_SCF_TORTURE_TEST is not set # end of Lock Debugging (spinlocks, mutexes, etc...) -# CONFIG_DEBUG_IRQFLAGS is not set CONFIG_STACKTRACE=y # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set # CONFIG_DEBUG_KOBJECT is not set @@ -7330,19 +7168,16 @@ CONFIG_BRANCH_PROFILE_NONE=y CONFIG_BLK_DEV_IO_TRACE=y # CONFIG_UPROBE_EVENTS is not set CONFIG_FTRACE_MCOUNT_RECORD=y -CONFIG_FTRACE_MCOUNT_USE_RECORDMCOUNT=y # CONFIG_SYNTH_EVENTS is not set -# CONFIG_HIST_TRIGGERS is not set # CONFIG_TRACE_EVENT_INJECT is not set # CONFIG_TRACEPOINT_BENCHMARK is not set # CONFIG_RING_BUFFER_BENCHMARK is not set # CONFIG_TRACE_EVAL_MAP_FILE is not set -# CONFIG_FTRACE_RECORD_RECURSION is not set # CONFIG_FTRACE_STARTUP_TEST is not set # CONFIG_RING_BUFFER_STARTUP_TEST is not set -# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set # CONFIG_PREEMPTIRQ_DELAY_TEST is not set # CONFIG_SAMPLES is not set +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y CONFIG_STRICT_DEVMEM=y # CONFIG_IO_STRICT_DEVMEM is not set diff --git a/patch/kernel/archive/rk322x-5.12/03-0001-fix-ddr-clock-gate-add-SIP-v2-calls.patch b/patch/kernel/archive/rk322x-5.12/03-0001-fix-ddr-clock-gate-add-SIP-v2-calls.patch new file mode 100644 index 0000000000..ed7158039f --- /dev/null +++ b/patch/kernel/archive/rk322x-5.12/03-0001-fix-ddr-clock-gate-add-SIP-v2-calls.patch @@ -0,0 +1,234 @@ +From e039790fb29227f646e91e6d7ec7c3e89c584243 Mon Sep 17 00:00:00 2001 +From: Paolo Sabatino +Date: Tue, 6 Jul 2021 14:21:52 +0000 +Subject: [PATCH 1/5] rk3228/rk3328: fix ddr clock gate, add SIP v2 calls + +--- + drivers/clk/rockchip/clk-ddr.c | 130 ++++++++++++++++++++++++++++++ + drivers/clk/rockchip/clk-rk3228.c | 14 ++-- + drivers/clk/rockchip/clk-rk3328.c | 7 +- + drivers/clk/rockchip/clk.h | 3 +- + 4 files changed, 143 insertions(+), 11 deletions(-) + +diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c +index 86718c54e..b16b3795f 100644 +--- a/drivers/clk/rockchip/clk-ddr.c ++++ b/drivers/clk/rockchip/clk-ddr.c +@@ -87,6 +87,133 @@ static const struct clk_ops rockchip_ddrclk_sip_ops = { + .get_parent = rockchip_ddrclk_get_parent, + }; + ++/* See v4.4/include/dt-bindings/display/rk_fb.h */ ++#define SCREEN_NULL 0 ++#define SCREEN_HDMI 6 ++ ++static inline int rk_drm_get_lcdc_type(void) ++{ ++ return SCREEN_NULL; ++} ++ ++struct share_params { ++ u32 hz; ++ u32 lcdc_type; ++ u32 vop; ++ u32 vop_dclk_mode; ++ u32 sr_idle_en; ++ u32 addr_mcu_el3; ++ /* ++ * 1: need to wait flag1 ++ * 0: never wait flag1 ++ */ ++ u32 wait_flag1; ++ /* ++ * 1: need to wait flag1 ++ * 0: never wait flag1 ++ */ ++ u32 wait_flag0; ++ u32 complt_hwirq; ++ /* if need, add parameter after */ ++}; ++ ++struct rockchip_ddrclk_data { ++ u32 inited_flag; ++ void __iomem *share_memory; ++}; ++ ++static struct rockchip_ddrclk_data ddr_data; ++ ++static void rockchip_ddrclk_data_init(void) ++{ ++ struct arm_smccc_res res; ++ ++ arm_smccc_smc(ROCKCHIP_SIP_SHARE_MEM, ++ 1, SHARE_PAGE_TYPE_DDR, 0, ++ 0, 0, 0, 0, &res); ++ ++ if (!res.a0) { ++ ddr_data.share_memory = (void __iomem *)ioremap(res.a1, 1<<12); ++ ddr_data.inited_flag = 1; ++ } ++} ++ ++static int rockchip_ddrclk_sip_set_rate_v2(struct clk_hw *hw, ++ unsigned long drate, ++ unsigned long prate) ++{ ++ struct share_params *p; ++ struct arm_smccc_res res; ++ ++ if (!ddr_data.inited_flag) ++ rockchip_ddrclk_data_init(); ++ ++ p = (struct share_params *)ddr_data.share_memory; ++ ++ p->hz = drate; ++ p->lcdc_type = rk_drm_get_lcdc_type(); ++ p->wait_flag1 = 1; ++ p->wait_flag0 = 1; ++ ++ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, ++ SHARE_PAGE_TYPE_DDR, 0, ++ ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE, ++ 0, 0, 0, 0, &res); ++ ++ if ((int)res.a1 == -6) { ++ pr_err("%s: timeout, drate = %lumhz\n", __func__, drate/1000000); ++ /* TODO: rockchip_dmcfreq_wait_complete(); */ ++ } ++ ++ return res.a0; ++} ++ ++static unsigned long rockchip_ddrclk_sip_recalc_rate_v2 ++ (struct clk_hw *hw, unsigned long parent_rate) ++{ ++ struct arm_smccc_res res; ++ ++ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, ++ SHARE_PAGE_TYPE_DDR, 0, ++ ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE, ++ 0, 0, 0, 0, &res); ++ if (!res.a0) ++ return res.a1; ++ else ++ return 0; ++} ++ ++static long rockchip_ddrclk_sip_round_rate_v2(struct clk_hw *hw, ++ unsigned long rate, ++ unsigned long *prate) ++{ ++ struct share_params *p; ++ struct arm_smccc_res res; ++ ++ if (!ddr_data.inited_flag) ++ rockchip_ddrclk_data_init(); ++ ++ p = (struct share_params *)ddr_data.share_memory; ++ ++ p->hz = rate; ++ ++ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, ++ SHARE_PAGE_TYPE_DDR, 0, ++ ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE, ++ 0, 0, 0, 0, &res); ++ if (!res.a0) ++ return res.a1; ++ else ++ return 0; ++} ++ ++static const struct clk_ops rockchip_ddrclk_sip_ops_v2 = { ++ .recalc_rate = rockchip_ddrclk_sip_recalc_rate_v2, ++ .set_rate = rockchip_ddrclk_sip_set_rate_v2, ++ .round_rate = rockchip_ddrclk_sip_round_rate_v2, ++ .get_parent = rockchip_ddrclk_get_parent, ++}; ++ + struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, + const char *const *parent_names, + u8 num_parents, int mux_offset, +@@ -114,6 +241,9 @@ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, + case ROCKCHIP_DDRCLK_SIP: + init.ops = &rockchip_ddrclk_sip_ops; + break; ++ case ROCKCHIP_DDRCLK_SIP_V2: ++ init.ops = &rockchip_ddrclk_sip_ops_v2; ++ break; + default: + pr_err("%s: unsupported ddrclk type %d\n", __func__, ddr_flag); + kfree(ddrclk); +diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c +index 1f9176a5c..96393aa16 100644 +--- a/drivers/clk/rockchip/clk-rk3228.c ++++ b/drivers/clk/rockchip/clk-rk3228.c +@@ -218,9 +218,9 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { + RK2928_CLKSEL_CON(4), 8, 5, DFLAGS), + + /* PD_DDR */ +- COMPOSITE(0, "clk_ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED, +- RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, +- RK2928_CLKGATE_CON(0), 2, GFLAGS), ++ COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0, ++ RK2928_CLKSEL_CON(26), 8, 2, 0, 2, ++ ROCKCHIP_DDRCLK_SIP_V2), + GATE(0, "ddrphy4x", "clk_ddrphy_src", CLK_IGNORE_UNUSED, + RK2928_CLKGATE_CON(7), 1, GFLAGS), + FACTOR_GATE(0, "ddrc", "clk_ddrphy_src", CLK_IGNORE_UNUSED, 1, 4, +@@ -576,8 +576,8 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { + GATE(HCLK_M_CRYPTO, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS), + GATE(HCLK_S_CRYPTO, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS), + +- GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS), +- GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS), ++ GATE(0, "pclk_ddr_upctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS), ++ GATE(0, "pclk_ddr_mon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS), + GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(10), 2, GFLAGS), + + GATE(PCLK_EFUSE_1024, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS), +@@ -652,8 +652,8 @@ static const char *const rk3228_critical_clocks[] __initconst = { + "sclk_initmem_mbist", + "aclk_initmem", + "hclk_rom", +- "pclk_ddrupctl", +- "pclk_ddrmon", ++ "pclk_ddr_upctl", ++ "pclk_ddr_mon", + "pclk_msch_noc", + "pclk_stimer", + "pclk_ddrphy", +diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c +index cc18dbc18..5fdd611bb 100644 +--- a/drivers/clk/rockchip/clk-rk3328.c ++++ b/drivers/clk/rockchip/clk-rk3328.c +@@ -317,9 +317,10 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = { + RK3328_CLKGATE_CON(14), 1, GFLAGS), + + /* PD_DDR */ +- COMPOSITE(0, "clk_ddr", mux_ddrphy_p, CLK_IGNORE_UNUSED, +- RK3328_CLKSEL_CON(3), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, +- RK3328_CLKGATE_CON(0), 4, GFLAGS), ++ COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0, ++ RK3328_CLKSEL_CON(3), 8, 2, 0, 3, ++ ROCKCHIP_DDRCLK_SIP_V2), ++ + GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IGNORE_UNUSED, + RK3328_CLKGATE_CON(18), 6, GFLAGS), + GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED, +diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h +index ae059b774..fdaa81ebb 100644 +--- a/drivers/clk/rockchip/clk.h ++++ b/drivers/clk/rockchip/clk.h +@@ -363,7 +363,8 @@ struct clk *rockchip_clk_register_mmc(const char *name, + * DDRCLK flags, including method of setting the rate + * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate. + */ +-#define ROCKCHIP_DDRCLK_SIP BIT(0) ++#define ROCKCHIP_DDRCLK_SIP 0x01 ++#define ROCKCHIP_DDRCLK_SIP_V2 0x03 + + struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, + const char *const *parent_names, +-- +2.25.1 + diff --git a/patch/kernel/archive/rk322x-5.12/03-0002-add-ddr-clock-and-SIP-related-constant.patch b/patch/kernel/archive/rk322x-5.12/03-0002-add-ddr-clock-and-SIP-related-constant.patch new file mode 100644 index 0000000000..efeaace362 --- /dev/null +++ b/patch/kernel/archive/rk322x-5.12/03-0002-add-ddr-clock-and-SIP-related-constant.patch @@ -0,0 +1,67 @@ +From 95358ea4a4434ad4af5545b3f762508e4f015fc3 Mon Sep 17 00:00:00 2001 +From: Paolo Sabatino +Date: Tue, 6 Jul 2021 14:23:36 +0000 +Subject: [PATCH 2/5] rk3228/rk3328: add ddr clock and SIP related constants + and defines + +--- + include/dt-bindings/clock/rk3228-cru.h | 1 + + include/soc/rockchip/rockchip_sip.h | 24 ++++++++++++++++++++++++ + 2 files changed, 25 insertions(+) + +diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h +index de550ea56..911824731 100644 +--- a/include/dt-bindings/clock/rk3228-cru.h ++++ b/include/dt-bindings/clock/rk3228-cru.h +@@ -15,6 +15,7 @@ + #define ARMCLK 5 + + /* sclk gates (special clocks) */ ++#define SCLK_DDRCLK 64 + #define SCLK_SPI0 65 + #define SCLK_NANDC 67 + #define SCLK_SDMMC 68 +diff --git a/include/soc/rockchip/rockchip_sip.h b/include/soc/rockchip/rockchip_sip.h +index c46a9ae2a..34e653751 100644 +--- a/include/soc/rockchip/rockchip_sip.h ++++ b/include/soc/rockchip/rockchip_sip.h +@@ -6,6 +6,7 @@ + #ifndef __SOC_ROCKCHIP_SIP_H + #define __SOC_ROCKCHIP_SIP_H + ++#define ROCKCHIP_SIP_ATF_VERSION 0x82000001 + #define ROCKCHIP_SIP_DRAM_FREQ 0x82000008 + #define ROCKCHIP_SIP_CONFIG_DRAM_INIT 0x00 + #define ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE 0x01 +@@ -16,5 +17,28 @@ + #define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ 0x06 + #define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM 0x07 + #define ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD 0x08 ++#define ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION 0x08 ++#define ROCKCHIP_SIP_CONFIG_DRAM_POST_SET_RATE 0x09 ++#define ROCKCHIP_SIP_CONFIG_DRAM_SET_MSCH_RL 0x0a ++#define ROCKCHIP_SIP_CONFIG_DRAM_DEBUG 0x0b ++ ++#define ROCKCHIP_SIP_SHARE_MEM 0x82000009 ++#define ROCKCHIP_SIP_SIP_VERSION 0x8200000a ++ ++/* Rockchip Sip version */ ++#define ROCKCHIP_SIP_IMPLEMENT_V1 (1) ++#define ROCKCHIP_SIP_IMPLEMENT_V2 (2) ++ ++/* SIP_ACCESS_REG: read or write */ ++#define SECURE_REG_RD 0x0 ++#define SECURE_REG_WR 0x1 ++ ++/* Share mem page types */ ++typedef enum { ++ SHARE_PAGE_TYPE_INVALID = 0, ++ SHARE_PAGE_TYPE_UARTDBG, ++ SHARE_PAGE_TYPE_DDR, ++ SHARE_PAGE_TYPE_MAX, ++} share_page_type_t; + + #endif +-- +2.25.1 + diff --git a/patch/kernel/archive/rk322x-5.12/03-0003-extend-rockchip-dfi-driver.patch b/patch/kernel/archive/rk322x-5.12/03-0003-extend-rockchip-dfi-driver.patch new file mode 100644 index 0000000000..ef382a1f9f --- /dev/null +++ b/patch/kernel/archive/rk322x-5.12/03-0003-extend-rockchip-dfi-driver.patch @@ -0,0 +1,743 @@ +From 415ed43c9b64ca38bc433bd5dc0359292dd80380 Mon Sep 17 00:00:00 2001 +From: Paolo Sabatino +Date: Tue, 6 Jul 2021 14:25:41 +0000 +Subject: [PATCH 3/5] rk3228/rk3328: extend rockchip dfi driver + +--- + arch/arm/boot/dts/rk322x.dtsi | 7 + + drivers/devfreq/event/rockchip-dfi.c | 598 ++++++++++++++++++++++++--- + 2 files changed, 557 insertions(+), 48 deletions(-) + +diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi +index 3845abe92..13e0b42e9 100644 +--- a/arch/arm/boot/dts/rk322x.dtsi ++++ b/arch/arm/boot/dts/rk322x.dtsi +@@ -100,6 +100,13 @@ opp-1200000000 { + }; + }; + ++ dfi: dfi@11210000 { ++ reg = <0x11210000 0x400>; ++ compatible = "rockchip,rk3228-dfi"; ++ rockchip,grf = <&grf>; ++ status = "okay"; ++ }; ++ + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , +diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c +index 9a88faaf8..01fb84b99 100644 +--- a/drivers/devfreq/event/rockchip-dfi.c ++++ b/drivers/devfreq/event/rockchip-dfi.c +@@ -18,25 +18,68 @@ + #include + #include + +-#include +- +-#define RK3399_DMC_NUM_CH 2 +- ++#define PX30_PMUGRF_OS_REG2 0x208 ++ ++#define RK3128_GRF_SOC_CON0 0x140 ++#define RK3128_GRF_OS_REG1 0x1cc ++#define RK3128_GRF_DFI_WRNUM 0x220 ++#define RK3128_GRF_DFI_RDNUM 0x224 ++#define RK3128_GRF_DFI_TIMERVAL 0x22c ++#define RK3128_DDR_MONITOR_EN ((1 << (16 + 6)) + (1 << 6)) ++#define RK3128_DDR_MONITOR_DISB ((1 << (16 + 6)) + (0 << 6)) ++ ++#define RK3228_GRF_OS_REG2 0x5d0 ++ ++#define RK3288_PMU_SYS_REG2 0x9c ++#define RK3288_GRF_SOC_CON4 0x254 ++#define RK3288_GRF_SOC_STATUS(n) (0x280 + (n) * 4) ++#define RK3288_DFI_EN (0x30003 << 14) ++#define RK3288_DFI_DIS (0x30000 << 14) ++#define RK3288_LPDDR_SEL (0x10001 << 13) ++#define RK3288_DDR3_SEL (0x10000 << 13) ++ ++#define RK3328_GRF_OS_REG2 0x5d0 ++ ++#define RK3368_GRF_DDRC0_CON0 0x600 ++#define RK3368_GRF_SOC_STATUS5 0x494 ++#define RK3368_GRF_SOC_STATUS6 0x498 ++#define RK3368_GRF_SOC_STATUS8 0x4a0 ++#define RK3368_GRF_SOC_STATUS9 0x4a4 ++#define RK3368_GRF_SOC_STATUS10 0x4a8 ++#define RK3368_DFI_EN (0x30003 << 5) ++#define RK3368_DFI_DIS (0x30000 << 5) ++ ++#define MAX_DMC_NUM_CH 2 ++#define READ_DRAMTYPE_INFO(n) (((n) >> 13) & 0x7) ++#define READ_CH_INFO(n) (((n) >> 28) & 0x3) + /* DDRMON_CTRL */ +-#define DDRMON_CTRL 0x04 +-#define CLR_DDRMON_CTRL (0x1f0000 << 0) +-#define LPDDR4_EN (0x10001 << 4) +-#define HARDWARE_EN (0x10001 << 3) +-#define LPDDR3_EN (0x10001 << 2) +-#define SOFTWARE_EN (0x10001 << 1) +-#define SOFTWARE_DIS (0x10000 << 1) +-#define TIME_CNT_EN (0x10001 << 0) ++#define DDRMON_CTRL 0x04 ++#define CLR_DDRMON_CTRL (0x3f0000 << 0) ++#define DDR4_EN (0x10001 << 5) ++#define LPDDR4_EN (0x10001 << 4) ++#define HARDWARE_EN (0x10001 << 3) ++#define LPDDR2_3_EN (0x10001 << 2) ++#define SOFTWARE_EN (0x10001 << 1) ++#define SOFTWARE_DIS (0x10000 << 1) ++#define TIME_CNT_EN (0x10001 << 0) + + #define DDRMON_CH0_COUNT_NUM 0x28 + #define DDRMON_CH0_DFI_ACCESS_NUM 0x2c + #define DDRMON_CH1_COUNT_NUM 0x3c + #define DDRMON_CH1_DFI_ACCESS_NUM 0x40 + ++/* pmu grf */ ++#define PMUGRF_OS_REG2 0x308 ++ ++enum { ++ DDR4 = 0, ++ DDR3 = 3, ++ LPDDR2 = 5, ++ LPDDR3 = 6, ++ LPDDR4 = 7, ++ UNUSED = 0xFF ++}; ++ + struct dmc_usage { + u32 access; + u32 total; +@@ -50,33 +93,261 @@ struct dmc_usage { + struct rockchip_dfi { + struct devfreq_event_dev *edev; + struct devfreq_event_desc *desc; +- struct dmc_usage ch_usage[RK3399_DMC_NUM_CH]; ++ struct dmc_usage ch_usage[MAX_DMC_NUM_CH]; + struct device *dev; + void __iomem *regs; + struct regmap *regmap_pmu; ++ struct regmap *regmap_grf; ++ struct regmap *regmap_pmugrf; + struct clk *clk; ++ u32 dram_type; ++ /* ++ * available mask, 1: available, 0: not available ++ * each bit represent a channel ++ */ ++ u32 ch_msk; ++}; ++ ++static void rk3128_dfi_start_hardware_counter(struct devfreq_event_dev *edev) ++{ ++ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); ++ ++ regmap_write(info->regmap_grf, ++ RK3128_GRF_SOC_CON0, ++ RK3128_DDR_MONITOR_EN); ++} ++ ++static void rk3128_dfi_stop_hardware_counter(struct devfreq_event_dev *edev) ++{ ++ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); ++ ++ regmap_write(info->regmap_grf, ++ RK3128_GRF_SOC_CON0, ++ RK3128_DDR_MONITOR_DISB); ++} ++ ++static int rk3128_dfi_disable(struct devfreq_event_dev *edev) ++{ ++ rk3128_dfi_stop_hardware_counter(edev); ++ ++ return 0; ++} ++ ++static int rk3128_dfi_enable(struct devfreq_event_dev *edev) ++{ ++ rk3128_dfi_start_hardware_counter(edev); ++ ++ return 0; ++} ++ ++static int rk3128_dfi_set_event(struct devfreq_event_dev *edev) ++{ ++ return 0; ++} ++ ++static int rk3128_dfi_get_event(struct devfreq_event_dev *edev, ++ struct devfreq_event_data *edata) ++{ ++ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); ++ unsigned long flags; ++ u32 dfi_wr, dfi_rd, dfi_timer; ++ ++ local_irq_save(flags); ++ ++ rk3128_dfi_stop_hardware_counter(edev); ++ ++ regmap_read(info->regmap_grf, RK3128_GRF_DFI_WRNUM, &dfi_wr); ++ regmap_read(info->regmap_grf, RK3128_GRF_DFI_RDNUM, &dfi_rd); ++ regmap_read(info->regmap_grf, RK3128_GRF_DFI_TIMERVAL, &dfi_timer); ++ ++ edata->load_count = (dfi_wr + dfi_rd) * 4; ++ edata->total_count = dfi_timer; ++ ++ rk3128_dfi_start_hardware_counter(edev); ++ ++ local_irq_restore(flags); ++ ++ return 0; ++} ++ ++static const struct devfreq_event_ops rk3128_dfi_ops = { ++ .disable = rk3128_dfi_disable, ++ .enable = rk3128_dfi_enable, ++ .get_event = rk3128_dfi_get_event, ++ .set_event = rk3128_dfi_set_event, ++}; ++ ++static void rk3288_dfi_start_hardware_counter(struct devfreq_event_dev *edev) ++{ ++ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); ++ ++ regmap_write(info->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_EN); ++} ++ ++static void rk3288_dfi_stop_hardware_counter(struct devfreq_event_dev *edev) ++{ ++ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); ++ ++ regmap_write(info->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_DIS); ++} ++ ++static int rk3288_dfi_disable(struct devfreq_event_dev *edev) ++{ ++ rk3288_dfi_stop_hardware_counter(edev); ++ ++ return 0; ++} ++ ++static int rk3288_dfi_enable(struct devfreq_event_dev *edev) ++{ ++ rk3288_dfi_start_hardware_counter(edev); ++ ++ return 0; ++} ++ ++static int rk3288_dfi_set_event(struct devfreq_event_dev *edev) ++{ ++ return 0; ++} ++ ++static int rk3288_dfi_get_busier_ch(struct devfreq_event_dev *edev) ++{ ++ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); ++ u32 tmp, max = 0; ++ u32 i, busier_ch = 0; ++ u32 rd_count, wr_count, total_count; ++ ++ rk3288_dfi_stop_hardware_counter(edev); ++ ++ /* Find out which channel is busier */ ++ for (i = 0; i < MAX_DMC_NUM_CH; i++) { ++ if (!(info->ch_msk & BIT(i))) ++ continue; ++ regmap_read(info->regmap_grf, ++ RK3288_GRF_SOC_STATUS(11 + i * 4), &wr_count); ++ regmap_read(info->regmap_grf, ++ RK3288_GRF_SOC_STATUS(12 + i * 4), &rd_count); ++ regmap_read(info->regmap_grf, ++ RK3288_GRF_SOC_STATUS(14 + i * 4), &total_count); ++ info->ch_usage[i].access = (wr_count + rd_count) * 4; ++ info->ch_usage[i].total = total_count; ++ tmp = info->ch_usage[i].access; ++ if (tmp > max) { ++ busier_ch = i; ++ max = tmp; ++ } ++ } ++ rk3288_dfi_start_hardware_counter(edev); ++ ++ return busier_ch; ++} ++ ++static int rk3288_dfi_get_event(struct devfreq_event_dev *edev, ++ struct devfreq_event_data *edata) ++{ ++ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); ++ int busier_ch; ++ unsigned long flags; ++ ++ local_irq_save(flags); ++ busier_ch = rk3288_dfi_get_busier_ch(edev); ++ local_irq_restore(flags); ++ ++ edata->load_count = info->ch_usage[busier_ch].access; ++ edata->total_count = info->ch_usage[busier_ch].total; ++ ++ return 0; ++} ++ ++static const struct devfreq_event_ops rk3288_dfi_ops = { ++ .disable = rk3288_dfi_disable, ++ .enable = rk3288_dfi_enable, ++ .get_event = rk3288_dfi_get_event, ++ .set_event = rk3288_dfi_set_event, ++}; ++ ++static void rk3368_dfi_start_hardware_counter(struct devfreq_event_dev *edev) ++{ ++ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); ++ ++ regmap_write(info->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_EN); ++} ++ ++static void rk3368_dfi_stop_hardware_counter(struct devfreq_event_dev *edev) ++{ ++ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); ++ ++ regmap_write(info->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_DIS); ++} ++ ++static int rk3368_dfi_disable(struct devfreq_event_dev *edev) ++{ ++ rk3368_dfi_stop_hardware_counter(edev); ++ ++ return 0; ++} ++ ++static int rk3368_dfi_enable(struct devfreq_event_dev *edev) ++{ ++ rk3368_dfi_start_hardware_counter(edev); ++ ++ return 0; ++} ++ ++static int rk3368_dfi_set_event(struct devfreq_event_dev *edev) ++{ ++ return 0; ++} ++ ++static int rk3368_dfi_get_event(struct devfreq_event_dev *edev, ++ struct devfreq_event_data *edata) ++{ ++ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); ++ unsigned long flags; ++ u32 dfi0_wr, dfi0_rd, dfi1_wr, dfi1_rd, dfi_timer; ++ ++ local_irq_save(flags); ++ ++ rk3368_dfi_stop_hardware_counter(edev); ++ ++ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS5, &dfi0_wr); ++ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS6, &dfi0_rd); ++ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS9, &dfi1_wr); ++ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS10, &dfi1_rd); ++ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS8, &dfi_timer); ++ ++ edata->load_count = (dfi0_wr + dfi0_rd + dfi1_wr + dfi1_rd) * 2; ++ edata->total_count = dfi_timer; ++ ++ rk3368_dfi_start_hardware_counter(edev); ++ ++ local_irq_restore(flags); ++ ++ return 0; ++} ++ ++static const struct devfreq_event_ops rk3368_dfi_ops = { ++ .disable = rk3368_dfi_disable, ++ .enable = rk3368_dfi_enable, ++ .get_event = rk3368_dfi_get_event, ++ .set_event = rk3368_dfi_set_event, + }; + + static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev) + { + struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); + void __iomem *dfi_regs = info->regs; +- u32 val; +- u32 ddr_type; +- +- /* get ddr type */ +- regmap_read(info->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val); +- ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) & +- RK3399_PMUGRF_DDRTYPE_MASK; + + /* clear DDRMON_CTRL setting */ + writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL); + + /* set ddr type to dfi */ +- if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3) +- writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL); +- else if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4) ++ if (info->dram_type == LPDDR3 || info->dram_type == LPDDR2) ++ writel_relaxed(LPDDR2_3_EN, dfi_regs + DDRMON_CTRL); ++ else if (info->dram_type == LPDDR4) + writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL); ++ else if (info->dram_type == DDR4) ++ writel_relaxed(DDR4_EN, dfi_regs + DDRMON_CTRL); + + /* enable count, use software mode */ + writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL); +@@ -100,12 +371,22 @@ static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev) + rockchip_dfi_stop_hardware_counter(edev); + + /* Find out which channel is busier */ +- for (i = 0; i < RK3399_DMC_NUM_CH; i++) { +- info->ch_usage[i].access = readl_relaxed(dfi_regs + +- DDRMON_CH0_DFI_ACCESS_NUM + i * 20) * 4; ++ for (i = 0; i < MAX_DMC_NUM_CH; i++) { ++ if (!(info->ch_msk & BIT(i))) ++ continue; ++ + info->ch_usage[i].total = readl_relaxed(dfi_regs + + DDRMON_CH0_COUNT_NUM + i * 20); +- tmp = info->ch_usage[i].access; ++ ++ /* LPDDR4 BL = 16,other DDR type BL = 8 */ ++ tmp = readl_relaxed(dfi_regs + ++ DDRMON_CH0_DFI_ACCESS_NUM + i * 20); ++ if (info->dram_type == LPDDR4) ++ tmp *= 8; ++ else ++ tmp *= 4; ++ info->ch_usage[i].access = tmp; ++ + if (tmp > max) { + busier_ch = i; + max = tmp; +@@ -118,10 +399,14 @@ static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev) + + static int rockchip_dfi_disable(struct devfreq_event_dev *edev) + { ++ struct device *dev = &edev->dev; + struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); + + rockchip_dfi_stop_hardware_counter(edev); +- clk_disable_unprepare(info->clk); ++ if (info->clk) ++ clk_disable_unprepare(info->clk); ++ ++ dev_notice(dev,"Rockchip DFI interface disabled\n"); + + return 0; + } +@@ -129,20 +414,28 @@ static int rockchip_dfi_disable(struct devfreq_event_dev *edev) + static int rockchip_dfi_enable(struct devfreq_event_dev *edev) + { + struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); ++ struct device *dev = &edev->dev; + int ret; + +- ret = clk_prepare_enable(info->clk); +- if (ret) { +- dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ret); +- return ret; ++ if (info->clk) { ++ ret = clk_prepare_enable(info->clk); ++ if (ret) { ++ dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ++ ret); ++ return ret; ++ } + } + + rockchip_dfi_start_hardware_counter(edev); ++ ++ dev_notice(dev,"Rockchip DFI interface enabled\n"); ++ + return 0; + } + + static int rockchip_dfi_set_event(struct devfreq_event_dev *edev) + { ++ + return 0; + } + +@@ -151,8 +444,11 @@ static int rockchip_dfi_get_event(struct devfreq_event_dev *edev, + { + struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); + int busier_ch; ++ unsigned long flags; + ++ local_irq_save(flags); + busier_ch = rockchip_dfi_get_busier_ch(edev); ++ local_irq_restore(flags); + + edata->load_count = info->ch_usage[busier_ch].access; + edata->total_count = info->ch_usage[busier_ch].total; +@@ -167,22 +463,151 @@ static const struct devfreq_event_ops rockchip_dfi_ops = { + .set_event = rockchip_dfi_set_event, + }; + +-static const struct of_device_id rockchip_dfi_id_match[] = { +- { .compatible = "rockchip,rk3399-dfi" }, +- { }, +-}; +-MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match); ++static __init int px30_dfi_init(struct platform_device *pdev, ++ struct rockchip_dfi *data, ++ struct devfreq_event_desc *desc) ++{ ++ struct device_node *np = pdev->dev.of_node, *node; ++ struct resource *res; ++ u32 val; + +-static int rockchip_dfi_probe(struct platform_device *pdev) ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ data->regs = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(data->regs)) ++ return PTR_ERR(data->regs); ++ ++ node = of_parse_phandle(np, "rockchip,pmugrf", 0); ++ if (node) { ++ data->regmap_pmugrf = syscon_node_to_regmap(node); ++ if (IS_ERR(data->regmap_pmugrf)) ++ return PTR_ERR(data->regmap_pmugrf); ++ } ++ ++ regmap_read(data->regmap_pmugrf, PX30_PMUGRF_OS_REG2, &val); ++ data->dram_type = READ_DRAMTYPE_INFO(val); ++ data->ch_msk = 1; ++ data->clk = NULL; ++ ++ desc->ops = &rockchip_dfi_ops; ++ ++ return 0; ++} ++ ++static __init int rk3128_dfi_init(struct platform_device *pdev, ++ struct rockchip_dfi *data, ++ struct devfreq_event_desc *desc) ++{ ++ struct device_node *np = pdev->dev.of_node, *node; ++ ++ node = of_parse_phandle(np, "rockchip,grf", 0); ++ if (node) { ++ data->regmap_grf = syscon_node_to_regmap(node); ++ if (IS_ERR(data->regmap_grf)) ++ return PTR_ERR(data->regmap_grf); ++ } ++ ++ desc->ops = &rk3128_dfi_ops; ++ ++ return 0; ++} ++ ++static __init int rk3228_dfi_init(struct platform_device *pdev, ++ struct rockchip_dfi *data, ++ struct devfreq_event_desc *desc) + { ++ struct device_node *np = pdev->dev.of_node, *node; ++ struct resource *res; + struct device *dev = &pdev->dev; +- struct rockchip_dfi *data; +- struct devfreq_event_desc *desc; ++ u32 val; ++ ++ dev_notice(dev,"rk3228_dfi_init enter\n"); ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ data->regs = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(data->regs)) ++ return PTR_ERR(data->regs); ++ ++ node = of_parse_phandle(np, "rockchip,grf", 0); ++ if (node) { ++ data->regmap_grf = syscon_node_to_regmap(node); ++ if (IS_ERR(data->regmap_grf)) ++ return PTR_ERR(data->regmap_grf); ++ } ++ ++ regmap_read(data->regmap_grf, RK3228_GRF_OS_REG2, &val); ++ data->dram_type = READ_DRAMTYPE_INFO(val); ++ data->ch_msk = 1; ++ data->clk = NULL; ++ ++ desc->ops = &rockchip_dfi_ops; ++ ++ dev_notice(dev,"rk3228-dfi initialized, dram type: 0x%x, channels: %d\n", data->dram_type, data->ch_msk); ++ ++ return 0; ++} ++ ++static __init int rk3288_dfi_init(struct platform_device *pdev, ++ struct rockchip_dfi *data, ++ struct devfreq_event_desc *desc) ++{ + struct device_node *np = pdev->dev.of_node, *node; ++ u32 val; + +- data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL); +- if (!data) +- return -ENOMEM; ++ node = of_parse_phandle(np, "rockchip,pmu", 0); ++ if (node) { ++ data->regmap_pmu = syscon_node_to_regmap(node); ++ if (IS_ERR(data->regmap_pmu)) ++ return PTR_ERR(data->regmap_pmu); ++ } ++ ++ node = of_parse_phandle(np, "rockchip,grf", 0); ++ if (node) { ++ data->regmap_grf = syscon_node_to_regmap(node); ++ if (IS_ERR(data->regmap_grf)) ++ return PTR_ERR(data->regmap_grf); ++ } ++ ++ regmap_read(data->regmap_pmu, RK3288_PMU_SYS_REG2, &val); ++ data->dram_type = READ_DRAMTYPE_INFO(val); ++ data->ch_msk = READ_CH_INFO(val); ++ ++ if (data->dram_type == DDR3) ++ regmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4, ++ RK3288_DDR3_SEL); ++ else ++ regmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4, ++ RK3288_LPDDR_SEL); ++ ++ desc->ops = &rk3288_dfi_ops; ++ ++ return 0; ++} ++ ++static __init int rk3368_dfi_init(struct platform_device *pdev, ++ struct rockchip_dfi *data, ++ struct devfreq_event_desc *desc) ++{ ++ struct device *dev = &pdev->dev; ++ ++ if (!dev->parent || !dev->parent->of_node) ++ return -EINVAL; ++ ++ data->regmap_grf = syscon_node_to_regmap(dev->parent->of_node); ++ if (IS_ERR(data->regmap_grf)) ++ return PTR_ERR(data->regmap_grf); ++ ++ desc->ops = &rk3368_dfi_ops; ++ ++ return 0; ++} ++ ++static __init int rockchip_dfi_init(struct platform_device *pdev, ++ struct rockchip_dfi *data, ++ struct devfreq_event_desc *desc) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *np = pdev->dev.of_node, *node; ++ u32 val; + + data->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(data->regs)) +@@ -202,21 +627,98 @@ static int rockchip_dfi_probe(struct platform_device *pdev) + if (IS_ERR(data->regmap_pmu)) + return PTR_ERR(data->regmap_pmu); + } +- data->dev = dev; ++ ++ regmap_read(data->regmap_pmu, PMUGRF_OS_REG2, &val); ++ data->dram_type = READ_DRAMTYPE_INFO(val); ++ data->ch_msk = READ_CH_INFO(val); ++ ++ desc->ops = &rockchip_dfi_ops; ++ ++ return 0; ++} ++ ++static __init int rk3328_dfi_init(struct platform_device *pdev, ++ struct rockchip_dfi *data, ++ struct devfreq_event_desc *desc) ++{ ++ struct device_node *np = pdev->dev.of_node, *node; ++ struct resource *res; ++ u32 val; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ data->regs = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(data->regs)) ++ return PTR_ERR(data->regs); ++ ++ node = of_parse_phandle(np, "rockchip,grf", 0); ++ if (node) { ++ data->regmap_grf = syscon_node_to_regmap(node); ++ if (IS_ERR(data->regmap_grf)) ++ return PTR_ERR(data->regmap_grf); ++ } ++ ++ regmap_read(data->regmap_grf, RK3328_GRF_OS_REG2, &val); ++ data->dram_type = READ_DRAMTYPE_INFO(val); ++ data->ch_msk = 1; ++ data->clk = NULL; ++ ++ desc->ops = &rockchip_dfi_ops; ++ ++ return 0; ++} ++ ++static const struct of_device_id rockchip_dfi_id_match[] = { ++ { .compatible = "rockchip,px30-dfi", .data = px30_dfi_init }, ++ { .compatible = "rockchip,rk1808-dfi", .data = px30_dfi_init }, ++ { .compatible = "rockchip,rk3128-dfi", .data = rk3128_dfi_init }, ++ { .compatible = "rockchip,rk3228-dfi", .data = rk3228_dfi_init }, ++ { .compatible = "rockchip,rk3288-dfi", .data = rk3288_dfi_init }, ++ { .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init }, ++ { .compatible = "rockchip,rk3368-dfi", .data = rk3368_dfi_init }, ++ { .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match); ++ ++static int rockchip_dfi_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct rockchip_dfi *data; ++ struct devfreq_event_desc *desc; ++ struct device_node *np = pdev->dev.of_node; ++ const struct of_device_id *match; ++ int (*init)(struct platform_device *pdev, struct rockchip_dfi *data, ++ struct devfreq_event_desc *desc); ++ ++ data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL); ++ if (!data) ++ return -ENOMEM; + + desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); + if (!desc) + return -ENOMEM; + +- desc->ops = &rockchip_dfi_ops; ++ match = of_match_node(rockchip_dfi_id_match, pdev->dev.of_node); ++ if (match) { ++ init = match->data; ++ if (init) { ++ if (init(pdev, data, desc)) ++ return -EINVAL; ++ } else { ++ return 0; ++ } ++ } else { ++ return 0; ++ } ++ + desc->driver_data = data; + desc->name = np->name; + data->desc = desc; ++ data->dev = dev; + +- data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc); ++ data->edev = devm_devfreq_event_add_edev(dev, desc); + if (IS_ERR(data->edev)) { +- dev_err(&pdev->dev, +- "failed to add devfreq-event device\n"); ++ dev_err(dev, "failed to add devfreq-event device\n"); + return PTR_ERR(data->edev); + } + +-- +2.25.1 diff --git a/patch/kernel/archive/rk322x-5.12/03-0004-add-dmc-driver.patch b/patch/kernel/archive/rk322x-5.12/03-0004-add-dmc-driver.patch new file mode 100644 index 0000000000..197f1f94c5 --- /dev/null +++ b/patch/kernel/archive/rk322x-5.12/03-0004-add-dmc-driver.patch @@ -0,0 +1,1936 @@ +From e7c97c57e2d5040e90662459239bc28c8ea89be5 Mon Sep 17 00:00:00 2001 +From: Paolo Sabatino +Date: Wed, 7 Jul 2021 19:27:03 +0000 +Subject: [PATCH] rk3228/rk3328: add dmc driver + +--- + arch/arm/boot/dts/rk322x.dtsi | 69 +- + drivers/devfreq/Kconfig | 24 + + drivers/devfreq/Makefile | 2 + + drivers/devfreq/rk3228_dmc.c | 623 ++++++++++++++ + drivers/devfreq/rk3328_dmc.c | 846 +++++++++++++++++++ + include/dt-bindings/clock/rockchip-ddr.h | 63 ++ + include/dt-bindings/memory/rockchip,rk322x.h | 90 ++ + 7 files changed, 1714 insertions(+), 3 deletions(-) + create mode 100644 drivers/devfreq/rk3228_dmc.c + create mode 100644 drivers/devfreq/rk3328_dmc.c + create mode 100644 include/dt-bindings/clock/rockchip-ddr.h + create mode 100644 include/dt-bindings/memory/rockchip,rk322x.h + +diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi +index 13e0b42e9..90002b43d 100644 +--- a/arch/arm/boot/dts/rk322x.dtsi ++++ b/arch/arm/boot/dts/rk322x.dtsi +@@ -7,6 +7,9 @@ + #include + #include + #include ++#include ++#include ++ + + / { + #address-cells = <1>; +@@ -107,6 +110,68 @@ dfi: dfi@11210000 { + status = "okay"; + }; + ++ dmc: dmc@11200000 { ++ compatible = "rockchip,rk3228-dmc", "rockchip,rk322x-dram"; ++ reg = <0x11200000 0x400>; ++ clocks = <&cru SCLK_DDRCLK>; ++ clock-names = "ddr_sclk"; ++ operating-points-v2 = <&dmc_opp_table>; ++ rockchip,dram_timing = <&dram_timing>; ++ rockchip,grf = <&grf>; ++ devfreq-events = <&dfi>; ++ upthreshold = <15>; ++ downdifferential = <10>; ++ #cooling-cells = <2>; ++ status = "disabled"; ++ }; ++ ++ dmc_opp_table: dmc-opp-table { ++ compatible = "operating-points-v2"; ++ ++ opp-330000000 { ++ opp-hz = /bits/ 64 <330000000>; ++ opp-microvolt = <1050000 1000000 1200000>; ++ }; ++ opp-534000000 { ++ opp-hz = /bits/ 64 <534000000>; ++ opp-microvolt = <1050000 1000000 1200000>; ++ }; ++ opp-660000000 { ++ opp-hz = /bits/ 64 <660000000>; ++ opp-microvolt = <1100000 1000000 1200000>; ++ }; ++ opp-786000000 { ++ opp-hz = /bits/ 64 <786000000>; ++ opp-microvolt = <1150000 1000000 1200000>; ++ status = "disabled"; ++ }; ++ }; ++ ++ dram_timing: dram-timing { ++ compatible = "rockchip,dram-timing"; ++ dram_spd_bin = ; ++ sr_idle = <0x18>; ++ pd_idle = <0x20>; ++ dram_dll_disb_freq = <300>; ++ phy_dll_disb_freq = <400>; ++ dram_odt_disb_freq = <333>; ++ phy_odt_disb_freq = <333>; ++ ddr3_drv = ; ++ ddr3_odt = ; ++ lpddr3_drv = ; ++ lpddr3_odt = ; ++ lpddr2_drv = ; ++ /* lpddr2 not supported odt */ ++ phy_ddr3_clk_drv = ; ++ phy_ddr3_cmd_drv = ; ++ phy_ddr3_dqs_drv = ; ++ phy_ddr3_odt = ; ++ phy_lp23_clk_drv = ; ++ phy_lp23_cmd_drv = ; ++ phy_lp23_dqs_drv = ; ++ phy_lp3_odt = ; ++ }; ++ + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , +@@ -669,17 +734,17 @@ gpu_opp_table: opp-table2 { + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; +- opp-microvolt = <1050000>; ++ opp-microvolt = <1050000 1000000 1200000>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; +- opp-microvolt = <1050000>; ++ opp-microvolt = <1050000 1000000 1200000>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; +- opp-microvolt = <1150000>; ++ opp-microvolt = <1150000 1000000 1200000>; + }; + }; + +diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig +index 37dc40d1f..5f864a855 100644 +--- a/drivers/devfreq/Kconfig ++++ b/drivers/devfreq/Kconfig +@@ -131,6 +131,30 @@ config ARM_TEGRA20_DEVFREQ + It reads Memory Controller counters and adjusts the operating + frequencies and voltages with OPP support. + ++config ARM_RK3328_DMC_DEVFREQ ++ tristate "ARM RK3328 DMC DEVFREQ Driver" ++ depends on ARCH_ROCKCHIP ++ select DEVFREQ_EVENT_ROCKCHIP_DFI ++ select DEVFREQ_GOV_SIMPLE_ONDEMAND ++ select PM_DEVFREQ_EVENT ++ select PM_OPP ++ help ++ This adds the DEVFREQ driver for the RK3328 DMC(Dynamic Memory Controller). ++ It sets the frequency for the memory controller and reads the usage counts ++ from hardware. ++ ++config ARM_RK3228_DMC_DEVFREQ ++ tristate "ARM RK3228 DMC DEVFREQ Driver" ++ depends on ARCH_ROCKCHIP ++ select DEVFREQ_EVENT_ROCKCHIP_DFI ++ select DEVFREQ_GOV_SIMPLE_ONDEMAND ++ select PM_DEVFREQ_EVENT ++ select PM_OPP ++ help ++ This adds the DEVFREQ driver for the RK3228 DMC(Dynamic Memory Controller). ++ It sets the frequency for the memory controller and reads the usage counts ++ from hardware. ++ + config ARM_RK3399_DMC_DEVFREQ + tristate "ARM RK3399 DMC DEVFREQ Driver" + depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \ +diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile +index 3ca1ad0ec..7d6d7be25 100644 +--- a/drivers/devfreq/Makefile ++++ b/drivers/devfreq/Makefile +@@ -12,6 +12,8 @@ obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o + obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o + obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o + obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o ++obj-$(CONFIG_ARM_RK3328_DMC_DEVFREQ) += rk3328_dmc.o ++obj-$(CONFIG_ARM_RK3228_DMC_DEVFREQ) += rk3228_dmc.o + obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o + obj-$(CONFIG_ARM_TEGRA20_DEVFREQ) += tegra20-devfreq.o + +diff --git a/drivers/devfreq/rk3328_dmc.c b/drivers/devfreq/rk3328_dmc.c +new file mode 100644 +index 000000000..5dcea91cf +--- /dev/null ++++ b/drivers/devfreq/rk3328_dmc.c +@@ -0,0 +1,846 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd. ++ * Author: Lin Huang ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define DTS_PAR_OFFSET (4096) ++ ++struct share_params { ++ u32 hz; ++ u32 lcdc_type; ++ u32 vop; ++ u32 vop_dclk_mode; ++ u32 sr_idle_en; ++ u32 addr_mcu_el3; ++ /* ++ * 1: need to wait flag1 ++ * 0: never wait flag1 ++ */ ++ u32 wait_flag1; ++ /* ++ * 1: need to wait flag1 ++ * 0: never wait flag1 ++ */ ++ u32 wait_flag0; ++ u32 complt_hwirq; ++ /* if need, add parameter after */ ++}; ++ ++static struct share_params *ddr_psci_param; ++ ++/* hope this define can adapt all future platform */ ++static const char * const rk3328_dts_timing[] = { ++ "ddr3_speed_bin", ++ "ddr4_speed_bin", ++ "pd_idle", ++ "sr_idle", ++ "sr_mc_gate_idle", ++ "srpd_lite_idle", ++ "standby_idle", ++ ++ "auto_pd_dis_freq", ++ "auto_sr_dis_freq", ++ "ddr3_dll_dis_freq", ++ "ddr4_dll_dis_freq", ++ "phy_dll_dis_freq", ++ ++ "ddr3_odt_dis_freq", ++ "phy_ddr3_odt_dis_freq", ++ "ddr3_drv", ++ "ddr3_odt", ++ "phy_ddr3_ca_drv", ++ "phy_ddr3_ck_drv", ++ "phy_ddr3_dq_drv", ++ "phy_ddr3_odt", ++ ++ "lpddr3_odt_dis_freq", ++ "phy_lpddr3_odt_dis_freq", ++ "lpddr3_drv", ++ "lpddr3_odt", ++ "phy_lpddr3_ca_drv", ++ "phy_lpddr3_ck_drv", ++ "phy_lpddr3_dq_drv", ++ "phy_lpddr3_odt", ++ ++ "lpddr4_odt_dis_freq", ++ "phy_lpddr4_odt_dis_freq", ++ "lpddr4_drv", ++ "lpddr4_dq_odt", ++ "lpddr4_ca_odt", ++ "phy_lpddr4_ca_drv", ++ "phy_lpddr4_ck_cs_drv", ++ "phy_lpddr4_dq_drv", ++ "phy_lpddr4_odt", ++ ++ "ddr4_odt_dis_freq", ++ "phy_ddr4_odt_dis_freq", ++ "ddr4_drv", ++ "ddr4_odt", ++ "phy_ddr4_ca_drv", ++ "phy_ddr4_ck_drv", ++ "phy_ddr4_dq_drv", ++ "phy_ddr4_odt", ++}; ++ ++static const char * const rk3328_dts_ca_timing[] = { ++ "ddr3a1_ddr4a9_de-skew", ++ "ddr3a0_ddr4a10_de-skew", ++ "ddr3a3_ddr4a6_de-skew", ++ "ddr3a2_ddr4a4_de-skew", ++ "ddr3a5_ddr4a8_de-skew", ++ "ddr3a4_ddr4a5_de-skew", ++ "ddr3a7_ddr4a11_de-skew", ++ "ddr3a6_ddr4a7_de-skew", ++ "ddr3a9_ddr4a0_de-skew", ++ "ddr3a8_ddr4a13_de-skew", ++ "ddr3a11_ddr4a3_de-skew", ++ "ddr3a10_ddr4cs0_de-skew", ++ "ddr3a13_ddr4a2_de-skew", ++ "ddr3a12_ddr4ba1_de-skew", ++ "ddr3a15_ddr4odt0_de-skew", ++ "ddr3a14_ddr4a1_de-skew", ++ "ddr3ba1_ddr4a15_de-skew", ++ "ddr3ba0_ddr4bg0_de-skew", ++ "ddr3ras_ddr4cke_de-skew", ++ "ddr3ba2_ddr4ba0_de-skew", ++ "ddr3we_ddr4bg1_de-skew", ++ "ddr3cas_ddr4a12_de-skew", ++ "ddr3ckn_ddr4ckn_de-skew", ++ "ddr3ckp_ddr4ckp_de-skew", ++ "ddr3cke_ddr4a16_de-skew", ++ "ddr3odt0_ddr4a14_de-skew", ++ "ddr3cs0_ddr4act_de-skew", ++ "ddr3reset_ddr4reset_de-skew", ++ "ddr3cs1_ddr4cs1_de-skew", ++ "ddr3odt1_ddr4odt1_de-skew", ++}; ++ ++static const char * const rk3328_dts_cs0_timing[] = { ++ "cs0_dm0_rx_de-skew", ++ "cs0_dm0_tx_de-skew", ++ "cs0_dq0_rx_de-skew", ++ "cs0_dq0_tx_de-skew", ++ "cs0_dq1_rx_de-skew", ++ "cs0_dq1_tx_de-skew", ++ "cs0_dq2_rx_de-skew", ++ "cs0_dq2_tx_de-skew", ++ "cs0_dq3_rx_de-skew", ++ "cs0_dq3_tx_de-skew", ++ "cs0_dq4_rx_de-skew", ++ "cs0_dq4_tx_de-skew", ++ "cs0_dq5_rx_de-skew", ++ "cs0_dq5_tx_de-skew", ++ "cs0_dq6_rx_de-skew", ++ "cs0_dq6_tx_de-skew", ++ "cs0_dq7_rx_de-skew", ++ "cs0_dq7_tx_de-skew", ++ "cs0_dqs0_rx_de-skew", ++ "cs0_dqs0p_tx_de-skew", ++ "cs0_dqs0n_tx_de-skew", ++ ++ "cs0_dm1_rx_de-skew", ++ "cs0_dm1_tx_de-skew", ++ "cs0_dq8_rx_de-skew", ++ "cs0_dq8_tx_de-skew", ++ "cs0_dq9_rx_de-skew", ++ "cs0_dq9_tx_de-skew", ++ "cs0_dq10_rx_de-skew", ++ "cs0_dq10_tx_de-skew", ++ "cs0_dq11_rx_de-skew", ++ "cs0_dq11_tx_de-skew", ++ "cs0_dq12_rx_de-skew", ++ "cs0_dq12_tx_de-skew", ++ "cs0_dq13_rx_de-skew", ++ "cs0_dq13_tx_de-skew", ++ "cs0_dq14_rx_de-skew", ++ "cs0_dq14_tx_de-skew", ++ "cs0_dq15_rx_de-skew", ++ "cs0_dq15_tx_de-skew", ++ "cs0_dqs1_rx_de-skew", ++ "cs0_dqs1p_tx_de-skew", ++ "cs0_dqs1n_tx_de-skew", ++ ++ "cs0_dm2_rx_de-skew", ++ "cs0_dm2_tx_de-skew", ++ "cs0_dq16_rx_de-skew", ++ "cs0_dq16_tx_de-skew", ++ "cs0_dq17_rx_de-skew", ++ "cs0_dq17_tx_de-skew", ++ "cs0_dq18_rx_de-skew", ++ "cs0_dq18_tx_de-skew", ++ "cs0_dq19_rx_de-skew", ++ "cs0_dq19_tx_de-skew", ++ "cs0_dq20_rx_de-skew", ++ "cs0_dq20_tx_de-skew", ++ "cs0_dq21_rx_de-skew", ++ "cs0_dq21_tx_de-skew", ++ "cs0_dq22_rx_de-skew", ++ "cs0_dq22_tx_de-skew", ++ "cs0_dq23_rx_de-skew", ++ "cs0_dq23_tx_de-skew", ++ "cs0_dqs2_rx_de-skew", ++ "cs0_dqs2p_tx_de-skew", ++ "cs0_dqs2n_tx_de-skew", ++ ++ "cs0_dm3_rx_de-skew", ++ "cs0_dm3_tx_de-skew", ++ "cs0_dq24_rx_de-skew", ++ "cs0_dq24_tx_de-skew", ++ "cs0_dq25_rx_de-skew", ++ "cs0_dq25_tx_de-skew", ++ "cs0_dq26_rx_de-skew", ++ "cs0_dq26_tx_de-skew", ++ "cs0_dq27_rx_de-skew", ++ "cs0_dq27_tx_de-skew", ++ "cs0_dq28_rx_de-skew", ++ "cs0_dq28_tx_de-skew", ++ "cs0_dq29_rx_de-skew", ++ "cs0_dq29_tx_de-skew", ++ "cs0_dq30_rx_de-skew", ++ "cs0_dq30_tx_de-skew", ++ "cs0_dq31_rx_de-skew", ++ "cs0_dq31_tx_de-skew", ++ "cs0_dqs3_rx_de-skew", ++ "cs0_dqs3p_tx_de-skew", ++ "cs0_dqs3n_tx_de-skew", ++}; ++ ++static const char * const rk3328_dts_cs1_timing[] = { ++ "cs1_dm0_rx_de-skew", ++ "cs1_dm0_tx_de-skew", ++ "cs1_dq0_rx_de-skew", ++ "cs1_dq0_tx_de-skew", ++ "cs1_dq1_rx_de-skew", ++ "cs1_dq1_tx_de-skew", ++ "cs1_dq2_rx_de-skew", ++ "cs1_dq2_tx_de-skew", ++ "cs1_dq3_rx_de-skew", ++ "cs1_dq3_tx_de-skew", ++ "cs1_dq4_rx_de-skew", ++ "cs1_dq4_tx_de-skew", ++ "cs1_dq5_rx_de-skew", ++ "cs1_dq5_tx_de-skew", ++ "cs1_dq6_rx_de-skew", ++ "cs1_dq6_tx_de-skew", ++ "cs1_dq7_rx_de-skew", ++ "cs1_dq7_tx_de-skew", ++ "cs1_dqs0_rx_de-skew", ++ "cs1_dqs0p_tx_de-skew", ++ "cs1_dqs0n_tx_de-skew", ++ ++ "cs1_dm1_rx_de-skew", ++ "cs1_dm1_tx_de-skew", ++ "cs1_dq8_rx_de-skew", ++ "cs1_dq8_tx_de-skew", ++ "cs1_dq9_rx_de-skew", ++ "cs1_dq9_tx_de-skew", ++ "cs1_dq10_rx_de-skew", ++ "cs1_dq10_tx_de-skew", ++ "cs1_dq11_rx_de-skew", ++ "cs1_dq11_tx_de-skew", ++ "cs1_dq12_rx_de-skew", ++ "cs1_dq12_tx_de-skew", ++ "cs1_dq13_rx_de-skew", ++ "cs1_dq13_tx_de-skew", ++ "cs1_dq14_rx_de-skew", ++ "cs1_dq14_tx_de-skew", ++ "cs1_dq15_rx_de-skew", ++ "cs1_dq15_tx_de-skew", ++ "cs1_dqs1_rx_de-skew", ++ "cs1_dqs1p_tx_de-skew", ++ "cs1_dqs1n_tx_de-skew", ++ ++ "cs1_dm2_rx_de-skew", ++ "cs1_dm2_tx_de-skew", ++ "cs1_dq16_rx_de-skew", ++ "cs1_dq16_tx_de-skew", ++ "cs1_dq17_rx_de-skew", ++ "cs1_dq17_tx_de-skew", ++ "cs1_dq18_rx_de-skew", ++ "cs1_dq18_tx_de-skew", ++ "cs1_dq19_rx_de-skew", ++ "cs1_dq19_tx_de-skew", ++ "cs1_dq20_rx_de-skew", ++ "cs1_dq20_tx_de-skew", ++ "cs1_dq21_rx_de-skew", ++ "cs1_dq21_tx_de-skew", ++ "cs1_dq22_rx_de-skew", ++ "cs1_dq22_tx_de-skew", ++ "cs1_dq23_rx_de-skew", ++ "cs1_dq23_tx_de-skew", ++ "cs1_dqs2_rx_de-skew", ++ "cs1_dqs2p_tx_de-skew", ++ "cs1_dqs2n_tx_de-skew", ++ ++ "cs1_dm3_rx_de-skew", ++ "cs1_dm3_tx_de-skew", ++ "cs1_dq24_rx_de-skew", ++ "cs1_dq24_tx_de-skew", ++ "cs1_dq25_rx_de-skew", ++ "cs1_dq25_tx_de-skew", ++ "cs1_dq26_rx_de-skew", ++ "cs1_dq26_tx_de-skew", ++ "cs1_dq27_rx_de-skew", ++ "cs1_dq27_tx_de-skew", ++ "cs1_dq28_rx_de-skew", ++ "cs1_dq28_tx_de-skew", ++ "cs1_dq29_rx_de-skew", ++ "cs1_dq29_tx_de-skew", ++ "cs1_dq30_rx_de-skew", ++ "cs1_dq30_tx_de-skew", ++ "cs1_dq31_rx_de-skew", ++ "cs1_dq31_tx_de-skew", ++ "cs1_dqs3_rx_de-skew", ++ "cs1_dqs3p_tx_de-skew", ++ "cs1_dqs3n_tx_de-skew", ++}; ++ ++struct rk3328_ddr_dts_config_timing { ++ unsigned int ddr3_speed_bin; ++ unsigned int ddr4_speed_bin; ++ unsigned int pd_idle; ++ unsigned int sr_idle; ++ unsigned int sr_mc_gate_idle; ++ unsigned int srpd_lite_idle; ++ unsigned int standby_idle; ++ ++ unsigned int auto_pd_dis_freq; ++ unsigned int auto_sr_dis_freq; ++ /* for ddr3 only */ ++ unsigned int ddr3_dll_dis_freq; ++ /* for ddr4 only */ ++ unsigned int ddr4_dll_dis_freq; ++ unsigned int phy_dll_dis_freq; ++ ++ unsigned int ddr3_odt_dis_freq; ++ unsigned int phy_ddr3_odt_dis_freq; ++ unsigned int ddr3_drv; ++ unsigned int ddr3_odt; ++ unsigned int phy_ddr3_ca_drv; ++ unsigned int phy_ddr3_ck_drv; ++ unsigned int phy_ddr3_dq_drv; ++ unsigned int phy_ddr3_odt; ++ ++ unsigned int lpddr3_odt_dis_freq; ++ unsigned int phy_lpddr3_odt_dis_freq; ++ unsigned int lpddr3_drv; ++ unsigned int lpddr3_odt; ++ unsigned int phy_lpddr3_ca_drv; ++ unsigned int phy_lpddr3_ck_drv; ++ unsigned int phy_lpddr3_dq_drv; ++ unsigned int phy_lpddr3_odt; ++ ++ unsigned int lpddr4_odt_dis_freq; ++ unsigned int phy_lpddr4_odt_dis_freq; ++ unsigned int lpddr4_drv; ++ unsigned int lpddr4_dq_odt; ++ unsigned int lpddr4_ca_odt; ++ unsigned int phy_lpddr4_ca_drv; ++ unsigned int phy_lpddr4_ck_cs_drv; ++ unsigned int phy_lpddr4_dq_drv; ++ unsigned int phy_lpddr4_odt; ++ ++ unsigned int ddr4_odt_dis_freq; ++ unsigned int phy_ddr4_odt_dis_freq; ++ unsigned int ddr4_drv; ++ unsigned int ddr4_odt; ++ unsigned int phy_ddr4_ca_drv; ++ unsigned int phy_ddr4_ck_drv; ++ unsigned int phy_ddr4_dq_drv; ++ unsigned int phy_ddr4_odt; ++ ++ unsigned int ca_skew[15]; ++ unsigned int cs0_skew[44]; ++ unsigned int cs1_skew[44]; ++ ++ unsigned int available; ++}; ++ ++struct rk3328_ddr_de_skew_setting { ++ unsigned int ca_de_skew[30]; ++ unsigned int cs0_de_skew[84]; ++ unsigned int cs1_de_skew[84]; ++}; ++ ++struct rk3328_dmcfreq { ++ struct device *dev; ++ struct devfreq *devfreq; ++ struct devfreq_simple_ondemand_data ondemand_data; ++ struct clk *dmc_clk; ++ struct devfreq_event_dev *edev; ++ struct mutex lock; ++ struct regulator *vdd_center; ++ unsigned long rate, target_rate; ++ unsigned long volt, target_volt; ++ ++ int (*set_auto_self_refresh)(u32 en); ++}; ++ ++static void ++rk3328_de_skew_setting_2_register(struct rk3328_ddr_de_skew_setting *de_skew, ++ struct rk3328_ddr_dts_config_timing *tim) ++{ ++ u32 n; ++ u32 offset; ++ u32 shift; ++ ++ memset_io(tim->ca_skew, 0, sizeof(tim->ca_skew)); ++ memset_io(tim->cs0_skew, 0, sizeof(tim->cs0_skew)); ++ memset_io(tim->cs1_skew, 0, sizeof(tim->cs1_skew)); ++ ++ /* CA de-skew */ ++ for (n = 0; n < ARRAY_SIZE(de_skew->ca_de_skew); n++) { ++ offset = n / 2; ++ shift = n % 2; ++ /* 0 => 4; 1 => 0 */ ++ shift = (shift == 0) ? 4 : 0; ++ tim->ca_skew[offset] &= ~(0xf << shift); ++ tim->ca_skew[offset] |= (de_skew->ca_de_skew[n] << shift); ++ } ++ ++ /* CS0 data de-skew */ ++ for (n = 0; n < ARRAY_SIZE(de_skew->cs0_de_skew); n++) { ++ offset = ((n / 21) * 11) + ((n % 21) / 2); ++ shift = ((n % 21) % 2); ++ if ((n % 21) == 20) ++ shift = 0; ++ else ++ /* 0 => 4; 1 => 0 */ ++ shift = (shift == 0) ? 4 : 0; ++ tim->cs0_skew[offset] &= ~(0xf << shift); ++ tim->cs0_skew[offset] |= (de_skew->cs0_de_skew[n] << shift); ++ } ++ ++ /* CS1 data de-skew */ ++ for (n = 0; n < ARRAY_SIZE(de_skew->cs1_de_skew); n++) { ++ offset = ((n / 21) * 11) + ((n % 21) / 2); ++ shift = ((n % 21) % 2); ++ if ((n % 21) == 20) ++ shift = 0; ++ else ++ /* 0 => 4; 1 => 0 */ ++ shift = (shift == 0) ? 4 : 0; ++ tim->cs1_skew[offset] &= ~(0xf << shift); ++ tim->cs1_skew[offset] |= (de_skew->cs1_de_skew[n] << shift); ++ } ++} ++ ++static void of_get_rk3328_timings(struct device *dev, ++ struct device_node *np, uint32_t *timing) ++{ ++ struct device_node *np_tim; ++ u32 *p; ++ struct rk3328_ddr_dts_config_timing *dts_timing; ++ struct rk3328_ddr_de_skew_setting *de_skew; ++ int ret = 0; ++ u32 i; ++ ++ dts_timing = ++ (struct rk3328_ddr_dts_config_timing *)(timing + ++ DTS_PAR_OFFSET / 4); ++ ++ np_tim = of_parse_phandle(np, "ddr_timing", 0); ++ if (!np_tim) { ++ ret = -EINVAL; ++ goto end; ++ } ++ de_skew = kmalloc(sizeof(*de_skew), GFP_KERNEL); ++ if (!de_skew) { ++ ret = -ENOMEM; ++ goto end; ++ } ++ ++ p = (u32 *)dts_timing; ++ for (i = 0; i < ARRAY_SIZE(rk3328_dts_timing); i++) { ++ ret |= of_property_read_u32(np_tim, rk3328_dts_timing[i], ++ p + i); ++ } ++ p = (u32 *)de_skew->ca_de_skew; ++ for (i = 0; i < ARRAY_SIZE(rk3328_dts_ca_timing); i++) { ++ ret |= of_property_read_u32(np_tim, rk3328_dts_ca_timing[i], ++ p + i); ++ } ++ p = (u32 *)de_skew->cs0_de_skew; ++ for (i = 0; i < ARRAY_SIZE(rk3328_dts_cs0_timing); i++) { ++ ret |= of_property_read_u32(np_tim, rk3328_dts_cs0_timing[i], ++ p + i); ++ } ++ p = (u32 *)de_skew->cs1_de_skew; ++ for (i = 0; i < ARRAY_SIZE(rk3328_dts_cs1_timing); i++) { ++ ret |= of_property_read_u32(np_tim, rk3328_dts_cs1_timing[i], ++ p + i); ++ } ++ if (!ret) ++ rk3328_de_skew_setting_2_register(de_skew, dts_timing); ++ ++ kfree(de_skew); ++end: ++ if (!ret) { ++ dts_timing->available = 1; ++ } else { ++ dts_timing->available = 0; ++ dev_err(dev, "of_get_ddr_timings: fail\n"); ++ } ++ ++ of_node_put(np_tim); ++} ++ ++static int rockchip_ddr_set_auto_self_refresh(uint32_t en) ++{ ++ struct arm_smccc_res res; ++ ++ ddr_psci_param->sr_idle_en = en; ++ ++ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, ++ SHARE_PAGE_TYPE_DDR, 0, ROCKCHIP_SIP_CONFIG_DRAM_SET_AT_SR, ++ 0, 0, 0, 0, &res); ++ ++ return res.a0; ++} ++ ++static int rk3328_dmc_init(struct platform_device *pdev, ++ struct rk3328_dmcfreq *dmcfreq) ++{ ++ struct arm_smccc_res res; ++ u32 size, page_num; ++ ++ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, ++ 0, 0, ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION, ++ 0, 0, 0, 0, &res); ++ if (res.a0 || (res.a1 < 0x101)) { ++ dev_err(&pdev->dev, ++ "trusted firmware need to update or is invalid\n"); ++ return -ENXIO; ++ } ++ ++ dev_notice(&pdev->dev, "current ATF version 0x%lx\n", res.a1); ++ ++ /* ++ * first 4KB is used for interface parameters ++ * after 4KB * N is dts parameters ++ */ ++ size = sizeof(struct rk3328_ddr_dts_config_timing); ++ page_num = DIV_ROUND_UP(size, 4096) + 1; ++ ++ arm_smccc_smc(ROCKCHIP_SIP_SHARE_MEM, ++ page_num, SHARE_PAGE_TYPE_DDR, 0, ++ 0, 0, 0, 0, &res); ++ if (res.a0 != 0) { ++ dev_err(&pdev->dev, "no ATF memory for init\n"); ++ return -ENOMEM; ++ } ++ ++ ddr_psci_param = ioremap(res.a1, page_num << 12); ++ of_get_rk3328_timings(&pdev->dev, pdev->dev.of_node, ++ (uint32_t *)ddr_psci_param); ++ ++ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, ++ SHARE_PAGE_TYPE_DDR, 0, ROCKCHIP_SIP_CONFIG_DRAM_INIT, ++ 0, 0, 0, 0, &res); ++ if (res.a0) { ++ dev_err(&pdev->dev, "Rockchip dram init error %lx\n", res.a0); ++ return -ENOMEM; ++ } ++ ++ dmcfreq->set_auto_self_refresh = rockchip_ddr_set_auto_self_refresh; ++ ++ return 0; ++} ++ ++static int rk3328_dmcfreq_target(struct device *dev, unsigned long *freq, ++ u32 flags) ++{ ++ struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev); ++ struct dev_pm_opp *opp; ++ unsigned long old_clk_rate = dmcfreq->rate; ++ unsigned long target_volt, target_rate; ++ int err; ++ ++ opp = devfreq_recommended_opp(dev, freq, flags); ++ if (IS_ERR(opp)) ++ return PTR_ERR(opp); ++ ++ target_rate = dev_pm_opp_get_freq(opp); ++ target_volt = dev_pm_opp_get_voltage(opp); ++ dev_pm_opp_put(opp); ++ ++ if (dmcfreq->rate == target_rate) ++ return 0; ++ ++ mutex_lock(&dmcfreq->lock); ++ ++ /* ++ * If frequency scaling from low to high, adjust voltage first. ++ * If frequency scaling from high to low, adjust frequency first. ++ */ ++ if (old_clk_rate < target_rate) { ++ err = regulator_set_voltage(dmcfreq->vdd_center, target_volt, ++ target_volt); ++ if (err) { ++ dev_err(dev, "Cannot set voltage %lu uV\n", ++ target_volt); ++ goto out; ++ } ++ } ++ ++ err = clk_set_rate(dmcfreq->dmc_clk, target_rate); ++ if (err) { ++ dev_err(dev, "Cannot set frequency %lu (%d)\n", target_rate, ++ err); ++ regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt, ++ dmcfreq->volt); ++ goto out; ++ } ++ ++ /* ++ * Check the dpll rate, ++ * There only two result we will get, ++ * 1. Ddr frequency scaling fail, we still get the old rate. ++ * 2. Ddr frequency scaling sucessful, we get the rate we set. ++ */ ++ dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk); ++ ++ /* If get the incorrect rate, set voltage to old value. */ ++ if (dmcfreq->rate != target_rate) { ++ dev_err(dev, "Got wrong frequency, Request %lu, Current %lu\n", ++ target_rate, dmcfreq->rate); ++ regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt, ++ dmcfreq->volt); ++ goto out; ++ } else if (old_clk_rate > target_rate) ++ err = regulator_set_voltage(dmcfreq->vdd_center, target_volt, ++ target_volt); ++ if (err) ++ dev_err(dev, "Cannot set voltage %lu uV\n", target_volt); ++ ++ dmcfreq->rate = target_rate; ++ dmcfreq->volt = target_volt; ++ ++out: ++ mutex_unlock(&dmcfreq->lock); ++ return err; ++} ++ ++static int rk3328_dmcfreq_get_dev_status(struct device *dev, ++ struct devfreq_dev_status *stat) ++{ ++ struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev); ++ struct devfreq_event_data edata; ++ int ret = 0; ++ ++ ret = devfreq_event_get_event(dmcfreq->edev, &edata); ++ if (ret < 0) ++ return ret; ++ ++ stat->current_frequency = dmcfreq->rate; ++ stat->busy_time = edata.load_count; ++ stat->total_time = edata.total_count; ++ ++ return ret; ++} ++ ++static int rk3328_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq) ++{ ++ struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev); ++ ++ *freq = dmcfreq->rate; ++ ++ return 0; ++} ++ ++static struct devfreq_dev_profile rk3328_devfreq_dmc_profile = { ++ .polling_ms = 200, ++ .target = rk3328_dmcfreq_target, ++ .get_dev_status = rk3328_dmcfreq_get_dev_status, ++ .get_cur_freq = rk3328_dmcfreq_get_cur_freq, ++}; ++ ++static __maybe_unused int rk3328_dmcfreq_suspend(struct device *dev) ++{ ++ struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev); ++ int ret = 0; ++ ++ ret = devfreq_event_disable_edev(dmcfreq->edev); ++ if (ret < 0) { ++ dev_err(dev, "failed to disable the devfreq-event devices\n"); ++ return ret; ++ } ++ ++ ret = devfreq_suspend_device(dmcfreq->devfreq); ++ if (ret < 0) { ++ dev_err(dev, "failed to suspend the devfreq devices\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static __maybe_unused int rk3328_dmcfreq_resume(struct device *dev) ++{ ++ struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev); ++ int ret = 0; ++ ++ ret = devfreq_event_enable_edev(dmcfreq->edev); ++ if (ret < 0) { ++ dev_err(dev, "failed to enable the devfreq-event devices\n"); ++ return ret; ++ } ++ ++ ret = devfreq_resume_device(dmcfreq->devfreq); ++ if (ret < 0) { ++ dev_err(dev, "failed to resume the devfreq devices\n"); ++ return ret; ++ } ++ return ret; ++} ++ ++static SIMPLE_DEV_PM_OPS(rk3328_dmcfreq_pm, rk3328_dmcfreq_suspend, ++ rk3328_dmcfreq_resume); ++ ++static int rk3328_dmcfreq_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *np = pdev->dev.of_node; ++ struct rk3328_dmcfreq *data; ++ struct dev_pm_opp *opp; ++ int ret; ++ ++ data = devm_kzalloc(dev, sizeof(struct rk3328_dmcfreq), GFP_KERNEL); ++ if (!data) ++ return -ENOMEM; ++ ++ mutex_init(&data->lock); ++ ++ data->vdd_center = devm_regulator_get(dev, "center"); ++ if (IS_ERR(data->vdd_center)) { ++ if (PTR_ERR(data->vdd_center) == -EPROBE_DEFER) ++ return -EPROBE_DEFER; ++ ++ dev_err(dev, "Cannot get the regulator \"center\"\n"); ++ return PTR_ERR(data->vdd_center); ++ } ++ ++ data->dmc_clk = devm_clk_get(dev, "dmc_clk"); ++ if (IS_ERR(data->dmc_clk)) { ++ if (PTR_ERR(data->dmc_clk) == -EPROBE_DEFER) ++ return -EPROBE_DEFER; ++ ++ dev_err(dev, "Cannot get the clk dmc_clk\n"); ++ return PTR_ERR(data->dmc_clk); ++ } ++ ++ data->edev = devfreq_event_get_edev_by_phandle(dev, "devfreq-events", 0); ++ if (IS_ERR(data->edev)) ++ return -EPROBE_DEFER; ++ ++ ret = devfreq_event_enable_edev(data->edev); ++ if (ret < 0) { ++ dev_err(dev, "failed to enable devfreq-event devices\n"); ++ return ret; ++ } ++ ++ ret = rk3328_dmc_init(pdev, data); ++ if (ret) ++ return ret; ++ ++ /* ++ * We add a devfreq driver to our parent since it has a device tree node ++ * with operating points. ++ */ ++ if (dev_pm_opp_of_add_table(dev)) { ++ dev_err(dev, "Invalid operating-points in device tree.\n"); ++ return -EINVAL; ++ } ++ ++ of_property_read_u32(np, "upthreshold", ++ &data->ondemand_data.upthreshold); ++ of_property_read_u32(np, "downdifferential", ++ &data->ondemand_data.downdifferential); ++ ++ data->rate = clk_get_rate(data->dmc_clk); ++ ++ opp = devfreq_recommended_opp(dev, &data->rate, 0); ++ if (IS_ERR(opp)) { ++ ret = PTR_ERR(opp); ++ goto err_free_opp; ++ } ++ ++ data->rate = dev_pm_opp_get_freq(opp); ++ data->volt = dev_pm_opp_get_voltage(opp); ++ dev_pm_opp_put(opp); ++ ++ rk3328_devfreq_dmc_profile.initial_freq = data->rate; ++ ++ data->devfreq = devm_devfreq_add_device(dev, ++ &rk3328_devfreq_dmc_profile, ++ DEVFREQ_GOV_SIMPLE_ONDEMAND, ++ &data->ondemand_data); ++ if (IS_ERR(data->devfreq)) { ++ ret = PTR_ERR(data->devfreq); ++ goto err_free_opp; ++ } ++ ++ devm_devfreq_register_opp_notifier(dev, data->devfreq); ++ ++ data->dev = dev; ++ platform_set_drvdata(pdev, data); ++ ++ return 0; ++ ++err_free_opp: ++ dev_pm_opp_of_remove_table(&pdev->dev); ++ return ret; ++} ++ ++static int rk3328_dmcfreq_remove(struct platform_device *pdev) ++{ ++ struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(&pdev->dev); ++ ++ /* ++ * Before remove the opp table we need to unregister the opp notifier. ++ */ ++ devm_devfreq_unregister_opp_notifier(dmcfreq->dev, dmcfreq->devfreq); ++ dev_pm_opp_of_remove_table(dmcfreq->dev); ++ ++ return 0; ++} ++ ++static const struct of_device_id rk3328dmc_devfreq_of_match[] = { ++ { .compatible = "rockchip,rk3328-dmc" }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, rk3328dmc_devfreq_of_match); ++ ++static struct platform_driver rk3328_dmcfreq_driver = { ++ .probe = rk3328_dmcfreq_probe, ++ .remove = rk3328_dmcfreq_remove, ++ .driver = { ++ .name = "rk3328-dmc-freq", ++ .pm = &rk3328_dmcfreq_pm, ++ .of_match_table = rk3328dmc_devfreq_of_match, ++ }, ++}; ++module_platform_driver(rk3328_dmcfreq_driver); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_AUTHOR("Lin Huang "); ++MODULE_DESCRIPTION("RK3328 dmcfreq driver with devfreq framework"); +diff --git a/include/dt-bindings/clock/rockchip-ddr.h b/include/dt-bindings/clock/rockchip-ddr.h +new file mode 100644 +index 000000000..b065432e7 +--- /dev/null ++++ b/include/dt-bindings/clock/rockchip-ddr.h +@@ -0,0 +1,63 @@ ++/* ++ * ++ * Copyright (C) 2017 ROCKCHIP, Inc. ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ */ ++ ++#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H ++#define _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H ++ ++#define DDR2_DEFAULT (0) ++ ++#define DDR3_800D (0) /* 5-5-5 */ ++#define DDR3_800E (1) /* 6-6-6 */ ++#define DDR3_1066E (2) /* 6-6-6 */ ++#define DDR3_1066F (3) /* 7-7-7 */ ++#define DDR3_1066G (4) /* 8-8-8 */ ++#define DDR3_1333F (5) /* 7-7-7 */ ++#define DDR3_1333G (6) /* 8-8-8 */ ++#define DDR3_1333H (7) /* 9-9-9 */ ++#define DDR3_1333J (8) /* 10-10-10 */ ++#define DDR3_1600G (9) /* 8-8-8 */ ++#define DDR3_1600H (10) /* 9-9-9 */ ++#define DDR3_1600J (11) /* 10-10-10 */ ++#define DDR3_1600K (12) /* 11-11-11 */ ++#define DDR3_1866J (13) /* 10-10-10 */ ++#define DDR3_1866K (14) /* 11-11-11 */ ++#define DDR3_1866L (15) /* 12-12-12 */ ++#define DDR3_1866M (16) /* 13-13-13 */ ++#define DDR3_2133K (17) /* 11-11-11 */ ++#define DDR3_2133L (18) /* 12-12-12 */ ++#define DDR3_2133M (19) /* 13-13-13 */ ++#define DDR3_2133N (20) /* 14-14-14 */ ++#define DDR3_DEFAULT (21) ++#define DDR_DDR2 (22) ++#define DDR_LPDDR (23) ++#define DDR_LPDDR2 (24) ++ ++#define DDR4_1600J (0) /* 10-10-10 */ ++#define DDR4_1600K (1) /* 11-11-11 */ ++#define DDR4_1600L (2) /* 12-12-12 */ ++#define DDR4_1866L (3) /* 12-12-12 */ ++#define DDR4_1866M (4) /* 13-13-13 */ ++#define DDR4_1866N (5) /* 14-14-14 */ ++#define DDR4_2133N (6) /* 14-14-14 */ ++#define DDR4_2133P (7) /* 15-15-15 */ ++#define DDR4_2133R (8) /* 16-16-16 */ ++#define DDR4_2400P (9) /* 15-15-15 */ ++#define DDR4_2400R (10) /* 16-16-16 */ ++#define DDR4_2400U (11) /* 18-18-18 */ ++#define DDR4_DEFAULT (12) ++ ++#define PAUSE_CPU_STACK_SIZE 16 ++ ++#endif +diff --git a/include/dt-bindings/memory/rockchip,rk322x.h b/include/dt-bindings/memory/rockchip,rk322x.h +new file mode 100644 +index 000000000..1ab3317d7 +--- /dev/null ++++ b/include/dt-bindings/memory/rockchip,rk322x.h +@@ -0,0 +1,90 @@ ++/* ++ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK322X_H ++#define _DT_BINDINGS_DRAM_ROCKCHIP_RK322X_H ++ ++#define DDR3_DS_34ohm (1 << 1) ++#define DDR3_DS_40ohm (0x0) ++ ++#define LP2_DS_34ohm (0x1) ++#define LP2_DS_40ohm (0x2) ++#define LP2_DS_48ohm (0x3) ++#define LP2_DS_60ohm (0x4) ++#define LP2_DS_68_6ohm (0x5)/* optional */ ++#define LP2_DS_80ohm (0x6) ++#define LP2_DS_120ohm (0x7)/* optional */ ++ ++#define LP3_DS_34ohm (0x1) ++#define LP3_DS_40ohm (0x2) ++#define LP3_DS_48ohm (0x3) ++#define LP3_DS_60ohm (0x4) ++#define LP3_DS_80ohm (0x6) ++#define LP3_DS_34D_40U (0x9) ++#define LP3_DS_40D_48U (0xa) ++#define LP3_DS_34D_48U (0xb) ++ ++#define DDR3_ODT_DIS (0) ++#define DDR3_ODT_40ohm ((1 << 2) | (1 << 6)) ++#define DDR3_ODT_60ohm (1 << 2) ++#define DDR3_ODT_120ohm (1 << 6) ++ ++#define LP3_ODT_DIS (0) ++#define LP3_ODT_60ohm (1) ++#define LP3_ODT_120ohm (2) ++#define LP3_ODT_240ohm (3) ++ ++#define PHY_DDR3_RON_RTT_DISABLE (0) ++#define PHY_DDR3_RON_RTT_451ohm (1) ++#define PHY_DDR3_RON_RTT_225ohm (2) ++#define PHY_DDR3_RON_RTT_150ohm (3) ++#define PHY_DDR3_RON_RTT_112ohm (4) ++#define PHY_DDR3_RON_RTT_90ohm (5) ++#define PHY_DDR3_RON_RTT_75ohm (6) ++#define PHY_DDR3_RON_RTT_64ohm (7) ++#define PHY_DDR3_RON_RTT_56ohm (16) ++#define PHY_DDR3_RON_RTT_50ohm (17) ++#define PHY_DDR3_RON_RTT_45ohm (18) ++#define PHY_DDR3_RON_RTT_41ohm (19) ++#define PHY_DDR3_RON_RTT_37ohm (20) ++#define PHY_DDR3_RON_RTT_34ohm (21) ++#define PHY_DDR3_RON_RTT_33ohm (22) ++#define PHY_DDR3_RON_RTT_30ohm (23) ++#define PHY_DDR3_RON_RTT_28ohm (24) ++#define PHY_DDR3_RON_RTT_26ohm (25) ++#define PHY_DDR3_RON_RTT_25ohm (26) ++#define PHY_DDR3_RON_RTT_23ohm (27) ++#define PHY_DDR3_RON_RTT_22ohm (28) ++#define PHY_DDR3_RON_RTT_21ohm (29) ++#define PHY_DDR3_RON_RTT_20ohm (30) ++#define PHY_DDR3_RON_RTT_19ohm (31) ++ ++#define PHY_LP23_RON_RTT_DISABLE (0) ++#define PHY_LP23_RON_RTT_480ohm (1) ++#define PHY_LP23_RON_RTT_240ohm (2) ++#define PHY_LP23_RON_RTT_160ohm (3) ++#define PHY_LP23_RON_RTT_120ohm (4) ++#define PHY_LP23_RON_RTT_96ohm (5) ++#define PHY_LP23_RON_RTT_80ohm (6) ++#define PHY_LP23_RON_RTT_68ohm (7) ++#define PHY_LP23_RON_RTT_60ohm (16) ++#define PHY_LP23_RON_RTT_53ohm (17) ++#define PHY_LP23_RON_RTT_48ohm (18) ++#define PHY_LP23_RON_RTT_43ohm (19) ++#define PHY_LP23_RON_RTT_40ohm (20) ++#define PHY_LP23_RON_RTT_37ohm (21) ++#define PHY_LP23_RON_RTT_34ohm (22) ++#define PHY_LP23_RON_RTT_32ohm (23) ++#define PHY_LP23_RON_RTT_30ohm (24) ++#define PHY_LP23_RON_RTT_28ohm (25) ++#define PHY_LP23_RON_RTT_26ohm (26) ++#define PHY_LP23_RON_RTT_25ohm (27) ++#define PHY_LP23_RON_RTT_24ohm (28) ++#define PHY_LP23_RON_RTT_22ohm (29) ++#define PHY_LP23_RON_RTT_21ohm (30) ++#define PHY_LP23_RON_RTT_20ohm (31) ++ ++#endif /* _DT_BINDINGS_DRAM_ROCKCHIP_RK322X_H */ + +diff --git a/drivers/devfreq/rk3228_dmc.c b/drivers/devfreq/rk3228_dmc.c +new file mode 100644 +index 000000000..3a34cb2b5 +--- /dev/null ++++ b/drivers/devfreq/rk3228_dmc.c +@@ -0,0 +1,738 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd. ++ * Author: Lin Huang ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define DTS_PAR_OFFSET (4096) ++ ++#define RK3228_GRF_OS_REG2 0x5d0 ++#define DDR_PCTL_MCFG 0x80 ++#define DDR_PCTL_TCL 0xe8 ++#define DDR_PCTL_TRAS 0xf0 ++#define DDR_PCTL_TRCD 0xf8 ++#define DDR_PCTL_TRP 0xdc ++ ++/* MCFG */ ++#define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT 24 ++#define PD_IDLE_SHIFT 8 ++#define MDDR_EN (2 << 22) ++#define LPDDR2_EN (3 << 22) ++#define LPDDR3_EN (1 << 22) ++#define DDR2_EN (0 << 5) ++#define DDR3_EN (1 << 5) ++#define LPDDR2_S2 (0 << 6) ++#define LPDDR2_S4 (1 << 6) ++#define MDDR_LPDDR2_BL_2 (0 << 20) ++#define MDDR_LPDDR2_BL_4 (1 << 20) ++#define MDDR_LPDDR2_BL_8 (2 << 20) ++#define MDDR_LPDDR2_BL_16 (3 << 20) ++#define DDR2_DDR3_BL_4 0 ++#define DDR2_DDR3_BL_8 1 ++#define TFAW_SHIFT 18 ++#define PD_EXIT_SLOW (0 << 17) ++#define PD_EXIT_FAST (1 << 17) ++#define PD_TYPE_SHIFT 16 ++#define BURSTLENGTH_SHIFT 20 ++ ++#define MCFG_CR_2T_BIT(x) ((x & (1 << 3)) >> 3) ++#define MCFG_DDR_MASK 0x60 ++#define MCFG_DDR_SHIFT 5 ++#define MCFG_LPDDR_MASK 0xC00000 ++#define MCFG_LPDDR_SHIFT 22 ++ ++#define MCFG_LPDDR2_S2 0x0 ++#define MCFG_DDR3 0x1 ++#define MCFG_LPDDR2_S4 0x2 ++ ++#define READ_DRAMTYPE_INFO(n) (((n) >> 13) & 0x7) ++ ++enum { ++ DDR4 = 0, ++ DDR2 = 2, ++ DDR3 = 3, ++ LPDDR2 = 5, ++ LPDDR3 = 6, ++ LPDDR4 = 7, ++ UNUSED = 0xFF ++}; ++ ++struct share_params { ++ u32 hz; ++ u32 lcdc_type; ++ u32 vop; ++ u32 vop_dclk_mode; ++ u32 sr_idle_en; ++ u32 addr_mcu_el3; ++ /* ++ * 1: need to wait flag1 ++ * 0: never wait flag1 ++ */ ++ u32 wait_flag1; ++ /* ++ * 1: need to wait flag1 ++ * 0: never wait flag1 ++ */ ++ u32 wait_flag0; ++ u32 complt_hwirq; ++ /* if need, add parameter after */ ++}; ++ ++static struct share_params *ddr_psci_param = NULL; ++ ++static const char * const rk3228_dts_timing[] = { ++ "dram_spd_bin", ++ "sr_idle", ++ "pd_idle", ++ "dram_dll_disb_freq", ++ "phy_dll_disb_freq", ++ "dram_odt_disb_freq", ++ "phy_odt_disb_freq", ++ "ddr3_drv", ++ "ddr3_odt", ++ "lpddr3_drv", ++ "lpddr3_odt", ++ "lpddr2_drv", ++ "phy_ddr3_clk_drv", ++ "phy_ddr3_cmd_drv", ++ "phy_ddr3_dqs_drv", ++ "phy_ddr3_odt", ++ "phy_lp23_clk_drv", ++ "phy_lp23_cmd_drv", ++ "phy_lp23_dqs_drv", ++ "phy_lp3_odt" ++}; ++ ++struct rk3228_ddr_dts_config_timing { ++ u32 dram_spd_bin; ++ u32 sr_idle; ++ u32 pd_idle; ++ u32 dram_dll_dis_freq; ++ u32 phy_dll_dis_freq; ++ u32 dram_odt_dis_freq; ++ u32 phy_odt_dis_freq; ++ u32 ddr3_drv; ++ u32 ddr3_odt; ++ u32 lpddr3_drv; ++ u32 lpddr3_odt; ++ u32 lpddr2_drv; ++ u32 phy_ddr3_clk_drv; ++ u32 phy_ddr3_cmd_drv; ++ u32 phy_ddr3_dqs_drv; ++ u32 phy_ddr3_odt; ++ u32 phy_lp23_clk_drv; ++ u32 phy_lp23_cmd_drv; ++ u32 phy_lp23_dqs_drv; ++ u32 phy_lp3_odt; ++}; ++ ++struct rk3228_devfreq { ++ struct devfreq *devfreq; ++ struct opp_table *clkname_opp_table; ++ struct opp_table *regulators_opp_table; ++ struct thermal_cooling_device *cooling; ++ bool opp_of_table_added; ++}; ++ ++struct rk3228_dmc { ++ struct device *dev; ++ void __iomem *iomem; ++ ++ int rate; ++ struct devfreq_simple_ondemand_data ondemand_data; ++ struct devfreq_event_dev *edev; ++ struct clk *dmc_clk; ++ struct rk3228_devfreq devfreq; ++ ++ uint32_t dram_type; ++ ++ //struct mutex lock; ++ ++ int (*set_auto_self_refresh)(u32 en); ++}; ++ ++static uint32_t of_get_rk3228_timings(struct device *dev, ++ struct device_node *np, uint32_t *timing) ++{ ++ struct device_node *np_tim; ++ uint32_t offset; ++ int ret = 0; ++ u32 idx; ++ ++ // first 4kb page is reserved for interface parameters, we calculate an offset ++ // after which the timing parameters start ++ offset = DTS_PAR_OFFSET / sizeof(uint32_t); ++ ++ np_tim = of_parse_phandle(np, "rockchip,dram_timing", 0); ++ ++ if (!np_tim) { ++ ret = -EINVAL; ++ goto end; ++ } ++ ++ for (idx = 0; idx < ARRAY_SIZE(rk3228_dts_timing); idx++) ++ ret |= of_property_read_u32(np_tim, rk3228_dts_timing[idx], &timing[offset + idx]); ++ ++end: ++ if (ret) ++ dev_err(dev, "of_get_ddr_timings: fail\n"); ++ ++ of_node_put(np_tim); ++ ++ return ret; ++ ++} ++ ++static int rockchip_ddr_set_auto_self_refresh(uint32_t en) ++{ ++ struct arm_smccc_res res; ++ ++ ddr_psci_param->sr_idle_en = en; ++ ++ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, ++ SHARE_PAGE_TYPE_DDR, 0, ROCKCHIP_SIP_CONFIG_DRAM_SET_AT_SR, ++ 0, 0, 0, 0, &res); ++ ++ return res.a0; ++} ++ ++static int rk3228_dmc_target(struct device *dev, unsigned long *freq, ++ u32 flags) ++{ ++ ++ struct rk3228_dmc *rdev = dev_get_drvdata(dev); ++ struct dev_pm_opp *opp; ++ int err; ++ ++ opp = devfreq_recommended_opp(dev, freq, flags); ++ if (IS_ERR(opp)) ++ return PTR_ERR(opp); ++ dev_pm_opp_put(opp); ++ ++ err = dev_pm_opp_set_rate(dev, *freq); ++ if (err) ++ return err; ++ ++ rdev->rate = *freq; ++ ++ return 0; ++ ++} ++ ++static int rk3228_dmc_get_dev_status(struct device *dev, ++ struct devfreq_dev_status *stat) ++{ ++ struct rk3228_dmc *rdev = dev_get_drvdata(dev); ++ struct devfreq_event_data edata; ++ int ret = 0; ++ ++ ret = devfreq_event_get_event(rdev->edev, &edata); ++ if (ret < 0) ++ return ret; ++ ++ stat->current_frequency = rdev->rate; ++ stat->busy_time = edata.load_count; ++ stat->total_time = edata.total_count; ++ ++ return ret; ++} ++ ++static int rk3228_dmc_get_cur_freq(struct device *dev, unsigned long *freq) ++{ ++ struct rk3228_dmc *rdev = dev_get_drvdata(dev); ++ ++ *freq = rdev->rate; ++ ++ return 0; ++} ++ ++static struct devfreq_dev_profile rk3228_devfreq_profile = { ++ .polling_ms = 50, ++ .target = rk3228_dmc_target, ++ .get_dev_status = rk3228_dmc_get_dev_status, ++ .get_cur_freq = rk3228_dmc_get_cur_freq, ++}; ++ ++void rk3228_devfreq_fini(struct rk3228_dmc *rdev) ++{ ++ struct rk3228_devfreq *devfreq = &rdev->devfreq; ++ ++ if (devfreq->cooling) { ++ devfreq_cooling_unregister(devfreq->cooling); ++ devfreq->cooling = NULL; ++ } ++ ++ if (devfreq->devfreq) { ++ devm_devfreq_remove_device(rdev->dev, devfreq->devfreq); ++ devfreq->devfreq = NULL; ++ } ++ ++ if (devfreq->opp_of_table_added) { ++ dev_pm_opp_of_remove_table(rdev->dev); ++ devfreq->opp_of_table_added = false; ++ } ++ ++ if (devfreq->regulators_opp_table) { ++ dev_pm_opp_put_regulators(devfreq->regulators_opp_table); ++ devfreq->regulators_opp_table = NULL; ++ } ++ ++ if (devfreq->clkname_opp_table) { ++ dev_pm_opp_put_clkname(devfreq->clkname_opp_table); ++ devfreq->clkname_opp_table = NULL; ++ } ++} ++ ++int rk3228_devfreq_init(struct rk3228_dmc *rdev) ++{ ++ struct thermal_cooling_device *cooling; ++ struct device *dev = rdev->dev; ++ struct opp_table *opp_table; ++ struct devfreq *devfreq; ++ struct rk3228_devfreq *rdevfreq = &rdev->devfreq; ++ ++ struct dev_pm_opp *opp; ++ unsigned long cur_freq; ++ int ret; ++ ++ if (!device_property_present(dev, "operating-points-v2")) ++ /* Optional, continue without devfreq */ ++ return 0; ++ ++ opp_table = dev_pm_opp_set_clkname(dev, "ddr_sclk"); ++ if (IS_ERR(opp_table)) { ++ ret = PTR_ERR(opp_table); ++ goto err_fini; ++ } ++ ++ rdevfreq->clkname_opp_table = opp_table; ++ ++ opp_table = dev_pm_opp_set_regulators(dev, ++ (const char *[]){ "logic" }, ++ 1); ++ if (IS_ERR(opp_table)) { ++ ret = PTR_ERR(opp_table); ++ ++ /* Continue if the optional regulator is missing */ ++ if (ret != -ENODEV) ++ goto err_fini; ++ } else { ++ rdevfreq->regulators_opp_table = opp_table; ++ } ++ ++ ret = dev_pm_opp_of_add_table(dev); ++ if (ret) ++ goto err_fini; ++ rdevfreq->opp_of_table_added = true; ++ ++ cur_freq = 0; ++ ++ opp = devfreq_recommended_opp(dev, &cur_freq, 0); ++ if (IS_ERR(opp)) { ++ ret = PTR_ERR(opp); ++ goto err_fini; ++ } ++ ++ rk3228_devfreq_profile.initial_freq = cur_freq; ++ dev_pm_opp_put(opp); ++ ++ rdev->ondemand_data.upthreshold = 30; ++ rdev->ondemand_data.downdifferential = 5; ++ ++ devfreq = devm_devfreq_add_device(dev, &rk3228_devfreq_profile, ++ DEVFREQ_GOV_SIMPLE_ONDEMAND, &rdev->ondemand_data); ++ if (IS_ERR(devfreq)) { ++ dev_err(dev, "Couldn't initialize GPU devfreq\n"); ++ ret = PTR_ERR(devfreq); ++ goto err_fini; ++ } ++ ++ rdevfreq->devfreq = devfreq; ++ ++ cooling = of_devfreq_cooling_register(dev->of_node, devfreq); ++ if (IS_ERR(cooling)) ++ dev_warn(dev, "Failed to register cooling device\n"); ++ else ++ rdevfreq->cooling = cooling; ++ ++ return 0; ++ ++err_fini: ++ rk3228_devfreq_fini(rdev); ++ return ret; ++} ++ ++static int rk3228_dmc_init(struct platform_device *pdev, ++ struct rk3228_dmc *rdev) ++{ ++ struct arm_smccc_res res; ++ u32 page_num; ++ ++ // Count of pages to request to trust os, in pages of 4kb ++ page_num = DIV_ROUND_UP(sizeof(struct rk3228_ddr_dts_config_timing), PAGE_SIZE) + 1; ++ ++ dev_dbg(&pdev->dev, "trying to allocate %d pages\n", page_num); ++ ++ // Do request to trust OS. res.a0 contains error code, res.a1 the *physical* ++ // initial location of pages ++ arm_smccc_smc( ++ ROCKCHIP_SIP_SHARE_MEM, ++ page_num, SHARE_PAGE_TYPE_DDR, 0, ++ 0, 0, 0, 0, &res ++ ); ++ ++ if (res.a0) { ++ dev_err(&pdev->dev, "no ATF memory for init\n"); ++ return -ENOMEM; ++ } ++ ++ dev_dbg(&pdev->dev, "allocated %d shared memory pages\n", page_num); ++ ++ // Remap the physical location to kernel space using ioremap ++ ddr_psci_param = (struct share_params *)ioremap(res.a1, page_num << PAGE_SHIFT); ++ ++ if (of_get_rk3228_timings(&pdev->dev, pdev->dev.of_node, ++ (uint32_t *)ddr_psci_param)) ++ return -ENOMEM; ++ ++ // Reset Hz value ++ ddr_psci_param->hz = 0; ++ ++ arm_smccc_smc( ++ ROCKCHIP_SIP_DRAM_FREQ, ++ SHARE_PAGE_TYPE_DDR, 0, ROCKCHIP_SIP_CONFIG_DRAM_INIT, ++ 0, 0, 0, 0, &res ++ ); ++ ++ if (res.a0) { ++ dev_err(&pdev->dev, "rockchip_sip_config_dram_init error:%lx\n", ++ res.a0); ++ return -EINVAL; ++ } ++ ++ dev_notice(&pdev->dev, "TEE DRAM configuration initialized\n"); ++ ++ rdev->set_auto_self_refresh = rockchip_ddr_set_auto_self_refresh; ++ ++ return 0; ++ ++} ++ ++static __maybe_unused int rk3228_dmc_suspend(struct device *dev) ++{ ++ struct rk3228_dmc *rdev = dev_get_drvdata(dev); ++ int ret = 0; ++ ++ ret = devfreq_event_disable_edev(rdev->edev); ++ if (ret < 0) { ++ dev_err(dev, "failed to disable the devfreq-event devices\n"); ++ return ret; ++ } ++ ++ ret = devfreq_suspend_device(rdev->devfreq.devfreq); ++ if (ret < 0) { ++ dev_err(dev, "failed to suspend the devfreq devices\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static __maybe_unused int rk3228_dmc_resume(struct device *dev) ++{ ++ struct rk3228_dmc *rdev = dev_get_drvdata(dev); ++ int ret = 0; ++ ++ ret = devfreq_event_enable_edev(rdev->edev); ++ if (ret < 0) { ++ dev_err(dev, "failed to enable the devfreq-event devices\n"); ++ return ret; ++ } ++ ++ ret = devfreq_resume_device(rdev->devfreq.devfreq); ++ if (ret < 0) { ++ dev_err(dev, "failed to resume the devfreq devices\n"); ++ return ret; ++ } ++ return ret; ++} ++ ++static uint32_t rk3228_get_dram_type(struct device *dev, struct device_node *node_grf, struct rk3228_dmc *data) ++{ ++ ++ struct regmap *regmap_grf; ++ uint32_t dram_type; ++ uint32_t val; ++ ++ dram_type = UNUSED; ++ ++ regmap_grf = syscon_node_to_regmap(node_grf); ++ ++ if (IS_ERR(regmap_grf)) { ++ dev_err(dev, "Cannot map rockchip,grf\n"); ++ goto err; ++ } ++ ++ regmap_read(regmap_grf, RK3228_GRF_OS_REG2, &val); ++ dram_type = READ_DRAMTYPE_INFO(val); ++ ++err: ++ ++ return dram_type; ++ ++} ++ ++static SIMPLE_DEV_PM_OPS(rk3228_dmc_pm, rk3228_dmc_suspend, ++ rk3228_dmc_resume); ++ ++static int rk3328_dmc_print_info(struct rk3228_dmc *rdev) ++{ ++ ++ u32 tcl; ++ u32 tras; ++ u32 trp; ++ u32 trcd; ++ ++ u32 mcfg; ++ u32 reg_ddr_type1; ++ u32 reg_ddr_type2; ++ ++ u32 dram_type; ++ u32 cr; ++ ++ const char * const dram_types[] = { ++ "LPDDR2 S2", ++ "LPDDR2 S4", ++ "DDR3", ++ "LPDDR3", ++ "Unknown" ++ }; ++ ++ const char * const cr_types[] = { ++ "1T", ++ "2T" ++ }; ++ ++ ++ tcl = readl(rdev->iomem + DDR_PCTL_TCL) & 0xf; ++ tras = readl(rdev->iomem + DDR_PCTL_TRAS) & 0x3f; ++ trp = readl(rdev->iomem + DDR_PCTL_TRP) & 0xf; ++ trcd = readl(rdev->iomem + DDR_PCTL_TRCD) & 0xf; ++ ++ mcfg = readl(rdev->iomem + DDR_PCTL_MCFG); ++ ++ reg_ddr_type1 = (mcfg & MCFG_DDR_MASK) >> MCFG_DDR_SHIFT; ++ reg_ddr_type2 = (mcfg & MCFG_LPDDR_MASK) >> MCFG_LPDDR_SHIFT; ++ cr = MCFG_CR_2T_BIT(mcfg); ++ ++ switch (reg_ddr_type1) { ++ case MCFG_LPDDR2_S2: ++ dram_type = 0; ++ break; ++ case MCFG_LPDDR2_S4: ++ dram_type = 1; ++ break; ++ case MCFG_DDR3: ++ dram_type = reg_ddr_type2 == LPDDR3_EN ? 3 : 2; ++ break; ++ default: ++ dram_type = 4; ++ break; ++ } ++ ++ dev_info(rdev->dev, ++ "memory type %s, timings (tCL, tRCD, tRP, tRAS): CL%d-%d-%d-%d command rate: %s (mcfg register: 0x%x)\n", ++ dram_types[dram_type], tcl, trcd, trp, tras, cr_types[cr], mcfg); ++ ++ return 0; ++ ++} ++ ++static int rk3228_dmc_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *np = pdev->dev.of_node; ++ struct rk3228_dmc *data; ++ struct device_node *node_grf; ++ int ret; ++ ++ data = devm_kzalloc(dev, sizeof(struct rk3228_dmc), GFP_KERNEL); ++ if (!data) ++ return -ENOMEM; ++ ++ //mutex_init(&data->lock); ++ ++ data->dmc_clk = devm_clk_get(dev, "ddr_sclk"); ++ if (IS_ERR(data->dmc_clk)) { ++ if (PTR_ERR(data->dmc_clk) == -EPROBE_DEFER) ++ return -EPROBE_DEFER; ++ ++ dev_err(dev, "Cannot get the clk dmc_clk\n"); ++ return PTR_ERR(data->dmc_clk); ++ } ++ ++ data->edev = devfreq_event_get_edev_by_phandle(dev, "devfreq-events", 0); ++ if (IS_ERR(data->edev)) ++ return -EPROBE_DEFER; ++ ++ data->iomem = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(data->iomem)) { ++ dev_err(dev, "fail to ioremap iomem\n"); ++ ret = PTR_ERR(data->iomem); ++ return ret; ++ } ++ ++ data->dev = dev; ++ ++ rk3328_dmc_print_info(data); ++ ++ node_grf = of_parse_phandle(np, "rockchip,grf", 0); ++ if (node_grf) { ++ ++ data->dram_type = rk3228_get_dram_type(dev, node_grf, data); ++ ++ if (data->dram_type == LPDDR2) { ++ dev_warn(dev, "detected LPDDR2 memory\n"); ++ } else if (data->dram_type == DDR2) { ++ dev_warn(dev, "detected DDR2 memory\n"); ++ } else if (data->dram_type == DDR3) { ++ dev_info(dev, "detected DDR3 memory\n"); ++ } else if (data->dram_type == LPDDR3) { ++ dev_info(dev, "detected LPDDR3 memory\n"); ++ } else if (data->dram_type == DDR4) { ++ dev_info(dev, "detected DDR4 memory\n"); ++ } else if (data->dram_type == LPDDR4) { ++ dev_info(dev, "detected LPDDR4 memory\n"); ++ } else if (data->dram_type == UNUSED) { ++ dev_info(dev, "memory type not detected\n"); ++ } else { ++ dev_info(dev, "unknown memory type: 0x%x\n", data->dram_type); ++ } ++ ++ } else { ++ ++ dev_warn(dev, "Cannot get rockchip,grf\n"); ++ data->dram_type = UNUSED; ++ ++ } ++ ++ if (data->dram_type == DDR3 || ++ data->dram_type == LPDDR3 || ++ data->dram_type == DDR4 || ++ data->dram_type == LPDDR4) { ++ ++ ret = devfreq_event_enable_edev(data->edev); ++ if (ret < 0) { ++ dev_err(dev, "failed to enable devfreq-event devices\n"); ++ return ret; ++ } ++ ++ ret = rk3228_dmc_init(pdev, data); ++ if (ret) ++ return ret; ++ ++ ++ ++ ret = rk3228_devfreq_init(data); ++ if (ret) ++ return ret; ++ ++ } else { ++ ++ dev_warn(dev, "detected memory type does not support clock scaling\n"); ++ ++ } ++ ++ platform_set_drvdata(pdev, data); ++ ++ return 0; ++ ++} ++ ++static int rk3228_dmc_remove(struct platform_device *pdev) ++{ ++ struct rk3228_dmc *rdev = dev_get_drvdata(&pdev->dev); ++ ++ /* ++ * Before remove the opp table we need to unregister the opp notifier. ++ */ ++ rk3228_devfreq_fini(rdev); ++ ++ if (ddr_psci_param) ++ iounmap(ddr_psci_param); ++ ++ if (rdev->iomem) ++ iounmap(rdev->iomem); ++ ++ return 0; ++} ++ ++static const struct of_device_id rk3228_dmc_of_match[] = { ++ { .compatible = "rockchip,rk3228-dmc" }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, rk3228_dmc_of_match); ++ ++static struct platform_driver rk3228_dmc_driver = { ++ .probe = rk3228_dmc_probe, ++ .remove = rk3228_dmc_remove, ++ .driver = { ++ .name = "rk3228-dmc", ++ .pm = &rk3228_dmc_pm, ++ .of_match_table = rk3228_dmc_of_match, ++ }, ++}; ++module_platform_driver(rk3228_dmc_driver); ++ ++#ifdef CONFIG_ARM ++static __init int sip_firmware_init(void) ++{ ++ struct arm_smccc_res res; ++ ++ /* ++ * OP-TEE works on kernel 3.10 and 4.4 and we have different sip ++ * implement. We should tell OP-TEE the current rockchip sip version. ++ */ ++ ++ /* ++ * ++ * res = __invoke_sip_fn_smc(ROCKCHIP_SIP_SIP_VERSION, ROCKCHIP_SIP_IMPLEMENT_V2, ++ SECURE_REG_WR, 0); ++ ++ arm_smccc_smc(function_id, arg0, arg1, arg2, 0, 0, 0, 0, &res); ++ */ ++ ++ arm_smccc_smc(ROCKCHIP_SIP_SIP_VERSION, ROCKCHIP_SIP_IMPLEMENT_V2, SECURE_REG_WR, 0, 0, 0, 0, 0, &res); ++ ++ if (res.a0) ++ pr_err("%s: set rockchip sip version v2 failed\n", __func__); ++ ++ pr_notice("Rockchip SIP initialized, version 0x%lx\n", res.a1); ++ ++ return 0; ++} ++arch_initcall(sip_firmware_init); ++#endif ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_AUTHOR("Lin Huang "); ++MODULE_DESCRIPTION("RK3228 dmcfreq driver with devfreq framework"); +-- +2.25.1 + diff --git a/patch/kernel/archive/rk322x-5.12/general-add-overlays.patch b/patch/kernel/archive/rk322x-5.12/general-add-overlays.patch index e801c9903c..2ad5c75770 100644 --- a/patch/kernel/archive/rk322x-5.12/general-add-overlays.patch +++ b/patch/kernel/archive/rk322x-5.12/general-add-overlays.patch @@ -1,9 +1,9 @@ diff --git a/arch/arm/boot/dts/overlay/Makefile b/arch/arm/boot/dts/overlay/Makefile new file mode 100755 -index 000000000..894db3d1e +index 000000000..092ff28da --- /dev/null +++ b/arch/arm/boot/dts/overlay/Makefile -@@ -0,0 +1,29 @@ +@@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0 +dtbo-$(CONFIG_ARCH_ROCKCHIP) += \ + rk322x-emmc.dtbo \ @@ -20,7 +20,11 @@ index 000000000..894db3d1e + rk322x-led-conf5.dtbo \ + rk322x-cpu-hs.dtbo \ + rk322x-wlan-alt-wiring.dtbo \ -+ rk322x-cpu-stability.dtbo ++ rk322x-cpu-stability.dtbo \ ++ rk322x-ddr3-330.dtbo \ ++ rk322x-ddr3-528.dtbo \ ++ rk322x-ddr3-660.dtbo \ ++ rk322x-ddr3-800.dtbo + +scr-$(CONFIG_ARCH_ROCKCHIP) += \ + rk322x-fixup.scr @@ -35,10 +39,10 @@ index 000000000..894db3d1e + diff --git a/arch/arm/boot/dts/overlay/README.rk322x-overlays b/arch/arm/boot/dts/overlay/README.rk322x-overlays new file mode 100755 -index 000000000..aeabdb0cc +index 000000000..c3d25a204 --- /dev/null +++ b/arch/arm/boot/dts/overlay/README.rk322x-overlays -@@ -0,0 +1,66 @@ +@@ -0,0 +1,75 @@ +This document describes overlays provided in the kernel packages +For generic Armbian overlays documentation please see +https://docs.armbian.com/User-Guide_Allwinner_overlays/ @@ -56,6 +60,7 @@ index 000000000..aeabdb0cc +- rk322x-emmc-nand +- rk322x-led-conf* +- rk322x-wlan-alt-wiring ++- rk322x-ddr3-* + +### Overlay details: + @@ -105,6 +110,14 @@ index 000000000..aeabdb0cc + +Some boards have different SDIO wiring setup for wifi chips. This overlay +enables the different pin controller wiring and power enable ++ ++### rk322x-ddr3-* ++ ++Enable DRAM memory controller and sets the speed to the given speed bin. ++The DRAM memory controller reclocking only works with DDR3/LPDDR3, if ++you enable one of these overlays on boards with DDR2 memory the system ++will not boot anymore ++ diff --git a/arch/arm/boot/dts/overlay/rk322x-bluetooth.dts b/arch/arm/boot/dts/overlay/rk322x-bluetooth.dts new file mode 100755 index 000000000..5698b14ba @@ -361,6 +374,142 @@ index 000000000..f434af926 + }; + +}; +diff --git a/arch/arm/boot/dts/overlay/rk322x-ddr3-330.dts b/arch/arm/boot/dts/overlay/rk322x-ddr3-330.dts +new file mode 100644 +index 000000000..78145548e +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/rk322x-ddr3-330.dts +@@ -0,0 +1,28 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ ++ fragment@0 { ++ target = <&dmc>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&dmc_opp_table>; ++ __overlay__ { ++ opp-534000000 { ++ status = "disabled"; ++ }; ++ opp-660000000 { ++ status = "disabled"; ++ }; ++ opp-786000000 { ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/overlay/rk322x-ddr3-528.dts b/arch/arm/boot/dts/overlay/rk322x-ddr3-528.dts +new file mode 100644 +index 000000000..dbbd222dd +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/rk322x-ddr3-528.dts +@@ -0,0 +1,28 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ ++ fragment@0 { ++ target = <&dmc>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&dmc_opp_table>; ++ __overlay__ { ++ opp-534000000 { ++ status = "okay"; ++ }; ++ opp-660000000 { ++ status = "disabled"; ++ }; ++ opp-786000000 { ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/overlay/rk322x-ddr3-660.dts b/arch/arm/boot/dts/overlay/rk322x-ddr3-660.dts +new file mode 100644 +index 000000000..65b707515 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/rk322x-ddr3-660.dts +@@ -0,0 +1,28 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ ++ fragment@0 { ++ target = <&dmc>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&dmc_opp_table>; ++ __overlay__ { ++ opp-534000000 { ++ status = "okay"; ++ }; ++ opp-660000000 { ++ status = "okay"; ++ }; ++ opp-786000000 { ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/overlay/rk322x-ddr3-800.dts b/arch/arm/boot/dts/overlay/rk322x-ddr3-800.dts +new file mode 100644 +index 000000000..7d11453ad +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/rk322x-ddr3-800.dts +@@ -0,0 +1,28 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ ++ fragment@0 { ++ target = <&dmc>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&dmc_opp_table>; ++ __overlay__ { ++ opp-534000000 { ++ status = "okay"; ++ }; ++ opp-660000000 { ++ status = "okay"; ++ }; ++ opp-786000000 { ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++}; diff --git a/arch/arm/boot/dts/overlay/rk322x-emmc-ddr-ph180.dts b/arch/arm/boot/dts/overlay/rk322x-emmc-ddr-ph180.dts new file mode 100644 index 000000000..4ba0afb8a