From d85c545f3be5df470d00505943b04d0350f24f24 Mon Sep 17 00:00:00 2001 From: The-going <48602507+The-going@users.noreply.github.com> Date: Thu, 1 Dec 2022 14:11:07 +0300 Subject: [PATCH] sunxi-6.0: fix for v6.0.10 (#4514) --- ...m64-dts-rk356x-Fix-pcie2x-reg-ranges.patch | 26 ++++++++++++------- .../sdhci-arasan-Add-runtime-PM-support.patch | 18 ++++++------- 2 files changed, 26 insertions(+), 18 deletions(-) diff --git a/patch/kernel/archive/sunxi-6.0/patches.megous/arm64-dts-rk356x-Fix-pcie2x-reg-ranges.patch b/patch/kernel/archive/sunxi-6.0/patches.megous/arm64-dts-rk356x-Fix-pcie2x-reg-ranges.patch index af1b4e218f..a437b2e160 100644 --- a/patch/kernel/archive/sunxi-6.0/patches.megous/arm64-dts-rk356x-Fix-pcie2x-reg-ranges.patch +++ b/patch/kernel/archive/sunxi-6.0/patches.megous/arm64-dts-rk356x-Fix-pcie2x-reg-ranges.patch @@ -1,7 +1,7 @@ -From 05f9ff5d7016001567d843736c05489030480953 Mon Sep 17 00:00:00 2001 +From 249cf8d9d4b3e03db740ea1bb2fe36372a091c66 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Sat, 22 Oct 2022 19:32:52 +0200 -Subject: [PATCH 482/484] arm64: dts: rk356x: Fix pcie2x reg/ranges +Subject: [PATCH 490/492] arm64: dts: rk356x: Fix pcie2x reg/ranges These values were suggested by pgwipeout: @@ -9,23 +9,31 @@ These values were suggested by pgwipeout: Signed-off-by: Ondrej Jirman --- - arch/arm64/boot/dts/rockchip/rk356x.dtsi | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -index e88e8c4fe..c7ca3d7b8 100644 +index 99fd9543fc6f..f7e069f4d352 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -885,8 +885,10 @@ pcie2x1: pcie@fe260000 { +@@ -855,7 +855,7 @@ pcie2x1: pcie@fe260000 { + compatible = "rockchip,rk3568-pcie"; + reg = <0x3 0xc0000000 0x0 0x00400000>, + <0x0 0xfe260000 0x0 0x00010000>, +- <0x3 0x00000000 0x0 0x01000000>; ++ <0x0 0xf4000000 0x0 0x00100000>; + + reg-names = "dbi", "apb", "config"; + interrupts = , +@@ -885,8 +885,9 @@ pcie2x1: pcie@fe260000 { phys = <&combphy2 PHY_TYPE_PCIE>; phy-names = "pcie-phy"; power-domains = <&power RK3568_PD_PIPE>; - ranges = <0x01000000 0x0 0x01000000 0x3 0x01000000 0x0 0x00100000 - 0x02000000 0x0 0x02000000 0x3 0x02000000 0x0 0x3e000000>; + ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, -+ <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>, -+ <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>; -+ ++ <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>, ++ <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>; resets = <&cru SRST_PCIE20_POWERUP>; reset-names = "pipe"; #address-cells = <3>; diff --git a/patch/kernel/archive/sunxi-6.0/patches.megous/sdhci-arasan-Add-runtime-PM-support.patch b/patch/kernel/archive/sunxi-6.0/patches.megous/sdhci-arasan-Add-runtime-PM-support.patch index 805a5d7b6f..9f32b23a52 100644 --- a/patch/kernel/archive/sunxi-6.0/patches.megous/sdhci-arasan-Add-runtime-PM-support.patch +++ b/patch/kernel/archive/sunxi-6.0/patches.megous/sdhci-arasan-Add-runtime-PM-support.patch @@ -1,7 +1,7 @@ -From 4a8881b980cc1ff8d7498d82cbdbf9a417b47161 Mon Sep 17 00:00:00 2001 +From 2e1ff05dfd21ee82a958be433ef48d3fd7eb69a5 Mon Sep 17 00:00:00 2001 From: Manish Narani Date: Tue, 18 Sep 2018 20:34:06 +0530 -Subject: [PATCH 290/486] sdhci: arasan: Add runtime PM support +Subject: [PATCH] sdhci: arasan: Add runtime PM support Add runtime PM support in Arasan SDHCI driver. @@ -11,7 +11,7 @@ Signed-off-by: Manish Narani 1 file changed, 86 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c -index 3997cad1f..d9c695efb 100644 +index cfb891430..77c046376 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -19,6 +19,7 @@ @@ -22,15 +22,15 @@ index 3997cad1f..d9c695efb 100644 #include #include #include -@@ -27,6 +28,7 @@ - #include "cqhci.h" +@@ -28,6 +29,7 @@ + #include "sdhci-cqhci.h" #include "sdhci-pltfm.h" +#define SDHCI_ARASAN_AUTOSUSPEND_DELAY 2000 /* ms */ #define SDHCI_ARASAN_VENDOR_REGISTER 0x78 #define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8 -@@ -472,6 +474,70 @@ static const struct sdhci_pltfm_data sdhci_arasan_thunderbay_pdata = { +@@ -473,6 +475,70 @@ static const struct sdhci_pltfm_data sdhci_arasan_thunderbay_pdata = { SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400, }; @@ -101,7 +101,7 @@ index 3997cad1f..d9c695efb 100644 #ifdef CONFIG_PM_SLEEP /** * sdhci_arasan_suspend - Suspend method for the driver -@@ -568,8 +634,10 @@ static int sdhci_arasan_resume(struct device *dev) +@@ -569,8 +635,10 @@ static int sdhci_arasan_resume(struct device *dev) } #endif /* ! CONFIG_PM_SLEEP */ @@ -114,7 +114,7 @@ index 3997cad1f..d9c695efb 100644 /** * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate -@@ -1711,13 +1779,25 @@ static int sdhci_arasan_probe(struct platform_device *pdev) +@@ -1712,13 +1780,25 @@ static int sdhci_arasan_probe(struct platform_device *pdev) host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; } @@ -140,7 +140,7 @@ index 3997cad1f..d9c695efb 100644 if (!IS_ERR(sdhci_arasan->phy)) phy_exit(sdhci_arasan->phy); unreg_clk: -@@ -1744,6 +1824,10 @@ static int sdhci_arasan_remove(struct platform_device *pdev) +@@ -1745,6 +1825,10 @@ static int sdhci_arasan_remove(struct platform_device *pdev) phy_exit(sdhci_arasan->phy); }