From d6f8693c0699a7dfa0f05cf0d47f1c4c4e039899 Mon Sep 17 00:00:00 2001 From: Aditya Prayoga Date: Wed, 26 Jun 2019 09:50:09 +0800 Subject: [PATCH] [#1429] SolidRun's ARMADA A388 SOM U-Boot ODT Update Old versions of U-Boot did not configure correctly the ODT on data signals of DDR RAM on SolidRun's ARMADA A388 SOMs. According to SolidRun Knowledge Base, the changes already pushed to mainline U-Boot. But then it was overwritten when Marvell DDR Training Tool updated [URL] https://developer.solid-run.com/knowledge-base/armada-38x-som-u-boot-odt-update/ Signed-off-by: Aditya Prayoga --- .../ARMADA-A388-SOM-U-Boot-ODT-Update.patch | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 patch/u-boot/u-boot-mvebu-next/ARMADA-A388-SOM-U-Boot-ODT-Update.patch diff --git a/patch/u-boot/u-boot-mvebu-next/ARMADA-A388-SOM-U-Boot-ODT-Update.patch b/patch/u-boot/u-boot-mvebu-next/ARMADA-A388-SOM-U-Boot-ODT-Update.patch new file mode 100644 index 0000000000..5cae2546ff --- /dev/null +++ b/patch/u-boot/u-boot-mvebu-next/ARMADA-A388-SOM-U-Boot-ODT-Update.patch @@ -0,0 +1,60 @@ +From befbb65412d22f698703207d8d29b7707fcb62b3 Mon Sep 17 00:00:00 2001 +Message-Id: +From: Aditya Prayoga +Date: Tue, 19 Mar 2019 19:28:44 +0800 +Subject: [PATCH] ARMADA A388 SOM U-Boot ODT Update + +Old versions of U-Boot did not configure correctly the ODT on data +signals of DDR RAM on ARMADA A388 SOMs.[1] + +The changes on [2] adapted into current source. + +[1] +https://developer.solid-run.com/knowledge-base/armada-38x-som-u-boot-odt-update/ + +[2]https://github.com/SolidRun/u-boot/commit/ab15b2d5b6ee50c106628dc0aa5943747a5dd772 + +Signed-off-by: Aditya Prayoga +--- + drivers/ddr/marvell/a38x/ddr3_training.c | 4 ++-- + drivers/ddr/marvell/a38x/mv_ddr_plat.h | 2 +- + 2 files changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c +index 799c5ba089..33d4255bba 100644 +--- a/drivers/ddr/marvell/a38x/ddr3_training.c ++++ b/drivers/ddr/marvell/a38x/ddr3_training.c +@@ -1606,7 +1606,7 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, + CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, + if_id, DDR_ODT_TIMING_LOW_REG, + val, 0xffff0)); +- val = 0x91 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12); ++ val = 0x71 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12); + CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, + if_id, DDR_ODT_TIMING_HIGH_REG, + val, 0xffff)); +@@ -1661,7 +1661,7 @@ static int ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type, + + CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, + DDR_ODT_TIMING_LOW_REG, val, 0xffff0)); +- val = 0x91 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12); ++ val = 0x71 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12); + CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, + DDR_ODT_TIMING_HIGH_REG, val, 0xffff)); + if (odt_additional == 1) { +diff --git a/drivers/ddr/marvell/a38x/mv_ddr_plat.h b/drivers/ddr/marvell/a38x/mv_ddr_plat.h +index 9c5fdecd93..e01e89ca05 100644 +--- a/drivers/ddr/marvell/a38x/mv_ddr_plat.h ++++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.h +@@ -33,7 +33,7 @@ + #define TUNE_TRAINING_PARAMS_N_ODT_CTRL 45 + #define TUNE_TRAINING_PARAMS_DIC 0x2 + #define TUNE_TRAINING_PARAMS_ODT_CONFIG_2CS 0x120012 +-#define TUNE_TRAINING_PARAMS_ODT_CONFIG_1CS 0x10000 ++#define TUNE_TRAINING_PARAMS_ODT_CONFIG_1CS 0x30000 + #define TUNE_TRAINING_PARAMS_RTT_NOM 0x44 + + #define TUNE_TRAINING_PARAMS_RTT_WR_1CS 0x0 /*off*/ +-- +2.17.1 +