diff --git a/patch/kernel/sunxi-current/fix-Pinebook-A64-LCD-revert-ccu-sun50i-a64.patch b/patch/kernel/sunxi-current/fix-Pinebook-A64-LCD-revert-ccu-sun50i-a64.patch
new file mode 100644
index 0000000000..bdc312a67e
--- /dev/null
+++ b/patch/kernel/sunxi-current/fix-Pinebook-A64-LCD-revert-ccu-sun50i-a64.patch
@@ -0,0 +1,39 @@
+diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+index 52bad5f61..47eeb9a1e 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
++++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+@@ -558,8 +558,8 @@ static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
+  * is required to restore the rate of TCON0 when the rate of PLL-Video0
+  * changed.
+  */
+-static const char * const tcon0_parents[] = { "pll-mipi", /* "pll-video0-2x" */ };
+-static const u8 tcon0_table[] = { 0, /* 2, */ };
++static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
++static const u8 tcon0_table[] = { 0, 2, };
+ static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents,
+ 				     tcon0_table, 0x118, 24, 3, BIT(31),
+ 				     CLK_SET_RATE_PARENT);
+@@ -1004,9 +1004,9 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	/* Force the parent of TCON0 to PLL-MIPI */
+-	val = readl(reg + SUN50I_A64_TCON0_REG);
+-	val &= ~GENMASK(26, 24);
+-	writel(val | (0 << 24), reg + SUN50I_A64_TCON0_REG);
++//	val = readl(reg + SUN50I_A64_TCON0_REG);
++//	val &= ~GENMASK(26, 24);
++//	writel(val | (0 << 24), reg + SUN50I_A64_TCON0_REG);
+ 
+ 	ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);
+ 	if (ret)
+@@ -1020,8 +1020,8 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
+ 				  &sun50i_a64_cpu_nb);
+ 
+ 	/* Reset the rate of TCON0 clock when PLL-VIDEO0 is changed */
+-	sun50i_a64_pll_video0_reset_tcon0_nb.target_clk = tcon0_clk.common.hw.clk;
+-	ccu_rate_reset_notifier_register(&sun50i_a64_pll_video0_reset_tcon0_nb);
++//	sun50i_a64_pll_video0_reset_tcon0_nb.target_clk = tcon0_clk.common.hw.clk;
++//	ccu_rate_reset_notifier_register(&sun50i_a64_pll_video0_reset_tcon0_nb);
+ 
+ 	return 0;
+ }