diff --git a/config/boards/turing-rk1.csc b/config/boards/turing-rk1.csc new file mode 100644 index 0000000000..499f32697d --- /dev/null +++ b/config/boards/turing-rk1.csc @@ -0,0 +1,66 @@ +# Rockchip RK3588 octa core 8/16/32GB RAM SoM GBE NVMe eMMC USB3 +BOARD_NAME="Turing RK1" +BOARDFAMILY="rockchip-rk3588" +BOARD_MAINTAINER="" +BOOTCONFIG="turing-rk1-rk3588_defconfig" +BOOT_SOC="rk3588" +KERNEL_TARGET="edge,current,vendor" +KERNEL_TEST_TARGET="vendor,current" +FULL_DESKTOP="yes" +BOOT_LOGO="desktop" +IMAGE_PARTITION_TABLE="gpt" +BOOT_FDT_FILE="rockchip/rk3588-turing-rk1.dtb" +BOOT_SCENARIO="spl-blobs" +DDR_BLOB='rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_uart9_115200_v1.16.bin' + +function post_family_config__turing-rk1_default_serial_console_by_branch() { + display_alert "$BOARD" "Declare serialcon for $BOARD / $BRANCH" "info" + + case $BRANCH in + vendor) + declare -g SERIALCON="ttyS9" + ;; + *) + declare -g SERIALCON="ttyS0" + ;; + esac + + return 0 +} + +function post_family_tweaks__turing-rk1_default_serial_console_by_branch() { + display_alert "$BOARD" "Modify bootscript serial console for $BOARD / $BRANCH" "info" + + case $BRANCH in + vendor) + sed -i 's/console=ttyS2,1500000/console=ttyS9,115200/g' $SDCARD/boot/boot.cmd + ;; + *) + sed -i 's/console=ttyS2,1500000/console=ttyS0,115200/g' $SDCARD/boot/boot.cmd + ;; + esac + + mkimage -C none -A arm -T script -d $SDCARD/boot/boot.cmd $SDCARD/boot/boot.scr + + return 0 +} + +function post_family_config__turing-rk1_use_mainline_uboot() { + display_alert "$BOARD" "Using mainline U-Boot for $BOARD / $BRANCH" "info" + + declare -g BOOTSOURCE="https://github.com/u-boot/u-boot.git" + declare -g BOOTBRANCH='tag:v2024.04' + declare -g BOOTPATCHDIR="v2024.04" + declare -g BOOTDELAY=1 + # Don't set BOOTDIR, allow shared U-Boot source directory for disk space efficiency + + declare -g UBOOT_TARGET_MAP="BL31=${RKBIN_DIR}/${BL31_BLOB} ROCKCHIP_TPL=${RKBIN_DIR}/${DDR_BLOB};;u-boot-rockchip.bin" + + # Disable stuff from rockchip64_common; we're using binman here which does all the work already + unset uboot_custom_postprocess write_uboot_platform write_uboot_platform_mtd + + # Just use the binman-provided u-boot-rockchip.bin, which is ready-to-go + function write_uboot_platform() { + dd "if=$1/u-boot-rockchip.bin" "of=$2" bs=32k seek=1 conv=notrunc status=none + } +} diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/1060-arm64-dts-rockchip-Split-pcie30x1m1-pinctrl.patch b/patch/kernel/archive/rockchip-rk3588-6.10/1060-arm64-dts-rockchip-Split-pcie30x1m1-pinctrl.patch new file mode 100644 index 0000000000..7055c6111f --- /dev/null +++ b/patch/kernel/archive/rockchip-rk3588-6.10/1060-arm64-dts-rockchip-Split-pcie30x1m1-pinctrl.patch @@ -0,0 +1,47 @@ +From 31f55e29d6b6a33d800b543c1e92825fe33fb4db Mon Sep 17 00:00:00 2001 +From: Joshua Riek +Date: Wed, 7 Aug 2024 10:19:47 -0400 +Subject: [PATCH] arm64: dts: rockchip: Split pcie30x1m1 pinctrl + +The PCIe 3.0 PHYs need an external clock and will assert CLKREQ# to +get it. Some RK3588 boards such as the Turning RK1, Mixtile 3588E, +and the ArmSoM AIM7 only provide this clock when CLKREQ# is asserted. + +Signed-off-by: Joshua Riek +--- + .../arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi | 16 +++++++++++++--- + 1 file changed, 13 insertions(+), 3 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi +index 30db12c4fc82..e8f5e252a5de 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi +@@ -1785,12 +1785,22 @@ pcie30x4m0_pins: pcie30x4m0-pins { + }; + + /omit-if-no-ref/ +- pcie30x4m1_pins: pcie30x4m1-pins { ++ pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 { + rockchip,pins = + /* pcie30x4_clkreqn_m1 */ +- <4 RK_PB4 4 &pcfg_pull_none>, ++ <4 RK_PB4 4 &pcfg_pull_down>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x4_perstn_m1: pcie30x4-perstn-m1 { ++ rockchip,pins = + /* pcie30x4_perstn_m1 */ +- <4 RK_PB6 4 &pcfg_pull_none>, ++ <4 RK_PB6 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x4_waken_m1: pcie30x4-waken-m1 { ++ rockchip,pins = + /* pcie30x4_waken_m1 */ + <4 RK_PB5 4 &pcfg_pull_none>; + }; +-- +2.25.1 + diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/1061-arm64-dts-rockchip-Add-PCIe-3.0-pinctrl-to-Turing-RK.patch b/patch/kernel/archive/rockchip-rk3588-6.10/1061-arm64-dts-rockchip-Add-PCIe-3.0-pinctrl-to-Turing-RK.patch new file mode 100644 index 0000000000..d2eab1f536 --- /dev/null +++ b/patch/kernel/archive/rockchip-rk3588-6.10/1061-arm64-dts-rockchip-Add-PCIe-3.0-pinctrl-to-Turing-RK.patch @@ -0,0 +1,30 @@ +From b8322ec8dc89b0020bb4d552e79f99fac04fa3aa Mon Sep 17 00:00:00 2001 +From: Joshua Riek +Date: Wed, 7 Aug 2024 10:30:50 -0400 +Subject: [PATCH 06/15] arm64: dts: rockchip: Add PCIe 3.0 pinctrl to Turing + RK1 + +The Turning RK1 needs to assert CLKREQ# to provide an external +clock to the PCIe 3.0 PHYs. + +Signed-off-by: Joshua Riek +--- + arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +index dbaa94ca69f4..5d0053ee3d45 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +@@ -223,7 +223,7 @@ &pcie30phy { + &pcie3x4 { + linux,pci-domain = <0>; + pinctrl-names = "default"; +- pinctrl-0 = <&pcie3_reset>; ++ pinctrl-0 = <&pcie3_reset>, <&pcie30x4_clkreqn_m1>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +-- +2.25.1 + diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/1062-arm64-dts-rockchip-Enable-GPU-node-on-Turing-RK1.patch b/patch/kernel/archive/rockchip-rk3588-6.10/1062-arm64-dts-rockchip-Enable-GPU-node-on-Turing-RK1.patch new file mode 100644 index 0000000000..2020f98c10 --- /dev/null +++ b/patch/kernel/archive/rockchip-rk3588-6.10/1062-arm64-dts-rockchip-Enable-GPU-node-on-Turing-RK1.patch @@ -0,0 +1,31 @@ +From 82e3d9c7dc918bb4278bdce7e9a0c4579781818d Mon Sep 17 00:00:00 2001 +From: Joshua Riek +Date: Wed, 7 Aug 2024 10:34:35 -0400 +Subject: [PATCH 07/15] arm64: dts: rockchip: Enable GPU node on Turing RK1 + +Enables the Mali G610 GPU. + +Signed-off-by: Joshua Riek +--- + arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +index 5d0053ee3d45..e157c5acfcb5 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +@@ -101,6 +101,11 @@ &cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; + }; + ++&gpu { ++ mali-supply = <&vdd_gpu_s0>; ++ status = "okay"; ++}; ++ + &gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; +-- +2.25.1 + diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/1063-arm64-dts-rockchip-Enable-automatic-fan-control-on-t.patch b/patch/kernel/archive/rockchip-rk3588-6.10/1063-arm64-dts-rockchip-Enable-automatic-fan-control-on-t.patch new file mode 100644 index 0000000000..08b3d5f722 --- /dev/null +++ b/patch/kernel/archive/rockchip-rk3588-6.10/1063-arm64-dts-rockchip-Enable-automatic-fan-control-on-t.patch @@ -0,0 +1,63 @@ +From ec302349e26ce4bc00b2d438348d302bd468cb11 Mon Sep 17 00:00:00 2001 +From: Joshua Riek +Date: Thu, 22 Aug 2024 22:32:47 -0400 +Subject: [PATCH 12/15] arm64: dts: rockchip: Enable automatic fan control on + the Turing RK1 + +--- + .../boot/dts/rockchip/rk3588-turing-rk1.dtsi | 32 ++++++++++++++++++- + 1 file changed, 31 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +index f56a6a10c2ad..18b687a30e94 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +@@ -24,7 +24,7 @@ aliases { + + fan: pwm-fan { + compatible = "pwm-fan"; +- cooling-levels = <0 25 95 145 195 255>; ++ cooling-levels = <0 120 150 180 210 240 255>; + fan-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0m2_pins &fan_int>; +@@ -234,6 +234,36 @@ rgmii_phy: ethernet-phy@1 { + }; + }; + ++&package_thermal { ++ polling-delay = <1000>; ++ ++ trips { ++ package_fan0: package-fan0 { ++ temperature = <55000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ package_fan1: package-fan1 { ++ temperature = <65000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ }; ++ ++ cooling-maps { ++ map1 { ++ trip = <&package_fan0>; ++ cooling-device = <&fan THERMAL_NO_LIMIT 1>; ++ }; ++ ++ map2 { ++ trip = <&package_fan1>; ++ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; ++ }; ++ }; ++}; ++ + &pcie2x1l1 { + linux,pci-domain = <1>; + pinctrl-names = "default"; +-- +2.25.1 + diff --git a/patch/kernel/archive/rockchip-rk3588-6.10/1064-arm64-dts-rockchip-Add-missing-hym8563-clock-frequen.patch b/patch/kernel/archive/rockchip-rk3588-6.10/1064-arm64-dts-rockchip-Add-missing-hym8563-clock-frequen.patch new file mode 100644 index 0000000000..8663612310 --- /dev/null +++ b/patch/kernel/archive/rockchip-rk3588-6.10/1064-arm64-dts-rockchip-Add-missing-hym8563-clock-frequen.patch @@ -0,0 +1,26 @@ +From 8fa9e89184e736af4b81fdb67d5efa35f5d1996e Mon Sep 17 00:00:00 2001 +From: Joshua Riek +Date: Wed, 7 Aug 2024 14:12:21 -0400 +Subject: [PATCH 08/15] arm64: dts: rockchip: Add missing hym8563 + clock-frequency for Turing RK1 + +Signed-off-by: Joshua Riek +--- + arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +index e157c5acfcb5..dc36a7e048da 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +@@ -191,6 +191,7 @@ hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; ++ clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; +-- +2.25.1 + diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/1060-arm64-dts-rockchip-Split-pcie30x1m1-pinctrl.patch b/patch/kernel/archive/rockchip-rk3588-6.11/1060-arm64-dts-rockchip-Split-pcie30x1m1-pinctrl.patch new file mode 100644 index 0000000000..7d7e430610 --- /dev/null +++ b/patch/kernel/archive/rockchip-rk3588-6.11/1060-arm64-dts-rockchip-Split-pcie30x1m1-pinctrl.patch @@ -0,0 +1,47 @@ +From 3d447d15299c7eab3058e259c2514d4b407d8de1 Mon Sep 17 00:00:00 2001 +From: Joshua Riek +Date: Wed, 7 Aug 2024 10:19:47 -0400 +Subject: [PATCH 05/15] arm64: dts: rockchip: Split pcie30x1m1 pinctrl + +The PCIe 3.0 PHYs need an external clock and will assert CLKREQ# to +get it. Some RK3588 boards such as the Turning RK1, Mixtile 3588E, +and the ArmSoM AIM7 only provide this clock when CLKREQ# is asserted. + +Signed-off-by: Joshua Riek +--- + .../boot/dts/rockchip/rk3588-base-pinctrl.dtsi | 16 +++++++++++++--- + 1 file changed, 13 insertions(+), 3 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi +index ca006f5a4c90..6de5729d2e65 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi +@@ -1799,12 +1799,22 @@ pcie30x4m0_pins: pcie30x4m0-pins { + }; + + /omit-if-no-ref/ +- pcie30x4m1_pins: pcie30x4m1-pins { ++ pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 { + rockchip,pins = + /* pcie30x4_clkreqn_m1 */ +- <4 RK_PB4 4 &pcfg_pull_none>, ++ <4 RK_PB4 4 &pcfg_pull_down>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x4_perstn_m1: pcie30x4-perstn-m1 { ++ rockchip,pins = + /* pcie30x4_perstn_m1 */ +- <4 RK_PB6 4 &pcfg_pull_none>, ++ <4 RK_PB6 4 &pcfg_pull_none>; ++ }; ++ ++ /omit-if-no-ref/ ++ pcie30x4_waken_m1: pcie30x4-waken-m1 { ++ rockchip,pins = + /* pcie30x4_waken_m1 */ + <4 RK_PB5 4 &pcfg_pull_none>; + }; +-- +2.25.1 + diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/1061-arm64-dts-rockchip-Add-PCIe-3.0-pinctrl-to-Turing-RK.patch b/patch/kernel/archive/rockchip-rk3588-6.11/1061-arm64-dts-rockchip-Add-PCIe-3.0-pinctrl-to-Turing-RK.patch new file mode 100644 index 0000000000..d2eab1f536 --- /dev/null +++ b/patch/kernel/archive/rockchip-rk3588-6.11/1061-arm64-dts-rockchip-Add-PCIe-3.0-pinctrl-to-Turing-RK.patch @@ -0,0 +1,30 @@ +From b8322ec8dc89b0020bb4d552e79f99fac04fa3aa Mon Sep 17 00:00:00 2001 +From: Joshua Riek +Date: Wed, 7 Aug 2024 10:30:50 -0400 +Subject: [PATCH 06/15] arm64: dts: rockchip: Add PCIe 3.0 pinctrl to Turing + RK1 + +The Turning RK1 needs to assert CLKREQ# to provide an external +clock to the PCIe 3.0 PHYs. + +Signed-off-by: Joshua Riek +--- + arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +index dbaa94ca69f4..5d0053ee3d45 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +@@ -223,7 +223,7 @@ &pcie30phy { + &pcie3x4 { + linux,pci-domain = <0>; + pinctrl-names = "default"; +- pinctrl-0 = <&pcie3_reset>; ++ pinctrl-0 = <&pcie3_reset>, <&pcie30x4_clkreqn_m1>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +-- +2.25.1 + diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/1062-arm64-dts-rockchip-Enable-GPU-node-on-Turing-RK1.patch b/patch/kernel/archive/rockchip-rk3588-6.11/1062-arm64-dts-rockchip-Enable-GPU-node-on-Turing-RK1.patch new file mode 100644 index 0000000000..2020f98c10 --- /dev/null +++ b/patch/kernel/archive/rockchip-rk3588-6.11/1062-arm64-dts-rockchip-Enable-GPU-node-on-Turing-RK1.patch @@ -0,0 +1,31 @@ +From 82e3d9c7dc918bb4278bdce7e9a0c4579781818d Mon Sep 17 00:00:00 2001 +From: Joshua Riek +Date: Wed, 7 Aug 2024 10:34:35 -0400 +Subject: [PATCH 07/15] arm64: dts: rockchip: Enable GPU node on Turing RK1 + +Enables the Mali G610 GPU. + +Signed-off-by: Joshua Riek +--- + arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +index 5d0053ee3d45..e157c5acfcb5 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +@@ -101,6 +101,11 @@ &cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; + }; + ++&gpu { ++ mali-supply = <&vdd_gpu_s0>; ++ status = "okay"; ++}; ++ + &gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; +-- +2.25.1 + diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/1063-arm64-dts-rockchip-Enable-automatic-fan-control-on-t.patch b/patch/kernel/archive/rockchip-rk3588-6.11/1063-arm64-dts-rockchip-Enable-automatic-fan-control-on-t.patch new file mode 100644 index 0000000000..08b3d5f722 --- /dev/null +++ b/patch/kernel/archive/rockchip-rk3588-6.11/1063-arm64-dts-rockchip-Enable-automatic-fan-control-on-t.patch @@ -0,0 +1,63 @@ +From ec302349e26ce4bc00b2d438348d302bd468cb11 Mon Sep 17 00:00:00 2001 +From: Joshua Riek +Date: Thu, 22 Aug 2024 22:32:47 -0400 +Subject: [PATCH 12/15] arm64: dts: rockchip: Enable automatic fan control on + the Turing RK1 + +--- + .../boot/dts/rockchip/rk3588-turing-rk1.dtsi | 32 ++++++++++++++++++- + 1 file changed, 31 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +index f56a6a10c2ad..18b687a30e94 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +@@ -24,7 +24,7 @@ aliases { + + fan: pwm-fan { + compatible = "pwm-fan"; +- cooling-levels = <0 25 95 145 195 255>; ++ cooling-levels = <0 120 150 180 210 240 255>; + fan-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0m2_pins &fan_int>; +@@ -234,6 +234,36 @@ rgmii_phy: ethernet-phy@1 { + }; + }; + ++&package_thermal { ++ polling-delay = <1000>; ++ ++ trips { ++ package_fan0: package-fan0 { ++ temperature = <55000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ package_fan1: package-fan1 { ++ temperature = <65000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ }; ++ ++ cooling-maps { ++ map1 { ++ trip = <&package_fan0>; ++ cooling-device = <&fan THERMAL_NO_LIMIT 1>; ++ }; ++ ++ map2 { ++ trip = <&package_fan1>; ++ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; ++ }; ++ }; ++}; ++ + &pcie2x1l1 { + linux,pci-domain = <1>; + pinctrl-names = "default"; +-- +2.25.1 + diff --git a/patch/kernel/archive/rockchip-rk3588-6.11/1064-arm64-dts-rockchip-Add-missing-hym8563-clock-frequen.patch b/patch/kernel/archive/rockchip-rk3588-6.11/1064-arm64-dts-rockchip-Add-missing-hym8563-clock-frequen.patch new file mode 100644 index 0000000000..8663612310 --- /dev/null +++ b/patch/kernel/archive/rockchip-rk3588-6.11/1064-arm64-dts-rockchip-Add-missing-hym8563-clock-frequen.patch @@ -0,0 +1,26 @@ +From 8fa9e89184e736af4b81fdb67d5efa35f5d1996e Mon Sep 17 00:00:00 2001 +From: Joshua Riek +Date: Wed, 7 Aug 2024 14:12:21 -0400 +Subject: [PATCH 08/15] arm64: dts: rockchip: Add missing hym8563 + clock-frequency for Turing RK1 + +Signed-off-by: Joshua Riek +--- + arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +index e157c5acfcb5..dc36a7e048da 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +@@ -191,6 +191,7 @@ hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; ++ clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; +-- +2.25.1 + diff --git a/patch/u-boot/v2024.04/board_turing-rk1/0001-include-turing-rk1-rk3588-define-boot-targets.patch b/patch/u-boot/v2024.04/board_turing-rk1/0001-include-turing-rk1-rk3588-define-boot-targets.patch new file mode 100644 index 0000000000..d1e7b7d39d --- /dev/null +++ b/patch/u-boot/v2024.04/board_turing-rk1/0001-include-turing-rk1-rk3588-define-boot-targets.patch @@ -0,0 +1,28 @@ +From 7e8b7d108febaa339b5be48345701de30f865c7a Mon Sep 17 00:00:00 2001 +From: Joshua Riek +Date: Fri, 19 Jan 2024 16:18:58 -0500 +Subject: [PATCH 1/3] include: turing-rk1-rk3588: define boot targets + +Signed-off-by: Joshua Riek +--- + include/configs/turing-rk1-rk3588.h | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/include/configs/turing-rk1-rk3588.h b/include/configs/turing-rk1-rk3588.h +index 760f3c6ab3..1e7e58f72c 100644 +--- a/include/configs/turing-rk1-rk3588.h ++++ b/include/configs/turing-rk1-rk3588.h +@@ -12,4 +12,10 @@ + + #include + ++#ifdef BOOT_TARGETS ++#undef BOOT_TARGETS ++#endif ++ ++#define BOOT_TARGETS "mmc1 nvme scsi usb mmc0 pxe dhcp spi" ++ + #endif /* __TURINGRK1_RK3588_H */ +-- +2.25.1 + diff --git a/patch/u-boot/v2024.04/board_turing-rk1/0002-arm-dts-rk3588-turing-rk1-fix-pcie3x4-hang.patch b/patch/u-boot/v2024.04/board_turing-rk1/0002-arm-dts-rk3588-turing-rk1-fix-pcie3x4-hang.patch new file mode 100644 index 0000000000..15e063d6f1 --- /dev/null +++ b/patch/u-boot/v2024.04/board_turing-rk1/0002-arm-dts-rk3588-turing-rk1-fix-pcie3x4-hang.patch @@ -0,0 +1,40 @@ +From e556737e9b1e70fd3bae957a55e75692c42fc163 Mon Sep 17 00:00:00 2001 +From: Joshua Riek +Date: Fri, 19 Jan 2024 16:22:50 -0500 +Subject: [PATCH 2/3] arm64: dts: rockchip: Add PCIe 3.0 pinctrl to Turing RK1 + +The Turning RK1 needs to assert CLKREQ# to provide an external +clock to the PCIe 3.0 PHYs. + +Signed-off-by: Joshua Riek +--- + arch/arm/dts/rk3588-turing-rk1.dtsi | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/dts/rk3588-turing-rk1.dtsi b/arch/arm/dts/rk3588-turing-rk1.dtsi +index 9570b34aca..978b1a82da 100644 +--- a/arch/arm/dts/rk3588-turing-rk1.dtsi ++++ b/arch/arm/dts/rk3588-turing-rk1.dtsi +@@ -226,7 +226,7 @@ + &pcie3x4 { + linux,pci-domain = <0>; + pinctrl-names = "default"; +- pinctrl-0 = <&pcie3_reset>; ++ pinctrl-0 = <&pcie3_reset>, <&pcie3_clkreqn_m1>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +@@ -259,6 +259,10 @@ + vcc3v3_pcie30_en: pcie3-reg { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; ++ ++ pcie3_clkreqn_m1: pcie3-clkreqn-m1 { ++ rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; + }; + + rtl8211f { +-- +2.25.1 +