From d4f572272e4b33f7d09b26c79412f78fd5dc33e6 Mon Sep 17 00:00:00 2001 From: Igor Pecovnik Date: Sat, 9 Feb 2019 19:20:36 +0100 Subject: [PATCH] [ sunxi ] Move legacy builds back to last known working u-boot 2018.05 until its not resolved why legacy kernels are not booting anymore with 2018.11, 2019.01, ... --- config/sources/sunxi_common.inc | 2 + ...ixup_ethernet-again-to-set-macaddr-f.patch | 42 + .../4kfix-limit-screen-to-full-hd.patch | 19 + .../Merrii_Hummingbird_A20.patch | 29 + ...add-a20-olinuxino-micro-emmc-support.patch | 163 ++++ .../add-a20-optional-eMMC.patch | 18 + .../add-awsom-defconfig.patch | 35 + .../add-bananapi-bpi-zero.patch | 184 ++++ .../u-boot-sunxi-legacy/add-beelink-x2.patch | 136 +++ .../add-emmc_support_to_neo1_and_2.patch | 24 + .../add-nanopi-air-emmc.patch | 9 + .../u-boot-sunxi-legacy/add-nanopi-duo.patch | 143 +++ .../add-nanopi-m1-plus2-emmc.patch | 173 ++++ .../add-nanopineoplus2.patch | 156 ++++ .../add-orangepi-plus2-emmc.patch | 9 + .../add-orangepi-zero-usb-boot-support.patch | 26 + .../add-orangepi-zeroplus.patch | 159 ++++ .../add-orangepi-zeroplus2_h3.patch | 219 +++++ .../u-boot-sunxi-legacy/add-sunvell-r69.patch | 212 +++++ .../add-tritium-series.patch | 497 +++++++++++ .../add-xx-boot-auto-dt-select-neo2.patch | 119 +++ .../add-xx-nanopi-k1-plus-emmc.patch | 143 +++ .../add-xx-nanopineocore2.patch | 156 ++++ .../add_emmc_olinuxino_a64.patch | 45 + .../add_emmc_orangepiwin.patch | 87 ++ .../adjust-default-dram-clockspeeds.patch | 272 ++++++ .../adjust-small-boards-cpufreq.patch | 33 + .../GMAC_TX_DELAY_autocorrection.patch | 75 ++ .../GMAC_TX_DELAY_autocorrection.patch | 72 ++ .../board_pine64so/fix-sopine-defconfig.patch | 206 +++++ .../01-add-sunxi-pwm-driver.patch | 274 ++++++ .../02-add-axp803-pmic-support.patch | 821 ++++++++++++++++++ .../04-pwm_backlight-regulator-optional.patch | 62 ++ .../05-add-pwm-node-DT.patch | 31 + .../12-add-pinebook-dt-and-defconfig.patch | 193 ++++ .../do-not-relocate-initrd.patch | 27 + .../enable-old-kernel-compat.patch | 13 + ...around-reboot-is-poweroff-olimex-a20.patch | 36 + ...around-reboot-is-poweroff-olimex-a20.patch | 36 + .../enable-DT-overlays-support.patch | 13 + .../enable-autoboot-keyed.patch | 34 + .../enable-ethernet-orangepiprime.patch | 13 + .../enable-r_pio-gpio-access-h3-h5.patch | 24 + .../fdt-setprop-fix-unaligned-access.patch | 24 + .../fix-usb-phy-probe.patch.disabled | 102 +++ .../fix-usb1-vbus-opiwin.patch | 60 ++ ...Fix-PLL1-setup-to-never-use-dividers.patch | 33 + .../h3-enable-power-led.patch | 17 + .../h3-set-safe-axi_apb-clock-dividers.patch | 42 + .../lower-default-DRAM-freq-A64-H5.patch | 13 + ...ove-boot-messages-from-hdmi.patch.disabled | 14 + .../sun8i-set-machid.patch | 11 + .../sunxi-boot-splash.patch | 62 ++ 53 files changed, 5418 insertions(+) create mode 100644 patch/u-boot/u-boot-sunxi-legacy/0020-sunxi-call-fdt_fixup_ethernet-again-to-set-macaddr-f.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/4kfix-limit-screen-to-full-hd.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/Merrii_Hummingbird_A20.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/add-a20-olinuxino-micro-emmc-support.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/add-a20-optional-eMMC.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/add-awsom-defconfig.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/add-bananapi-bpi-zero.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/add-beelink-x2.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/add-emmc_support_to_neo1_and_2.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/add-nanopi-air-emmc.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/add-nanopi-duo.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/add-nanopi-m1-plus2-emmc.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/add-nanopineoplus2.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/add-orangepi-plus2-emmc.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/add-orangepi-zero-usb-boot-support.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/add-orangepi-zeroplus.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/add-orangepi-zeroplus2_h3.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/add-sunvell-r69.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/add-tritium-series.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/add-xx-boot-auto-dt-select-neo2.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/add-xx-nanopi-k1-plus-emmc.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/add-xx-nanopineocore2.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/add_emmc_olinuxino_a64.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/add_emmc_orangepiwin.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/adjust-default-dram-clockspeeds.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/adjust-small-boards-cpufreq.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/board_lime2/GMAC_TX_DELAY_autocorrection.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/board_olimex-som-a20/GMAC_TX_DELAY_autocorrection.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/board_pine64so/fix-sopine-defconfig.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/board_pinebook-a64/01-add-sunxi-pwm-driver.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/board_pinebook-a64/02-add-axp803-pmic-support.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/board_pinebook-a64/04-pwm_backlight-regulator-optional.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/board_pinebook-a64/05-add-pwm-node-DT.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/board_pinebook-a64/12-add-pinebook-dt-and-defconfig.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/branch_default/do-not-relocate-initrd.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/branch_default/enable-old-kernel-compat.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/branch_dev/workaround-reboot-is-poweroff-olimex-a20.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/branch_next/workaround-reboot-is-poweroff-olimex-a20.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/enable-DT-overlays-support.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/enable-autoboot-keyed.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/enable-ethernet-orangepiprime.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/enable-r_pio-gpio-access-h3-h5.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/fdt-setprop-fix-unaligned-access.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/fix-usb-phy-probe.patch.disabled create mode 100644 patch/u-boot/u-boot-sunxi-legacy/fix-usb1-vbus-opiwin.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/h3-Fix-PLL1-setup-to-never-use-dividers.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/h3-enable-power-led.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/h3-set-safe-axi_apb-clock-dividers.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/lower-default-DRAM-freq-A64-H5.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/remove-boot-messages-from-hdmi.patch.disabled create mode 100644 patch/u-boot/u-boot-sunxi-legacy/sun8i-set-machid.patch create mode 100644 patch/u-boot/u-boot-sunxi-legacy/sunxi-boot-splash.patch diff --git a/config/sources/sunxi_common.inc b/config/sources/sunxi_common.inc index d76706d7d8..2af33b0a6c 100644 --- a/config/sources/sunxi_common.inc +++ b/config/sources/sunxi_common.inc @@ -21,6 +21,8 @@ case $BRANCH in GOVERNOR=interactive CAN_BUILD_STRETCH=no + BOOTBRANCH='tag:v2018.05' + BOOTPATCHDIR='u-boot-sunxi-legacy' ;; diff --git a/patch/u-boot/u-boot-sunxi-legacy/0020-sunxi-call-fdt_fixup_ethernet-again-to-set-macaddr-f.patch b/patch/u-boot/u-boot-sunxi-legacy/0020-sunxi-call-fdt_fixup_ethernet-again-to-set-macaddr-f.patch new file mode 100644 index 0000000000..bdd63efabd --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/0020-sunxi-call-fdt_fixup_ethernet-again-to-set-macaddr-f.patch @@ -0,0 +1,42 @@ +From 55d3cc28b37000d1a3d7224c0ba4a808274e0b33 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Fri, 27 Oct 2017 17:25:00 +0800 +Subject: [PATCH 20/20] sunxi: call fdt_fixup_ethernet again to set macaddr for + more aliases + +Sometimes some ethernet aliases do not exist in U-Boot FDT but they +exist in the FDT used to boot the system. In this situation +setup_environment is called again in ft_board_setup to generate macaddr +environment variable for them. However now the call to +fdt_fixup_ethernet is moved before the call of ft_board_setup. + +Call fdt_fixup_ethernet again to add MAC addresses for the extra +ethernet aliases. + +Signed-off-by: Icenowy Zheng +--- + board/sunxi/board.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/board/sunxi/board.c b/board/sunxi/board.c +index 192cf8ca45..0fe70f47cb 100644 +--- a/board/sunxi/board.c ++++ b/board/sunxi/board.c +@@ -751,10 +751,12 @@ int ft_board_setup(void *blob, bd_t *bd) + int __maybe_unused r; + + /* +- * Call setup_environment again in case the boot fdt has +- * ethernet aliases the u-boot copy does not have. ++ * Call setup_environment and fdt_fixup_ethernet again ++ * in case the boot fdt has ethernet aliases the u-boot ++ * copy does not have. + */ + setup_environment(blob); ++ fdt_fixup_ethernet(blob); + + #ifdef CONFIG_VIDEO_DT_SIMPLEFB + r = sunxi_simplefb_setup(blob); +-- +2.13.6 + diff --git a/patch/u-boot/u-boot-sunxi-legacy/4kfix-limit-screen-to-full-hd.patch b/patch/u-boot/u-boot-sunxi-legacy/4kfix-limit-screen-to-full-hd.patch new file mode 100644 index 0000000000..4bbb37a86d --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/4kfix-limit-screen-to-full-hd.patch @@ -0,0 +1,19 @@ +diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c +index 92c9d06054..cd16d69e30 100644 +--- a/drivers/video/sunxi/sunxi_display.c ++++ b/drivers/video/sunxi/sunxi_display.c +@@ -1274,8 +1274,12 @@ void *video_hw_init(void) + ret = sunxi_hdmi_hpd_detect(hpd_delay); + if (ret) { + printf("HDMI connected: "); +- if (edid && sunxi_hdmi_edid_get_mode(&custom) == 0) +- mode = &custom; ++ if (edid && sunxi_hdmi_edid_get_mode(&custom) == 0) { ++ if ((custom.xres <= 1920) && (custom.yres <= 1080)) ++ mode = &custom; ++ else ++ mode = &res_mode_init[RES_MODE_1920x1080]; ++ } + } else if (hpd) { + sunxi_hdmi_shutdown(); + sunxi_display.monitor = sunxi_get_default_mon(false); diff --git a/patch/u-boot/u-boot-sunxi-legacy/Merrii_Hummingbird_A20.patch b/patch/u-boot/u-boot-sunxi-legacy/Merrii_Hummingbird_A20.patch new file mode 100644 index 0000000000..652a58d338 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/Merrii_Hummingbird_A20.patch @@ -0,0 +1,29 @@ +diff --git a/configs/Merrii_Hummingbird_A20_defconfig b/configs/Merrii_Hummingbird_A20_defconfig +new file mode 100644 +index 0000000..20a98bb +--- /dev/null ++++ b/configs/Merrii_Hummingbird_A20_defconfig +@@ -0,0 +1,22 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SPL_I2C_SUPPORT=y ++CONFIG_MACH_SUN7I=y ++CONFIG_DRAM_CLK=432 ++CONFIG_MMC0_CD_PIN="PH1" ++CONFIG_SATAPWR="PB8" ++CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-hummingbird" ++CONFIG_AHCI=y ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SPL_I2C_SUPPORT=y ++CONFIG_SPL=y ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_FPGA is not set ++CONFIG_SCSI_AHCI=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_SUN7I_GMAC=y ++CONFIG_SCSI=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 + diff --git a/patch/u-boot/u-boot-sunxi-legacy/add-a20-olinuxino-micro-emmc-support.patch b/patch/u-boot/u-boot-sunxi-legacy/add-a20-olinuxino-micro-emmc-support.patch new file mode 100644 index 0000000000..175b63a5e4 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/add-a20-olinuxino-micro-emmc-support.patch @@ -0,0 +1,163 @@ +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 9cc5c1e..7ed687e 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -281,6 +281,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \ + sun7i-a20-olinuxino-lime2.dtb \ + sun7i-a20-olinuxino-lime2-emmc.dtb \ + sun7i-a20-olinuxino-micro.dtb \ ++ sun7i-a20-olinuxino-micro-emmc.dtb \ + sun7i-a20-orangepi.dtb \ + sun7i-a20-orangepi-mini.dtb \ + sun7i-a20-pcduino3.dtb \ +diff --git a/arch/arm/dts/sun7i-a20-olinuxino-micro-emmc.dts b/arch/arm/dts/sun7i-a20-olinuxino-micro-emmc.dts +new file mode 100644 +index 0000000..a39247a +--- /dev/null ++++ b/arch/arm/dts/sun7i-a20-olinuxino-micro-emmc.dts +@@ -0,0 +1,83 @@ ++ /* ++ * Copyright 2017 Olimex Ltd. ++ * Stefan Mavrodiev ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#include "sun7i-a20-olinuxino-micro.dts" ++ ++/ { ++ model = "Olimex A20-OLinuXino-MICRO-eMMC"; ++ compatible = "olimex,a20-olinuxino-micro-emmc", "allwinner,sun7i-a20"; ++ ++ mmc2_pwrseq: pwrseq { ++ pinctrl-0 = <&mmc2_pins_nrst>; ++ pinctrl-names = "default"; ++ compatible = "mmc-pwrseq-emmc"; ++ reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&pio { ++ mmc2_pins_nrst: mmc2@0 { ++ allwinner,pins = "PC16"; ++ allwinner,function = "gpio_out"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_pins_a>; ++ vmmc-supply = <®_vcc3v3>; ++ vqmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ non-removable; ++ mmc-pwrseq = <&mmc2_pwrseq>; ++ status = "okay"; ++ ++ emmc: emmc@0 { ++ reg = <0>; ++ compatible = "mmc-card"; ++ broken-hpi; ++ }; ++}; ++ +diff --git a/arch/arm/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/dts/sun7i-a20-olinuxino-micro.dts +index 7e3006f..eb701e3 100644 +--- a/arch/arm/dts/sun7i-a20-olinuxino-micro.dts ++++ b/arch/arm/dts/sun7i-a20-olinuxino-micro.dts +@@ -95,7 +95,7 @@ + + &gmac { + pinctrl-names = "default"; +- pinctrl-0 = <&gmac_pins_mii_a>; ++ pinctrl-0 = <&gmac_pins_mii_a>,<&gmac_txerr>; + phy = <&phy1>; + phy-mode = "mii"; + status = "okay"; +@@ -226,6 +226,13 @@ + }; + + &pio { ++ gmac_txerr: gmac_txerr@0 { ++ allwinner,pins = "PA17"; ++ allwinner,function = "gmac"; ++ allwinner,drive = ; ++ allwinner,pull = ; ++ }; ++ + mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 { + allwinner,pins = "PH11"; + allwinner,function = "gpio_in"; +diff --git a/configs/A20-OLinuXino_MICRO_eMMC_defconfig b/configs/A20-OLinuXino_MICRO_eMMC_defconfig +new file mode 100644 +index 0000000..1ec93e4 +--- /dev/null ++++ b/configs/A20-OLinuXino_MICRO_eMMC_defconfig +@@ -0,0 +1,29 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SYS_TEXT_BASE=0x4a000000 ++CONFIG_MACH_SUN7I=y ++CONFIG_DRAM_CLK=384 ++CONFIG_MMC0_CD_PIN="PH1" ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++CONFIG_I2C1_ENABLE=y ++CONFIG_VIDEO_VGA=y ++CONFIG_SATAPWR="PB8" ++CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro-emmc" ++CONFIG_AHCI=y ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SPL=y ++CONFIG_SPL_I2C_SUPPORT=y ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_FPGA is not set ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_SPL_ISO_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_SCSI_AHCI=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_SUN7I_GMAC=y ++CONFIG_AXP_ALDO3_VOLT=2800 ++CONFIG_AXP_ALDO4_VOLT=2800 ++CONFIG_USB_EHCI_HCD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++CONFIG_SCSI=y diff --git a/patch/u-boot/u-boot-sunxi-legacy/add-a20-optional-eMMC.patch b/patch/u-boot/u-boot-sunxi-legacy/add-a20-optional-eMMC.patch new file mode 100644 index 0000000000..a1719b6d37 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/add-a20-optional-eMMC.patch @@ -0,0 +1,18 @@ +diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig +index ef95ac6a5e..7565786648 100644 +--- a/configs/Cubieboard2_defconfig ++++ b/configs/Cubieboard2_defconfig +@@ -19,3 +19,4 @@ CONFIG_SUN7I_GMAC=y + CONFIG_SCSI=y + CONFIG_USB_EHCI_HCD=y + CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig +index f9f73fdb23..ecb4f2f24e 100644 +--- a/configs/Cubietruck_defconfig ++++ b/configs/Cubietruck_defconfig +@@ -30,3 +30,4 @@ CONFIG_SCSI=y + CONFIG_USB_EHCI_HCD=y + CONFIG_USB_MUSB_GADGET=y + CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 diff --git a/patch/u-boot/u-boot-sunxi-legacy/add-awsom-defconfig.patch b/patch/u-boot/u-boot-sunxi-legacy/add-awsom-defconfig.patch new file mode 100644 index 0000000000..ee708eb780 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/add-awsom-defconfig.patch @@ -0,0 +1,35 @@ +=================================================================== +--- /dev/null ++++ u-boot-2015.01/configs/Awsom_defconfig +@@ -0,0 +1,31 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_MACH_SUN7I=y ++CONFIG_DRAM_CLK=480 ++CONFIG_DRAM_ZQ=127 ++CONFIG_DRAM_EMR1=4 ++CONFIG_MMC0_CD_PIN="PB9" ++CONFIG_SATAPWR="PB8" ++CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2" ++CONFIG_AHCI=y ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SPL_I2C_SUPPORT=y ++CONFIG_SPL=y ++CONFIG_HUSH_PARSER=y ++CONFIG_CMD_BOOTZ=y ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_FPGA is not set ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_I2C=y ++CONFIG_DM_ETH=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_SUN7I_GMAC=y ++CONFIG_DM_SERIAL=y ++CONFIG_USB=y ++CONFIG_DM_USB=y diff --git a/patch/u-boot/u-boot-sunxi-legacy/add-bananapi-bpi-zero.patch b/patch/u-boot/u-boot-sunxi-legacy/add-bananapi-bpi-zero.patch new file mode 100644 index 0000000000..3cf7e2417b --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/add-bananapi-bpi-zero.patch @@ -0,0 +1,184 @@ +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index aaaa9d8..b6eebe8 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -341,6 +341,7 @@ dtb-$(CONFIG_MACH_SUN8I_A83T) += \ + sun8i-a83t-cubietruck-plus.dtb \ + sun8i-a83t-tbs-a711.dts + dtb-$(CONFIG_MACH_SUN8I_H3) += \ ++ sun8i-h2-plus-bananapi-m2-zero.dtb \ + sun8i-h2-plus-orangepi-zero.dtb \ + sun8i-h2-plus-nanopi-duo.dtb \ + sun8i-h2-plus-sunvell-r69.dtb \ +diff --git a/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts +new file mode 100644 +index 0000000..61de91d +--- /dev/null ++++ b/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts +@@ -0,0 +1,141 @@ ++/* ++ * Copyright (C) 2017 Icenowy Zheng ++ * ++ * Based on sun8i-h3-bananapi-m2-plus.dts, which is: ++ * Copyright (C) 2016 Chen-Yu Tsai ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++#include "sun8i-h3.dtsi" ++#include "sunxi-common-regulators.dtsi" ++ ++#include ++#include ++ ++/ { ++ model = "Banana Pi BPI-M2-Zero"; ++ compatible = "sinovoip,bpi-m2-zero", "allwinner,sun8i-h2-plus"; ++ ++ aliases { ++ serial0 = &uart0; ++ serial1 = &uart1; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ ++ pwr_led { ++ label = "bananapi-m2-zero:red:pwr"; ++ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ ++ default-state = "on"; ++ }; ++ }; ++ ++ gpio_keys { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ ++ sw4 { ++ label = "power"; ++ linux,code = ; ++ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ pinctrl-names = "default"; ++ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ ++ }; ++}; ++ ++&mmc0 { ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ /* ++ * On the production batch of this board the card detect GPIO is ++ * high active (card inserted), although on the early samples it's ++ * low active. ++ */ ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ ++ status = "okay"; ++}; ++ ++&mmc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins_a>; ++ vmmc-supply = <®_vcc3v3>; ++ vqmmc-supply = <®_vcc3v3>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ brcmf: wifi@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ interrupt-parent = <&pio>; ++ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ ++ interrupt-names = "host-wake"; ++ }; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++}; ++ ++&usbphy { ++ usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ ++ /* ++ * There're two micro-USB connectors, one is power-only and another is ++ * OTG. The Vbus of these two connectors are connected together, so ++ * the external USB device will be powered just by the power input ++ * from the power-only USB port. ++ */ ++ status = "okay"; ++}; +diff --git a/configs/Sinovoip_BPI_M2_Zero_defconfig b/configs/Sinovoip_BPI_M2_Zero_defconfig +new file mode 100644 +index 0000000..8f96ac1 +--- /dev/null ++++ b/configs/Sinovoip_BPI_M2_Zero_defconfig +@@ -0,0 +1,19 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SYS_TEXT_BASE=0x4a000000 ++CONFIG_MACH_SUN8I_H3=y ++CONFIG_DRAM_CLK=408 ++CONFIG_DRAM_ZQ=3881979 ++CONFIG_DRAM_ODT_EN=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=-1 ++CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-bananapi-m2-zero" ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SPL=y ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_FPGA is not set ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_SPL_ISO_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_SUN8I_EMAC=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_MMC0_CD_PIN="" diff --git a/patch/u-boot/u-boot-sunxi-legacy/add-beelink-x2.patch b/patch/u-boot/u-boot-sunxi-legacy/add-beelink-x2.patch new file mode 100644 index 0000000000..f4a3985f07 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/add-beelink-x2.patch @@ -0,0 +1,136 @@ +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +old mode 100644 +new mode 100755 +index d1bd78c..f268593 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -317,6 +317,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \ + sun8i-h3-orangepi-2.dtb \ + sun8i-h3-orangepi-lite.dtb \ + sun8i-h3-orangepi-one.dtb \ ++ sun8i-h3-beelink-x2.dtb \ + sun8i-h3-orangepi-pc.dtb \ + sun8i-h3-orangepi-pc-plus.dtb \ + sun8i-h3-orangepi-plus.dtb \ +diff --git a/arch/arm/dts/sun8i-h3-beelink-x2.dts b/arch/arm/dts/sun8i-h3-beelink-x2.dts +new file mode 100755 +index 0000000..515a3da +--- /dev/null ++++ b/arch/arm/dts/sun8i-h3-beelink-x2.dts +@@ -0,0 +1,88 @@ ++/* ++ * Copyright (C) 2016 Hans de Goede ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/* The Orange Pi PC Plus is an extended version of the regular PC */ ++#include "sun8i-h3-orangepi-pc.dts" ++ ++/ { ++ model = "Beelink X2"; ++ compatible = "xunlong,orangepi-pc-plus", "allwinner,sun8i-h3"; ++ ++ aliases { ++ /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ ++ ethernet1 = &rtl8189ftv; ++ }; ++}; ++ ++&mmc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins_a>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ /* ++ * Explicitly define the sdio device, so that we can add an ethernet ++ * alias for it (which e.g. makes u-boot set a mac-address). ++ */ ++ rtl8189ftv: sdio_wifi@1 { ++ reg = <1>; ++ }; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&mmc2_8bit_pins { ++ /* Increase drive strength for DDR modes */ ++ allwinner,drive = ; ++ /* eMMC is missing pull-ups */ ++ allwinner,pull = ; ++}; +diff --git a/configs/beelink_x2_defconfig b/configs/beelink_x2_defconfig +new file mode 100755 +index 0000000..098fc05 +--- /dev/null ++++ b/configs/beelink_x2_defconfig +@@ -0,0 +1,22 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SYS_TEXT_BASE=0x4a000000 ++CONFIG_MACH_SUN8I_H3=y ++CONFIG_DRAM_CLK=624 ++CONFIG_DRAM_ZQ=3881979 ++CONFIG_DRAM_ODT_EN=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-beelink-x2" ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SPL=y ++CONFIG_SPL_I2C_SUPPORT=y ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_FPGA is not set ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_SPL_ISO_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_SUN8I_EMAC=y ++CONFIG_SY8106A_POWER=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/patch/u-boot/u-boot-sunxi-legacy/add-emmc_support_to_neo1_and_2.patch b/patch/u-boot/u-boot-sunxi-legacy/add-emmc_support_to_neo1_and_2.patch new file mode 100644 index 0000000000..dace2afef8 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/add-emmc_support_to_neo1_and_2.patch @@ -0,0 +1,24 @@ +diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig +old mode 100644 +new mode 100755 +index fc3465a..a885a85 +--- a/configs/nanopi_neo2_defconfig ++++ b/configs/nanopi_neo2_defconfig +@@ -14,3 +14,4 @@ CONFIG_SPL=y + CONFIG_SUN8I_EMAC=y + CONFIG_USB_EHCI_HCD=y + CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +\ No newline at end of file +diff --git a/configs/nanopi_neo_defconfig b/configs/nanopi_neo_defconfig +old mode 100644 +new mode 100755 +index f87148c..9c8689b +--- a/configs/nanopi_neo_defconfig ++++ b/configs/nanopi_neo_defconfig +@@ -18,3 +18,4 @@ CONFIG_SYS_CLK_FREQ=480000000 + CONFIG_SUN8I_EMAC=y + CONFIG_USB_EHCI_HCD=y + CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +\ No newline at end of file diff --git a/patch/u-boot/u-boot-sunxi-legacy/add-nanopi-air-emmc.patch b/patch/u-boot/u-boot-sunxi-legacy/add-nanopi-air-emmc.patch new file mode 100644 index 0000000000..03a612394d --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/add-nanopi-air-emmc.patch @@ -0,0 +1,9 @@ +diff --git a/configs/nanopi_neo_air_defconfig b/configs/nanopi_neo_air_defconfig +index 11eb3ab13b..9f83068dd7 100644 +--- a/configs/nanopi_neo_air_defconfig ++++ b/configs/nanopi_neo_air_defconfig +@@ -16,3 +16,4 @@ CONFIG_SPL=y + # CONFIG_SPL_EFI_PARTITION is not set + CONFIG_USB_EHCI_HCD=y + CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 diff --git a/patch/u-boot/u-boot-sunxi-legacy/add-nanopi-duo.patch b/patch/u-boot/u-boot-sunxi-legacy/add-nanopi-duo.patch new file mode 100644 index 0000000000..4168706fd4 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/add-nanopi-duo.patch @@ -0,0 +1,143 @@ +diff --git a/configs/nanopi_duo_defconfig b/configs/nanopi_duo_defconfig +new file mode 100644 +index 0000000..1e51018 +--- /dev/null ++++ b/configs/nanopi_duo_defconfig +@@ -0,0 +1,21 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SYS_TEXT_BASE=0x4a000000 ++CONFIG_SPL_SPI_FLASH_SUPPORT=y ++CONFIG_MACH_SUN8I_H3=y ++CONFIG_DRAM_CLK=408 ++CONFIG_DRAM_ZQ=3881979 ++CONFIG_DRAM_ODT_EN=y ++# CONFIG_VIDEO_DE2 is not set ++CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-nanopi-duo" ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_CONSOLE_MUX=y ++CONFIG_SPL=y ++CONFIG_SYS_CLK_FREQ=480000000 ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_FPGA is not set ++CONFIG_SPL_SPI_SUNXI=y ++CONFIG_SUN8I_EMAC=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 4f8ca34..019ac0b 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -312,6 +312,7 @@ dtb-$(CONFIG_MACH_SUN8I_A83T) += \ + sun8i-a83t-sinovoip-bpi-m3.dtb + dtb-$(CONFIG_MACH_SUN8I_H3) += \ + sun8i-h2-plus-orangepi-zero.dtb \ ++ sun8i-h2-plus-nanopi-duo.dtb \ + sun8i-h3-bananapi-m2-plus.dtb \ + sun8i-h3-orangepi-2.dtb \ + sun8i-h3-orangepi-lite.dtb \ +diff --git a/arch/arm/dts/sun8i-h2-plus-nanopi-duo.dts b/arch/arm/dts/sun8i-h2-plus-nanopi-duo.dts +new file mode 100644 +index 0000000..b6afe20 +--- /dev/null ++++ b/arch/arm/dts/sun8i-h2-plus-nanopi-duo.dts +@@ -0,0 +1,98 @@ ++/* ++ * adapted by , based on ++ * Copyright (C) 2017 Jelle van der Waa ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++#include "sun8i-h3.dtsi" ++#include "sunxi-common-regulators.dtsi" ++ ++#include ++#include ++ ++/ { ++ model = "FriendlyARM NanoPi DUO Air"; ++ compatible = "friendlyarm,nanopi-duo-air", "allwinner,sun8i-h3"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ pwr { ++ label = "nanopi:green:pwr"; ++ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ ++ default-state = "on"; ++ }; ++ ++ status { ++ label = "nanopi:blue:status"; ++ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ ++ }; ++ }; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ ++ cd-inverted; ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++}; ++ ++&usbphy { ++ /* USB VBUS is always on */ ++ status = "okay"; ++}; diff --git a/patch/u-boot/u-boot-sunxi-legacy/add-nanopi-m1-plus2-emmc.patch b/patch/u-boot/u-boot-sunxi-legacy/add-nanopi-m1-plus2-emmc.patch new file mode 100644 index 0000000000..07f239283c --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/add-nanopi-m1-plus2-emmc.patch @@ -0,0 +1,173 @@ +diff --git a/arch/arm/dts/sun50i-h5-nanopi-m1-plus2.dts b/arch/arm/dts/sun50i-h5-nanopi-m1-plus2.dts +new file mode 100644 +index 0000000..fdf2c87 +--- /dev/null ++++ b/arch/arm/dts/sun50i-h5-nanopi-m1-plus2.dts +@@ -0,0 +1,126 @@ ++/* ++ * Copyright (C) 2017 Antony Antony ++ * Copyright (c) 2016 ARM Ltd. ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-h5.dtsi" ++ ++#include ++ ++/ { ++ model = "FriendlyARM Nanopi M1 Plus 2"; ++ compatible = "friendlyarm,nanopi-m1-plus2", "allwinner,sun50i-h5"; ++ ++ aliases { ++ serial0 = &uart0; ++ ethernet0 = &emac; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory { ++ reg = <0x40000000 0x40000000>; ++ }; ++ ++ reg_vcc3v3: vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&emac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emac_rgmii_pins>; ++ phy-mode = "rgmii"; ++ phy = <&phy1>; ++ status = "okay"; ++ ++ phy1: ethernet-phy@1 { ++ reg = <1>; ++ }; ++}; ++ ++&mmc0 { ++ compatible = "allwinner,sun50i-h5-mmc", ++ "allwinner,sun50i-a64-mmc", ++ "allwinner,sun5i-a13-mmc"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; ++ cd-inverted; ++ status = "okay"; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++}; ++ ++&usbphy { ++ status = "okay"; ++}; +diff --git a/configs/nanopi_m1_plus2_defconfig b/configs/nanopi_m1_plus2_defconfig +new file mode 100644 +index 0000000..f710366 +--- /dev/null ++++ b/configs/nanopi_m1_plus2_defconfig +@@ -0,0 +1,22 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SYS_TEXT_BASE=0x4a000000 ++CONFIG_SPL_SPI_FLASH_SUPPORT=y ++CONFIG_MACH_SUN50I_H5=y ++CONFIG_DRAM_CLK=576 ++CONFIG_DRAM_ZQ=3881977 ++CONFIG_MACPWR="PD6" ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-m1-plus2" ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SPL=y ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_FPGA is not set ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_SPL_ISO_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_SPL_SPI_SUNXI=y ++CONFIG_SUN8I_EMAC=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index c9ace9f..d1bd78c +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -332,7 +332,8 @@ dtb-$(CONFIG_MACH_SUN8I_V3S) += \ + sun8i-v3s-licheepi-zero.dtb + dtb-$(CONFIG_MACH_SUN50I_H5) += \ + sun50i-h5-nanopi-neo2.dtb \ + sun50i-h5-nanopi-neo-plus2.dtb \ ++ sun50i-h5-nanopi-m1-plus2.dts \ + sun50i-h5-orangepi-pc2.dtb \ + sun50i-h5-orangepi-prime.dtb \ + sun50i-h5-orangepi-zero-plus2.dtb diff --git a/patch/u-boot/u-boot-sunxi-legacy/add-nanopineoplus2.patch b/patch/u-boot/u-boot-sunxi-legacy/add-nanopineoplus2.patch new file mode 100644 index 0000000000..3ac093f64b --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/add-nanopineoplus2.patch @@ -0,0 +1,156 @@ +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index fee4680..295a675 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -377,6 +377,7 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \ + dtb-$(CONFIG_MACH_SUN8I_V3S) += \ + sun8i-v3s-licheepi-zero.dtb + dtb-$(CONFIG_MACH_SUN50I_H5) += \ ++ sun50i-h5-nanopi-neo-plus2.dtb \ + sun50i-h5-nanopi-neo2.dtb \ + sun50i-h5-nanopi-neo-plus2.dtb \ + sun50i-h5-orangepi-zero-plus.dtb \ +diff --git a/configs/nanopi_neo_plus2_defconfig b/configs/nanopi_neo_plus2_defconfig +new file mode 100644 +index 0000000..ff99213 +--- /dev/null ++++ b/configs/nanopi_neo_plus2_defconfig +@@ -0,0 +1,19 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_MACH_SUN50I_H5=y ++CONFIG_DRAM_CLK=408 ++CONFIG_DRAM_ZQ=3881977 ++CONFIG_MACPWR="PD6" ++CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo-plus2" ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SPL=y ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_FPGA is not set ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_SPL_ISO_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_SUN8I_EMAC=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++CONFIG_SD_BOOT=y +diff --git a/arch/arm/dts/sun50i-h5-nanopi-neo-plus2.dts b/arch/arm/dts/sun50i-h5-nanopi-neo-plus2.dts +new file mode 100644 +index 0000000..7d12774 +--- /dev/null ++++ b/arch/arm/dts/sun50i-h5-nanopi-neo-plus2.dts +@@ -0,0 +1,113 @@ ++/* ++ * Copyright (C) 2017 Antony Antony ++ * Copyright (c) 2016 ARM Ltd. ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-h5.dtsi" ++ ++#include ++ ++/ { ++ model = "FriendlyARM NanoPi NEO Plus 2"; ++ compatible = "friendlyarm,nanopi-neo-plus2", "allwinner,sun50i-h5"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory { ++ reg = <0x40000000 0x40000000>; ++ }; ++ ++ reg_vcc3v3: vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&mmc0 { ++ compatible = "allwinner,sun50i-h5-mmc", ++ "allwinner,sun50i-a64-mmc", ++ "allwinner,sun5i-a13-mmc"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; ++ cd-inverted; ++ status = "okay"; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++}; ++ ++&usbphy { ++ status = "okay"; ++}; diff --git a/patch/u-boot/u-boot-sunxi-legacy/add-orangepi-plus2-emmc.patch b/patch/u-boot/u-boot-sunxi-legacy/add-orangepi-plus2-emmc.patch new file mode 100644 index 0000000000..9dea5cc193 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/add-orangepi-plus2-emmc.patch @@ -0,0 +1,9 @@ +diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig +index 7c9cc454c3..2642239c6a 100644 +--- a/configs/orangepi_2_defconfig ++++ b/configs/orangepi_2_defconfig +@@ -20,3 +20,4 @@ CONFIG_SUN8I_EMAC=y + CONFIG_SY8106A_POWER=y + CONFIG_USB_EHCI_HCD=y + CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 diff --git a/patch/u-boot/u-boot-sunxi-legacy/add-orangepi-zero-usb-boot-support.patch b/patch/u-boot/u-boot-sunxi-legacy/add-orangepi-zero-usb-boot-support.patch new file mode 100644 index 0000000000..f995858609 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/add-orangepi-zero-usb-boot-support.patch @@ -0,0 +1,26 @@ +diff --git a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts +index e0efcb3..0fb2099 100644 +--- a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts ++++ b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts +@@ -99,6 +99,10 @@ + status = "okay"; + }; + ++&ehci2 { ++ status = "okay"; ++}; ++ + &emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; +@@ -138,6 +142,10 @@ + status = "okay"; + }; + ++&ohci2 { ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; diff --git a/patch/u-boot/u-boot-sunxi-legacy/add-orangepi-zeroplus.patch b/patch/u-boot/u-boot-sunxi-legacy/add-orangepi-zeroplus.patch new file mode 100644 index 0000000000..c50635a152 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/add-orangepi-zeroplus.patch @@ -0,0 +1,159 @@ +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index fee4680..295a675 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -333,6 +333,7 @@ dtb-$(CONFIG_MACH_SUN8I_V3S) += \ + sun8i-v3s-licheepi-zero.dtb + dtb-$(CONFIG_MACH_SUN50I_H5) += \ + sun50i-h5-nanopi-neo2.dtb \ + sun50i-h5-nanopi-neo-plus2.dtb \ ++ sun50i-h5-orangepi-zero-plus.dtb \ + sun50i-h5-nanopi-m1-plus2.dts \ + sun50i-h5-orangepi-pc2.dtb \ +diff --git a/configs/orangepizero_plus_defconfig b/configs/orangepizero_plus_defconfig +new file mode 100644 +index 0000000..ff99213 +--- /dev/null ++++ b/configs/orangepizero_plus_defconfig +@@ -0,0 +1,22 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SYS_TEXT_BASE=0x4a000000 ++CONFIG_SPL_SPI_FLASH_SUPPORT=y ++CONFIG_MACH_SUN50I_H5=y ++CONFIG_DRAM_CLK=624 ++CONFIG_DRAM_ZQ=3881977 ++CONFIG_MACPWR="PD6" ++CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-zero-plus" ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SPL=y ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_FPGA is not set ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_SPL_ISO_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_SPL_SPI_SUNXI=y ++CONFIG_SUN8I_EMAC=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++CONFIG_SD_BOOT=y +diff --git a/arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts b/arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts +new file mode 100644 +index 0000000..7d12774 +--- /dev/null ++++ b/arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts +@@ -0,0 +1,113 @@ ++/* ++ * Copyright (C) 2017 Antony Antony ++ * Copyright (c) 2016 ARM Ltd. ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-h5.dtsi" ++ ++#include ++ ++/ { ++ model = "Xunlong Orange Pi Zero Plus"; ++ compatible = "xunlong,orangepizero-zero-plus", "allwinner,sun50i-h5"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory { ++ reg = <0x40000000 0x40000000>; ++ }; ++ ++ reg_vcc3v3: vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&mmc0 { ++ compatible = "allwinner,sun50i-h5-mmc", ++ "allwinner,sun50i-a64-mmc", ++ "allwinner,sun5i-a13-mmc"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; ++ cd-inverted; ++ status = "okay"; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++}; ++ ++&usbphy { ++ status = "okay"; ++}; diff --git a/patch/u-boot/u-boot-sunxi-legacy/add-orangepi-zeroplus2_h3.patch b/patch/u-boot/u-boot-sunxi-legacy/add-orangepi-zeroplus2_h3.patch new file mode 100644 index 0000000000..2e19639cd0 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/add-orangepi-zeroplus2_h3.patch @@ -0,0 +1,219 @@ +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 9cc5c1e0aa..a3ef6854c2 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -318,6 +318,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \ + sun8i-h3-orangepi-pc-plus.dtb \ + sun8i-h3-orangepi-plus.dtb \ + sun8i-h3-orangepi-plus2e.dtb \ ++ sun8i-h3-orangepi-zeroplus2.dtb \ + sun8i-h3-nanopi-m1.dtb \ + sun8i-h3-nanopi-m1-plus.dtb \ + sun8i-h3-nanopi-neo.dtb \ +diff --git a/arch/arm/dts/sun8i-h3-orangepi-zeroplus2.dts b/arch/arm/dts/sun8i-h3-orangepi-zeroplus2.dts +new file mode 100644 +index 0000000000..b03e3a51a2 +--- /dev/null ++++ b/arch/arm/dts/sun8i-h3-orangepi-zeroplus2.dts +@@ -0,0 +1,175 @@ ++/* ++ * Copyright (C) 2016 Icenowy Zheng ++ * ++ * Based on sun8i-h3-orangepi-one.dts, which is: ++ * Copyright (C) 2016 Hans de Goede ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++#include "sun8i-h3.dtsi" ++#include "sunxi-common-regulators.dtsi" ++ ++#include ++#include ++#include ++ ++/ { ++ model = "Xunlong Orange Pi Zero Plus 2"; ++ compatible = "xunlong,orangepi-zeroplus", "allwinner,sun8i-h3"; ++ ++ aliases { ++ serial0 = &uart0; ++ /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ ++ ethernet1 = &brcmf; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ pwr_led { ++ label = "orangepi:green:pwr"; ++ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ }; ++ ++ status_led { ++ label = "orangepi:red:status"; ++ gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ pinctrl-names = "default"; ++ reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; ++ post-power-on-delay-ms = <50>; ++ }; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&ehci2 { ++ status = "okay"; ++}; ++ ++&ehci3 { ++ status = "okay"; ++}; ++ ++&emac { ++ phy = <&phy1>; ++ phy-mode = "mii"; ++ allwinner,use-internal-phy; ++ allwinner,leds-active-low; ++ status = "okay"; ++ phy1: ethernet-phy@1 { ++ reg = <1>; ++ }; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins_a>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ ++ cd-inverted; ++ status = "okay"; ++}; ++ ++&mmc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins_a>; ++ vmmc-supply = <®_vcc3v3>; ++ vqmmc-supply = <®_vcc3v3>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ brcmf: bcrmf@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ interrupt-parent = <&r_pio>; ++ interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 / EINT7 */ ++ interrupt-names = "host-wake"; ++ }; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&ohci2 { ++ status = "okay"; ++}; ++ ++&ohci3 { ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++}; ++ ++&usbphy { ++ /* USB VBUS is always on */ ++ status = "okay"; ++}; ++ +diff --git a/configs/orangepi_zero_plus2_h3_defconfig b/configs/orangepi_zero_plus2_h3_defconfig +new file mode 100644 +index 0000000000..9257b7c1ed +--- /dev/null ++++ b/configs/orangepi_zero_plus2_h3_defconfig +@@ -0,0 +1,20 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SYS_TEXT_BASE=0x4a000000 ++CONFIG_MACH_SUN8I_H3=y ++CONFIG_DRAM_CLK=408 ++CONFIG_DRAM_ZQ=3881979 ++CONFIG_DRAM_ODT_EN=y ++CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-zeroplus2" ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SPL=y ++CONFIG_SPL_SPI_FLASH_SUPPORT=y ++CONFIG_SPL_SPI_SUNXI=y ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_FPGA is not set ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_SPL_ISO_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_USB_EHCI_HCD=y diff --git a/patch/u-boot/u-boot-sunxi-legacy/add-sunvell-r69.patch b/patch/u-boot/u-boot-sunxi-legacy/add-sunvell-r69.patch new file mode 100644 index 0000000000..b5c87f7a79 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/add-sunvell-r69.patch @@ -0,0 +1,212 @@ +diff --git a/configs/sunvell_r69_defconfig b/configs/sunvell_r69_defconfig +new file mode 100644 +index 0000000..f4947ab +--- /dev/null ++++ b/configs/sunvell_r69_defconfig +@@ -0,0 +1,22 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SYS_TEXT_BASE=0x4a000000 ++CONFIG_MACH_SUN8I_H3=y ++CONFIG_DRAM_CLK=408 ++CONFIG_DRAM_ZQ=3881979 ++CONFIG_DRAM_ODT_EN=y ++# CONFIG_VIDEO_DE2 is not set ++# CONFIG_VIDEO_COMPOSITE is not set ++CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-sunvell-r69" ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++# CONFIG_CONSOLE_MUX is not set ++CONFIG_SPL=y ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_FPGA is not set ++# CONFIG_SPL_SPI_SUNXI is not set ++CONFIG_SUN8I_EMAC=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_SYS_CLK_FREQ=480000000 ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++ +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 7202541..1af2005 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -320,6 +320,7 @@ dtb-$(CONFIG_MACH_SUN8I_A83T) += \ + dtb-$(CONFIG_MACH_SUN8I_H3) += \ + sun8i-h2-plus-orangepi-zero.dtb \ + sun8i-h2-plus-nanopi-duo.dtb \ ++ sun8i-h2-plus-sunvell-r69.dtb \ + sun8i-h3-bananapi-m2-plus.dtb \ + sun8i-h3-orangepi-2.dtb \ + sun8i-h3-orangepi-lite.dtb \ +diff --git a/arch/arm/dts/sun8i-h2-plus-sunvell-r69.dts b/arch/arm/dts/sun8i-h2-plus-sunvell-r69.dts +new file mode 100644 +index 0000000..4b41116 +--- /dev/null ++++ b/arch/arm/dts/sun8i-h2-plus-sunvell-r69.dts +@@ -0,0 +1,166 @@ ++/* ++ * Based original Sunvell R69 FEX file (2017 ) ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This file is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This file is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++#include "sun8i-h3.dtsi" ++#include "sunxi-common-regulators.dtsi" ++ ++#include ++#include ++#include ++ ++/ { ++ model = "Sunvell R69"; ++ compatible = "sunvell,sunvell-r69", "allwinner,sun8i-h2-plus"; ++ ++ aliases { ++ serial0 = &uart0; ++ /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ ++ ethernet1 = &xr819; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ pwr_led { ++ label = "sunvell-r69:blue:pwr"; ++ gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ }; ++ ++ status_led { ++ label = "sunvell-r69:red:status"; ++ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ reg_vcc_wifi: reg_vcc_wifi { ++ compatible = "regulator-fixed"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-wifi"; ++ enable-active-high; ++ gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&r_pio 0 0 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&emac { ++ phy = <&phy1>; ++ phy-mode = "mii"; ++ allwinner,use-internal-phy; ++ allwinner,leds-active-low; ++ status = "okay"; ++ phy1: ethernet-phy@1 { ++ reg = <1>; ++ }; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins_a>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ ++ cd-inverted; ++ status = "okay"; ++}; ++ ++&mmc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins_a>; ++ vmmc-supply = <®_vcc_wifi>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ /* ++ * Explicitly define the sdio device, so that we can add an ethernet ++ * alias for it (which e.g. makes u-boot set a mac-address). ++ */ ++ xr819: sdio_wifi@1 { ++ reg = <1>; ++ }; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&mmc2_8bit_pins { ++ /* Increase current from 30mA to 40mA for DDR eMMC */ ++ allwinner,drive = ; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++}; ++ ++&usbphy { ++ /* USB VBUS is always on */ ++ status = "okay"; ++}; diff --git a/patch/u-boot/u-boot-sunxi-legacy/add-tritium-series.patch b/patch/u-boot/u-boot-sunxi-legacy/add-tritium-series.patch new file mode 100644 index 0000000000..a6ddfc42eb --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/add-tritium-series.patch @@ -0,0 +1,497 @@ +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index f4b8088..a912dae 100755 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -351,6 +351,7 @@ dtb-$(CONFIG_MACH_SUN8I_A83T) += \ + sun8i-a83t-tbs-a711.dts + dtb-$(CONFIG_MACH_SUN8I_H3) += \ + sun8i-h2-plus-bananapi-m2-zero.dtb \ ++ sun8i-h2-plus-libretech-all-h3-cc.dtb \ + sun8i-h2-plus-orangepi-zero.dtb \ + sun8i-h2-plus-nanopi-duo.dtb \ + sun8i-h2-plus-sunvell-r69.dtb \ +@@ -360,6 +361,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \ + sun8i-h3-orangepi-lite.dtb \ + sun8i-h3-orangepi-one.dtb \ + sun8i-h3-beelink-x2.dtb \ ++ sun8i-h3-libretech-all-h3-cc.dtb \ + sun8i-h3-orangepi-pc.dtb \ + sun8i-h3-orangepi-pc-plus.dtb \ + sun8i-h3-orangepi-plus.dtb \ +@@ -374,6 +376,7 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \ + dtb-$(CONFIG_MACH_SUN8I_V3S) += \ + sun8i-v3s-licheepi-zero.dtb + dtb-$(CONFIG_MACH_SUN50I_H5) += \ ++ sun50i-h5-libretech-all-h3-cc.dtb \ + sun50i-h5-nanopi-neo-plus2.dtb \ + sun50i-h5-nanopi-neo-core2.dtb \ + sun50i-h5-nanopi-neo2.dtb \ +diff --git a/arch/arm/dts/sun50i-h5-libretech-all-h3-cc.dts b/arch/arm/dts/sun50i-h5-libretech-all-h3-cc.dts +new file mode 100644 +index 0000000..a35f77d +--- /dev/null ++++ b/arch/arm/dts/sun50i-h5-libretech-all-h3-cc.dts +@@ -0,0 +1,14 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (C) 2018 BayLibre, SAS ++ * Author: Neil Armstrong ++ */ ++ ++/dts-v1/; ++#include "sun50i-h5.dtsi" ++#include ++ ++/ { ++ model = "Libre Computer Board ALL-H3-CC H5"; ++ compatible = "libretech,all-h3-cc-h5", "allwinner,sun50i-h5"; ++}; +diff --git a/arch/arm/dts/sun8i-h2-plus-libretech-all-h3-cc.dts b/arch/arm/dts/sun8i-h2-plus-libretech-all-h3-cc.dts +new file mode 100644 +index 0000000..4db0d4b +--- /dev/null ++++ b/arch/arm/dts/sun8i-h2-plus-libretech-all-h3-cc.dts +@@ -0,0 +1,13 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (C) 2018 Chen-Yu Tsai ++ */ ++ ++/dts-v1/; ++#include "sun8i-h3.dtsi" ++#include "sunxi-libretech-all-h3-cc.dtsi" ++ ++/ { ++ model = "Libre Computer Board ALL-H3-CC H2+"; ++ compatible = "libretech,all-h3-cc-h2-plus", "allwinner,sun8i-h2-plus"; ++}; +diff --git a/arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts b/arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts +index 1fcb16c..a8b2f0f 100644 +--- a/arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts ++++ b/arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts +@@ -1,174 +1,14 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + /* + * Copyright (C) 2017 Chen-Yu Tsai ++ * ++ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + + /dts-v1/; + #include "sun8i-h3.dtsi" +- +-#include +-#include ++#include "sunxi-libretech-all-h3-cc.dtsi" + + / { + model = "Libre Computer Board ALL-H3-CC H3"; + compatible = "libretech,all-h3-cc-h3", "allwinner,sun8i-h3"; +- +- aliases { +- ethernet0 = &emac; +- serial0 = &uart0; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +- +- leds { +- compatible = "gpio-leds"; +- +- pwr_led { +- label = "librecomputer:green:pwr"; +- gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ +- default-state = "on"; +- }; +- +- status_led { +- label = "librecomputer:blue:status"; +- gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */ +- }; +- }; +- +- gpio_keys { +- compatible = "gpio-keys"; +- +- power { +- label = "power"; +- linux,code = ; +- gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ +- }; +- }; +- +- reg_vcc1v2: vcc1v2 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc1v2"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <®_vcc5v0>; +- gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ +- enable-active-high; +- }; +- +- reg_vcc3v3: vcc3v3 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc3v3"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- vin-supply = <®_vcc5v0>; +- }; +- +- /* This represents the board's 5V input */ +- reg_vcc5v0: vcc5v0 { +- compatible = "regulator-fixed"; +- regulator-name = "vcc5v0"; +- regulator-min-microvolt = <5000000>; +- regulator-max-microvolt = <5000000>; +- }; +- +- reg_vcc_dram: vcc-dram { +- compatible = "regulator-fixed"; +- regulator-name = "vcc-dram"; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <1500000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <®_vcc5v0>; +- gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ +- enable-active-high; +- }; +- +- reg_vcc_io: vcc-io { +- compatible = "regulator-fixed"; +- regulator-name = "vcc-io"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <®_vcc3v3>; +- gpio = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */ +- }; +- +- reg_vdd_cpux: vdd-cpux { +- compatible = "regulator-fixed"; +- regulator-name = "vdd-cpux"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- regulator-always-on; +- regulator-boot-on; +- vin-supply = <®_vcc5v0>; +- gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ +- enable-active-high; +- }; +-}; +- +-&ehci1 { +- status = "okay"; +-}; +- +-&ehci2 { +- status = "okay"; +-}; +- +-&ehci3 { +- status = "okay"; +-}; +- +-&emac { +- phy-handle = <&int_mii_phy>; +- phy-mode = "mii"; +- allwinner,leds-active-low; +- status = "okay"; +-}; +- +-&ir { +- pinctrl-names = "default"; +- pinctrl-0 = <&ir_pins_a>; +- status = "okay"; +-}; +- +-&mmc0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&mmc0_pins_a>; +- vmmc-supply = <®_vcc_io>; +- bus-width = <4>; +- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ +- cd-inverted; +- status = "okay"; +-}; +- +-&ohci1 { +- status = "okay"; +-}; +- +-&ohci2 { +- status = "okay"; +-}; +- +-&ohci3 { +- status = "okay"; +-}; +- +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins_a>; +- status = "okay"; +-}; +- +-&usbphy { +- /* VBUS on USB ports are always on */ +- usb0_vbus-supply = <®_vcc5v0>; +- usb1_vbus-supply = <®_vcc5v0>; +- usb2_vbus-supply = <®_vcc5v0>; +- usb3_vbus-supply = <®_vcc5v0>; +- status = "okay"; + }; +diff --git a/arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi b/arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi +new file mode 100644 +index 0000000..14c8ec1 +--- /dev/null ++++ b/arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi +@@ -0,0 +1,175 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (C) 2017 Chen-Yu Tsai ++ */ ++ ++#include ++#include ++ ++/ { ++ aliases { ++ ethernet0 = &emac; ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ pwr_led { ++ label = "librecomputer:green:pwr"; ++ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ ++ default-state = "on"; ++ }; ++ ++ status_led { ++ label = "librecomputer:blue:status"; ++ gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */ ++ }; ++ }; ++ ++ gpio_keys { ++ compatible = "gpio-keys"; ++ ++ power { ++ label = "power"; ++ linux,code = ; ++ gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ ++ }; ++ }; ++ ++ reg_vcc1v2: vcc1v2 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc1v2"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <®_vcc5v0>; ++ gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ ++ enable-active-high; ++ }; ++ ++ reg_vcc3v3: vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <®_vcc5v0>; ++ }; ++ ++ /* This represents the board's 5V input */ ++ reg_vcc5v0: vcc5v0 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ reg_vcc_dram: vcc-dram { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-dram"; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <®_vcc5v0>; ++ gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ ++ enable-active-high; ++ }; ++ ++ reg_vcc_io: vcc-io { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-io"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <®_vcc3v3>; ++ gpio = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */ ++ }; ++ ++ reg_vdd_cpux: vdd-cpux { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd-cpux"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <®_vcc5v0>; ++ gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ ++ enable-active-high; ++ }; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&ehci2 { ++ status = "okay"; ++}; ++ ++&ehci3 { ++ status = "okay"; ++}; ++ ++&emac { ++ phy-handle = <&int_mii_phy>; ++ phy-mode = "mii"; ++ allwinner,leds-active-low; ++ status = "okay"; ++}; ++ ++&ir { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ir_pins_a>; ++ status = "okay"; ++}; ++ ++&mmc0 { ++ vmmc-supply = <®_vcc_io>; ++ bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ ++ cd-inverted; ++ status = "okay"; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_vcc_io>; ++ bus-width = <8>; ++ non-removable; ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&ohci2 { ++ status = "okay"; ++}; ++ ++&ohci3 { ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++}; ++ ++&usbphy { ++ /* VBUS on USB ports are always on */ ++ usb0_vbus-supply = <®_vcc5v0>; ++ usb1_vbus-supply = <®_vcc5v0>; ++ usb2_vbus-supply = <®_vcc5v0>; ++ usb3_vbus-supply = <®_vcc5v0>; ++ status = "okay"; ++}; +diff --git a/configs/libretech_all_h3_cc_h2_plus_defconfig b/configs/libretech_all_h3_cc_h2_plus_defconfig +new file mode 100644 +index 0000000..2c7a3ff +--- /dev/null ++++ b/configs/libretech_all_h3_cc_h2_plus_defconfig +@@ -0,0 +1,17 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SPL=y ++CONFIG_MACH_SUN8I_H3=y ++CONFIG_DRAM_CLK=672 ++CONFIG_DRAM_ZQ=3881979 ++CONFIG_DRAM_ODT_EN=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++CONFIG_NR_DRAM_BANKS=1 ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-libretech-all-h3-cc" ++CONFIG_SUN8I_EMAC=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +diff --git a/configs/libretech_all_h3_cc_h3_defconfig b/configs/libretech_all_h3_cc_h3_defconfig +index 6072680..bd2c708 100644 +--- a/configs/libretech_all_h3_cc_h3_defconfig ++++ b/configs/libretech_all_h3_cc_h3_defconfig +@@ -5,13 +5,13 @@ CONFIG_MACH_SUN8I_H3=y + CONFIG_DRAM_CLK=672 + CONFIG_DRAM_ZQ=3881979 + CONFIG_DRAM_ODT_EN=y +-CONFIG_R_I2C_ENABLE=y +-CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-libretech-all-h3-cc" ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++CONFIG_NR_DRAM_BANKS=1 + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +-CONFIG_SPL_I2C_SUPPORT=y + # CONFIG_CMD_FLASH is not set + # CONFIG_SPL_DOS_PARTITION is not set + # CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-libretech-all-h3-cc" + CONFIG_SUN8I_EMAC=y + CONFIG_USB_EHCI_HCD=y + CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +diff --git a/configs/libretech_all_h3_cc_h5_defconfig b/configs/libretech_all_h3_cc_h5_defconfig +new file mode 100644 +index 0000000..001f53d +--- /dev/null ++++ b/configs/libretech_all_h3_cc_h5_defconfig +@@ -0,0 +1,17 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SPL=y ++CONFIG_MACH_SUN50I_H5=y ++CONFIG_DRAM_CLK=672 ++CONFIG_DRAM_ZQ=3881979 ++CONFIG_DRAM_ODT_EN=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++CONFIG_NR_DRAM_BANKS=1 ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-libretech-all-h3-cc" ++CONFIG_SUN8I_EMAC=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/patch/u-boot/u-boot-sunxi-legacy/add-xx-boot-auto-dt-select-neo2.patch b/patch/u-boot/u-boot-sunxi-legacy/add-xx-boot-auto-dt-select-neo2.patch new file mode 100644 index 0000000000..85a98b445b --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/add-xx-boot-auto-dt-select-neo2.patch @@ -0,0 +1,119 @@ +diff --git a/board/sunxi/board.c b/board/sunxi/board.c +index 818d2a0..a3ee6ed 100644 +--- a/board/sunxi/board.c ++++ b/board/sunxi/board.c +@@ -725,6 +725,74 @@ static void setup_environment(const void *fdt) + } + } + ++#if defined(CONFIG_BOOT_PROCESS_MULTI_DTB) && !defined(CONFIG_SPL_BUILD) ++ ++#define NP_NEO2_DT_SS "nanopi-neo2." ++ ++#define NP_NEO2_DT_EXT_V1_1 "-v1.1.dtb" ++ ++#define NP_NEO2_BOARD_ID_GPIO "PL3" ++#define NP_NEO2_BOARD_ID_1_0 1 ++#define NP_NEO2_BOARD_ID_1_1 0 ++ ++void boot_process_multi_dtb(void) ++{ ++ const char *fdtfile = env_get("fdtfile"); ++ if (fdtfile == NULL) { ++ return; ++ } ++ ++ /* check for a NanoPi NEO2 */ ++ if (strstr(fdtfile, NP_NEO2_DT_SS) != NULL) { ++ int board_id_pin, prev_cfg, ret, rev_1_1; ++ ++ /* NEO2 DT found; process board revision and select corresponding DT */ ++ ++ board_id_pin = sunxi_name_to_gpio(NP_NEO2_BOARD_ID_GPIO); ++ if (board_id_pin < 0) { ++ return; ++ } ++ ++ ret = gpio_request(board_id_pin, "board_id_pin"); ++ if (ret) { ++ return; ++ } ++ ++ prev_cfg = sunxi_gpio_get_cfgpin(board_id_pin); ++ ++ gpio_direction_input(board_id_pin); ++ sunxi_gpio_set_pull(board_id_pin, SUNXI_GPIO_PULL_DISABLE); ++ ++ mdelay(2); ++ ++ rev_1_1 = gpio_get_value(board_id_pin) == NP_NEO2_BOARD_ID_1_1; ++ ++ sunxi_gpio_set_cfgpin(board_id_pin, prev_cfg); ++ gpio_free(board_id_pin); ++ ++ printf("NanoPi NEO2 v1.%d detected\n", rev_1_1); ++ ++ if (rev_1_1) { ++ int ddt_len = sizeof(CONFIG_DEFAULT_DEVICE_TREE); ++ int fdt_len = strlen(fdtfile); ++ ++ char *n_fdtfile = (char *)malloc(max(fdt_len, ddt_len) + sizeof(NP_NEO2_DT_EXT_V1_1) + 1); ++ if (n_fdtfile != NULL) { ++ char *cp = strstr(strcpy(n_fdtfile, fdtfile), CONFIG_DEFAULT_DEVICE_TREE); ++ if (cp != NULL) { ++ cp[ddt_len - 1] = '\0'; ++ strcat(cp, NP_NEO2_DT_EXT_V1_1); ++ ++ env_set("fdtfile", n_fdtfile); ++ } ++ ++ free(n_fdtfile); ++ } ++ } ++ } ++} ++#endif ++ + int misc_init_r(void) + { + __maybe_unused int ret; +@@ -758,6 +826,10 @@ int misc_init_r(void) + usb_ether_init(); + #endif + ++#if defined(CONFIG_BOOT_PROCESS_MULTI_DTB) && !defined(CONFIG_SPL_BUILD) ++ boot_process_multi_dtb(); ++#endif ++ + return 0; + } + +diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig +index 78d587f..ca8a842 100755 +--- a/configs/nanopi_neo2_defconfig ++++ b/configs/nanopi_neo2_defconfig +@@ -12,4 +12,5 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo2" + CONFIG_SUN8I_EMAC=y + CONFIG_USB_EHCI_HCD=y + CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +-CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +\ No newline at end of file ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++CONFIG_BOOT_PROCESS_MULTI_DTB=y +diff --git a/dts/Kconfig b/dts/Kconfig +index 0cef225..cd4d101 100644 +--- a/dts/Kconfig ++++ b/dts/Kconfig +@@ -166,6 +166,12 @@ config SPL_OF_LIST + device tree files (without the directory or .dtb suffix) + separated by . + ++if ARCH_SUNXI ++config BOOT_PROCESS_MULTI_DTB ++ bool "Adjust default board DT as necessary at boot" ++ default n ++endif ++ + choice + prompt "SPL OF LIST compression" + depends on SPL_MULTI_DTB_FIT diff --git a/patch/u-boot/u-boot-sunxi-legacy/add-xx-nanopi-k1-plus-emmc.patch b/patch/u-boot/u-boot-sunxi-legacy/add-xx-nanopi-k1-plus-emmc.patch new file mode 100644 index 0000000000..5c5414eb0b --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/add-xx-nanopi-k1-plus-emmc.patch @@ -0,0 +1,143 @@ +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index b6eebe8..a6eb75b 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -371,6 +371,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \ + sun50i-h5-orangepi-zero-plus.dtb \ + sun50i-h5-nanopi-m1-plus2.dts \ + sun50i-h5-orangepi-pc2.dtb \ ++ sun50i-h5-nanopi-k1-plus.dtb \ + sun50i-h5-orangepi-prime.dtb \ + sun50i-h5-orangepi-zero-plus2.dtb + dtb-$(CONFIG_MACH_SUN50I) += \ +diff --git a/arch/arm/dts/sun50i-h5-nanopi-k1-plus.dts b/arch/arm/dts/sun50i-h5-nanopi-k1-plus.dts +new file mode 100644 +index 0000000..c08af78 +--- /dev/null ++++ b/arch/arm/dts/sun50i-h5-nanopi-k1-plus.dts +@@ -0,0 +1,96 @@ ++/* ++ * Copyright (C) 2017 Icenowy Zheng ++ * Copyright (C) 2017 Jagan Teki ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-h5.dtsi" ++ ++#include ++ ++/ { ++ model = "FriendlyARM NanoPi K1 plus"; ++ compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ reg_vcc3v3: vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++}; ++ ++&mmc0 { ++ compatible = "allwinner,sun50i-h5-mmc", ++ "allwinner,sun50i-a64-mmc", ++ "allwinner,sun5i-a13-mmc"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ ++ status = "okay"; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++}; +diff --git a/configs/nanopi_k1_plus_defconfig b/configs/nanopi_k1_plus_defconfig +new file mode 100644 +index 0000000..670c3c7 +--- /dev/null ++++ b/configs/nanopi_k1_plus_defconfig +@@ -0,0 +1,23 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SYS_TEXT_BASE=0x4a000000 ++CONFIG_SPL_SPI_FLASH_SUPPORT=y ++CONFIG_MACH_SUN50I_H5=y ++CONFIG_DRAM_CLK=504 ++CONFIG_DRAM_ZQ=3881977 ++CONFIG_MACPWR="PD6" ++CONFIG_DRAM_ODT_EN=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-k1-plus" ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SPL=y ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_FPGA is not set ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_SPL_ISO_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_SPL_SPI_SUNXI=y ++CONFIG_SUN8I_EMAC=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/patch/u-boot/u-boot-sunxi-legacy/add-xx-nanopineocore2.patch b/patch/u-boot/u-boot-sunxi-legacy/add-xx-nanopineocore2.patch new file mode 100644 index 0000000000..3f7875f3f0 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/add-xx-nanopineocore2.patch @@ -0,0 +1,156 @@ +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 6b064ad..2ef6fae 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -378,6 +378,7 @@ dtb-$(CONFIG_MACH_SUN8I_V3S) += \ + sun8i-v3s-licheepi-zero.dtb + dtb-$(CONFIG_MACH_SUN50I_H5) += \ + sun50i-h5-nanopi-neo-plus2.dtb \ ++ sun50i-h5-nanopi-neo-core2.dtb \ + sun50i-h5-nanopi-neo2.dtb \ + sun50i-h5-nanopi-neo-plus2.dtb \ + sun50i-h5-orangepi-zero-plus.dtb \ +diff --git a/arch/arm/dts/sun50i-h5-nanopi-neo-core2.dts b/arch/arm/dts/sun50i-h5-nanopi-neo-core2.dts +new file mode 100644 +index 0000000..dd25549 +--- /dev/null ++++ b/arch/arm/dts/sun50i-h5-nanopi-neo-core2.dts +@@ -0,0 +1,113 @@ ++/* ++ * Copyright (C) 2017 Antony Antony ++ * Copyright (c) 2016 ARM Ltd. ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-h5.dtsi" ++ ++#include ++ ++/ { ++ model = "FriendlyARM NanoPi NEO Core 2"; ++ compatible = "friendlyarm,nanopi-neo-core2", "allwinner,sun50i-h5"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory { ++ reg = <0x40000000 0x40000000>; ++ }; ++ ++ reg_vcc3v3: vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&mmc0 { ++ compatible = "allwinner,sun50i-h5-mmc", ++ "allwinner,sun50i-a64-mmc", ++ "allwinner,sun5i-a13-mmc"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; ++ cd-inverted; ++ status = "okay"; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++}; ++ ++&usbphy { ++ status = "okay"; ++}; +diff --git a/configs/nanopi_neo_core2_defconfig b/configs/nanopi_neo_core2_defconfig +new file mode 100644 +index 0000000..4624ec3 +--- /dev/null ++++ b/configs/nanopi_neo_core2_defconfig +@@ -0,0 +1,19 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_MACH_SUN50I_H5=y ++CONFIG_DRAM_CLK=624 ++CONFIG_DRAM_ZQ=3881977 ++CONFIG_MACPWR="PD6" ++CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo-core2" ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SPL=y ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_FPGA is not set ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_SPL_ISO_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_SUN8I_EMAC=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++CONFIG_SD_BOOT=y diff --git a/patch/u-boot/u-boot-sunxi-legacy/add_emmc_olinuxino_a64.patch b/patch/u-boot/u-boot-sunxi-legacy/add_emmc_olinuxino_a64.patch new file mode 100644 index 0000000000..48c3318c7c --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/add_emmc_olinuxino_a64.patch @@ -0,0 +1,45 @@ +--- a/arch/arm/dts/sun50i-a64-olinuxino.dts ++++ b/arch/arm/dts/sun50i-a64-olinuxino.dts +@@ -66,6 +66,16 @@ + }; + }; + ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ status = "okay"; ++}; ++ ++&i2c1_pins { ++ bias-pull-up; ++}; ++ + &mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; +@@ -77,6 +87,25 @@ + status = "okay"; + }; + ++&mmc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; diff --git a/patch/u-boot/u-boot-sunxi-legacy/add_emmc_orangepiwin.patch b/patch/u-boot/u-boot-sunxi-legacy/add_emmc_orangepiwin.patch new file mode 100644 index 0000000000..407ba28bc7 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/add_emmc_orangepiwin.patch @@ -0,0 +1,87 @@ +diff --git a/arch/arm/dts/sun50i-a64-orangepi-win.dts b/arch/arm/dts/sun50i-a64-orangepi-win.dts +old mode 100644 +new mode 100755 +index 2c39d10..819fd97 +--- a/arch/arm/dts/sun50i-a64-orangepi-win.dts ++++ b/arch/arm/dts/sun50i-a64-orangepi-win.dts +@@ -52,6 +52,7 @@ + + aliases { + serial0 = &uart0; ++ serial1 = &uart1; + }; + + chosen { +@@ -83,12 +84,44 @@ + status = "okay"; + }; + ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ status = "okay"; ++}; ++ ++ ++&i2c1_pins { ++ bias-pull-up; ++}; ++ + &mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_vcc3v3>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; + cd-inverted; ++ disable-wp; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&mmc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; + status = "okay"; + }; + +@@ -109,6 +142,12 @@ + status = "okay"; + }; + ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; ++ status = "okay"; ++}; ++ + &usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig +old mode 100644 +new mode 100755 +index 7039d68..29006a8 +--- a/configs/orangepi_win_defconfig ++++ b/configs/orangepi_win_defconfig +@@ -3,6 +3,8 @@ CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN50I=y + CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y + CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-orangepi-win" ++CONFIG_MMC0_CD_PIN="PH13" ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL=y + # CONFIG_CMD_FLASH is not set diff --git a/patch/u-boot/u-boot-sunxi-legacy/adjust-default-dram-clockspeeds.patch b/patch/u-boot/u-boot-sunxi-legacy/adjust-default-dram-clockspeeds.patch new file mode 100644 index 0000000000..2ba790e4eb --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/adjust-default-dram-clockspeeds.patch @@ -0,0 +1,272 @@ +diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig +index fe75eef513..74bcfc64af 100644 +--- a/configs/Bananapi_defconfig ++++ b/configs/Bananapi_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN7I=y +-CONFIG_DRAM_CLK=432 ++CONFIG_DRAM_CLK=384 + CONFIG_MACPWR="PH23" + CONFIG_VIDEO_COMPOSITE=y + CONFIG_GMAC_TX_DELAY=3 +diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig +index df65922e83..80a45fde6f 100644 +--- a/configs/Bananapro_defconfig ++++ b/configs/Bananapro_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN7I=y +-CONFIG_DRAM_CLK=432 ++CONFIG_DRAM_CLK=384 + CONFIG_MACPWR="PH23" + CONFIG_USB1_VBUS_PIN="PH0" + CONFIG_USB2_VBUS_PIN="PH1" +diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig +index 02c503f672..cf9c16351d 100644 +--- a/configs/Cubieboard2_defconfig ++++ b/configs/Cubieboard2_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN7I=y +-CONFIG_DRAM_CLK=480 ++CONFIG_DRAM_CLK=432 + CONFIG_MMC0_CD_PIN="PH1" + CONFIG_SATAPWR="PB8" + CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2" +diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig +index a8e9c988d5..9d892d6343 100644 +--- a/configs/Cubieboard_defconfig ++++ b/configs/Cubieboard_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN4I=y +-CONFIG_DRAM_CLK=480 ++CONFIG_DRAM_CLK=432 + CONFIG_MMC0_CD_PIN="PH1" + CONFIG_SATAPWR="PB8" + CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cubieboard" +diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig +index f9d56c8f9d..5d42b59e57 100644 +--- a/configs/Cubietruck_defconfig ++++ b/configs/Cubietruck_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN7I=y +-CONFIG_DRAM_CLK=432 ++CONFIG_DRAM_CLK=384 + CONFIG_MMC0_CD_PIN="PH1" + CONFIG_USB0_VBUS_PIN="PH17" + CONFIG_USB0_VBUS_DET="PH22" +diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig +index cc29d606a9..dbbdfcc529 100644 +--- a/configs/Lamobo_R1_defconfig ++++ b/configs/Lamobo_R1_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN7I=y +-CONFIG_DRAM_CLK=432 ++CONFIG_DRAM_CLK=384 + CONFIG_MACPWR="PH23" + CONFIG_MMC0_CD_PIN="PH10" + CONFIG_SATAPWR="PB3" +diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig +index b9f89a013e..6a42c4b500 100644 +--- a/configs/Linksprite_pcDuino3_defconfig ++++ b/configs/Linksprite_pcDuino3_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN7I=y +-CONFIG_DRAM_CLK=480 ++CONFIG_DRAM_CLK=408 + CONFIG_DRAM_ZQ=122 + CONFIG_SATAPWR="PH2" + CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3" +diff --git a/configs/nanopi_m1_plus_defconfig b/configs/nanopi_m1_plus_defconfig +index abe93f6..1fc2e53 100644 +--- a/configs/nanopi_m1_plus_defconfig ++++ b/configs/nanopi_m1_plus_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN8I_H3=y +-CONFIG_DRAM_CLK=408 ++CONFIG_DRAM_CLK=576 + CONFIG_DRAM_ZQ=3881979 + CONFIG_DRAM_ODT_EN=y + CONFIG_MMC0_CD_PIN="PH13" +diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig +index c7db07a..38b6646 100644 +--- a/configs/nanopi_neo2_defconfig ++++ b/configs/nanopi_neo2_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN50I_H5=y +-CONFIG_DRAM_CLK=672 ++CONFIG_DRAM_CLK=624 + CONFIG_DRAM_ZQ=3881977 + CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo2" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +diff --git a/configs/nanopi_neo_plus2_defconfig b/configs/nanopi_neo_plus2_defconfig +index f6b4ca7..34437fc 100644 +--- a/configs/nanopi_neo_plus2_defconfig ++++ b/configs/nanopi_neo_plus2_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN50I_H5=y +-CONFIG_DRAM_CLK=408 ++CONFIG_DRAM_CLK=624 + CONFIG_DRAM_ZQ=3881977 + CONFIG_MACPWR="PD6" + CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo-plus2" +diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig +index b8c1ea4d7c..b4b20372aa 100644 +--- a/configs/Orangepi_defconfig ++++ b/configs/Orangepi_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN7I=y +-CONFIG_DRAM_CLK=432 ++CONFIG_DRAM_CLK=384 + CONFIG_MACPWR="PH23" + CONFIG_USB1_VBUS_PIN="PH26" + CONFIG_USB2_VBUS_PIN="PH22" +diff --git a/configs/orangepi_lite_defconfig b/configs/orangepi_lite_defconfig +index a72d506..2c49525 100644 +--- a/configs/orangepi_lite_defconfig ++++ b/configs/orangepi_lite_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN8I_H3=y +-CONFIG_DRAM_CLK=672 ++CONFIG_DRAM_CLK=624 + CONFIG_DRAM_ZQ=3881979 + CONFIG_DRAM_ODT_EN=y + CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-lite" +diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig +index 19c35ef103..80404ab377 100644 +--- a/configs/Orangepi_mini_defconfig ++++ b/configs/Orangepi_mini_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN7I=y +-CONFIG_DRAM_CLK=432 ++CONFIG_DRAM_CLK=384 + CONFIG_MACPWR="PH23" + CONFIG_MMC0_CD_PIN="PH10" + CONFIG_MMC3_CD_PIN="PH11" +diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig +index 5a7aba1..3ba4009 100644 +--- a/configs/orangepi_one_defconfig ++++ b/configs/orangepi_one_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN8I_H3=y +-CONFIG_DRAM_CLK=672 ++CONFIG_DRAM_CLK=624 + CONFIG_DRAM_ZQ=3881979 + CONFIG_DRAM_ODT_EN=y + CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one" +diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig +index 61b2d98705..e4771dce7d 100644 +--- a/configs/orangepi_pc2_defconfig ++++ b/configs/orangepi_pc2_defconfig +@@ -2,7 +2,7 @@ CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_MACH_SUN50I_H5=y +-CONFIG_DRAM_CLK=672 ++CONFIG_DRAM_CLK=624 + CONFIG_DRAM_ZQ=3881977 + CONFIG_MACPWR="PD6" + CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-pc2" +diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig +index 2374f1d..579bc70 100644 +--- a/configs/orangepi_plus2e_defconfig ++++ b/configs/orangepi_plus2e_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN8I_H3=y +-CONFIG_DRAM_CLK=672 ++CONFIG_DRAM_CLK=624 + CONFIG_DRAM_ZQ=3881979 + CONFIG_DRAM_ODT_EN=y + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig +index f2ed941..e8219bb 100644 +--- a/configs/orangepi_plus_defconfig ++++ b/configs/orangepi_plus_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN8I_H3=y +-CONFIG_DRAM_CLK=672 ++CONFIG_DRAM_CLK=624 + CONFIG_DRAM_ZQ=3881979 + CONFIG_DRAM_ODT_EN=y + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +diff --git a/configs/orangepi_prime_defconfig b/configs/orangepi_prime_defconfig +index 103936d772..990cf2a8c0 100644 +--- a/configs/orangepi_prime_defconfig ++++ b/configs/orangepi_prime_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN50I_H5=y +-CONFIG_DRAM_CLK=672 ++CONFIG_DRAM_CLK=624 + CONFIG_DRAM_ZQ=3881977 + CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-prime" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig +index ac44937..0e761b6 100644 +--- a/configs/orangepi_zero_defconfig ++++ b/configs/orangepi_zero_defconfig +@@ -2,7 +2,7 @@ CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_MACH_SUN8I_H3=y +-CONFIG_DRAM_CLK=624 ++CONFIG_DRAM_CLK=408 + CONFIG_DRAM_ZQ=3881979 + CONFIG_DRAM_ODT_EN=y + # CONFIG_VIDEO_DE2 is not set +diff --git a/configs/orangepi_zero_plus2_defconfig b/configs/orangepi_zero_plus2_defconfig +index 57c63b962a..ec9e5c73b1 100644 +--- a/configs/orangepi_zero_plus2_defconfig ++++ b/configs/orangepi_zero_plus2_defconfig +@@ -1,7 +1,7 @@ + CONFIG_ARM=y + CONFIG_ARCH_SUNXI=y + CONFIG_MACH_SUN50I_H5=y +-CONFIG_DRAM_CLK=672 ++CONFIG_DRAM_CLK=624 + CONFIG_DRAM_ZQ=3881977 + CONFIG_MMC0_CD_PIN="PH13" + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +diff --git a/configs/a64-olinuxino_defconfig b/configs/a64-olinuxino_defconfig +index 48e174a..7d74791 100644 +--- a/configs/a64-olinuxino_defconfig ++++ b/configs/a64-olinuxino_defconfig +@@ -7,5 +7,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 + CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-olinuxino" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_DRAM_CLK=624 ++CONFIG_DRAM_ZQ=3881949 + # CONFIG_CMD_FLASH is not set + # CONFIG_SPL_DOS_PARTITION is not set + # CONFIG_SPL_EFI_PARTITION is not set diff --git a/patch/u-boot/u-boot-sunxi-legacy/adjust-small-boards-cpufreq.patch b/patch/u-boot/u-boot-sunxi-legacy/adjust-small-boards-cpufreq.patch new file mode 100644 index 0000000000..dffd0ba81d --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/adjust-small-boards-cpufreq.patch @@ -0,0 +1,33 @@ +diff --git a/configs/nanopi_neo_defconfig b/configs/nanopi_neo_defconfig +index ed30708f90..f87148c7e6 100644 +--- a/configs/nanopi_neo_defconfig ++++ b/configs/nanopi_neo_defconfig +@@ -9,5 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_CONSOLE_MUX=y ++CONFIG_SYS_CLK_FREQ=480000000 + # CONFIG_CMD_FLASH is not set + # CONFIG_SPL_DOS_PARTITION is not set + # CONFIG_SPL_EFI_PARTITION is not set +diff --git a/configs/nanopi_neo_air_defconfig b/configs/nanopi_neo_air_defconfig +index 11eb3ab13b..d8f3f75192 100644 +--- a/configs/nanopi_neo_air_defconfig ++++ b/configs/nanopi_neo_air_defconfig +@@ -9,5 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-neo-air" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_CONSOLE_MUX=y ++CONFIG_SYS_CLK_FREQ=480000000 + # CONFIG_CMD_FLASH is not set + # CONFIG_SPL_DOS_PARTITION is not set + # CONFIG_SPL_EFI_PARTITION is not set +diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig +index 5792e7a4a3..46805991d2 100644 +--- a/configs/orangepi_zero_defconfig ++++ b/configs/orangepi_zero_defconfig +@@ -9,5 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-zero" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_CONSOLE_MUX=y ++CONFIG_SYS_CLK_FREQ=480000000 + # CONFIG_CMD_FLASH is not set + # CONFIG_SPL_DOS_PARTITION is not set + # CONFIG_SPL_EFI_PARTITION is not set diff --git a/patch/u-boot/u-boot-sunxi-legacy/board_lime2/GMAC_TX_DELAY_autocorrection.patch b/patch/u-boot/u-boot-sunxi-legacy/board_lime2/GMAC_TX_DELAY_autocorrection.patch new file mode 100644 index 0000000000..ee31c3d7b6 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/board_lime2/GMAC_TX_DELAY_autocorrection.patch @@ -0,0 +1,75 @@ +diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig +index cd1fa64..f817b8c 100644 +--- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig ++++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig +@@ -7,6 +7,8 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 + CONFIG_USB0_VBUS_PIN="PC17" + CONFIG_USB0_VBUS_DET="PH5" + CONFIG_I2C1_ENABLE=y ++CONFIG_PHY_MICREL=y ++CONFIG_PHY_MICREL_KSZ90X1=y + CONFIG_SATAPWR="PC3" + CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2-emmc" + CONFIG_AHCI=y +diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c +index b350a61..701a3d1 100644 +--- a/drivers/net/phy/micrel_ksz90x1.c ++++ b/drivers/net/phy/micrel_ksz90x1.c +@@ -16,6 +16,8 @@ + #include + #include + #include ++#include ++#include + + DECLARE_GLOBAL_DATA_PTR; + +@@ -334,6 +336,10 @@ static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr, + static int ksz9031_config(struct phy_device *phydev) + { + int ret; ++ struct sunxi_ccm_reg *const ccm = ++ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; ++ ++ setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_DELAY(4)); + + ret = ksz9031_of_config(phydev); + if (ret) +diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c +index 6d917f8..87956c0 100644 +--- a/drivers/net/phy/realtek.c ++++ b/drivers/net/phy/realtek.c +@@ -11,6 +11,8 @@ + #include + #include + #include ++#include ++#include + + #define PHY_RTL8211x_FORCE_MASTER BIT(1) + +@@ -63,6 +65,9 @@ static int rtl8211b_probe(struct phy_device *phydev) + /* RealTek RTL8211x */ + static int rtl8211x_config(struct phy_device *phydev) + { ++ struct sunxi_ccm_reg *const ccm = ++ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; ++ + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); + + /* mask interrupt at init; if the interrupt is +@@ -71,6 +76,14 @@ static int rtl8211x_config(struct phy_device *phydev) + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER, + MIIM_RTL8211x_PHY_INTR_DIS); + ++ if(phydev->drv->uid == 0x1cc912) { ++ /* With RTL8211C Force Master must be enabled */ ++ phydev->flags |= PHY_RTL8211x_FORCE_MASTER; ++ } else if(phydev->drv->uid == 0x1cc915) { ++ /* RTL8211E has different GMAC_TX_DELAY requirements */ ++ setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_DELAY(2)); ++ } ++ + if (phydev->flags & PHY_RTL8211x_FORCE_MASTER) { + unsigned int reg; + diff --git a/patch/u-boot/u-boot-sunxi-legacy/board_olimex-som-a20/GMAC_TX_DELAY_autocorrection.patch b/patch/u-boot/u-boot-sunxi-legacy/board_olimex-som-a20/GMAC_TX_DELAY_autocorrection.patch new file mode 100644 index 0000000000..173a9bbc69 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/board_olimex-som-a20/GMAC_TX_DELAY_autocorrection.patch @@ -0,0 +1,72 @@ +diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig +index ee94155..0ff93b8 100644 +--- a/configs/A20-Olimex-SOM-EVB_defconfig ++++ b/configs/A20-Olimex-SOM-EVB_defconfig +@@ -27,3 +27,5 @@ CONFIG_AXP_ALDO4_VOLT=2800 + CONFIG_SCSI=y + CONFIG_USB_EHCI_HCD=y + CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++CONFIG_PHY_MICREL=y ++CONFIG_PHY_MICREL_KSZ90X1=y +diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c +index b350a61..701a3d1 100644 +--- a/drivers/net/phy/micrel_ksz90x1.c ++++ b/drivers/net/phy/micrel_ksz90x1.c +@@ -16,6 +16,8 @@ + #include + #include + #include ++#include ++#include + + DECLARE_GLOBAL_DATA_PTR; + +@@ -334,6 +336,10 @@ static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr, + static int ksz9031_config(struct phy_device *phydev) + { + int ret; ++ struct sunxi_ccm_reg *const ccm = ++ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; ++ ++ setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_DELAY(4)); + + ret = ksz9031_of_config(phydev); + if (ret) +diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c +index 6d917f8..87956c0 100644 +--- a/drivers/net/phy/realtek.c ++++ b/drivers/net/phy/realtek.c +@@ -11,6 +11,8 @@ + #include + #include + #include ++#include ++#include + + #define PHY_RTL8211x_FORCE_MASTER BIT(1) + +@@ -63,6 +65,9 @@ static int rtl8211b_probe(struct phy_device *phydev) + /* RealTek RTL8211x */ + static int rtl8211x_config(struct phy_device *phydev) + { ++ struct sunxi_ccm_reg *const ccm = ++ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; ++ + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); + + /* mask interrupt at init; if the interrupt is +@@ -71,6 +76,14 @@ static int rtl8211x_config(struct phy_device *phydev) + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER, + MIIM_RTL8211x_PHY_INTR_DIS); + ++ if(phydev->drv->uid == 0x1cc912) { ++ /* With RTL8211C Force Master must be enabled */ ++ phydev->flags |= PHY_RTL8211x_FORCE_MASTER; ++ } else if(phydev->drv->uid == 0x1cc915) { ++ /* RTL8211E has different GMAC_TX_DELAY requirements */ ++ setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_DELAY(2)); ++ } ++ + if (phydev->flags & PHY_RTL8211x_FORCE_MASTER) { + unsigned int reg; + diff --git a/patch/u-boot/u-boot-sunxi-legacy/board_pine64so/fix-sopine-defconfig.patch b/patch/u-boot/u-boot-sunxi-legacy/board_pine64so/fix-sopine-defconfig.patch new file mode 100644 index 0000000000..04252e064d --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/board_pine64so/fix-sopine-defconfig.patch @@ -0,0 +1,206 @@ +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 98f57e0..c4321f6 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -338,7 +338,8 @@ dtb-$(CONFIG_MACH_SUN50I) += \ + sun50i-a64-olinuxino.dtb \ + sun50i-a64-orangepi-win.dtb \ + sun50i-a64-pine64-plus.dtb \ +- sun50i-a64-pine64.dtb ++ sun50i-a64-pine64.dtb \ ++ sun50i-a64-sopine-baseboard.dtb + dtb-$(CONFIG_MACH_SUN9I) += \ + sun9i-a80-optimus.dtb \ + sun9i-a80-cubieboard4.dtb \ +diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig +index 122bba3..8659bc3 100644 +--- a/configs/sopine_baseboard_defconfig ++++ b/configs/sopine_baseboard_defconfig +@@ -8,7 +8,7 @@ CONFIG_DRAM_ZQ=3881949 + CONFIG_DRAM_ODT_EN=y + CONFIG_MMC0_CD_PIN="" + CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +-CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus" ++CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-sopine-baseboard" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + CONFIG_SPL=y + # CONFIG_CMD_IMLS is not set +diff --git a/arch/arm/dts/sun50i-a64-sopine-baseboard.dts b/arch/arm/dts/sun50i-a64-sopine-baseboard.dts +new file mode 100644 +index 0000000..42c0f10 +--- /dev/null ++++ b/arch/arm/dts/sun50i-a64-sopine-baseboard.dts +@@ -0,0 +1,102 @@ ++/* ++ * Copyright (c) 2017 Icenowy Zheng ++ * ++ * Based on sun50i-a64-pine64.dts, which is: ++ * Copyright (c) 2016 ARM Ltd. ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-a64-sopine.dtsi" ++ ++/ { ++ model = "SoPine with baseboard"; ++ compatible = "pine64,sopine-baseboard", "pine64,sopine", ++ "allwinner,sun50i-a64"; ++ ++ aliases { ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ reg_vcc1v8: vcc1v8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ }; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ vqmmc-supply = <®_vcc1v8>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++}; +diff --git a/arch/arm/dts/sun50i-a64-sopine.dtsi b/arch/arm/dts/sun50i-a64-sopine.dtsi +new file mode 100644 +index 0000000..475518b +--- /dev/null ++++ b/arch/arm/dts/sun50i-a64-sopine.dtsi +@@ -0,0 +1,65 @@ ++/* ++ * Copyright (c) 2017 Icenowy Zheng ++ * ++ * Based on sun50i-a64-pine64.dts, which is: ++ * Copyright (c) 2016 ARM Ltd. ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#include "sun50i-a64.dtsi" ++ ++/ { ++ reg_vcc3v3: vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ non-removable; ++ disable-wp; ++ bus-width = <4>; ++ status = "okay"; ++}; diff --git a/patch/u-boot/u-boot-sunxi-legacy/board_pinebook-a64/01-add-sunxi-pwm-driver.patch b/patch/u-boot/u-boot-sunxi-legacy/board_pinebook-a64/01-add-sunxi-pwm-driver.patch new file mode 100644 index 0000000000..45cc182473 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/board_pinebook-a64/01-add-sunxi-pwm-driver.patch @@ -0,0 +1,274 @@ +From 485a09477c96edda8dd737493efd6f6e03ecf06e Mon Sep 17 00:00:00 2001 +From: Vasily Khoruzhick +Date: Sun, 17 Sep 2017 09:19:52 -0700 +Subject: [PATCH] pwm: sunxi: add support for PWM found on Allwinner A64 and H3 + +This commit adds basic support for PWM found on Allwinner A64 and H3 +It can be used for pwm_backlight driver (e.g. for Pinebook) + +Signed-off-by: Vasily Khoruzhick +--- + arch/arm/include/asm/arch-sunxi/gpio.h | 1 + + arch/arm/include/asm/arch-sunxi/pwm.h | 12 +++ + drivers/pwm/Kconfig | 7 ++ + drivers/pwm/Makefile | 1 + + drivers/pwm/sunxi_pwm.c | 184 +++++++++++++++++++++++++++++++++ + 5 files changed, 205 insertions(+) + create mode 100644 drivers/pwm/sunxi_pwm.c + +diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h +index 24f85206c8..7265d18099 100644 +--- a/arch/arm/include/asm/arch-sunxi/gpio.h ++++ b/arch/arm/include/asm/arch-sunxi/gpio.h +@@ -173,6 +173,7 @@ enum sunxi_gpio_number { + #define SUN8I_GPD_SDC1 3 + #define SUNXI_GPD_LCD0 2 + #define SUNXI_GPD_LVDS0 3 ++#define SUNXI_GPD_PWM 2 + + #define SUN5I_GPE_SDC2 3 + #define SUN8I_GPE_TWI2 3 +diff --git a/arch/arm/include/asm/arch-sunxi/pwm.h b/arch/arm/include/asm/arch-sunxi/pwm.h +index 5884b5dbe7..673e0eb7b5 100644 +--- a/arch/arm/include/asm/arch-sunxi/pwm.h ++++ b/arch/arm/include/asm/arch-sunxi/pwm.h +@@ -11,8 +11,15 @@ + #define SUNXI_PWM_CH0_PERIOD (SUNXI_PWM_BASE + 4) + + #define SUNXI_PWM_CTRL_PRESCALE0(x) ((x) & 0xf) ++#define SUNXI_PWM_CTRL_PRESCALE0_MASK (0xf) + #define SUNXI_PWM_CTRL_ENABLE0 (0x5 << 4) + #define SUNXI_PWM_CTRL_POLARITY0(x) ((x) << 5) ++#define SUNXI_PWM_CTRL_POLARITY0_MASK (1 << 5) ++#define SUNXI_PWM_CTRL_CLK_GATE (1 << 6) ++ ++#define SUNXI_PWM_CH0_PERIOD_MAX (0xffff) ++#define SUNXI_PWM_CH0_PERIOD_PRD(x) ((x & 0xffff) << 16) ++#define SUNXI_PWM_CH0_PERIOD_DUTY(x) ((x) & 0xffff) + + #define SUNXI_PWM_PERIOD_80PCT 0x04af03c0 + +@@ -31,4 +38,9 @@ + #define SUNXI_PWM_MUX SUN8I_GPH_PWM + #endif + ++struct sunxi_pwm { ++ u32 ctrl; ++ u32 ch0_period; ++}; ++ + #endif +diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig +index e827558052..2984b79766 100644 +--- a/drivers/pwm/Kconfig ++++ b/drivers/pwm/Kconfig +@@ -43,3 +43,10 @@ config PWM_TEGRA + four channels with a programmable period and duty cycle. Only a + 32KHz clock is supported by the driver but the duty cycle is + configurable. ++ ++config PWM_SUNXI ++ bool "Enable support for the Allwinner Sunxi PWM" ++ depends on DM_PWM ++ help ++ This PWM is found on H3, A64 and other Allwinner SoCs. It supports a ++ programmable period and duty cycle. A 16-bit counter is used. +diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile +index 29d59916cb..1a8f8a58bc 100644 +--- a/drivers/pwm/Makefile ++++ b/drivers/pwm/Makefile +@@ -17,3 +17,4 @@ obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o + obj-$(CONFIG_PWM_ROCKCHIP) += rk_pwm.o + obj-$(CONFIG_PWM_SANDBOX) += sandbox_pwm.o + obj-$(CONFIG_PWM_TEGRA) += tegra_pwm.o ++obj-$(CONFIG_PWM_SUNXI) += sunxi_pwm.o +diff --git a/drivers/pwm/sunxi_pwm.c b/drivers/pwm/sunxi_pwm.c +new file mode 100644 +index 0000000000..cfea7d69f3 +--- /dev/null ++++ b/drivers/pwm/sunxi_pwm.c +@@ -0,0 +1,184 @@ ++/* ++ * Copyright (c) 2017 Vasily Khoruzhick ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++struct sunxi_pwm_priv { ++ struct sunxi_pwm *regs; ++ ulong freq; ++ bool invert; ++ uint32_t prescaler; ++}; ++ ++static const uint32_t prescaler_table[] = { ++ 120, /* 0000 */ ++ 180, /* 0001 */ ++ 240, /* 0010 */ ++ 360, /* 0011 */ ++ 480, /* 0100 */ ++ 0, /* 0101 */ ++ 0, /* 0110 */ ++ 0, /* 0111 */ ++ 12000, /* 1000 */ ++ 24000, /* 1001 */ ++ 36000, /* 1010 */ ++ 48000, /* 1011 */ ++ 72000, /* 1100 */ ++ 0, /* 1101 */ ++ 0, /* 1110 */ ++ 1, /* 1111 */ ++}; ++ ++static const uint64_t nsecs_per_sec = 1000000000L; ++ ++static int sunxi_pwm_config_pinmux(void) ++{ ++#ifdef CONFIG_MACH_SUN50I ++ sunxi_gpio_set_cfgpin(SUNXI_GPD(22), SUNXI_GPD_PWM); ++#endif ++ return 0; ++} ++ ++static int sunxi_pwm_set_invert(struct udevice *dev, uint channel, bool polarity) ++{ ++ struct sunxi_pwm_priv *priv = dev_get_priv(dev); ++ ++ debug("%s: polarity=%u\n", __func__, polarity); ++ priv->invert = polarity; ++ ++ return 0; ++} ++ ++static int sunxi_pwm_set_config(struct udevice *dev, uint channel, uint period_ns, ++ uint duty_ns) ++{ ++ struct sunxi_pwm_priv *priv = dev_get_priv(dev); ++ struct sunxi_pwm *regs = priv->regs; ++ int prescaler; ++ u32 v, period, duty; ++ uint64_t div = 0, pval = 0, scaled_freq = 0; ++ ++ debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns); ++ ++ for (prescaler = 0; prescaler < SUNXI_PWM_CTRL_PRESCALE0_MASK; prescaler++) { ++ if (!prescaler_table[prescaler]) ++ continue; ++ div = priv->freq; ++ pval = prescaler_table[prescaler]; ++ scaled_freq = lldiv(div, pval); ++ div = scaled_freq * period_ns; ++ div = lldiv(div, nsecs_per_sec); ++ if (div - 1 <= SUNXI_PWM_CH0_PERIOD_MAX) ++ break; ++ } ++ ++ if (div - 1 > SUNXI_PWM_CH0_PERIOD_MAX) { ++ debug("%s: failed to find prescaler value\n", __func__); ++ return -EINVAL; ++ } ++ ++ period = div; ++ div = scaled_freq * duty_ns; ++ div = lldiv(div, nsecs_per_sec); ++ duty = div; ++ ++ if (priv->prescaler != prescaler) { ++ /* Mask clock to update prescaler */ ++ v = readl(®s->ctrl); ++ v &= ~SUNXI_PWM_CTRL_CLK_GATE; ++ writel(v, ®s->ctrl); ++ v &= ~SUNXI_PWM_CTRL_PRESCALE0_MASK; ++ v |= (priv->prescaler & SUNXI_PWM_CTRL_PRESCALE0_MASK); ++ writel(v, ®s->ctrl); ++ v |= SUNXI_PWM_CTRL_CLK_GATE; ++ writel(v, ®s->ctrl); ++ priv->prescaler = prescaler; ++ } ++ ++ writel(SUNXI_PWM_CH0_PERIOD_PRD(period) | ++ SUNXI_PWM_CH0_PERIOD_DUTY(duty), ®s->ch0_period); ++ ++ debug("%s: prescaler: %d, period: %d, duty: %d\n", __func__, priv->prescaler, ++ period, duty); ++ ++ return 0; ++} ++ ++static int sunxi_pwm_set_enable(struct udevice *dev, uint channel, bool enable) ++{ ++ struct sunxi_pwm_priv *priv = dev_get_priv(dev); ++ struct sunxi_pwm *regs = priv->regs; ++ uint32_t v; ++ ++ debug("%s: Enable '%s'\n", __func__, dev->name); ++ ++ v = readl(®s->ctrl); ++ if (!enable) { ++ v &= ~SUNXI_PWM_CTRL_ENABLE0; ++ writel(v, ®s->ctrl); ++ return 0; ++ } ++ ++ sunxi_pwm_config_pinmux(); ++ ++ v &= ~SUNXI_PWM_CTRL_POLARITY0_MASK; ++ v |= priv->invert ? SUNXI_PWM_CTRL_POLARITY0(0) : ++ SUNXI_PWM_CTRL_POLARITY0(1); ++ v |= SUNXI_PWM_CTRL_ENABLE0; ++ writel(v, ®s->ctrl); ++ ++ return 0; ++} ++ ++static int sunxi_pwm_ofdata_to_platdata(struct udevice *dev) ++{ ++ struct sunxi_pwm_priv *priv = dev_get_priv(dev); ++ ++ priv->regs = (struct sunxi_pwm *)devfdt_get_addr(dev); ++ ++ return 0; ++} ++ ++static int sunxi_pwm_probe(struct udevice *dev) ++{ ++ struct sunxi_pwm_priv *priv = dev_get_priv(dev); ++ ++ priv->freq = 24000000; ++ ++ return 0; ++} ++ ++static const struct pwm_ops sunxi_pwm_ops = { ++ .set_invert = sunxi_pwm_set_invert, ++ .set_config = sunxi_pwm_set_config, ++ .set_enable = sunxi_pwm_set_enable, ++}; ++ ++static const struct udevice_id sunxi_pwm_ids[] = { ++ { .compatible = "allwinner,sun8i-h3-pwm" }, ++ { } ++}; ++ ++U_BOOT_DRIVER(sunxi_pwm) = { ++ .name = "sunxi_pwm", ++ .id = UCLASS_PWM, ++ .of_match = sunxi_pwm_ids, ++ .ops = &sunxi_pwm_ops, ++ .ofdata_to_platdata = sunxi_pwm_ofdata_to_platdata, ++ .probe = sunxi_pwm_probe, ++ .priv_auto_alloc_size = sizeof(struct sunxi_pwm_priv), ++}; diff --git a/patch/u-boot/u-boot-sunxi-legacy/board_pinebook-a64/02-add-axp803-pmic-support.patch b/patch/u-boot/u-boot-sunxi-legacy/board_pinebook-a64/02-add-axp803-pmic-support.patch new file mode 100644 index 0000000000..5a152f993f --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/board_pinebook-a64/02-add-axp803-pmic-support.patch @@ -0,0 +1,821 @@ +From 15d68b2115b24dcf3a20f67942db867e5887b624 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng +Date: Mon, 27 Mar 2017 19:22:34 +0200 +Subject: [PATCH] sunxi: add AXP803 support + +The A64 uses the AXP803 as its PMIC. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Jernej Skrabec +--- + arch/arm/mach-sunxi/Makefile | 3 + + arch/arm/mach-sunxi/pmic_bus.c | 6 +- + arch/arm/mach-sunxi/rsb.c | 2 +- + board/sunxi/board.c | 31 ++--- + drivers/power/Kconfig | 85 +++++++++----- + drivers/power/Makefile | 1 + + drivers/power/axp803.c | 259 +++++++++++++++++++++++++++++++++++++++++ + drivers/power/axp818.c | 2 +- + include/axp803.h | 73 ++++++++++++ + include/axp_pmic.h | 3 + + 10 files changed, 415 insertions(+), 50 deletions(-) + create mode 100644 drivers/power/axp803.c + create mode 100644 include/axp803.h + +diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile +index 2a3c379b72..0bbfda9364 100644 +--- a/arch/arm/mach-sunxi/Makefile ++++ b/arch/arm/mach-sunxi/Makefile +@@ -19,9 +19,11 @@ endif + obj-$(CONFIG_MACH_SUN6I) += prcm.o + obj-$(CONFIG_MACH_SUN8I) += prcm.o + obj-$(CONFIG_MACH_SUN9I) += prcm.o ++obj-$(CONFIG_MACH_SUN50I) += prcm.o + obj-$(CONFIG_MACH_SUN6I) += p2wi.o + obj-$(CONFIG_MACH_SUN8I) += rsb.o + obj-$(CONFIG_MACH_SUN9I) += rsb.o ++obj-$(CONFIG_MACH_SUN50I) += rsb.o + obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o + obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o + obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o +@@ -37,6 +39,7 @@ obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o gtbus_sun9i.o + obj-$(CONFIG_AXP152_POWER) += pmic_bus.o + obj-$(CONFIG_AXP209_POWER) += pmic_bus.o + obj-$(CONFIG_AXP221_POWER) += pmic_bus.o ++obj-$(CONFIG_AXP803_POWER) += pmic_bus.o + obj-$(CONFIG_AXP809_POWER) += pmic_bus.o + obj-$(CONFIG_AXP818_POWER) += pmic_bus.o + +diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c +index f917c3e070..e021b58b60 100644 +--- a/arch/arm/mach-sunxi/pmic_bus.c ++++ b/arch/arm/mach-sunxi/pmic_bus.c +@@ -36,7 +36,7 @@ int pmic_bus_init(void) + if (!needs_init) + return 0; + +-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER ++#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER + # ifdef CONFIG_MACH_SUN6I + p2wi_init(); + ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR, +@@ -65,7 +65,7 @@ int pmic_bus_read(u8 reg, u8 *data) + return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1); + #elif defined CONFIG_AXP209_POWER + return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1); +-#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER ++#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER + # ifdef CONFIG_MACH_SUN6I + return p2wi_read(reg, data); + # elif defined CONFIG_MACH_SUN8I_R40 +@@ -82,7 +82,7 @@ int pmic_bus_write(u8 reg, u8 data) + return i2c_write(AXP152_I2C_ADDR, reg, 1, &data, 1); + #elif defined CONFIG_AXP209_POWER + return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1); +-#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER ++#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER + # ifdef CONFIG_MACH_SUN6I + return p2wi_write(reg, data); + # elif defined CONFIG_MACH_SUN8I_R40 +diff --git a/arch/arm/mach-sunxi/rsb.c b/arch/arm/mach-sunxi/rsb.c +index 6fd11f1529..28d05e962a 100644 +--- a/arch/arm/mach-sunxi/rsb.c ++++ b/arch/arm/mach-sunxi/rsb.c +@@ -20,7 +20,7 @@ static int rsb_set_device_mode(void); + + static void rsb_cfg_io(void) + { +-#ifdef CONFIG_MACH_SUN8I ++#if defined CONFIG_MACH_SUN8I || defined CONFIG_MACH_SUN50I + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB); + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB); + sunxi_gpio_set_pull(SUNXI_GPL(0), 1); +diff --git a/board/sunxi/board.c b/board/sunxi/board.c +index 70e01437c4..192cf8ca45 100644 +--- a/board/sunxi/board.c ++++ b/board/sunxi/board.c +@@ -519,26 +519,27 @@ void sunxi_board_init(void) + #endif + + #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ +- defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ +- defined CONFIG_AXP818_POWER ++ defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || \ ++ defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER + power_failed = axp_init(); + +-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ +- defined CONFIG_AXP818_POWER ++#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || \ ++ defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER + power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT); + #endif + power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT); + power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT); +-#if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER) ++#if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP803_POWER) && \ ++ !defined(CONFIG_AXP818_POWER) + power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT); + #endif +-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ +- defined CONFIG_AXP818_POWER ++#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || \ ++ defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER + power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT); + #endif + +-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ +- defined CONFIG_AXP818_POWER ++#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || \ ++ defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER + power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT); + #endif + power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT); +@@ -549,8 +550,8 @@ void sunxi_board_init(void) + power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT); + #endif + +-#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \ +- defined(CONFIG_AXP818_POWER) ++#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP803_POWER) || \ ++ defined(CONFIG_AXP809_POWER) || defined(CONFIG_AXP818_POWER) + power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT); + power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT); + #if !defined CONFIG_AXP809_POWER +@@ -562,13 +563,17 @@ void sunxi_board_init(void) + power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT); + #endif + +-#ifdef CONFIG_AXP818_POWER ++#if defined CONFIG_AXP803_POWER || defined CONFIG_AXP818_POWER + power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT); + power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT); ++#endif ++ ++#ifdef CONFIG_AXP818_POWER + power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT); + #endif + +-#if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER ++#if defined CONFIG_AXP803_POWER || defined CONFIG_AXP809_POWER || \ ++ defined CONFIG_AXP818_POWER + power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON)); + #endif + #endif +diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig +index d8c107e206..2da80ae04b 100644 +--- a/drivers/power/Kconfig ++++ b/drivers/power/Kconfig +@@ -11,8 +11,9 @@ choice + depends on ARCH_SUNXI + default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I + default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40 ++ default AXP803_POWER if MACH_SUN50I + default AXP818_POWER if MACH_SUN8I_A83T +- default SUNXI_NO_PMIC if MACH_SUNXI_H3_H5 || MACH_SUN50I ++ default SUNXI_NO_PMIC if MACH_SUNXI_H3_H5 + + config SUNXI_NO_PMIC + bool "board without a pmic" +@@ -43,6 +44,13 @@ config AXP221_POWER + Select this to enable support for the axp221/axp223 pmic found on most + A23 and A31 boards. + ++config AXP803_POWER ++ bool "axp803 pmic support" ++ depends on MACH_SUN50I ++ select CMD_POWEROFF ++ ---help--- ++ Say y here to enable support for the axp803 pmic found on A64 boards. ++ + config AXP809_POWER + bool "axp809 pmic support" + depends on MACH_SUN9I +@@ -69,25 +77,25 @@ endchoice + + config AXP_DCDC1_VOLT + int "axp pmic dcdc1 voltage" +- depends on AXP221_POWER || AXP809_POWER || AXP818_POWER +- default 3300 if AXP818_POWER || MACH_SUN8I_R40 ++ depends on AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER ++ default 3300 if AXP818_POWER || MACH_SUN8I_R40 || MACH_SUN50I + default 3000 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I + ---help--- + Set the voltage (mV) to program the axp pmic dcdc1 at, set to 0 to + disable dcdc1. On A23 / A31 / A33 (axp221) boards dcdc1 is used for + generic 3.3V IO voltage for external devices like the lcd-panal and + sdcard interfaces, etc. On most boards dcdc1 is undervolted to 3.0V to +- save battery. On A31 devices dcdc1 is also used for VCC-IO. On A83T +- dcdc1 is used for VCC-IO, nand, usb0, sd , etc. On A80 dcdc1 normally +- powers some of the pingroups, NAND/eMMC, SD/MMC, and USB OTG. ++ save battery. On A31 devices dcdc1 is also used for VCC-IO. On A83T and ++ A64 dcdc1 is used for VCC-IO, nand, usb0, sd , etc. On A80 dcdc1 ++ normally powers some of the pingroups, NAND/eMMC, SD/MMC, and USB OTG. + + config AXP_DCDC2_VOLT + int "axp pmic dcdc2 voltage" +- depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER ++ depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER + default 900 if AXP818_POWER + default 1400 if AXP152_POWER || AXP209_POWER + default 1200 if MACH_SUN6I +- default 1100 if MACH_SUN8I ++ default 1100 if MACH_SUN8I || MACH_SUN50I + default 0 if MACH_SUN9I + ---help--- + Set the voltage (mV) to program the axp pmic dcdc2 at, set to 0 to +@@ -98,14 +106,15 @@ config AXP_DCDC2_VOLT + On A80 boards dcdc2 powers the GPU and can be left off. + On A83T boards dcdc2 is used for VDD-CPUA(cluster 0) and should be 0.9V. + On R40 boards dcdc2 is VDD-CPU and should be 1.1V ++ On A64 boards dcdc2 is used with dcdc3 for VDD-CPU and should be 1.1V. + + config AXP_DCDC3_VOLT + int "axp pmic dcdc3 voltage" +- depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER ++ depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER + default 900 if AXP809_POWER || AXP818_POWER + default 1500 if AXP152_POWER + default 1250 if AXP209_POWER +- default 1100 if MACH_SUN8I_R40 ++ default 1100 if MACH_SUN8I_R40 || MACH_SUN50I + default 1200 if MACH_SUN6I || MACH_SUN8I + ---help--- + Set the voltage (mV) to program the axp pmic dcdc3 at, set to 0 to +@@ -117,39 +126,42 @@ config AXP_DCDC3_VOLT + On A80 boards dcdc3 is used for VDD-CPUA(cluster 0) and should be 0.9V. + On A83T boards dcdc3 is used for VDD-CPUB(cluster 1) and should be 0.9V. + On R40 boards dcdc3 is VDD-SYS and VDD-GPU and should be 1.1V. ++ On A64 boards dcdc3 is used with dcdc2 for VDD-CPU and should be 1.1V. + + config AXP_DCDC4_VOLT + int "axp pmic dcdc4 voltage" +- depends on AXP152_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER ++ depends on AXP152_POWER || AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER + default 1250 if AXP152_POWER + default 1200 if MACH_SUN6I +- default 0 if MACH_SUN8I ++ default 0 if MACH_SUN8I || MACH_SUN50I + default 900 if MACH_SUN9I + ---help--- + Set the voltage (mV) to program the axp pmic dcdc4 at, set to 0 to + disable dcdc4. + On A10s boards with an axp152 dcdc4 is VDD-INT-DLL and should be 1.25V. + On A31 boards dcdc4 is used for VDD-SYS and should be 1.2V. +- On A23 / A33 boards dcdc4 is unused and should be disabled. ++ On A23 / A33 / A64 boards dcdc4 is unused and should be disabled. + On A80 boards dcdc4 powers VDD-SYS, HDMI, USB OTG and should be 0.9V. + On A83T boards dcdc4 is used for VDD-GPU. + + config AXP_DCDC5_VOLT + int "axp pmic dcdc5 voltage" +- depends on AXP221_POWER || AXP809_POWER || AXP818_POWER ++ depends on AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER + default 1500 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I ++ default 1350 if MACH_SUN50I + ---help--- + Set the voltage (mV) to program the axp pmic dcdc5 at, set to 0 to + disable dcdc5. +- On A23 / A31 / A33 / A80 / A83T / R40 boards dcdc5 is VCC-DRAM and ++ On A23 / A31 / A33 / A64 / A80 / A83T / R40 boards dcdc5 is VCC-DRAM and + should be 1.5V, 1.35V if DDR3L is used. + + config AXP_ALDO1_VOLT + int "axp pmic (a)ldo1 voltage" +- depends on AXP221_POWER || AXP809_POWER || AXP818_POWER ++ depends on AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER + default 0 if MACH_SUN6I || MACH_SUN8I_R40 + default 1800 if MACH_SUN8I_A83T + default 3000 if MACH_SUN8I || MACH_SUN9I ++ default 2800 if MACH_SUN50I + ---help--- + Set the voltage (mV) to program the axp pmic aldo1 at, set to 0 to + disable aldo1. +@@ -158,14 +170,16 @@ config AXP_ALDO1_VOLT + On A80 boards aldo1 powers the USB hosts and should be 3.0V. + On A83T / H8 boards aldo1 is used for MIPI CSI, DSI, HDMI, EFUSE, and + should be 1.8V. ++ On A64 boards aldo1 powers PE pingroup and CSI and should be 2.8V. + + config AXP_ALDO2_VOLT + int "axp pmic (a)ldo2 voltage" +- depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER ++ depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER + default 3000 if AXP152_POWER || AXP209_POWER + default 0 if MACH_SUN6I || MACH_SUN9I + default 1800 if MACH_SUN8I_A83T + default 2500 if MACH_SUN8I ++ default 1800 if MACH_SUN50I + ---help--- + Set the voltage (mV) to program the axp pmic aldo2 at, set to 0 to + disable aldo2. +@@ -176,17 +190,18 @@ config AXP_ALDO2_VOLT + On A80 boards aldo2 powers PB pingroup and camera IO and can be left off. + On A83T / H8 boards aldo2 powers VDD-DLL, VCC18-PLL, CPVDD, VDD18-ADC, + LPDDR2, and the codec. It should be 1.8V. ++ On A64 boards aldo2 powers PL pingroup and should be 1.8V. + + config AXP_ALDO3_VOLT + int "axp pmic (a)ldo3 voltage" +- depends on AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER ++ depends on AXP209_POWER || AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER + default 0 if AXP209_POWER || MACH_SUN9I +- default 3000 if MACH_SUN6I || MACH_SUN8I ++ default 3000 if MACH_SUN6I || MACH_SUN8I || MACH_SUN50I + ---help--- + Set the voltage (mV) to program the axp pmic aldo3 at, set to 0 to + disable aldo3. + On A10(s) / A13 / A20 boards aldo3 should be 2.8V. +- On A23 / A31 / A33 / R40 boards aldo3 is VCC-PLL and AVCC and should ++ On A23 / A31 / A33 / A64 / R40 boards aldo3 is VCC-PLL and AVCC and should + be 3.0V. + On A80 boards aldo3 is normally not used. + On A83T / H8 boards aldo3 is AVCC, VCC-PL, and VCC-LED, and should be +@@ -203,17 +218,19 @@ config AXP_ALDO4_VOLT + + config AXP_DLDO1_VOLT + int "axp pmic dldo1 voltage" +- depends on AXP221_POWER || AXP809_POWER || AXP818_POWER ++ depends on AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER ++ default 3300 if MACH_SUN50I + default 0 + ---help--- + Set the voltage (mV) to program the axp pmic dldo1 at, set to 0 to + disable dldo1. On sun6i (A31) boards with ethernet dldo1 is often used + to power the ethernet phy. On A23, A33 and A80 boards this is often +- used to power the wifi. ++ used to power the wifi. On A64 boards this is often used to power the ++ HDMI. + + config AXP_DLDO2_VOLT + int "axp pmic dldo2 voltage" +- depends on AXP221_POWER || AXP809_POWER || AXP818_POWER ++ depends on AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER + default 3000 if MACH_SUN9I + default 0 + ---help--- +@@ -223,7 +240,7 @@ config AXP_DLDO2_VOLT + + config AXP_DLDO3_VOLT + int "axp pmic dldo3 voltage" +- depends on AXP221_POWER || AXP818_POWER ++ depends on AXP221_POWER || AXP803_POWER || AXP818_POWER + default 0 + ---help--- + Set the voltage (mV) to program the axp pmic dldo3 at, set to 0 to +@@ -231,7 +248,7 @@ config AXP_DLDO3_VOLT + + config AXP_DLDO4_VOLT + int "axp pmic dldo4 voltage" +- depends on AXP221_POWER || AXP818_POWER ++ depends on AXP221_POWER || AXP803_POWER || AXP818_POWER + default 0 + ---help--- + Set the voltage (mV) to program the axp pmic dldo4 at, set to 0 to +@@ -239,15 +256,17 @@ config AXP_DLDO4_VOLT + + config AXP_ELDO1_VOLT + int "axp pmic eldo1 voltage" +- depends on AXP221_POWER || AXP809_POWER || AXP818_POWER ++ depends on AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER ++ default 1800 if MACH_SUN50I + default 0 + ---help--- + Set the voltage (mV) to program the axp pmic eldo1 at, set to 0 to + disable eldo1. ++ On A64 boards it's used for the codec and should be 1.8V. + + config AXP_ELDO2_VOLT + int "axp pmic eldo2 voltage" +- depends on AXP221_POWER || AXP809_POWER || AXP818_POWER ++ depends on AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER + default 0 + ---help--- + Set the voltage (mV) to program the axp pmic eldo2 at, set to 0 to +@@ -255,7 +274,7 @@ config AXP_ELDO2_VOLT + + config AXP_ELDO3_VOLT + int "axp pmic eldo3 voltage" +- depends on AXP221_POWER || AXP809_POWER || AXP818_POWER ++ depends on AXP221_POWER || AXP803_POWER || AXP809_POWER || AXP818_POWER + default 3000 if MACH_SUN9I + default 0 + ---help--- +@@ -267,8 +286,8 @@ config AXP_ELDO3_VOLT + + config AXP_FLDO1_VOLT + int "axp pmic fldo1 voltage" +- depends on AXP818_POWER +- default 0 if MACH_SUN8I_A83T ++ depends on AXP803_POWER || AXP818_POWER ++ default 0 + ---help--- + Set the voltage (mV) to program the axp pmic fldo1 at, set to 0 to + disable fldo1. +@@ -277,11 +296,13 @@ config AXP_FLDO1_VOLT + + config AXP_FLDO2_VOLT + int "axp pmic fldo2 voltage" +- depends on AXP818_POWER ++ depends on AXP803_POWER || AXP818_POWER ++ default 1100 if MACH_SUN50I + default 900 if MACH_SUN8I_A83T + ---help--- + Set the voltage (mV) to program the axp pmic fldo2 at, set to 0 to + disable fldo2. ++ On A64 boards fldo2 is VCC-CPUS and should be 1.1V. + On A83T / H8 boards fldo2 is VCC-CPUS and should be 0.9V. + + config AXP_FLDO3_VOLT +@@ -294,7 +315,7 @@ config AXP_FLDO3_VOLT + + config AXP_SW_ON + bool "axp pmic sw on" +- depends on AXP809_POWER || AXP818_POWER ++ depends on AXP803_POWER || AXP809_POWER || AXP818_POWER + default n + ---help--- + Enable to turn on axp pmic sw. +diff --git a/drivers/power/Makefile b/drivers/power/Makefile +index 90a3b00a7c..55413a66d2 100644 +--- a/drivers/power/Makefile ++++ b/drivers/power/Makefile +@@ -8,6 +8,7 @@ + obj-$(CONFIG_AXP152_POWER) += axp152.o + obj-$(CONFIG_AXP209_POWER) += axp209.o + obj-$(CONFIG_AXP221_POWER) += axp221.o ++obj-$(CONFIG_AXP803_POWER) += axp803.o + obj-$(CONFIG_AXP809_POWER) += axp809.o + obj-$(CONFIG_AXP818_POWER) += axp818.o + obj-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o +diff --git a/drivers/power/axp803.c b/drivers/power/axp803.c +new file mode 100644 +index 0000000000..af20fce8b1 +--- /dev/null ++++ b/drivers/power/axp803.c +@@ -0,0 +1,259 @@ ++/* ++ * AXP803 driver based on AXP818 driver ++ * ++ * Based on axp818.c ++ * (C) Copyright 2015 Vishnu Patekar ++ * ++ * Based on axp221.c ++ * (C) Copyright 2014 Hans de Goede ++ * (C) Copyright 2013 Oliver Schinagl ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++static u8 axp803_mvolt_to_cfg(int mvolt, int min, int max, int div) ++{ ++ if (mvolt < min) ++ mvolt = min; ++ else if (mvolt > max) ++ mvolt = max; ++ ++ return (mvolt - min) / div; ++} ++ ++int axp_set_dcdc1(unsigned int mvolt) ++{ ++ int ret; ++ u8 cfg = axp803_mvolt_to_cfg(mvolt, 1600, 3400, 100); ++ ++ if (mvolt == 0) ++ return pmic_bus_clrbits(AXP803_OUTPUT_CTRL1, ++ AXP803_OUTPUT_CTRL1_DCDC1_EN); ++ ++ ret = pmic_bus_write(AXP803_DCDC1_CTRL, cfg); ++ if (ret) ++ return ret; ++ ++ return pmic_bus_setbits(AXP803_OUTPUT_CTRL1, ++ AXP803_OUTPUT_CTRL1_DCDC1_EN); ++} ++ ++int axp_set_dcdc2(unsigned int mvolt) ++{ ++ int ret; ++ u8 cfg; ++ ++ if (mvolt >= 1220) ++ cfg = 70 + axp803_mvolt_to_cfg(mvolt, 1220, 1300, 20); ++ else ++ cfg = axp803_mvolt_to_cfg(mvolt, 500, 1200, 10); ++ ++ if (mvolt == 0) ++ return pmic_bus_clrbits(AXP803_OUTPUT_CTRL1, ++ AXP803_OUTPUT_CTRL1_DCDC2_EN); ++ ++ ret = pmic_bus_write(AXP803_DCDC2_CTRL, cfg); ++ if (ret) ++ return ret; ++ ++ return pmic_bus_setbits(AXP803_OUTPUT_CTRL1, ++ AXP803_OUTPUT_CTRL1_DCDC2_EN); ++} ++ ++int axp_set_dcdc3(unsigned int mvolt) ++{ ++ int ret; ++ u8 cfg; ++ ++ if (mvolt >= 1220) ++ cfg = 70 + axp803_mvolt_to_cfg(mvolt, 1220, 1300, 20); ++ else ++ cfg = axp803_mvolt_to_cfg(mvolt, 500, 1200, 10); ++ ++ if (mvolt == 0) ++ return pmic_bus_clrbits(AXP803_OUTPUT_CTRL1, ++ AXP803_OUTPUT_CTRL1_DCDC3_EN); ++ ++ ret = pmic_bus_write(AXP803_DCDC3_CTRL, cfg); ++ if (ret) ++ return ret; ++ ++ return pmic_bus_setbits(AXP803_OUTPUT_CTRL1, ++ AXP803_OUTPUT_CTRL1_DCDC3_EN); ++} ++ ++int axp_set_dcdc5(unsigned int mvolt) ++{ ++ int ret; ++ u8 cfg; ++ ++ if (mvolt >= 1140) ++ cfg = 32 + axp803_mvolt_to_cfg(mvolt, 1140, 1840, 20); ++ else ++ cfg = axp803_mvolt_to_cfg(mvolt, 800, 1120, 10); ++ ++ if (mvolt == 0) ++ return pmic_bus_clrbits(AXP803_OUTPUT_CTRL1, ++ AXP803_OUTPUT_CTRL1_DCDC5_EN); ++ ++ ret = pmic_bus_write(AXP803_DCDC5_CTRL, cfg); ++ if (ret) ++ return ret; ++ ++ return pmic_bus_setbits(AXP803_OUTPUT_CTRL1, ++ AXP803_OUTPUT_CTRL1_DCDC5_EN); ++} ++ ++int axp_set_aldo(int aldo_num, unsigned int mvolt) ++{ ++ int ret; ++ u8 cfg; ++ ++ if (aldo_num < 1 || aldo_num > 3) ++ return -EINVAL; ++ ++ if (mvolt == 0) ++ return pmic_bus_clrbits(AXP803_OUTPUT_CTRL3, ++ AXP803_OUTPUT_CTRL3_ALDO1_EN << (aldo_num - 1)); ++ ++ cfg = axp803_mvolt_to_cfg(mvolt, 700, 3300, 100); ++ ret = pmic_bus_write(AXP803_ALDO1_CTRL + (aldo_num - 1), cfg); ++ if (ret) ++ return ret; ++ ++ return pmic_bus_setbits(AXP803_OUTPUT_CTRL3, ++ AXP803_OUTPUT_CTRL3_ALDO1_EN << (aldo_num - 1)); ++} ++ ++/* TODO: re-work other AXP drivers to consolidate ALDO functions. */ ++int axp_set_aldo1(unsigned int mvolt) ++{ ++ return axp_set_aldo(1, mvolt); ++} ++ ++int axp_set_aldo2(unsigned int mvolt) ++{ ++ return axp_set_aldo(2, mvolt); ++} ++ ++int axp_set_aldo3(unsigned int mvolt) ++{ ++ return axp_set_aldo(3, mvolt); ++} ++ ++int axp_set_dldo(int dldo_num, unsigned int mvolt) ++{ ++ int ret; ++ u8 cfg; ++ ++ if (dldo_num < 1 || dldo_num > 4) ++ return -EINVAL; ++ ++ if (mvolt == 0) ++ return pmic_bus_clrbits(AXP803_OUTPUT_CTRL2, ++ AXP803_OUTPUT_CTRL2_DLDO1_EN << (dldo_num - 1)); ++ ++ cfg = axp803_mvolt_to_cfg(mvolt, 700, 3300, 100); ++ if (dldo_num == 2 && mvolt > 3300) ++ cfg += 1 + axp803_mvolt_to_cfg(mvolt, 3400, 4200, 200); ++ ret = pmic_bus_write(AXP803_DLDO1_CTRL + (dldo_num - 1), cfg); ++ if (ret) ++ return ret; ++ ++ return pmic_bus_setbits(AXP803_OUTPUT_CTRL2, ++ AXP803_OUTPUT_CTRL2_DLDO1_EN << (dldo_num - 1)); ++} ++ ++int axp_set_eldo(int eldo_num, unsigned int mvolt) ++{ ++ int ret; ++ u8 cfg; ++ ++ if (eldo_num < 1 || eldo_num > 3) ++ return -EINVAL; ++ ++ if (mvolt == 0) ++ return pmic_bus_clrbits(AXP803_OUTPUT_CTRL2, ++ AXP803_OUTPUT_CTRL2_ELDO1_EN << (eldo_num - 1)); ++ ++ cfg = axp803_mvolt_to_cfg(mvolt, 700, 1900, 50); ++ ret = pmic_bus_write(AXP803_ELDO1_CTRL + (eldo_num - 1), cfg); ++ if (ret) ++ return ret; ++ ++ return pmic_bus_setbits(AXP803_OUTPUT_CTRL2, ++ AXP803_OUTPUT_CTRL2_ELDO1_EN << (eldo_num - 1)); ++} ++ ++int axp_set_fldo(int fldo_num, unsigned int mvolt) ++{ ++ int ret; ++ u8 cfg; ++ ++ if (fldo_num < 1 || fldo_num > 2) ++ return -EINVAL; ++ ++ if (mvolt == 0) ++ return pmic_bus_clrbits(AXP803_OUTPUT_CTRL3, ++ AXP803_OUTPUT_CTRL3_FLDO1_EN << (fldo_num - 1)); ++ ++ cfg = axp803_mvolt_to_cfg(mvolt, 700, 1450, 50); ++ ret = pmic_bus_write(AXP803_FLDO1_CTRL + (fldo_num - 1), cfg); ++ if (ret) ++ return ret; ++ ++ return pmic_bus_setbits(AXP803_OUTPUT_CTRL3, ++ AXP803_OUTPUT_CTRL3_FLDO1_EN << (fldo_num - 1)); ++} ++ ++int axp_set_sw(bool on) ++{ ++ if (on) ++ return pmic_bus_setbits(AXP803_OUTPUT_CTRL2, ++ AXP803_OUTPUT_CTRL2_SW_EN); ++ ++ return pmic_bus_clrbits(AXP803_OUTPUT_CTRL2, ++ AXP803_OUTPUT_CTRL2_SW_EN); ++} ++ ++int axp_init(void) ++{ ++ u8 axp_chip_id; ++ int ret; ++ ++ ret = pmic_bus_init(); ++ if (ret) ++ return ret; ++ ++ ret = pmic_bus_read(AXP803_CHIP_ID, &axp_chip_id); ++ if (ret) ++ return ret; ++ ++ if (!(axp_chip_id == 0x51)) ++ return -ENODEV; ++ else ++ return ret; ++ ++ return 0; ++} ++ ++/* ARM64 has its own poweroff implementation using PSCI */ ++#ifndef CONFIG_ARM64 ++int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) ++{ ++ pmic_bus_write(AXP803_SHUTDOWN, AXP803_SHUTDOWN_POWEROFF); ++ ++ /* infinite loop during shutdown */ ++ while (1) ++ ; ++ ++ /* not reached */ ++ return 0; ++} ++#endif +diff --git a/drivers/power/axp818.c b/drivers/power/axp818.c +index af4d7a6903..ad0c330ca5 100644 +--- a/drivers/power/axp818.c ++++ b/drivers/power/axp818.c +@@ -162,7 +162,7 @@ int axp_set_dldo(int dldo_num, unsigned int mvolt) + cfg = axp818_mvolt_to_cfg(mvolt, 700, 3300, 100); + if (dldo_num == 2 && mvolt > 3300) + cfg += 1 + axp818_mvolt_to_cfg(mvolt, 3400, 4200, 200); +- ret = pmic_bus_write(AXP818_ELDO1_CTRL + (dldo_num - 1), cfg); ++ ret = pmic_bus_write(AXP818_DLDO1_CTRL + (dldo_num - 1), cfg); + if (ret) + return ret; + +diff --git a/include/axp803.h b/include/axp803.h +new file mode 100644 +index 0000000000..b382f3a5ec +--- /dev/null ++++ b/include/axp803.h +@@ -0,0 +1,73 @@ ++/* ++ * (C) Copyright 2016 Icenowy Zheng ++ * ++ * Based on axp818.h, which is: ++ * (C) Copyright 2015 Vishnu Patekar ++ * ++ * X-Powers AXP803 Power Management IC driver ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#define AXP803_CHIP_ID 0x03 ++ ++#define AXP803_OUTPUT_CTRL1 0x10 ++#define AXP803_OUTPUT_CTRL1_DCDC1_EN (1 << 0) ++#define AXP803_OUTPUT_CTRL1_DCDC2_EN (1 << 1) ++#define AXP803_OUTPUT_CTRL1_DCDC3_EN (1 << 2) ++#define AXP803_OUTPUT_CTRL1_DCDC4_EN (1 << 3) ++#define AXP803_OUTPUT_CTRL1_DCDC5_EN (1 << 4) ++#define AXP803_OUTPUT_CTRL1_DCDC6_EN (1 << 5) ++#define AXP803_OUTPUT_CTRL2 0x12 ++#define AXP803_OUTPUT_CTRL2_ELDO1_EN (1 << 0) ++#define AXP803_OUTPUT_CTRL2_ELDO2_EN (1 << 1) ++#define AXP803_OUTPUT_CTRL2_ELDO3_EN (1 << 2) ++#define AXP803_OUTPUT_CTRL2_DLDO1_EN (1 << 3) ++#define AXP803_OUTPUT_CTRL2_DLDO2_EN (1 << 4) ++#define AXP803_OUTPUT_CTRL2_DLDO3_EN (1 << 5) ++#define AXP803_OUTPUT_CTRL2_DLDO4_EN (1 << 6) ++#define AXP803_OUTPUT_CTRL2_SW_EN (1 << 7) ++#define AXP803_OUTPUT_CTRL3 0x13 ++#define AXP803_OUTPUT_CTRL3_FLDO1_EN (1 << 2) ++#define AXP803_OUTPUT_CTRL3_FLDO2_EN (1 << 3) ++#define AXP803_OUTPUT_CTRL3_ALDO1_EN (1 << 5) ++#define AXP803_OUTPUT_CTRL3_ALDO2_EN (1 << 6) ++#define AXP803_OUTPUT_CTRL3_ALDO3_EN (1 << 7) ++ ++#define AXP803_DLDO1_CTRL 0x15 ++#define AXP803_DLDO2_CTRL 0x16 ++#define AXP803_DLDO3_CTRL 0x17 ++#define AXP803_DLDO4_CTRL 0x18 ++#define AXP803_ELDO1_CTRL 0x19 ++#define AXP803_ELDO2_CTRL 0x1a ++#define AXP803_ELDO3_CTRL 0x1b ++#define AXP803_FLDO1_CTRL 0x1c ++#define AXP803_FLDO2_CTRL 0x1d ++#define AXP803_DCDC1_CTRL 0x20 ++#define AXP803_DCDC2_CTRL 0x21 ++#define AXP803_DCDC3_CTRL 0x22 ++#define AXP803_DCDC4_CTRL 0x23 ++#define AXP803_DCDC5_CTRL 0x24 ++#define AXP803_DCDC6_CTRL 0x25 ++ ++#define AXP803_ALDO1_CTRL 0x28 ++#define AXP803_ALDO2_CTRL 0x29 ++#define AXP803_ALDO3_CTRL 0x2a ++ ++#define AXP803_SHUTDOWN 0x32 ++#define AXP803_SHUTDOWN_POWEROFF (1 << 7) ++ ++/* For axp_gpio.c */ ++#define AXP_POWER_STATUS 0x00 ++#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5) ++#define AXP_VBUS_IPSOUT 0x30 ++#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2) ++#define AXP_MISC_CTRL 0x8f ++#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4) ++#define AXP_GPIO0_CTRL 0x90 ++#define AXP_GPIO1_CTRL 0x92 ++#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ ++#define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */ ++#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */ ++#define AXP_GPIO_STATE 0x94 ++#define AXP_GPIO_STATE_OFFSET 0 +diff --git a/include/axp_pmic.h b/include/axp_pmic.h +index d789ad8086..8cb4d5763c 100644 +--- a/include/axp_pmic.h ++++ b/include/axp_pmic.h +@@ -16,6 +16,9 @@ + #ifdef CONFIG_AXP221_POWER + #include + #endif ++#ifdef CONFIG_AXP803_POWER ++#include ++#endif + #ifdef CONFIG_AXP809_POWER + #include + #endif diff --git a/patch/u-boot/u-boot-sunxi-legacy/board_pinebook-a64/04-pwm_backlight-regulator-optional.patch b/patch/u-boot/u-boot-sunxi-legacy/board_pinebook-a64/04-pwm_backlight-regulator-optional.patch new file mode 100644 index 0000000000..57579e0fa6 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/board_pinebook-a64/04-pwm_backlight-regulator-optional.patch @@ -0,0 +1,62 @@ +From 732153bd114162e8afa22a025d065c5c1d5359f5 Mon Sep 17 00:00:00 2001 +From: Vasily Khoruzhick +Date: Sun, 17 Sep 2017 09:21:33 -0700 +Subject: [PATCH] video: pwm_backlight: make regulator optional + +u-boot doesn't have dummy regulators, so pwm_backlight probe +will fail if regulator is missing. Make it optional to get this +driver working on platforms where there's no backlight regultor. + +Signed-off-by: Vasily Khoruzhick +--- + drivers/video/pwm_backlight.c | 28 ++++++++++++++++------------ + 1 file changed, 16 insertions(+), 12 deletions(-) + +diff --git a/drivers/video/pwm_backlight.c b/drivers/video/pwm_backlight.c +index fbd7bf7838..05e56ffead 100644 +--- a/drivers/video/pwm_backlight.c ++++ b/drivers/video/pwm_backlight.c +@@ -32,16 +32,21 @@ static int pwm_backlight_enable(struct udevice *dev) + uint duty_cycle; + int ret; + +- plat = dev_get_uclass_platdata(priv->reg); +- debug("%s: Enable '%s', regulator '%s'/'%s'\n", __func__, dev->name, +- priv->reg->name, plat->name); +- ret = regulator_set_enable(priv->reg, true); +- if (ret) { +- debug("%s: Cannot enable regulator for PWM '%s'\n", __func__, +- dev->name); +- return ret; ++ if (priv->reg) { ++ plat = dev_get_uclass_platdata(priv->reg); ++ debug("%s: Enable '%s', regulator '%s'/'%s'\n", __func__, dev->name, ++ priv->reg->name, plat->name); ++ ret = regulator_set_enable(priv->reg, true); ++ if (ret) { ++ debug("%s: Cannot enable regulator for PWM '%s'\n", __func__, ++ dev->name); ++ return ret; ++ } ++ mdelay(120); + } +- mdelay(120); ++ ++ debug("%s: default: %d, min: %d, max: %d\n", __func__, ++ priv->default_level, priv->min_level, priv->max_level); + + duty_cycle = priv->period_ns * (priv->default_level - priv->min_level) / + (priv->max_level - priv->min_level + 1); +@@ -68,10 +73,9 @@ static int pwm_backlight_ofdata_to_platdata(struct udevice *dev) + debug("%s: start\n", __func__); + ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev, + "power-supply", &priv->reg); +- if (ret) { ++ if (ret) + debug("%s: Cannot get power supply: ret=%d\n", __func__, ret); +- return ret; +- } ++ + ret = gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable, + GPIOD_IS_OUT); + if (ret) { diff --git a/patch/u-boot/u-boot-sunxi-legacy/board_pinebook-a64/05-add-pwm-node-DT.patch b/patch/u-boot/u-boot-sunxi-legacy/board_pinebook-a64/05-add-pwm-node-DT.patch new file mode 100644 index 0000000000..2ea03c926c --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/board_pinebook-a64/05-add-pwm-node-DT.patch @@ -0,0 +1,31 @@ +From 4644c442c8b14585881995f1c901782c3dad0e46 Mon Sep 17 00:00:00 2001 +From: Vasily Khoruzhick +Date: Sun, 17 Sep 2017 09:24:13 -0700 +Subject: [PATCH] dts: sunxi: add PWM node for sun50i + +Add PWM definition to sun50i-a64.dtsi - it's compatible with PWM found on H3 + +Signed-off-by: Vasily Khoruzhick +--- + arch/arm/dts/sun50i-a64.dtsi | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi +index 65a344d9ce..00132855ff 100644 +--- a/arch/arm/dts/sun50i-a64.dtsi ++++ b/arch/arm/dts/sun50i-a64.dtsi +@@ -319,6 +319,14 @@ + }; + }; + ++ pwm: pwm@01c21400 { ++ compatible = "allwinner,sun8i-h3-pwm"; ++ reg = <0x01c21400 0x8>; ++ clocks = <&osc24M>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ + uart0: serial@1c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; diff --git a/patch/u-boot/u-boot-sunxi-legacy/board_pinebook-a64/12-add-pinebook-dt-and-defconfig.patch b/patch/u-boot/u-boot-sunxi-legacy/board_pinebook-a64/12-add-pinebook-dt-and-defconfig.patch new file mode 100644 index 0000000000..c9fb44c453 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/board_pinebook-a64/12-add-pinebook-dt-and-defconfig.patch @@ -0,0 +1,193 @@ +From 0e9350e3ff11c91eb6959d0d4589a4cc5e576e35 Mon Sep 17 00:00:00 2001 +From: Vasily Khoruzhick +Date: Sat, 16 Sep 2017 07:44:11 -0700 +Subject: [PATCH] sunxi: add support for Pinebook + +Pinebook is a laptop produced by Pine64, with USB-connected keyboard, +I2C-connected touchpad and an eDP LCD panel connected via a RGB-eDP +bridge by Analogix. + +Signed-off-by: Icenowy Zheng +Signed-off-by: Vasily Khoruzhick +--- + arch/arm/dts/Makefile | 3 +- + arch/arm/dts/sun50i-a64-pinebook.dts | 114 +++++++++++++++++++++++++++++++++++ + configs/pinebook_defconfig | 36 +++++++++++ + 3 files changed, 152 insertions(+), 1 deletion(-) + create mode 100644 arch/arm/dts/sun50i-a64-pinebook.dts + create mode 100644 configs/pinebook_defconfig + +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index fee4680057..130d1944be 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -342,7 +342,8 @@ dtb-$(CONFIG_MACH_SUN50I) += \ + sun50i-a64-olinuxino.dtb \ + sun50i-a64-orangepi-win.dtb \ + sun50i-a64-pine64-plus.dtb \ +- sun50i-a64-pine64.dtb ++ sun50i-a64-pine64.dtb \ ++ sun50i-a64-pinebook.dtb + dtb-$(CONFIG_MACH_SUN9I) += \ + sun9i-a80-optimus.dtb \ + sun9i-a80-cubieboard4.dtb \ +diff --git a/arch/arm/dts/sun50i-a64-pinebook.dts b/arch/arm/dts/sun50i-a64-pinebook.dts +new file mode 100644 +index 0000000000..17d4c598b8 +--- /dev/null ++++ b/arch/arm/dts/sun50i-a64-pinebook.dts +@@ -0,0 +1,112 @@ ++/* ++ * Copyright (c) 2016 ARM Ltd. ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#include "sun50i-a64-pine64.dts" ++#include ++ ++/ { ++ model = "Pinebook"; ++ compatible = "pine64,pinebook", "allwinner,sun50i-a64"; ++ ++ aliases { ++ serial0 = &uart0; ++ i2c0 = "/i2c_gpio@0"; ++ }; ++ ++ backlight: backlight { ++ compatible = "pwm-backlight"; ++ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; ++ brightness-levels = <0 10 20 30 40 50 60 70 100>; ++ default-brightness-level = <3>; ++ enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */ ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ memory { ++ reg = <0x40000000 0x40000000>; ++ }; ++ ++ soc { ++ i2c_gpio@0 { ++ compatible = "i2c-gpio"; ++ gpios = <&r_pio 0 9 GPIO_ACTIVE_HIGH>, /* sda - PL9 */ ++ <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* scl - PL8 */ ++ i2c-gpio,sda-open-drain; ++ i2c-gpio,scl-open-drain; ++ i2c-gpio,delay-us = <2>; /* ~100 kHz */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ anx6345: edp-bridge@38 { ++ compatible = "analogix,anx6345"; ++ reg = <0x38>; ++ sleep-gpios = <&pio 7 6 GPIO_ACTIVE_LOW>; /* PH6 */ ++ reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */ ++ status = "okay"; ++ ++ /* ++ ports { ++ port@0 { ++ bridge_out: endpoint { ++ remote-endpoint = <&panel_in>; ++ }; ++ }; ++ ++ port@1 { ++ bridge_in: endpoint { ++ remote-endpoint = <&rgb_out>; ++ }; ++ }; ++ }; ++ */ ++ }; ++ }; ++ }; ++}; ++ ++&pwm { ++ status = "okay"; ++}; +diff --git a/configs/pinebook-a64_defconfig b/configs/pinebook-a64_defconfig +new file mode 100644 +index 0000000000..e90c863f76 +--- /dev/null ++++ b/configs/pinebook-a64_defconfig +@@ -0,0 +1,36 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_MACH_SUN50I=y ++CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y ++CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y ++CONFIG_DRAM_CLK=552 ++CONFIG_DRAM_ZQ=3881949 ++CONFIG_DRAM_ODT_EN=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinebook" ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SPL=y ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set ++CONFIG_SPL_ATF_SUPPORT=y ++CONFIG_SPL_ATF_TEXT_BASE=0x44000 ++# CONFIG_CMD_IMLS is not set ++# CONFIG_CMD_FLASH is not set ++# CONFIG_CMD_FPGA is not set ++CONFIG_CMD_I2C=y ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_SPL_ISO_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y ++CONFIG_DM_I2C_GPIO=y ++CONFIG_SPL_SPI_SUNXI=y ++CONFIG_DM_REGULATOR=y ++CONFIG_AXP_DLDO2_VOLT=2500 ++CONFIG_AXP_FLDO1_VOLT=1200 ++CONFIG_AXP_SW_ON=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_SUNXI=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y ++CONFIG_VIDEO_BRIDGE=y ++CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345=y diff --git a/patch/u-boot/u-boot-sunxi-legacy/branch_default/do-not-relocate-initrd.patch b/patch/u-boot/u-boot-sunxi-legacy/branch_default/do-not-relocate-initrd.patch new file mode 100644 index 0000000000..b3d4e3f79d --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/branch_default/do-not-relocate-initrd.patch @@ -0,0 +1,27 @@ +diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h +index 64a190059a..bbec551cac 100644 +--- a/include/configs/sunxi-common.h ++++ b/include/configs/sunxi-common.h +@@ -503,6 +503,12 @@ extern int soft_i2c_gpio_scl; + #define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb" + #endif + ++#ifdef CONFIG_MACH_SUN8I_H3 ++#define INITRD_HIGH_ENV "initrd_high=0xFFFFFFFF\0" ++#else ++#define INITRD_HIGH_ENV ++#endif ++ + #define CONFIG_EXTRA_ENV_SETTINGS \ + CONSOLE_ENV_SETTINGS \ + MEM_LAYOUT_ENV_SETTINGS \ +@@ -512,7 +518,8 @@ extern int soft_i2c_gpio_scl; + SUNXI_MTDIDS_DEFAULT \ + SUNXI_MTDPARTS_DEFAULT \ + BOOTCMD_SUNXI_COMPAT \ +- BOOTENV ++ BOOTENV \ ++ INITRD_HIGH_ENV + + #else /* ifndef CONFIG_SPL_BUILD */ + #define CONFIG_EXTRA_ENV_SETTINGS diff --git a/patch/u-boot/u-boot-sunxi-legacy/branch_default/enable-old-kernel-compat.patch b/patch/u-boot/u-boot-sunxi-legacy/branch_default/enable-old-kernel-compat.patch new file mode 100644 index 0000000000..d31bb98fe4 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/branch_default/enable-old-kernel-compat.patch @@ -0,0 +1,13 @@ +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index 513a35fc4e..77bc949cb7 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -623,7 +623,8 @@ config ARCH_SOCFPGA + + config ARCH_SUNXI + bool "Support sunxi (Allwinner) SoCs" + select BINMAN ++ select OLD_SUNXI_KERNEL_COMPAT + select CMD_GPIO + select CMD_MMC if MMC + select CMD_USB if DISTRO_DEFAULTS diff --git a/patch/u-boot/u-boot-sunxi-legacy/branch_dev/workaround-reboot-is-poweroff-olimex-a20.patch b/patch/u-boot/u-boot-sunxi-legacy/branch_dev/workaround-reboot-is-poweroff-olimex-a20.patch new file mode 100644 index 0000000000..d51534c375 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/branch_dev/workaround-reboot-is-poweroff-olimex-a20.patch @@ -0,0 +1,36 @@ +diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig +index f817b8c..ee7b429 +--- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig ++++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig +@@ -27,7 +27,6 @@ CONFIG_DFU_RAM=y + CONFIG_ETH_DESIGNWARE=y + CONFIG_RGMII=y + CONFIG_SUN7I_GMAC=y +-CONFIG_AXP_ALDO3_VOLT=2800 + CONFIG_AXP_ALDO4_VOLT=2800 + CONFIG_SCSI=y + CONFIG_USB_EHCI_HCD=y +diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig +index 6d7c588..7a85e20 +--- a/configs/A20-OLinuXino-Lime2_defconfig ++++ b/configs/A20-OLinuXino-Lime2_defconfig +@@ -26,7 +26,6 @@ CONFIG_DFU_RAM=y + CONFIG_ETH_DESIGNWARE=y + CONFIG_RGMII=y + CONFIG_SUN7I_GMAC=y +-CONFIG_AXP_ALDO3_VOLT=2800 + CONFIG_AXP_ALDO4_VOLT=2800 + CONFIG_SCSI=y + CONFIG_USB_EHCI_HCD=y +diff --git a/configs/A20-OLinuXino_MICRO_eMMC_defconfig b/configs/A20-OLinuXino_MICRO_eMMC_defconfig +index 046a805..fb966e1 +--- a/configs/A20-OLinuXino_MICRO_eMMC_defconfig ++++ b/configs/A20-OLinuXino_MICRO_eMMC_defconfig +@@ -20,7 +20,6 @@ CONFIG_SPL_I2C_SUPPORT=y + # CONFIG_SPL_EFI_PARTITION is not set + CONFIG_ETH_DESIGNWARE=y + CONFIG_SUN7I_GMAC=y +-CONFIG_AXP_ALDO3_VOLT=2800 + CONFIG_AXP_ALDO4_VOLT=2800 + CONFIG_USB_EHCI_HCD=y + CONFIG_SCSI=y diff --git a/patch/u-boot/u-boot-sunxi-legacy/branch_next/workaround-reboot-is-poweroff-olimex-a20.patch b/patch/u-boot/u-boot-sunxi-legacy/branch_next/workaround-reboot-is-poweroff-olimex-a20.patch new file mode 100644 index 0000000000..d51534c375 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/branch_next/workaround-reboot-is-poweroff-olimex-a20.patch @@ -0,0 +1,36 @@ +diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig +index f817b8c..ee7b429 +--- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig ++++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig +@@ -27,7 +27,6 @@ CONFIG_DFU_RAM=y + CONFIG_ETH_DESIGNWARE=y + CONFIG_RGMII=y + CONFIG_SUN7I_GMAC=y +-CONFIG_AXP_ALDO3_VOLT=2800 + CONFIG_AXP_ALDO4_VOLT=2800 + CONFIG_SCSI=y + CONFIG_USB_EHCI_HCD=y +diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig +index 6d7c588..7a85e20 +--- a/configs/A20-OLinuXino-Lime2_defconfig ++++ b/configs/A20-OLinuXino-Lime2_defconfig +@@ -26,7 +26,6 @@ CONFIG_DFU_RAM=y + CONFIG_ETH_DESIGNWARE=y + CONFIG_RGMII=y + CONFIG_SUN7I_GMAC=y +-CONFIG_AXP_ALDO3_VOLT=2800 + CONFIG_AXP_ALDO4_VOLT=2800 + CONFIG_SCSI=y + CONFIG_USB_EHCI_HCD=y +diff --git a/configs/A20-OLinuXino_MICRO_eMMC_defconfig b/configs/A20-OLinuXino_MICRO_eMMC_defconfig +index 046a805..fb966e1 +--- a/configs/A20-OLinuXino_MICRO_eMMC_defconfig ++++ b/configs/A20-OLinuXino_MICRO_eMMC_defconfig +@@ -20,7 +20,6 @@ CONFIG_SPL_I2C_SUPPORT=y + # CONFIG_SPL_EFI_PARTITION is not set + CONFIG_ETH_DESIGNWARE=y + CONFIG_SUN7I_GMAC=y +-CONFIG_AXP_ALDO3_VOLT=2800 + CONFIG_AXP_ALDO4_VOLT=2800 + CONFIG_USB_EHCI_HCD=y + CONFIG_SCSI=y diff --git a/patch/u-boot/u-boot-sunxi-legacy/enable-DT-overlays-support.patch b/patch/u-boot/u-boot-sunxi-legacy/enable-DT-overlays-support.patch new file mode 100644 index 0000000000..f4d971b643 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/enable-DT-overlays-support.patch @@ -0,0 +1,13 @@ +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index 0ed36cded..822ebb812 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -578,6 +578,8 @@ config ARCH_SUNXI + select CMD_GPIO + select CMD_MMC if MMC + select CMD_USB if DISTRO_DEFAULTS ++ select OF_LIBFDT ++ select OF_LIBFDT_OVERLAY + select DM + select DM_ETH + select DM_GPIO diff --git a/patch/u-boot/u-boot-sunxi-legacy/enable-autoboot-keyed.patch b/patch/u-boot/u-boot-sunxi-legacy/enable-autoboot-keyed.patch new file mode 100644 index 0000000000..c59629dc8f --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/enable-autoboot-keyed.patch @@ -0,0 +1,34 @@ +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index 53eae8953e..1e931a0eb0 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -696,6 +696,8 @@ config ARCH_SUNXI + select USB_STORAGE if DISTRO_DEFAULTS + select USB_KEYBOARD if DISTRO_DEFAULTS + select USE_TINY_PRINTF ++ imply AUTOBOOT_KEYED ++ imply AUTOBOOT_KEYED_CTRLC + imply CMD_GPT + imply FAT_WRITE + imply PRE_CONSOLE_BUFFER +diff --git a/cmd/Kconfig b/cmd/Kconfig +index d6d130edfa..46ed3a9d76 100644 +--- a/cmd/Kconfig ++++ b/cmd/Kconfig +@@ -51,7 +51,7 @@ config AUTOBOOT_KEYED + config AUTOBOOT_PROMPT + string "Autoboot stop prompt" + depends on AUTOBOOT_KEYED +- default "Autoboot in %d seconds\\n" ++ default "Autoboot in %d seconds, press to stop\\n" + help + This string is displayed before the boot delay selected by + CONFIG_BOOTDELAY starts. If it is not defined there is no +@@ -84,6 +84,7 @@ config AUTOBOOT_DELAY_STR + config AUTOBOOT_STOP_STR + string "Stop autobooting via specific input key / string" + depends on AUTOBOOT_KEYED && !AUTOBOOT_ENCRYPTION ++ default " " + help + This option enables stopping (aborting) of the automatic + boot feature only by issuing a specific input key or diff --git a/patch/u-boot/u-boot-sunxi-legacy/enable-ethernet-orangepiprime.patch b/patch/u-boot/u-boot-sunxi-legacy/enable-ethernet-orangepiprime.patch new file mode 100644 index 0000000000..ec5e573d37 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/enable-ethernet-orangepiprime.patch @@ -0,0 +1,13 @@ +diff --git a/configs/orangepi_prime_defconfig b/configs/orangepi_prime_defconfig +index 27163ce..f19a3d8 100644 +--- a/configs/orangepi_prime_defconfig ++++ b/configs/orangepi_prime_defconfig +@@ -4,6 +4,8 @@ CONFIG_SPL=y + CONFIG_MACH_SUN50I_H5=y + CONFIG_DRAM_CLK=624 + CONFIG_DRAM_ZQ=3881977 ++CONFIG_MACPWR="PD6" ++CONFIG_SPL_SPI_SUNXI=y + CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-prime" + # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set + # CONFIG_CMD_FLASH is not set diff --git a/patch/u-boot/u-boot-sunxi-legacy/enable-r_pio-gpio-access-h3-h5.patch b/patch/u-boot/u-boot-sunxi-legacy/enable-r_pio-gpio-access-h3-h5.patch new file mode 100644 index 0000000000..9d492d80df --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/enable-r_pio-gpio-access-h3-h5.patch @@ -0,0 +1,24 @@ +diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c +index 7ac8360..0484e7a 100644 +--- a/arch/arm/mach-sunxi/board.c ++++ b/arch/arm/mach-sunxi/board.c +@@ -23,6 +23,7 @@ + #include + #include + #include ++#include + + #include + +@@ -65,6 +66,11 @@ struct mm_region *mem_map = sunxi_mem_map; + + static int gpio_init(void) + { ++#if defined(CONFIG_MACH_SUNXI_H3_H5) ++ /* enable R_PIO GPIO access */ ++ prcm_apb0_enable(PRCM_APB0_GATE_PIO); ++#endif ++ + #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) + #if defined(CONFIG_MACH_SUN4I) || \ + defined(CONFIG_MACH_SUN7I) || \ diff --git a/patch/u-boot/u-boot-sunxi-legacy/fdt-setprop-fix-unaligned-access.patch b/patch/u-boot/u-boot-sunxi-legacy/fdt-setprop-fix-unaligned-access.patch new file mode 100644 index 0000000000..f164f18806 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/fdt-setprop-fix-unaligned-access.patch @@ -0,0 +1,24 @@ +diff --git a/cmd/fdt.c b/cmd/fdt.c +index d7654b2c4f..a71b7713a8 100644 +--- a/cmd/fdt.c ++++ b/cmd/fdt.c +@@ -17,6 +17,7 @@ + #include + #include + #include ++#include + + #define MAX_LEVEL 32 /* how deeply nested we will go */ + #define SCRATCHPAD 1024 /* bytes of scratchpad memory */ +@@ -781,7 +782,10 @@ static int fdt_parse_prop(char * const *newval, int count, char *data, int *len) + cp = newp; + tmp = simple_strtoul(cp, &newp, 0); + if (*cp != '?') +- *(fdt32_t *)data = cpu_to_fdt32(tmp); ++ { ++ tmp = cpu_to_fdt32(tmp); ++ put_unaligned(tmp, (fdt32_t *)data); ++ } + else + newp++; + diff --git a/patch/u-boot/u-boot-sunxi-legacy/fix-usb-phy-probe.patch.disabled b/patch/u-boot/u-boot-sunxi-legacy/fix-usb-phy-probe.patch.disabled new file mode 100644 index 0000000000..85dda51ae6 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/fix-usb-phy-probe.patch.disabled @@ -0,0 +1,102 @@ +diff --git a/arch/arm/include/asm/arch-sunxi/usb_phy.h b/arch/arm/include/asm/arch-sunxi/usb_phy.h +index cef6c98..5670d9b 100644 +--- a/arch/arm/include/asm/arch-sunxi/usb_phy.h ++++ b/arch/arm/include/asm/arch-sunxi/usb_phy.h +@@ -10,8 +10,8 @@ + * SPDX-License-Identifier: GPL-2.0+ + */ + +-int sunxi_usb_phy_probe(void); +-int sunxi_usb_phy_remove(void); ++int sunxi_usb_phy_probe(int index); ++int sunxi_usb_phy_remove(int index); + void sunxi_usb_phy_init(int index); + void sunxi_usb_phy_exit(int index); + void sunxi_usb_phy_power_on(int index); +diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c +index 9bf0b56..405cf99 100644 +--- a/arch/arm/mach-sunxi/usb_phy.c ++++ b/arch/arm/mach-sunxi/usb_phy.c +@@ -329,13 +329,13 @@ int sunxi_usb_phy_id_detect(int index) + return gpio_get_value(phy->gpio_id_det); + } + +-int sunxi_usb_phy_probe(void) ++int sunxi_usb_phy_probe(int i) + { + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_usb_phy *phy; +- int i, ret = 0; ++ int ret = 0; + +- for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) { ++ { + phy = &sunxi_usb_phy[i]; + + phy->gpio_vbus = get_vbus_gpio(i); +@@ -376,15 +376,14 @@ int sunxi_usb_phy_probe(void) + return 0; + } + +-int sunxi_usb_phy_remove(void) ++int sunxi_usb_phy_remove(int i) + { + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_usb_phy *phy; +- int i; + + clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE); + +- for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) { ++ { + phy = &sunxi_usb_phy[i]; + + if (phy->gpio_vbus >= 0) +diff --git a/board/sunxi/board.c b/board/sunxi/board.c +index 70e0143..77f282b 100644 +--- a/board/sunxi/board.c ++++ b/board/sunxi/board.c +@@ -514,6 +514,11 @@ void sunxi_board_init(void) + { + int power_failed = 0; + ++#ifdef CONFIG_MACH_SUN8I_H3 ++ /* turn on power LED (PL10) on H3 boards */ ++ gpio_direction_output(SUNXI_GPL(10), 1); ++#endif ++ + #ifdef CONFIG_SY8106A_POWER + power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT); + #endif +@@ -731,11 +736,6 @@ int misc_init_r(void) + + setup_environment(gd->fdt_blob); + +-#ifndef CONFIG_MACH_SUN9I +- ret = sunxi_usb_phy_probe(); +- if (ret) +- return ret; +-#endif + sunxi_musb_board_init(); + + return 0; +diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c +index 6ecb7c4..6f1463e 100644 +--- a/drivers/usb/host/ehci-sunxi.c ++++ b/drivers/usb/host/ehci-sunxi.c +@@ -60,6 +60,7 @@ static int ehci_usb_probe(struct udevice *dev) + priv->ahb_gate_mask | extra_ahb_gate_mask); + #endif + ++ sunxi_usb_phy_probe(priv->phy_index); + sunxi_usb_phy_init(priv->phy_index); + sunxi_usb_phy_power_on(priv->phy_index); + +@@ -80,6 +81,7 @@ static int ehci_usb_remove(struct udevice *dev) + return ret; + + sunxi_usb_phy_exit(priv->phy_index); ++ sunxi_usb_phy_remove(priv->phy_index); + + #ifdef CONFIG_SUNXI_GEN_SUN6I + clrbits_le32(&ccm->ahb_reset0_cfg, priv->ahb_gate_mask); diff --git a/patch/u-boot/u-boot-sunxi-legacy/fix-usb1-vbus-opiwin.patch b/patch/u-boot/u-boot-sunxi-legacy/fix-usb1-vbus-opiwin.patch new file mode 100644 index 0000000000..5e24d7aeee --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/fix-usb1-vbus-opiwin.patch @@ -0,0 +1,60 @@ +diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig +index a3e278f..39e83f1 100644 +--- a/configs/orangepi_win_defconfig ++++ b/configs/orangepi_win_defconfig +@@ -12,6 +12,9 @@ CONFIG_SPL=y + # CONFIG_CMD_FLASH is not set + # CONFIG_SPL_DOS_PARTITION is not set + # CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_SPL_SPI_FLASH_SUPPORT=y ++CONFIG_USB1_VBUS_PIN="PD7" ++CONFIG_USB_HOST=y + CONFIG_SUN8I_EMAC=y + CONFIG_USB_EHCI_HCD=y + CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y +diff --git a/arch/arm/dts/sun50i-a64-orangepi-win.dts b/arch/arm/dts/sun50i-a64-orangepi-win.dts +index cf76c35..a7d36a5 100644 +--- a/arch/arm/dts/sun50i-a64-orangepi-win.dts ++++ b/arch/arm/dts/sun50i-a64-orangepi-win.dts +@@ -64,6 +64,19 @@ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; ++ ++ reg_usb1_vbus: usb1-vbus { ++ compatible = "regulator-fixed"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&usb1_vbus_pin_opiwin>; ++ regulator-name = "usb1-vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-boot-on; ++ enable-active-high; ++ gpio = <&pio 3 7 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++ }; + }; + + &ehci1 { +@@ -83,6 +96,13 @@ + status = "okay"; + }; + ++&pio { ++ usb1_vbus_pin_opiwin: usb1_vbus_pin@0 { ++ allwinner,pins = "PD7"; ++ allwinner,function = "gpio_out"; ++ }; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; +@@ -90,5 +112,6 @@ + }; + + &usbphy { +- status = "okay"; ++ usb1_vbus-supply = <®_usb1_vbus>; ++ status = "okay"; + }; diff --git a/patch/u-boot/u-boot-sunxi-legacy/h3-Fix-PLL1-setup-to-never-use-dividers.patch b/patch/u-boot/u-boot-sunxi-legacy/h3-Fix-PLL1-setup-to-never-use-dividers.patch new file mode 100644 index 0000000000..60badbd235 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/h3-Fix-PLL1-setup-to-never-use-dividers.patch @@ -0,0 +1,33 @@ +From 7f5071f906f79bdc99d6b4b0ccf0cb280abe740b Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Tue, 20 Dec 2016 11:25:12 +0100 +Subject: [PATCH] sunxi: h3: Fix PLL1 setup to never use dividers + +Kernel would lower the divider on first CLK change and cause the +lock up. +--- + arch/arm/mach-sunxi/clock_sun6i.c | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c +index 50fb302a19..91aa2a0478 100644 +--- a/arch/arm/mach-sunxi/clock_sun6i.c ++++ b/arch/arm/mach-sunxi/clock_sun6i.c +@@ -94,11 +94,10 @@ void clock_set_pll1(unsigned int clk) + int k = 1; + int m = 1; + +- if (clk > 1152000000) { +- k = 2; +- } else if (clk > 768000000) { ++ if (clk >= 1368000000) { + k = 3; +- m = 2; ++ } else if (clk >= 768000000) { ++ k = 2; + } + + /* Switch to 24MHz clock while changing PLL1 */ +-- +2.11.0 + diff --git a/patch/u-boot/u-boot-sunxi-legacy/h3-enable-power-led.patch b/patch/u-boot/u-boot-sunxi-legacy/h3-enable-power-led.patch new file mode 100644 index 0000000000..aec4cccffc --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/h3-enable-power-led.patch @@ -0,0 +1,17 @@ +diff --git a/board/sunxi/board.c b/board/sunxi/board.c +index 3cf3614..89cf7f5 100644 +--- a/board/sunxi/board.c ++++ b/board/sunxi/board.c +@@ -478,6 +478,11 @@ void sunxi_board_init(void) + int power_failed = 0; + unsigned long ramsize; + ++#ifdef CONFIG_MACH_SUN8I_H3 ++ /* turn on power LED (PL10) on H3 boards */ ++ gpio_direction_output(SUNXI_GPL(10), 1); ++#endif ++ + #ifdef CONFIG_SY8106A_POWER + power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT); + #endif + diff --git a/patch/u-boot/u-boot-sunxi-legacy/h3-set-safe-axi_apb-clock-dividers.patch b/patch/u-boot/u-boot-sunxi-legacy/h3-set-safe-axi_apb-clock-dividers.patch new file mode 100644 index 0000000000..128bf50eb9 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/h3-set-safe-axi_apb-clock-dividers.patch @@ -0,0 +1,42 @@ +diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c +index 15272c9..cedddc2 100644 +--- a/arch/arm/mach-sunxi/clock_sun6i.c ++++ b/arch/arm/mach-sunxi/clock_sun6i.c +@@ -117,8 +117,8 @@ void clock_set_pll1(unsigned int clk) + sdelay(200); + + /* Switch CPU to PLL1 */ +- writel(AXI_DIV_3 << AXI_DIV_SHIFT | +- ATB_DIV_2 << ATB_DIV_SHIFT | ++ writel(AXI_DIV_4 << AXI_DIV_SHIFT | ++ ATB_DIV_4 << ATB_DIV_SHIFT | + CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, + &ccm->cpu_axi_cfg); + } +diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +index f2990db..b3a8575 100644 +--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h ++++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +@@ -180,6 +180,7 @@ struct sunxi_ccm_reg { + #define CCM_PLL1_CTRL_N(n) ((((n) - 1) & 0x1f) << 8) + #define CCM_PLL1_CTRL_P(n) (((n) & 0x3) << 16) + #define CCM_PLL1_CTRL_EN (0x1 << 31) ++#define CCM_PLL1_CTRL_LOCK (0x1 << 28) + + #define CCM_PLL3_CTRL_M_SHIFT 0 + #define CCM_PLL3_CTRL_M_MASK (0xf << CCM_PLL3_CTRL_M_SHIFT) +diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c +index cedddc2..3fe9305 100644 +--- a/arch/arm/mach-sunxi/clock_sun6i.c ++++ b/arch/arm/mach-sunxi/clock_sun6i.c +@@ -114,7 +114,9 @@ void clock_set_pll1(unsigned int clk) + writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | + CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) | + CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg); +- sdelay(200); ++ ++ while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_CTRL_LOCK)) ++ ; + + /* Switch CPU to PLL1 */ + writel(AXI_DIV_4 << AXI_DIV_SHIFT | diff --git a/patch/u-boot/u-boot-sunxi-legacy/lower-default-DRAM-freq-A64-H5.patch b/patch/u-boot/u-boot-sunxi-legacy/lower-default-DRAM-freq-A64-H5.patch new file mode 100644 index 0000000000..c107d79288 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/lower-default-DRAM-freq-A64-H5.patch @@ -0,0 +1,13 @@ +diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig +index 2309f59999..716e9c5e26 100644 +--- a/arch/arm/mach-sunxi/Kconfig ++++ b/arch/arm/mach-sunxi/Kconfig +@@ -278,7 +278,7 @@ config DRAM_CLK + default 312 if MACH_SUN6I || MACH_SUN8I + default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \ + MACH_SUN8I_V3S +- default 672 if MACH_SUN50I ++ default 648 if MACH_SUN50I || MACH_SUN50I_H5 + ---help--- + Set the dram clock speed, valid range 240 - 480 (prior to sun9i), + must be a multiple of 24. For the sun9i (A80), the tested values diff --git a/patch/u-boot/u-boot-sunxi-legacy/remove-boot-messages-from-hdmi.patch.disabled b/patch/u-boot/u-boot-sunxi-legacy/remove-boot-messages-from-hdmi.patch.disabled new file mode 100644 index 0000000000..d162f1008c --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/remove-boot-messages-from-hdmi.patch.disabled @@ -0,0 +1,14 @@ +diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h +--- a/include/configs/sunxi-common.h ++++ b/include/configs/sunxi-common.h +@@ -487,8 +487,8 @@ extern int soft_i2c_gpio_scl; + + #ifdef CONFIG_VIDEO + #define CONSOLE_STDOUT_SETTINGS \ +- "stdout=serial,vga\0" \ +- "stderr=serial,vga\0" ++ "stdout=serial\0" \ ++ "stderr=serial\0" + #else + #define CONSOLE_STDOUT_SETTINGS \ + "stdout=serial\0" \ diff --git a/patch/u-boot/u-boot-sunxi-legacy/sun8i-set-machid.patch b/patch/u-boot/u-boot-sunxi-legacy/sun8i-set-machid.patch new file mode 100644 index 0000000000..24a33afa45 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/sun8i-set-machid.patch @@ -0,0 +1,11 @@ +diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h +index a4c3fb69e..47ce2e9e6 100644 +--- a/include/configs/sun8i.h ++++ b/include/configs/sun8i.h +@@ -30,4 +30,6 @@ + */ + #include + ++#define CONFIG_MACH_TYPE (0x1029) ++ + #endif /* __CONFIG_H */ diff --git a/patch/u-boot/u-boot-sunxi-legacy/sunxi-boot-splash.patch b/patch/u-boot/u-boot-sunxi-legacy/sunxi-boot-splash.patch new file mode 100644 index 0000000000..868cac93d4 --- /dev/null +++ b/patch/u-boot/u-boot-sunxi-legacy/sunxi-boot-splash.patch @@ -0,0 +1,62 @@ +diff --git a/cmd/Kconfig b/cmd/Kconfig +index d6d130edfa..92795119ea 100644 +--- a/cmd/Kconfig ++++ b/cmd/Kconfig +@@ -1029,6 +1029,7 @@ menu "Misc commands" + config CMD_BMP + bool "Enable 'bmp' command" + depends on LCD || DM_VIDEO || VIDEO ++ default y + help + This provides a way to obtain information about a BMP-format iamge + and to display it. BMP (which presumably stands for BitMaP) is a +diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h +index 9ed6b9892c..75d5176edf 100644 +--- a/include/config_distro_bootcmd.h ++++ b/include/config_distro_bootcmd.h +@@ -323,6 +323,15 @@ + BOOTENV_SHARED_UBIFS \ + BOOTENV_SHARED_EFI \ + "boot_prefixes=/ /boot/\0" \ ++ "splashpos=m,m\0" \ ++ "splashimage=66000000\0" \ ++ "loadsplash= " \ ++ "for prefix in ${boot_prefixes}; do " \ ++ "if test -e mmc 0 ${prefix}boot.bmp; then " \ ++ "load mmc 0 ${splashimage} ${prefix}boot.bmp; " \ ++ "bmp d ${splashimage}; " \ ++ "fi; " \ ++ "done\0" \ + "boot_scripts=boot.scr.uimg boot.scr\0" \ + "boot_script_dhcp=boot.scr.uimg\0" \ + BOOTENV_BOOT_TARGETS \ +diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h +index 02d7be0849..cbdea20d08 100644 +--- a/include/configs/sunxi-common.h ++++ b/include/configs/sunxi-common.h +@@ -284,6 +284,16 @@ extern int soft_i2c_gpio_scl; + + #endif /* CONFIG_VIDEO */ + ++#if defined CONFIG_VIDEO || defined CONFIG_DM_VIDEO ++#define CONFIG_VIDEO_LOGO ++#define CONFIG_SPLASH_SCREEN ++#define CONFIG_SPLASH_SCREEN_ALIGN ++#define CONFIG_BMP_16BPP ++#define CONFIG_BMP_24BPP ++#define CONFIG_BMP_32BPP ++#define CONFIG_VIDEO_BMP_RLE8 ++#endif ++ + /* Ethernet support */ + #ifdef CONFIG_SUNXI_EMAC + #define CONFIG_PHY_ADDR 1 +@@ -444,7 +454,7 @@ extern int soft_i2c_gpio_scl; + + #ifdef CONFIG_USB_KEYBOARD + #define CONSOLE_STDIN_SETTINGS \ +- "preboot=usb start\0" \ ++ "preboot=run loadsplash; usb start\0" \ + "stdin=serial,usbkbd\0" + #else + #define CONSOLE_STDIN_SETTINGS \