From d04155533ca76e1902cc0733d04952d0d19638e4 Mon Sep 17 00:00:00 2001 From: Jianfeng Liu Date: Wed, 20 Apr 2022 02:28:48 +0800 Subject: [PATCH] add patch to fix rk3568 vop in kernel 5.17.3 (#3699) --- .../rk35xx-5.17/rk3568-fix-vop-clk.patch | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 patch/kernel/archive/rk35xx-5.17/rk3568-fix-vop-clk.patch diff --git a/patch/kernel/archive/rk35xx-5.17/rk3568-fix-vop-clk.patch b/patch/kernel/archive/rk35xx-5.17/rk3568-fix-vop-clk.patch new file mode 100644 index 0000000000..782815c24c --- /dev/null +++ b/patch/kernel/archive/rk35xx-5.17/rk3568-fix-vop-clk.patch @@ -0,0 +1,31 @@ +diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c +index 604a367bc498..63dfbeeeb06d 100644 +--- a/drivers/clk/rockchip/clk-rk3568.c ++++ b/drivers/clk/rockchip/clk-rk3568.c +@@ -71,11 +71,17 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = { + RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0), + RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), + RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0), ++ RK3036_PLL_RATE(297000000, 2, 99, 4, 1, 1, 0), ++ RK3036_PLL_RATE(241500000, 2, 161, 4, 2, 1, 0), + RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), + RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0), + RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0), ++ RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0), ++ RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0), ++ RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0), + RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0), + RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0), ++ RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0), + RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0), + { /* sentinel */ }, + }; +@@ -1562,7 +1568,7 @@ static struct rockchip_clk_branch rk3568_clk_pmu_branches[] __initdata = { + RK3568_PMU_CLKGATE_CON(2), 14, GFLAGS), + GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 0, + RK3568_PMU_CLKGATE_CON(2), 15, GFLAGS), +- MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, 0, ++ MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, CLK_SET_RATE_PARENT, + RK3568_PMU_CLKSEL_CON(8), 7, 1, MFLAGS), + }; +