diff --git a/patch/kernel/sun8i-dev/add-h3-overlays.patch b/patch/kernel/sun8i-dev/add-h3-overlays.patch index faec6caf71..ef20148d42 100644 --- a/patch/kernel/sun8i-dev/add-h3-overlays.patch +++ b/patch/kernel/sun8i-dev/add-h3-overlays.patch @@ -12,7 +12,7 @@ index 01d178a2..bfba239c 100644 +dts-dirs += overlay diff --git a/arch/arm/boot/dts/overlay/Makefile b/arch/arm/boot/dts/overlay/Makefile new file mode 100644 -index 00000000..1764aed8 +index 00000000..c305bf94 --- /dev/null +++ b/arch/arm/boot/dts/overlay/Makefile @@ -0,0 +1,29 @@ @@ -25,8 +25,8 @@ index 00000000..1764aed8 + sun8i-h3-i2c1.dtbo \ + sun8i-h3-i2c2.dtbo \ + sun8i-h3-spi-jedec-nor.dtbo \ -+ sun8i-h3-spi-spidev.dtbo \ + sun8i-h3-spi-mcp2515.dtbo \ ++ sun8i-h3-spi-spidev.dtbo \ + sun8i-h3-uart1.dtbo \ + sun8i-h3-uart2.dtbo \ + sun8i-h3-uart3.dtbo \ @@ -47,10 +47,10 @@ index 00000000..1764aed8 +clean-files := *.dtbo *.scr diff --git a/arch/arm/boot/dts/overlay/README.sun8i-h3-overlays b/arch/arm/boot/dts/overlay/README.sun8i-h3-overlays new file mode 100644 -index 00000000..1bdfdd59 +index 00000000..c4024a05 --- /dev/null +++ b/arch/arm/boot/dts/overlay/README.sun8i-h3-overlays -@@ -0,0 +1,188 @@ +@@ -0,0 +1,202 @@ +This document describes overlays provided in the kernel packages +For generic Armbian overlays documentation please see +https://docs.armbian.com/Hardware_Allwinner_overlays/ @@ -67,7 +67,7 @@ index 00000000..1bdfdd59 +so SPI chip select is always set to 0 + +Using software (GPIO) SPI chip selects is possible, but since -+GPIO pins cannot be changed dynamically dur to u-boot limitation, ++GPIO pins cannot be changed dynamically due to u-boot limitation, +this feature is not used in provided overlays. + +### Provided overlays: @@ -97,25 +97,35 @@ index 00000000..1bdfdd59 + +### cir + -+Activates CIR (Infrared remote) receiver connected to the standard pin (PL11) ++Activates CIR (Infrared remote) receiver ++ ++CIR pin: PL11 + +### i2c0 + -+Activates TWI/I2C bus 0, exposed on pins PA11 and PA12 ++Activates TWI/I2C bus 0 ++ ++I2C0 pins (SCL, SDA): PA11, PA12 + +### i2c1 + -+Activates TWI/I2C bus 1, exposed on pins PA18 and PA19 ++Activates TWI/I2C bus 1 ++ ++I2C1 pins (SCL, SDA): PA18, PA19 + +### i2c2 + -+Activates TWI/I2C bus 2, exposed on pins PE12 and PE13 -+On most board this but is wired to Camera (CSI) socket ++Activates TWI/I2C bus 2 ++ ++I2C2 pins (SCL, SDA): PE12, PE13 ++ ++On most board this bus is wired to Camera (CSI) socket + +### spi-jedec-nor + +Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus +supported by the kernel SPI NOR driver ++ +SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3 +SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13 + @@ -123,7 +133,7 @@ index 00000000..1bdfdd59 + +param_spinor_spi_bus (int) + SPI bus to activate SPI NOR flash support on -+ Default: 0 ++ Required + Supported values: 0, 1 + +param_spinor_max_freq (int) @@ -134,6 +144,7 @@ index 00000000..1bdfdd59 +### spi-mcp2515 + +Activates mcp2515 SPI CAN controller connected to SPI bus ++ +SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3 +SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13 + @@ -141,7 +152,7 @@ index 00000000..1bdfdd59 + +param_mcp2515_spi_bus (int) + SPI bus to activate mcp2515 support on -+ Default: 0 ++ Required + Supported values: 0, 1 + +param_mcp2515_clk_freq (int) @@ -156,8 +167,8 @@ index 00000000..1bdfdd59 + +### spi-spidev + -+Activates SPIdev device node (/dev/spidev0.0 or /dev/spidev1.0) -+for userspace SPI access ++Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access, ++where X is the bus number and Y is the CS number + +SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3 +SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13 @@ -166,7 +177,7 @@ index 00000000..1bdfdd59 + +param_spidev_spi_bus (int) + SPI bus to activate SPIdev support on -+ Default: 0 ++ Required + Supported values: 0, 1 + +param_spidev_max_freq (int) @@ -177,6 +188,7 @@ index 00000000..1bdfdd59 +### uart1 + +Activates serial port 1 (/dev/ttyS1) ++ +UART 1 pins (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9 + +Parameters: @@ -189,6 +201,7 @@ index 00000000..1bdfdd59 +### uart2 + +Activates serial port 2 (/dev/ttyS2) ++ +UART 2 pins (TX, RX, RTS, CTS): PA0, PA1, PA2, PA3 + +Parameters: @@ -201,6 +214,7 @@ index 00000000..1bdfdd59 +### uart3 + +Activates serial port 3 (/dev/ttyS3) ++ +UART 3 pins (TX, RX, RTS, CTS): PA13, PA14, PA15, PA16 + +Parameters: @@ -283,10 +297,10 @@ index 00000000..f611d823 +}; diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-fixup.scr-cmd b/arch/arm/boot/dts/overlay/sun8i-h3-fixup.scr-cmd new file mode 100644 -index 00000000..7d083989 +index 00000000..ceb21b21 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun8i-h3-fixup.scr-cmd -@@ -0,0 +1,113 @@ +@@ -0,0 +1,122 @@ +# overlays fixup script +# implements (or rather substitutes) overlay arguments functionality +# using u-boot scripting, environment variables and "fdt" command @@ -301,24 +315,33 @@ index 00000000..7d083989 +test "${tmp_bank}" = "D" && setenv tmp_bank 3; +test "${tmp_bank}" = "G" && setenv tmp_bank 6' + ++if test "${param_spinor_spi_bus}" = "0"; then ++ fdt set /soc/spi@01c68000 status "okay" ++ fdt set /soc/spi@01c68000/spiflash@0 status "okay" ++fi ++ +if test "${param_spinor_spi_bus}" = "1"; then -+ fdt set /soc/spi@01c68000 status "disabled" + fdt set /soc/spi@01c69000 status "okay" -+ fdt set /soc/spi@01c68000/spiflash@0 status "disabled" + fdt set /soc/spi@01c69000/spiflash@0 status "okay" +fi + ++if test "${param_mcp2515_spi_bus}" = "0"; then ++ fdt set /soc/spi@01c68000 status "okay" ++ fdt set /soc/spi@01c68000/mcp2515@0 status "okay" ++fi ++ +if test "${param_mcp2515_spi_bus}" = "1"; then -+ fdt set /soc/spi@01c68000 status "disabled" + fdt set /soc/spi@01c69000 status "okay" -+ fdt set /soc/spi@01c68000/mcp2515@0 status "disabled" + fdt set /soc/spi@01c69000/mcp2515@0 status "okay" +fi + ++if test "${param_spidev_spi_bus}" = "0"; then ++ fdt set /soc/spi@01c68000 status "okay" ++ fdt set /soc/spi@01c68000/spidev@0 status "okay" ++fi ++ +if test "${param_spidev_spi_bus}" = "1"; then -+ fdt set /soc/spi@01c68000 status "disabled" + fdt set /soc/spi@01c69000 status "okay" -+ fdt set /soc/spi@01c68000/spidev@0 status "disabled" + fdt set /soc/spi@01c69000/spidev@0 status "okay" +fi + @@ -477,10 +500,10 @@ index 00000000..0e1de089 +}; diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-spi-jedec-nor.dts b/arch/arm/boot/dts/overlay/sun8i-h3-spi-jedec-nor.dts new file mode 100644 -index 00000000..93efa936 +index 00000000..4df8a5ee --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun8i-h3-spi-jedec-nor.dts -@@ -0,0 +1,43 @@ +@@ -0,0 +1,41 @@ +/dts-v1/ /plugin/; + +/ { @@ -497,14 +520,13 @@ index 00000000..93efa936 + fragment@1 { + target = <&spi0>; + __overlay__ { -+ status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + spiflash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <1000000>; -+ status = "okay"; ++ status = "disabled"; + }; + }; + }; @@ -512,24 +534,23 @@ index 00000000..93efa936 + fragment@2 { + target = <&spi1>; + __overlay__ { -+ status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + spiflash@0 { + compatible = "jedec,spi-nor"; -+ status = "disabled"; + reg = <0>; + spi-max-frequency = <1000000>; ++ status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-spi-mcp2515.dts b/arch/arm/boot/dts/overlay/sun8i-h3-spi-mcp2515.dts new file mode 100644 -index 00000000..8796019c +index 00000000..f9ae57ab --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun8i-h3-spi-mcp2515.dts -@@ -0,0 +1,79 @@ +@@ -0,0 +1,77 @@ +/dts-v1/ /plugin/; + +#include @@ -550,11 +571,11 @@ index 00000000..8796019c + __overlay__ { + #address-cells = <1>; + #size-cells = <1>; -+ can0_osc_fixed: can0_osc_fixed { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <8000000>; -+ }; ++ can0_osc_fixed: can0_osc_fixed { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <8000000>; ++ }; + }; + }; + @@ -572,19 +593,18 @@ index 00000000..8796019c + fragment@3 { + target = <&spi0>; + __overlay__ { -+ status = "okay"; + #address-cells = <1>; + #size-cells = <0>; -+ mcp2515@0 { -+ reg = <0>; /* Chip Select 0 */ -+ compatible = "microchip,mcp2515"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&can0_pin_irq>; -+ spi-max-frequency = <10000000>; ++ mcp2515@0 { ++ reg = <0>; ++ compatible = "microchip,mcp2515"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&can0_pin_irq>; ++ spi-max-frequency = <10000000>; + interrupt-parent = <&pio>; + interrupts = <0 7 IRQ_TYPE_EDGE_FALLING>; /* PA7 */ + clocks = <&can0_osc_fixed>; -+ status = "okay"; ++ status = "disabled"; + }; + }; + }; @@ -592,15 +612,14 @@ index 00000000..8796019c + fragment@4 { + target = <&spi1>; + __overlay__ { -+ status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; -+ mcp2515@0 { -+ reg = <0>; /* Chip Select 0 */ -+ compatible = "microchip,mcp2515"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&can0_pin_irq>; -+ spi-max-frequency = <10000000>; ++ mcp2515@0 { ++ reg = <0>; ++ compatible = "microchip,mcp2515"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&can0_pin_irq>; ++ spi-max-frequency = <10000000>; + interrupt-parent = <&pio>; + interrupts = <0 7 IRQ_TYPE_EDGE_FALLING>; /* PA7 */ + clocks = <&can0_osc_fixed>; @@ -611,10 +630,10 @@ index 00000000..8796019c +}; diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-spi-spidev.dts b/arch/arm/boot/dts/overlay/sun8i-h3-spi-spidev.dts new file mode 100644 -index 00000000..5eb2e2c9 +index 00000000..e178e6a1 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun8i-h3-spi-spidev.dts -@@ -0,0 +1,43 @@ +@@ -0,0 +1,41 @@ +/dts-v1/ /plugin/; + +/ { @@ -631,12 +650,11 @@ index 00000000..5eb2e2c9 + fragment@1 { + target = <&spi0>; + __overlay__ { -+ status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + spidev@0 { + compatible = "spidev"; -+ status = "okay"; ++ status = "disabled"; + reg = <0>; + spi-max-frequency = <1000000>; + }; @@ -646,7 +664,6 @@ index 00000000..5eb2e2c9 + fragment@2 { + target = <&spi1>; + __overlay__ { -+ status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + spidev@0 { @@ -687,10 +704,10 @@ index 00000000..902e3e5a +}; diff --git a/arch/arm/boot/dts/overlay/sun8i-h3-uart2.dts b/arch/arm/boot/dts/overlay/sun8i-h3-uart2.dts new file mode 100644 -index 00000000..8a910690 +index 00000000..bf35d82c --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun8i-h3-uart2.dts -@@ -0,0 +1,21 @@ +@@ -0,0 +1,31 @@ +/dts-v1/ /plugin/; + +/ { @@ -704,10 +721,20 @@ index 00000000..8a910690 + }; + + fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart2_pins_a_2: uart2@1 { ++ pins = "PI18", "PI19"; ++ function = "uart2"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { + target = <&uart2>; + __overlay__ { + pinctrl-names = "default"; -+ pinctrl-0 = <&uart2_pins>; ++ pinctrl-0 = <&uart2_pins_a_2>; + status = "okay"; + }; + }; diff --git a/patch/kernel/sunxi-next/add-a20-overlays.patch b/patch/kernel/sunxi-next/add-a20-overlays.patch index fad2e5df12..ec3922256f 100644 --- a/patch/kernel/sunxi-next/add-a20-overlays.patch +++ b/patch/kernel/sunxi-next/add-a20-overlays.patch @@ -1,9 +1,21 @@ +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index 01d178a2..bfba239c 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -990,4 +990,7 @@ dtstree := $(srctree)/$(src) + dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts)) + + always := $(dtb-y) ++subdir-y := overlay + clean-files := *.dtb ++ ++dts-dirs += overlay diff --git a/arch/arm/boot/dts/overlay/Makefile b/arch/arm/boot/dts/overlay/Makefile new file mode 100644 -index 00000000..194dddba +index 00000000..945091fd --- /dev/null +++ b/arch/arm/boot/dts/overlay/Makefile -@@ -0,0 +1,29 @@ +@@ -0,0 +1,33 @@ +ifeq ($(CONFIG_OF_CONFIGFS),y) + +dtbo-$(CONFIG_MACH_SUN7I) += \ @@ -13,26 +25,283 @@ index 00000000..194dddba + sun7i-a20-i2c2.dtbo \ + sun7i-a20-i2c3.dtbo \ + sun7i-a20-i2c3-edt-ft5x06.dtbo \ ++ sun7i-a20-i2c4.dtbo \ + sun7i-a20-nand.dtbo \ + sun7i-a20-spdif-out.dtbo \ -+ sun7i-a20-spi0-cs0-spidev.dtbo \ -+ sun7i-a20-spi0-cs1-spidev.dtbo \ -+ sun7i-a20-spi1-a-spidev.dtbo \ -+ sun7i-a20-spi1-b-spidev.dtbo \ -+ sun7i-a20-spi2-a-spidev.dtbo \ -+ sun7i-a20-spi2-b-spidev.dtbo \ -+ sun7i-a20-uart1.dtbo \ ++ sun7i-a20-spi-jedec-nor.dtbo \ ++ sun7i-a20-spi-mcp2515.dtbo \ ++ sun7i-a20-spi-spidev.dtbo \ + sun7i-a20-uart2.dtbo \ + sun7i-a20-uart3.dtbo \ -+ sun7i-a20-w1.dtbo ++ sun7i-a20-uart4.dtbo \ ++ sun7i-a20-uart5.dtbo \ ++ sun7i-a20-uart6.dtbo \ ++ sun7i-a20-uart7.dtbo \ ++ sun7i-a20-w1-gpio.dtbo + -+targets += dtbs dtbs_install -+targets += $(dtbo-y) ++scr-$(CONFIG_MACH_SUN7I) += sun7i-a20-fixup.scr ++ ++dtbotxt-$(CONFIG_MACH_SUN7I) += README.sun7i-a20-overlays ++ ++targets += $(dtbo-y) $(scr-y) $(dtbotxt-y) + +endif + -+always := $(dtbo-y) -+clean-files := *.dtbo ++always := $(dtbo-y) $(scr-y) $(dtbotxt-y) ++clean-files := *.dtbo *.scr +diff --git a/arch/arm/boot/dts/overlay/README.sun7i-a20-overlays b/arch/arm/boot/dts/overlay/README.sun7i-a20-overlays +new file mode 100644 +index 00000000..176345f1 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/README.sun7i-a20-overlays +@@ -0,0 +1,247 @@ ++This document describes overlays provided in the kernel packages ++For generic Armbian overlays documentation please see ++https://docs.armbian.com/Hardware_Allwinner_overlays/ ++ ++### Platform: ++ ++sun7i-a20 (Allwinner A20) ++ ++### Platform details: ++ ++Supported pin banks: PB, PC, PD, PE, PG, PH, PI ++ ++SPI controller 0 have 2 exposed hardware CS, ++other SPI controllers have only one hardware CS ++Reference: A20 Datasheet sections 6.3.5.1, 1.19.2 ++ ++I2C bus 0 is used for the AXP209 PMIC ++ ++### Provided overlays: ++ ++- analog-codec ++- can ++- i2c1 ++- i2c2 ++- i2c3 ++- i2c4 ++- nand ++- spdif-out ++- spi-jedec-nor ++- spi-mcp2515 ++- spi-spidev ++- uart1 ++- uart2 ++- uart3 ++- uart4 ++- uart5 ++- uart6 ++- uart7 ++- w1-gpio ++ ++### Overlay details: ++ ++### analog-codec ++ ++Activates SoC analog codec driver that provides Line Out and Mic In ++functionality ++ ++## can ++ ++Activates SoC CAN controller ++ ++CAN pins (TX, RX): PH20, PH21 ++ ++### i2c1 ++ ++Activates TWI/I2C bus 1 ++ ++I2C1 pins (SCL, SDA): PB18, PB19 ++ ++### i2c2 ++ ++Activates TWI/I2C bus 2 ++ ++I2C2 pins (SCL, SDA): PB20, PB21 ++ ++### i2c3 ++ ++Activates TWI/I2C bus 3 ++ ++I2C3 pins (SCL, SDA): PI0, PI1 ++ ++### i2c4 ++ ++Activates TWI/I2C bus 4 ++ ++I2C4 pins (SCL, SDA): PI2, PI3 ++ ++### nand ++ ++Activates NAND controller ++ ++This overlay should not be used until mainline MLC NAND support ++allows using NAND storage reliably ++ ++### spdif-out ++ ++Activates SPDIF/Toslink audio output ++ ++SPDIF pin: PB13 ++ ++### spi-jedec-nor ++ ++Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus ++supported by the kernel SPI NOR driver ++ ++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 ++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 ++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 ++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 ++ ++Parameters: ++ ++param_spinor_spi_bus (int) ++ SPI bus to activate SPI NOR flash support on ++ Required ++ Supported values: 0, 1, 2 ++ ++param_spi2_bus_pins (char) ++ SPI bus 2 pinmux variant ++ Determines what pins SPI bus 2 is exposed on if SPI 2 is used by any overlay ++ Default: a ++ Supported values: a, b ++ ++param_spinor_max_freq (int) ++ Maximum SPI frequency ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ ++### spi-mcp2515 ++ ++Activates mcp2515 SPI CAN controller connected to SPI bus ++ ++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 ++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 ++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 ++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 ++ ++Parameters: ++ ++param_mcp2515_spi_bus (int) ++ SPI bus to activate mcp2515 support on ++ Required ++ Supported values: 0, 1, 2 ++ ++param_spi2_bus_pins (char) ++ SPI bus 2 pinmux variant ++ Determines what pins SPI bus 2 is exposed on if SPI 2 is used by any overlay ++ Default: a ++ Supported values: a, b ++ ++param_mcp2515_clk_freq (int) ++ Onboard oscillator clock frequency ++ Default: 8000000 ++ Typical values: 8000000, 16000000 ++ ++param_mcp2515_int_pin (pin) ++ Interrupt pin ++ Default: PH15 ++ Selected pin should support interrupts (EINT) ++ ++### spi-spidev ++ ++Activates SPIdev device node (/dev/spidev0.0) for userspace SPI access ++ ++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14 ++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16 ++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19 ++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14 ++ ++Parameters: ++ ++param_spi2_bus_pins (char) ++ SPI bus 2 pinmux variant ++ Determines what pins SPI bus 2 is exposed on if SPI 2 is used by any overlay ++ Default: a ++ Supported values: a, b ++ ++param_spidev_max_freq (int) ++ Maximum SPIdev frequency ++ Default: 1000000 ++ Range: 3000 - 100000000 ++ ++### uart2 ++ ++Activates serial port 2 (/dev/ttyS2) ++ ++UART 2 pins (TX, RX, RTS, CTS): PI18, PI19, PI16, PI17 ++ ++Parameters: ++ ++param_uart2_rtscts (bool) ++ Enable RTS and CTS pins ++ Default: 0 ++ Set to 1 to enable CTS and RTS pins ++ ++### uart3 ++ ++Activates serial port 3 (/dev/ttyS3) ++ ++UART 3 pins (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9 ++ ++Parameters: ++ ++param_uart3_rtscts (bool) ++ Enable RTS and CTS pins ++ Default: 0 ++ Set to 1 to enable CTS and RTS pins ++ ++### uart4 ++ ++Activates serial port 4 (/dev/ttyS4) ++ ++UART 4 pins a (TX, RX): PG10, PG11 ++UART 4 pins b (TX, RX): PH4, PH5 ++ ++Parameters: ++ ++param_uart4_pins (char) ++ Determines what pins UART 4 is exposed on ++ Default: a ++ Supported values: a, b ++ ++### uart 5 ++ ++Activates serial port 5 (/dev/ttyS5) ++ ++UART 5 pins (TX, RX): PH6, PH7 ++ ++### uart 6 ++ ++Activates serial port 6 (/dev/ttyS6) ++ ++UART 6 pins (TX, RX): PI12, PI13 ++ ++### uart 7 ++ ++Activates serial port 7 (/dev/ttyS7) ++ ++UART 7 pins (TX, RX): PI20, PI21 ++ ++### w1-gpio ++ ++Activates 1-Wire GPIO master ++Requires external pull-up resistor on data pin ++ ++Parameters: ++ ++param_w1_pin (pin) ++ Data pin for 1-Wire master ++ Default: PI15 ++ ++param_w1_pin_int_pullup (bool) ++ Enable internal pull-up for the data pin ++ This option should not be used with multiple sensors or long wires - ++ please use external pull-up resistor instead ++ Default: 0 ++ Set to 1 to enable the pull-up diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-analog-codec.dts b/arch/arm/boot/dts/overlay/sun7i-a20-analog-codec.dts new file mode 100644 index 00000000..74bb13d0 @@ -53,10 +322,10 @@ index 00000000..74bb13d0 +}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-can.dts b/arch/arm/boot/dts/overlay/sun7i-a20-can.dts new file mode 100644 -index 00000000..4d2b33af +index 00000000..17601ec1 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-can.dts -@@ -0,0 +1,34 @@ +@@ -0,0 +1,32 @@ +/dts-v1/ /plugin/; + +#include @@ -67,11 +336,9 @@ index 00000000..4d2b33af + fragment@0 { + target = <&pio>; + __overlay__ { -+ can0_pins_a: can0@0 { -+ allwinner,pins = "PH20", "PH21"; -+ allwinner,function = "can"; -+ allwinner,drive = <0>; -+ allwinner,pull = <0>; ++ can_pins: can_pins { ++ pins = "PH20", "PH21"; ++ function = "can"; + }; + }; + }; @@ -85,15 +352,175 @@ index 00000000..4d2b33af + interrupts = ; + clocks = <&apb1_gates 4>; + pinctrl-names = "default"; -+ pinctrl-0 = <&can0_pins_a>; ++ pinctrl-0 = <&can_pins>; + status = "okay"; + }; + }; + }; +}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-fixup.scr-cmd b/arch/arm/boot/dts/overlay/sun7i-a20-fixup.scr-cmd +new file mode 100644 +index 00000000..9ff225a4 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-fixup.scr-cmd +@@ -0,0 +1,154 @@ ++# overlays fixup script ++# implements (or rather substitutes) overlay arguments functionality ++# using u-boot scripting, environment variables and "fdt" command ++ ++# setexpr test_var ${tmp_bank} - A ++# works only for hex numbers (A-F) ++ ++setenv decompose_pin 'setexpr tmp_bank sub "P(B|C|D|E|G|H|I)\\d+" "\\1"; ++setexpr tmp_pin sub "P\\S(\\d+)" "\\1"; ++test "${tmp_bank}" = "B" && setenv tmp_bank 1; ++test "${tmp_bank}" = "C" && setenv tmp_bank 2; ++test "${tmp_bank}" = "D" && setenv tmp_bank 3; ++test "${tmp_bank}" = "E" && setenv tmp_bank 4; ++test "${tmp_bank}" = "G" && setenv tmp_bank 6; ++test "${tmp_bank}" = "H" && setenv tmp_bank 7; ++test "${tmp_bank}" = "I" && setenv tmp_bank 8' ++ ++if test "${param_spinor_spi_bus}" = "0"; then ++ fdt set /soc@01c00000/spi@01c05000 status "okay" ++ fdt set /soc@01c00000/spi@01c05000/spiflash status "okay" ++fi ++ ++if test "${param_spinor_spi_bus}" = "1"; then ++ fdt set /soc@01c00000/spi@01c06000 status "okay" ++ fdt set /soc@01c00000/spi@01c06000/spiflash status "okay" ++fi ++ ++if test "${param_spinor_spi_bus}" = "2"; then ++ fdt set /soc@01c00000/spi@01c17000 status "okay" ++ fdt set /soc@01c00000/spi@01c17000/spiflash status "okay" ++fi ++ ++if test "${param_mcp2515_spi_bus}" = "0"; then ++ fdt set /soc@01c00000/spi@01c05000 status "okay" ++ fdt set /soc@01c00000/spi@01c05000/mcp2515 status "okay" ++fi ++ ++if test "${param_mcp2515_spi_bus}" = "1"; then ++ fdt set /soc@01c00000/spi@01c06000 status "okay" ++ fdt set /soc@01c00000/spi@01c06000/mcp2515 status "okay" ++fi ++ ++if test "${param_mcp2515_spi_bus}" = "2"; then ++ fdt set /soc@01c00000/spi@01c17000 status "okay" ++ fdt set /soc@01c00000/spi@01c17000/mcp2515 status "okay" ++fi ++ ++if test "${param_spidev_spi_bus}" = "0"; then ++ fdt set /soc@01c00000/spi@01c05000 status "okay" ++ fdt set /soc@01c00000/spi@01c05000/spidev status "okay" ++fi ++ ++if test "${param_spidev_spi_bus}" = "1"; then ++ fdt set /soc@01c00000/spi@01c06000 status "okay" ++ fdt set /soc@01c00000/spi@01c06000/spidev status "okay" ++fi ++ ++if test "${param_spidev_spi_bus}" = "2"; then ++ fdt set /soc@01c00000/spi@01c17000 status "okay" ++ fdt set /soc@01c00000/spi@01c17000/spidev status "okay" ++fi ++ ++if test -n "${param_mcp2515_clk_freq}"; then ++ fdt set /clocks/can0_osc_fixed clock-frequency "<${param_mcp2515_clk_freq}>" ++fi ++ ++if test "${param_spi2_bus_pins}" = "b"; then ++ fdt get value tmp_phandle1 /soc@01c00000/pinctrl@01c20800/spi2@1 phandle ++ fdt get value tmp_phandle2 /soc@01c00000/pinctrl@01c20800/spi2_cs0@1 phandle ++ fdt set /soc@01c00000/spi@01c17000 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc@01c00000/spi@01c17000 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi ++ ++if test -n "${param_mcp2515_int_pin}"; then ++ setenv tmp_bank "${param_mcp2515_int_pin}" ++ setenv tmp_pin "${param_mcp2515_int_pin}" ++ run decompose_pin ++ fdt set /soc@01c00000/pinctrl@01c20800/can0_pin_irq pins "${param_mcp2515_int_pin}" ++ if test "${param_mcp2515_spi_bus}" = "0"; then ++ setenv tmp_spi_path "spi@01c05000" ++ fi ++ if test "${param_mcp2515_spi_bus}" = "1"; then ++ setenv tmp_spi_path "spi@01c06000" ++ fi ++ if test "${param_mcp2515_spi_bus}" = "2"; then ++ setenv tmp_spi_path "spi@01c17000" ++ fi ++ fdt set /soc@01c00000/${tmp_spi_path}/mcp2515 interrupts "<${tmp_bank} ${tmp_pin} 0x2>" ++ env delete tmp_pin tmp_bank tmp_spi_path ++fi ++ ++if test -n "${param_spidev_max_freq}"; then ++ if test "${param_spidev_spi_bus}" = "0"; then ++ setenv tmp_spi_path "spi@01c05000" ++ fi ++ if test "${param_spidev_spi_bus}" = "1"; then ++ setenv tmp_spi_path "spi@01c06000" ++ fi ++ if test "${param_spidev_spi_bus}" = "2"; then ++ setenv tmp_spi_path "spi@01c17000" ++ fi ++ fdt set /soc@01c00000/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>" ++ env delete tmp_spi_path ++fi ++ ++if test -n "${param_spinor_max_freq}"; then ++ if test "${param_spinor_spi_bus}" = "0"; then ++ setenv tmp_spi_path "spi@01c05000" ++ fi ++ if test "${param_spinor_spi_bus}" = "1"; then ++ setenv tmp_spi_path "spi@01c06000" ++ fi ++ if test "${param_spinor_spi_bus}" = "2"; then ++ setenv tmp_spi_path "spi@01c17000" ++ fi ++ fdt set /soc@01c00000/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>" ++ env delete tmp_spi_path ++fi ++ ++if test -n "${param_w1_pin}"; then ++ setenv tmp_bank "${param_w1_pin}" ++ setenv tmp_pin "${param_w1_pin}" ++ run decompose_pin ++ fdt set /soc@01c00000/pinctrl@01c20800/w1_pins pins "${param_w1_pin}" ++ fdt get value tmp_phandle /soc@01c00000/pinctrl@01c20800 phandle ++ fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>" ++ env delete tmp_pin tmp_bank tmp_phandle ++fi ++ ++if test "${param_w1_pin_int_pullup}" = "1"; then ++ fdt set /soc@01c00000/pinctrl@01c20800/w1_pins bias-pull-up ++fi ++ ++if test "${param_uart2_rtscts}" = "1"; then ++ fdt get value tmp_phandle /soc@01c00000/pinctrl@01c20800/uart2@0 phandle ++ fdt set /soc@01c00000/serial@01c28800 pinctrl-0 "<${tmp_phandle}>" ++ env delete tmp_phandle ++fi ++ ++if test "${param_uart3_rtscts}" = "1"; then ++ fdt get value tmp_phandle1 /soc@01c00000/pinctrl@01c20800/uart3 phandle ++ fdt get value tmp_phandle2 /soc@01c00000/pinctrl@01c20800/uart3_rts_cts phandle ++ fdt set /soc@01c00000/serial@01c28c00 pinctrl-names "default" "default" ++ fdt set /soc@01c00000/serial@01c28c00 pinctrl-0 "<${tmp_phandle1}>" ++ fdt set /soc@01c00000/serial@01c28c00 pinctrl-1 "<${tmp_phandle2}>" ++ env delete tmp_phandle1 tmp_phandle2 ++fi ++ ++if test "${param_uart4_pins}" = "b"; then ++ fdt get value tmp_phandle /soc@01c00000/pinctrl@01c20800/uart4@1 phandle ++ fdt set /soc@01c00000/serial@01c29000 pinctrl-0 "<${tmp_phandle}>" ++ env delete tmp_phandle ++fi diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c1.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c1.dts new file mode 100644 -index 00000000..1a5dc776 +index 00000000..4c551399 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c1.dts @@ -0,0 +1,21 @@ @@ -105,10 +532,10 @@ index 00000000..1a5dc776 + fragment@0 { + target-path = "/aliases"; + __overlay__ { -+ /* Path to the i2c1 controller node */ + i2c1 = "/soc@01c00000/i2c@01c2b000"; + }; + }; ++ + fragment@1 { + target = <&i2c1>; + __overlay__ { @@ -120,7 +547,7 @@ index 00000000..1a5dc776 +}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c2.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c2.dts new file mode 100644 -index 00000000..3f94c827 +index 00000000..db4478fb --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c2.dts @@ -0,0 +1,21 @@ @@ -132,10 +559,10 @@ index 00000000..3f94c827 + fragment@0 { + target-path = "/aliases"; + __overlay__ { -+ /* Path to the i2c2 controller node */ + i2c2 = "/soc@01c00000/i2c@01c2b400"; + }; + }; ++ + fragment@1 { + target = <&i2c2>; + __overlay__ { @@ -147,10 +574,10 @@ index 00000000..3f94c827 +}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c3-edt-ft5x06.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c3-edt-ft5x06.dts new file mode 100644 -index 00000000..3ff36cd0 +index 00000000..e3f13e7b --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c3-edt-ft5x06.dts -@@ -0,0 +1,43 @@ +@@ -0,0 +1,41 @@ +/dts-v1/ /plugin/; + +#include @@ -162,11 +589,9 @@ index 00000000..3ff36cd0 + fragment@0 { + target = <&pio>; + __overlay__ { -+ edt_ft5x06_pins: edt_ft5x06_pins@0 { -+ allwinner,pins = "PH7", "PH9"; -+ allwinner,function = "gpio_out"; -+ allwinner,drive = <0>; -+ allwinner,pull = <0>; ++ edt_ft5x06_pins: edt_ft5x06_pins { ++ pins = "PH7", "PH9"; ++ function = "gpio_out"; + }; + }; + }; @@ -196,7 +621,7 @@ index 00000000..3ff36cd0 +}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c3.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c3.dts new file mode 100644 -index 00000000..0236b5ae +index 00000000..a04e0264 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c3.dts @@ -0,0 +1,21 @@ @@ -208,10 +633,10 @@ index 00000000..0236b5ae + fragment@0 { + target-path = "/aliases"; + __overlay__ { -+ /* Path to the i2c3 controller node */ + i2c3 = "/soc@01c00000/i2c@01c2b800"; + }; + }; ++ + fragment@1 { + target = <&i2c3>; + __overlay__ { @@ -221,12 +646,49 @@ index 00000000..0236b5ae + }; + }; +}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-i2c4.dts b/arch/arm/boot/dts/overlay/sun7i-a20-i2c4.dts +new file mode 100644 +index 00000000..5f8c313a +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-i2c4.dts +@@ -0,0 +1,31 @@ ++/dts-v1/ /plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ i2c4 = "/soc@01c00000/i2c@01c2c000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ i2c4_pins_a: i2c4@0 { ++ pins = "PI2", "PI3"; ++ function = "i2c4"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c4>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c4_pins_a>; ++ status = "okay"; ++ }; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-nand.dts b/arch/arm/boot/dts/overlay/sun7i-a20-nand.dts new file mode 100644 -index 00000000..fa778acc +index 00000000..dec3a70c --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-nand.dts -@@ -0,0 +1,116 @@ +@@ -0,0 +1,102 @@ +/dts-v1/ /plugin/; + +/ { @@ -235,56 +697,42 @@ index 00000000..fa778acc + fragment@0 { + target = <&pio>; + __overlay__ { -+ nand_pins_a: nand_base0@0 { -+ allwinner,pins = "PC0", "PC1", "PC2", ++ nand_pins_a: nand_pins@0 { ++ pins = "PC0", "PC1", "PC2", + "PC5", "PC8", "PC9", "PC10", + "PC11", "PC12", "PC13", "PC14", + "PC15", "PC16"; -+ allwinner,function = "nand0"; -+ allwinner,drive = <0>; -+ allwinner,pull = <0>; ++ function = "nand0"; + }; + + nand_cs0_pins_a: nand_cs@0 { -+ allwinner,pins = "PC4"; -+ allwinner,function = "nand0"; -+ allwinner,drive = <0>; -+ allwinner,pull = <0>; ++ pins = "PC4"; ++ function = "nand0"; + }; + + nand_cs1_pins_a: nand_cs@1 { -+ allwinner,pins = "PC3"; -+ allwinner,function = "nand0"; -+ allwinner,drive = <0>; -+ allwinner,pull = <0>; ++ pins = "PC3"; ++ function = "nand0"; + }; + + nand_cs2_pins_a: nand_cs@2 { -+ allwinner,pins = "PC17"; -+ allwinner,function = "nand0"; -+ allwinner,drive = <0>; -+ allwinner,pull = <0>; ++ pins = "PC17"; ++ function = "nand0"; + }; + + nand_cs3_pins_a: nand_cs@3 { -+ allwinner,pins = "PC18"; -+ allwinner,function = "nand0"; -+ allwinner,drive = <0>; -+ allwinner,pull = <0>; ++ pins = "PC18"; ++ function = "nand0"; + }; + + nand_rb0_pins_a: nand_rb@0 { -+ allwinner,pins = "PC6"; -+ allwinner,function = "nand0"; -+ allwinner,drive = <0>; -+ allwinner,pull = <0>; ++ pins = "PC6"; ++ function = "nand0"; + }; + + nand_rb1_pins_a: nand_rb@1 { -+ allwinner,pins = "PC7"; -+ allwinner,function = "nand0"; -+ allwinner,drive = <0>; -+ allwinner,pull = <0>; ++ pins = "PC7"; ++ function = "nand0"; + }; + }; + }; @@ -386,12 +834,12 @@ index 00000000..0463f43c + }; + }; +}; -diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi0-cs0-spidev.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi0-cs0-spidev.dts +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi-jedec-nor.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi-jedec-nor.dts new file mode 100644 -index 00000000..926d6325 +index 00000000..e8d2e17d --- /dev/null -+++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi0-cs0-spidev.dts -@@ -0,0 +1,29 @@ ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi-jedec-nor.dts +@@ -0,0 +1,67 @@ +/dts-v1/ /plugin/; + +/ { @@ -400,138 +848,182 @@ index 00000000..926d6325 + fragment@0 { + target-path = "/aliases"; + __overlay__ { -+ /* Path to the SPI controller nodes */ -+ spi0 = "/soc@01c00000/spi@01c05000"; ++ spi0 = "/soc/spi@01c05000"; ++ spi1 = "/soc/spi@01c06000"; ++ spi2 = "/soc/spi@01c17000"; + }; + }; ++ + fragment@1 { + target = <&spi0>; + __overlay__ { ++ status = "okay"; ++ pinctrl-names = "default", "default"; ++ pinctrl-0 = <&spi0_pins_a>; ++ pinctrl-1 = <&spi0_cs0_pins_a>; + #address-cells = <1>; + #size-cells = <0>; ++ spiflash { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi1>; ++ __overlay__ { ++ status = "disabled"; + pinctrl-names = "default"; -+ /* "PI11" "PI12" "PI13", "PI10" */ -+ pinctrl-0 = <&spi0_pins_a>, <&spi0_cs0_pins_a>; -+ status = "okay"; -+ spidev@0 { -+ compatible = "spidev"; ++ pinctrl-0 = <&spi1_pins_a>, <&spi1_cs0_pins_a>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spiflash { ++ compatible = "jedec,spi-nor"; ++ status = "disabled"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; -+}; -diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi0-cs1-spidev.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi0-cs1-spidev.dts -new file mode 100644 -index 00000000..4258672a ---- /dev/null -+++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi0-cs1-spidev.dts -@@ -0,0 +1,29 @@ -+/dts-v1/ /plugin/; + -+/ { -+ compatible = "allwinner,sun7i-a20"; -+ -+ fragment@0 { -+ target-path = "/aliases"; -+ __overlay__ { -+ /* Path to the SPI controller nodes */ -+ spi0 = "/soc@01c00000/spi@01c05000"; -+ }; -+ }; -+ fragment@1 { -+ target = <&spi0>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ /* "PI11" "PI12" "PI13", "PI14" */ -+ pinctrl-0 = <&spi0_pins_a>, <&spi0_cs1_pins_a>; -+ status = "okay"; -+ spidev@1 { -+ compatible = "spidev"; -+ reg = <1>; -+ spi-max-frequency = <1000000>; -+ }; -+ }; -+ }; -+}; -diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi1-a-spidev.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi1-a-spidev.dts -new file mode 100644 -index 00000000..9034b747 ---- /dev/null -+++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi1-a-spidev.dts -@@ -0,0 +1,29 @@ -+/dts-v1/ /plugin/; -+ -+/ { -+ compatible = "allwinner,sun7i-a20"; -+ -+ fragment@0 { -+ target-path = "/aliases"; -+ __overlay__ { -+ /* Path to the SPI controller nodes */ -+ spi0 = "/soc@01c00000/spi@01c05000"; -+ }; -+ }; -+ fragment@1 { -+ target = <&spi0>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi2_pins_a>, <&spi2_cs0_pins_a>; -+ -+ status = "okay"; -+ spidev@0 { -+ compatible = "spidev"; -+ reg = <0>; -+ spi-max-frequency = <1000000>; -+ }; -+ }; -+ }; -+}; -diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi1-b-spidev.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi1-b-spidev.dts -new file mode 100644 -index 00000000..a49ca8a3 ---- /dev/null -+++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi1-b-spidev.dts -@@ -0,0 +1,29 @@ -+/dts-v1/ /plugin/; -+ -+/ { -+ compatible = "allwinner,sun7i-a20"; -+ -+ fragment@0 { -+ target-path = "/aliases"; -+ __overlay__ { -+ /* Path to the SPI controller nodes */ -+ spi2 = "/soc@01c00000/spi@01c05000"; -+ }; -+ }; -+ fragment@1 { ++ fragment@3 { + target = <&spi2>; + __overlay__ { ++ status = "disabled"; ++ pinctrl-names = "default", "default"; ++ pinctrl-0 = <&spi2_pins_a>; ++ pinctrl-1 = <&spi2_cs0_pins_a>; + #address-cells = <1>; + #size-cells = <0>; -+ pinctrl-names = "default"; -+ /* "PB15" "PB16" "PB17", "PB14" */ -+ pinctrl-0 = <&spi2_pins_b>, <&spi2_cs0_pins_b>; -+ status = "okay"; -+ spidev@0 { -+ compatible = "spidev"; ++ spiflash { ++ compatible = "jedec,spi-nor"; ++ status = "disabled"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; +}; -diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi2-a-spidev.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi2-a-spidev.dts +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi-mcp2515.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi-mcp2515.dts new file mode 100644 -index 00000000..9034b747 +index 00000000..5ebcf66d --- /dev/null -+++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi2-a-spidev.dts -@@ -0,0 +1,29 @@ ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi-mcp2515.dts +@@ -0,0 +1,105 @@ ++/dts-v1/ /plugin/; ++ ++#include ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ spi1 = "/soc/spi@01c06000"; ++ spi2 = "/soc/spi@01c17000"; ++ spi3 = "/soc/spi@01c1f000"; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/clocks"; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ can0_osc_fixed: can0_osc_fixed { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <8000000>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&pio>; ++ __overlay__ { ++ can0_pin_irq: can0_pin_irq { ++ pins = "PH15"; ++ function = "irq"; ++ bias-pull-up; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&spi0>; ++ __overlay__ { ++ pinctrl-names = "default", "default"; ++ pinctrl-0 = <&spi0_pins_a>; ++ pinctrl-1 = <&spi0_cs0_pins_a>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ mcp2515 { ++ reg = <0>; ++ compatible = "microchip,mcp2515"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&can0_pin_irq>; ++ spi-max-frequency = <10000000>; ++ interrupt-parent = <&pio>; ++ interrupts = <7 15 IRQ_TYPE_EDGE_FALLING>; /* PH15 */ ++ clocks = <&can0_osc_fixed>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@4 { ++ target = <&spi1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins_a>, <&spi1_cs0_pins_a>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ mcp2515 { ++ reg = <0>; ++ compatible = "microchip,mcp2515"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&can0_pin_irq>; ++ spi-max-frequency = <10000000>; ++ interrupt-parent = <&pio>; ++ interrupts = <7 15 IRQ_TYPE_EDGE_FALLING>; /* PH15 */ ++ clocks = <&can0_osc_fixed>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@5 { ++ target = <&spi2>; ++ __overlay__ { ++ pinctrl-names = "default", "default"; ++ pinctrl-0 = <&spi2_pins_a>; ++ pinctrl-1 = <&spi2_cs0_pins_a>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ mcp2515 { ++ reg = <0>; ++ compatible = "microchip,mcp2515"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&can0_pin_irq>; ++ spi-max-frequency = <10000000>; ++ interrupt-parent = <&pio>; ++ interrupts = <7 15 IRQ_TYPE_EDGE_FALLING>; /* PH15 */ ++ clocks = <&can0_osc_fixed>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi-spidev.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi-spidev.dts +new file mode 100644 +index 00000000..4d448661 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi-spidev.dts +@@ -0,0 +1,64 @@ +/dts-v1/ /plugin/; + +/ { @@ -540,94 +1032,68 @@ index 00000000..9034b747 + fragment@0 { + target-path = "/aliases"; + __overlay__ { -+ /* Path to the SPI controller nodes */ -+ spi0 = "/soc@01c00000/spi@01c05000"; ++ spi0 = "/soc/spi@01c05000"; ++ spi1 = "/soc/spi@01c06000"; ++ spi2 = "/soc/spi@01c17000"; + }; + }; ++ + fragment@1 { + target = <&spi0>; + __overlay__ { ++ pinctrl-names = "default", "default"; ++ pinctrl-0 = <&spi0_pins_a>; ++ pinctrl-1 = <&spi0_cs0_pins_a>; + #address-cells = <1>; + #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi2_pins_a>, <&spi2_cs0_pins_a>; -+ -+ status = "okay"; -+ spidev@0 { ++ spidev { + compatible = "spidev"; ++ status = "disabled"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; -+}; -diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-spi2-b-spidev.dts b/arch/arm/boot/dts/overlay/sun7i-a20-spi2-b-spidev.dts -new file mode 100644 -index 00000000..a49ca8a3 ---- /dev/null -+++ b/arch/arm/boot/dts/overlay/sun7i-a20-spi2-b-spidev.dts -@@ -0,0 +1,29 @@ -+/dts-v1/ /plugin/; + -+/ { -+ compatible = "allwinner,sun7i-a20"; -+ -+ fragment@0 { -+ target-path = "/aliases"; ++ fragment@2 { ++ target = <&spi1>; + __overlay__ { -+ /* Path to the SPI controller nodes */ -+ spi2 = "/soc@01c00000/spi@01c05000"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins_a>, <&spi1_cs0_pins_a>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spidev { ++ compatible = "spidev"; ++ status = "disabled"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; ++ }; + }; + }; -+ fragment@1 { ++ ++ fragment@3 { + target = <&spi2>; + __overlay__ { ++ pinctrl-names = "default", "default"; ++ pinctrl-0 = <&spi2_pins_a>; ++ pinctrl-1 = <&spi2_cs0_pins_a>; + #address-cells = <1>; + #size-cells = <0>; -+ pinctrl-names = "default"; -+ /* "PB15" "PB16" "PB17", "PB14" */ -+ pinctrl-0 = <&spi2_pins_b>, <&spi2_cs0_pins_b>; -+ status = "okay"; -+ spidev@0 { ++ spidev { + compatible = "spidev"; ++ status = "disabled"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; +}; -diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart1.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart1.dts -new file mode 100644 -index 00000000..4fd6eede ---- /dev/null -+++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart1.dts -@@ -0,0 +1,20 @@ -+/dts-v1/ /plugin/; -+ -+/ { -+ compatible = "allwinner,sun7i-a20"; -+ -+ fragment@0 { -+ target-path = "/aliases"; -+ __overlay__ { -+ uart1 = "/soc@01c00000/serial@01c28400"; -+ }; -+ }; -+ fragment@1 { -+ target = <&uart1>; -+ __overlay__ { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; -+ status = "okay"; -+ }; -+ }; -+}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart2.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart2.dts new file mode 100644 -index 00000000..56774b07 +index 00000000..e4992768 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart2.dts -@@ -0,0 +1,20 @@ +@@ -0,0 +1,21 @@ +/dts-v1/ /plugin/; + +/ { @@ -639,6 +1105,7 @@ index 00000000..56774b07 + uart2 = "/soc@01c00000/serial@01c28800"; + }; + }; ++ + fragment@1 { + target = <&uart2>; + __overlay__ { @@ -650,10 +1117,10 @@ index 00000000..56774b07 +}; diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart3.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart3.dts new file mode 100644 -index 00000000..b34cf534 +index 00000000..4f932c54 --- /dev/null +++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart3.dts -@@ -0,0 +1,20 @@ +@@ -0,0 +1,31 @@ +/dts-v1/ /plugin/; + +/ { @@ -665,48 +1132,164 @@ index 00000000..b34cf534 + uart3 = "/soc@01c00000/serial@01c28c00"; + }; + }; ++ + fragment@1 { ++ target = <&pio>; ++ __overlay__ { ++ uart3_pins_a_2: uart3@2 { ++ pins = "PG6", "PG7"; ++ function = "uart3"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { + target = <&uart3>; + __overlay__ { + pinctrl-names = "default"; -+ pinctrl-0 = <&uart3_pins>; ++ pinctrl-0 = <&uart3_pins_a_2>; + status = "okay"; + }; + }; +}; -diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-w1.dts b/arch/arm/boot/dts/overlay/sun7i-a20-w1.dts +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart4.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart4.dts new file mode 100644 -index 00000000..0b28406a +index 00000000..e6fd8a3b --- /dev/null -+++ b/arch/arm/boot/dts/overlay/sun7i-a20-w1.dts -@@ -0,0 +1,31 @@ ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart4.dts +@@ -0,0 +1,21 @@ +/dts-v1/ /plugin/; + +/ { + compatible = "allwinner,sun7i-a20"; + + fragment@0 { -+ target-path = "/"; ++ target-path = "/aliases"; + __overlay__ { ++ serial4 = "/soc@01c00000/serial@01c29000"; ++ }; ++ }; + -+ w1: onewire@0 { -+ compatible = "w1-gpio"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&w1_pins>; -+ gpios = <&pio 3 14 0>; /* PD14 */ -+ status = "okay"; ++ fragment@1 { ++ target = <&uart4>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart4_pins_a>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart5.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart5.dts +new file mode 100644 +index 00000000..65675241 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart5.dts +@@ -0,0 +1,21 @@ ++/dts-v1/ /plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial5 = "/soc@01c00000/serial@01c29400"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart5>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart5_pins_a>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart6.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart6.dts +new file mode 100644 +index 00000000..3642fd35 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart6.dts +@@ -0,0 +1,21 @@ ++/dts-v1/ /plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial6 = "/soc@01c00000/serial@01c29800"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart6>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart6_pins_a>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-uart7.dts b/arch/arm/boot/dts/overlay/sun7i-a20-uart7.dts +new file mode 100644 +index 00000000..bd0d1b48 +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-uart7.dts +@@ -0,0 +1,21 @@ ++/dts-v1/ /plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target-path = "/aliases"; ++ __overlay__ { ++ serial7 = "/soc@01c00000/serial@01c29c00"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart7>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart7_pins_a>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlay/sun7i-a20-w1-gpio.dts b/arch/arm/boot/dts/overlay/sun7i-a20-w1-gpio.dts +new file mode 100644 +index 00000000..771af0de +--- /dev/null ++++ b/arch/arm/boot/dts/overlay/sun7i-a20-w1-gpio.dts +@@ -0,0 +1,28 @@ ++/dts-v1/ /plugin/; ++ ++/ { ++ compatible = "allwinner,sun7i-a20"; ++ ++ fragment@0 { ++ target = <&pio>; ++ __overlay__ { ++ w1_pins: w1_pins { ++ pins = "PI15"; ++ function = "gpio_in"; + }; + }; + }; + + fragment@1 { -+ target = <&pio>; ++ target-path = "/"; + __overlay__ { -+ w1_pins: w1_pins@0 { -+ allwinner,pins = "PD14"; -+ allwinner,function = "gpio_in"; -+ allwinner,drive = <0>; -+ allwinner,pull = <0>; ++ w1: onewire@0 { ++ compatible = "w1-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&w1_pins>; ++ gpios = <&pio 8 15 0>; /* PI15 */ ++ status = "okay"; + }; + }; + }; diff --git a/patch/kernel/sunxi-next/add-overlay-compilation-support.patch b/patch/kernel/sunxi-next/add-overlay-compilation-support.patch index 403a1e2c9c..361e9f86a7 100644 --- a/patch/kernel/sunxi-next/add-overlay-compilation-support.patch +++ b/patch/kernel/sunxi-next/add-overlay-compilation-support.patch @@ -2,12 +2,15 @@ diff --git a/arch/arm/Makefile b/arch/arm/Makefile index ab30cc63..cc176797 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile -@@ -339,6 +339,9 @@ $(INSTALL_TARGETS): +@@ -339,6 +339,12 @@ $(INSTALL_TARGETS): %.dtb: | scripts $(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $(boot)/dts/$@ +%.dtbo: | scripts + $(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $(boot)/dts/$@ ++ ++%.scr: | scripts ++ $(Q)$(MAKE) $(build)=$(boot)/dts ARCH=$(ARCH) $(boot)/dts/$@ + PHONY += dtbs dtbs_install @@ -16,72 +19,85 @@ diff --git a/arch/arm/boot/.gitignore b/arch/arm/boot/.gitignore index 3c79f859..eaaeb17e 100644 --- a/arch/arm/boot/.gitignore +++ b/arch/arm/boot/.gitignore -@@ -3,4 +3,4 @@ zImage +@@ -3,4 +3,5 @@ zImage xipImage bootpImage uImage -*.dtb +*.dtb* -diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile -index 01d178a2..48e5a5f5 100644 ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -984,10 +984,16 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ - dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb - dtb-$(CONFIG_ARCH_ASPEED) += aspeed-bmc-opp-palmetto.dtb \ - aspeed-ast2500-evb.dtb -+ -+targets += dtbs dtbs_install -+targets += $(dtb-y) - endif ++*.scr +diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile +index b9a4a934..54e3c38d 100644 +--- a/arch/arm64/Makefile ++++ b/arch/arm64/Makefile +@@ -119,6 +119,12 @@ zinstall install: + %.dtb: scripts + $(Q)$(MAKE) $(build)=$(boot)/dts $(boot)/dts/$@ - dtstree := $(srctree)/$(src) - dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts)) - - always := $(dtb-y) -+subdir-y := overlay - clean-files := *.dtb ++%.dtbo: | scripts ++ $(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $(boot)/dts/$@ + -+dts-dirs += overlay ++%.scr: | scripts ++ $(Q)$(MAKE) $(build)=$(boot)/dts ARCH=$(ARCH) $(boot)/dts/$@ ++ + PHONY += dtbs dtbs_install + + dtbs: prepare scripts +diff --git a/arch/arm64/boot/dts/.gitignore b/arch/arm64/boot/dts/.gitignore +index b60ed208..5d65b54b 100644 +--- a/arch/arm64/boot/dts/.gitignore ++++ b/arch/arm64/boot/dts/.gitignore +@@ -1 +1,2 @@ +-*.dtb ++*.dtb* ++*.scr diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst index a1be75d0..ad8dc1c9 100644 --- a/scripts/Makefile.dtbinst +++ b/scripts/Makefile.dtbinst -@@ -27,6 +27,7 @@ ifeq ("$(dtbinst-root)", "$(obj)") +@@ -27,6 +27,9 @@ ifeq ("$(dtbinst-root)", "$(obj)") endif dtbinst-files := $(dtb-y) +dtboinst-files := $(dtbo-y) ++script-files := $(scr-y) ++readme-files := $(dtbotxt-y) dtbinst-dirs := $(dts-dirs) # Helper targets for Installing DTBs into the boot directory -@@ -35,15 +36,18 @@ quiet_cmd_dtb_install = INSTALL $< +@@ -35,15 +38,24 @@ quiet_cmd_dtb_install = INSTALL $< install-dir = $(patsubst $(dtbinst-root)%,$(INSTALL_DTBS_PATH)%,$(obj)) -$(dtbinst-files) $(dtbinst-dirs): | __dtbs_install_prep -+$(dtbinst-files) $(dtboinst-files) $(dtbinst-dirs): | __dtbs_install_prep ++$(dtbinst-files) $(dtboinst-files) $(readme-files) $(script-files) $(dtbinst-dirs): | __dtbs_install_prep $(dtbinst-files): %.dtb: $(obj)/%.dtb $(call cmd,dtb_install,$(install-dir)) +$(dtboinst-files): %.dtbo: $(obj)/%.dtbo + $(call cmd,dtb_install,$(install-dir)) ++ ++$(script-files): %.scr: $(obj)/%.scr ++ $(call cmd,dtb_install,$(install-dir)) ++ ++$(readme-files): %: $(src)/% ++ $(call cmd,dtb_install,$(install-dir)) + $(dtbinst-dirs): $(Q)$(MAKE) $(dtbinst)=$(obj)/$@ -PHONY += $(dtbinst-files) $(dtbinst-dirs) -__dtbs_install: $(dtbinst-files) $(dtbinst-dirs) -+PHONY += $(dtbinst-files) $(dtboinst-files) $(dtbinst-dirs) -+__dtbs_install: $(dtbinst-files) $(dtboinst-files) $(dtbinst-dirs) ++PHONY += $(dtbinst-files) $(dtboinst-files) $(script-files) $(readme-files) $(dtbinst-dirs) ++__dtbs_install: $(dtbinst-files) $(dtboinst-files) $(script-files) $(readme-files) $(dtbinst-dirs) .PHONY: $(PHONY) diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 0a07f901..5ccd3490 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib -@@ -312,6 +312,17 @@ cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \ +@@ -312,6 +312,23 @@ cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \ $(obj)/%.dtb: $(src)/%.dts FORCE $(call if_changed_dep,dtc) @@ -95,6 +111,12 @@ index 0a07f901..5ccd3490 100644 + +$(obj)/%.dtbo: $(src)/%.dts FORCE + $(call if_changed_dep,dtco) ++ ++quiet_cmd_scr = MKIMAGE $@ ++cmd_scr = mkimage -C none -A $(ARCH) -T script -d $< $@ ++ ++$(obj)/%.scr: $(src)/%.scr-cmd FORCE ++ $(call if_changed,scr) + dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp)