From c91039bc285827f3a6ecbd75bb5b68086548a709 Mon Sep 17 00:00:00 2001 From: ColorfulRhino <131405023+ColorfulRhino@users.noreply.github.com> Date: Sun, 30 Jun 2024 21:00:30 +0200 Subject: [PATCH] SpacemiT: Add SpacemiT Keystone K1 SoC dts files They will be applied on-the-fly by the dt auto-patcher. --- .../spacemit-6.1/dt/k1-x-camera-sdk.dtsi | 187 ++ .../spacemit-6.1/dt/k1-x-camera-sensor.dtsi | 73 + .../archive/spacemit-6.1/dt/k1-x-hdmi.dtsi | 62 + .../archive/spacemit-6.1/dt/k1-x-lcd.dtsi | 116 + .../kernel/archive/spacemit-6.1/dt/k1-x.dtsi | 2536 +++++++++++++++++ .../archive/spacemit-6.1/dt/k1-x_deb1.dts | 1129 ++++++++ .../archive/spacemit-6.1/dt/k1-x_pinctrl.dtsi | 1157 ++++++++ .../spacemit-6.1/dt/lcd_gx09inx101_mipi.dtsi | 157 + 8 files changed, 5417 insertions(+) create mode 100644 patch/kernel/archive/spacemit-6.1/dt/k1-x-camera-sdk.dtsi create mode 100644 patch/kernel/archive/spacemit-6.1/dt/k1-x-camera-sensor.dtsi create mode 100644 patch/kernel/archive/spacemit-6.1/dt/k1-x-hdmi.dtsi create mode 100644 patch/kernel/archive/spacemit-6.1/dt/k1-x-lcd.dtsi create mode 100644 patch/kernel/archive/spacemit-6.1/dt/k1-x.dtsi create mode 100644 patch/kernel/archive/spacemit-6.1/dt/k1-x_deb1.dts create mode 100644 patch/kernel/archive/spacemit-6.1/dt/k1-x_pinctrl.dtsi create mode 100644 patch/kernel/archive/spacemit-6.1/dt/lcd_gx09inx101_mipi.dtsi diff --git a/patch/kernel/archive/spacemit-6.1/dt/k1-x-camera-sdk.dtsi b/patch/kernel/archive/spacemit-6.1/dt/k1-x-camera-sdk.dtsi new file mode 100644 index 0000000000..97b5c24345 --- /dev/null +++ b/patch/kernel/archive/spacemit-6.1/dt/k1-x-camera-sdk.dtsi @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 SPACEMIT Micro Limited + */ + +//#include "k1-x-camera-reserved-mm.dtsi" +#include "k1-x-camera-sensor.dtsi" + +&soc { + plat-cam { + compatible = "spacemit,plat-cam", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + interconnects = <&dram_range1>; + interconnect-names = "dma-mem"; + status = "okay"; + }; + + csiphy0: csiphy@d420a000 { + compatible = "spacemit,csi-dphy"; + cell-index = <0>; + reg = <0x0 0xd420a000 0x0 0x13f>; + reg-names = "csiphy-regs"; + clocks = <&ccu CLK_CCIC1PHY>; + clock-names = "csi_dphy"; + resets = <&reset RESET_CCIC1_PHY>; + reset-names = "cphy_reset"; + interconnects = <&dram_range1>; + interconnect-names = "dma-mem"; + status = "okay"; + }; + + csiphy1: csiphy@d420a800 { + compatible = "spacemit,csi-dphy"; + cell-index = <1>; + reg = <0x0 0xd420a800 0x0 0x13f>; + reg-names = "csiphy-regs"; + clocks = <&ccu CLK_CCIC2PHY>; + clock-names = "csi_dphy"; + resets = <&reset RESET_CCIC2_PHY>; + reset-names = "cphy_reset"; + interconnects = <&dram_range1>; + interconnect-names = "dma-mem"; + status = "okay"; + }; + + csiphy2: csiphy@d4206000 { + compatible = "spacemit,csi-dphy"; + cell-index = <2>; + spacemit,bifmode-enable; + reg = <0x0 0xd4206000 0x0 0x13f>; + reg-names = "csiphy-regs"; + clocks = <&ccu CLK_CCIC3PHY>; + clock-names = "csi_dphy"; + resets = <&reset RESET_CCIC3_PHY>; + reset-names = "cphy_reset"; + interconnects = <&dram_range1>; + interconnect-names = "dma-mem"; + status = "okay"; + }; + + ccic0: ccic@d420a000 { + compatible = "spacemit,k1xccic"; + cell-index = <0>; + spacemit,csiphy = <&csiphy0>; + reg = <0x0 0xd420a000 0x0 0x3ff>; + reg-names = "ccic-regs"; + interrupt-parent = <&intc>; + interrupts = <81>; + interrupt-names = "ipe-irq"; + clocks = <&ccu CLK_CSI>, + <&ccu CLK_CCIC_4X>, + <&ccu CLK_ISP_BUS>; + clock-names = "csi_func", "ccic_func", "isp_axi"; + resets = <&reset RESET_ISP_AHB>, <&reset RESET_CSI>, + <&reset RESET_CCIC_4X>, <&reset RESET_ISP_CI>; + reset-names = "isp_ahb_reset", "csi_reset", + "ccic_4x_reset", "isp_ci_reset"; + interconnects = <&dram_range1>; + interconnect-names = "dma-mem"; + status = "okay"; + }; + + ccic1: ccic@d420a800 { + compatible = "spacemit,k1xccic"; + cell-index = <1>; + spacemit,csiphy = <&csiphy2>; + reg = <0x0 0xd420a800 0x0 0x3ff>; + reg-names = "ccic-regs"; + interrupt-parent = <&intc>; + interrupts = <82>; + interrupt-names = "ipe-irq"; + clocks = <&ccu CLK_CSI>, <&ccu CLK_CCIC_4X>, + <&ccu CLK_ISP_BUS>; + clock-names = "csi_func", "ccic_func", + "isp_axi"; + resets = <&reset RESET_ISP_AHB>, <&reset RESET_CSI>, + <&reset RESET_CCIC_4X>, <&reset RESET_ISP_CI>; + reset-names = "isp_ahb_reset", "csi_reset", + "ccic_4x_reset", "isp_ci_reset"; + interconnects = <&dram_range1>; + interconnect-names = "dma-mem"; + status = "okay"; + }; + + ccic2: ccic@d4206000 { + compatible = "spacemit,k1xccic"; + cell-index = <2>; + spacemit,csiphy = <&csiphy2>; + reg = <0x0 0xd4206000 0x0 0x3ff>; + reg-names = "ccic-regs"; + interrupt-parent = <&intc>; + interrupts = <83>; + interrupt-names = "ipe-irq"; + clocks = <&ccu CLK_CSI>, <&ccu CLK_CCIC_4X>, + <&ccu CLK_ISP_BUS>; + clock-names = "csi_func", "ccic_func", + "isp_axi"; + resets = <&reset RESET_ISP_AHB>, <&reset RESET_CSI>, + <&reset RESET_CCIC_4X>, <&reset RESET_ISP_CI>; + reset-names = "isp_ahb_reset", "csi_reset", + "ccic_4x_reset", "isp_ci_reset"; + interconnects = <&dram_range1>; + interconnect-names = "dma-mem"; + status = "okay"; + }; + + isp: isp@C0230000 { + compatible = "spacemit,k1xisp"; + reg = <0x0 0xC0230000 0x0 0x12700>; + reg-names = "isp"; + interrupt-parent = <&intc>; + interrupts = <79>, <85>; + interrupt-names = "feisp-irq", "feisp-dma-irq"; + clocks = <&ccu CLK_ISP>, + <&ccu CLK_ISP_BUS>, + <&ccu CLK_DPU_MCLK>; + clock-names = "isp_func", "isp_axi", "dpu_mclk"; + resets = <&reset RESET_ISP_AHB>, <&reset RESET_ISP>, + <&reset RESET_ISP_CI>, <&reset RESET_LCD_MCLK>; + reset-names = "isp_ahb_reset", "isp_reset", + "isp_ci_reset", "lcd_mclk_reset"; + interconnects = <&dram_range1>; + interconnect-names = "dma-mem"; + status = "okay"; + }; + + vi: vi@C0230000 { + compatible = "spacemit,k1xvi"; + reg = <0x0 0xc0230000 0x0 0x14000>; + reg-names = "vi"; + interrupt-parent = <&intc>; + interrupts = <79>, <85>; + interrupt-names = "feisp-irq", "feisp-dma-irq"; + clocks = <&ccu CLK_ISP>, <&ccu CLK_ISP_BUS>, + <&ccu CLK_DPU_MCLK>; + clock-names = "isp_func", "isp_axi", + "dpu_mclk"; + resets = <&reset RESET_ISP_AHB>, <&reset RESET_ISP>, + <&reset RESET_ISP_CI>, <&reset RESET_LCD_MCLK>; + reset-names = "isp_ahb_reset", "isp_reset", + "isp_ci_reset", "lcd_mclk_reset"; + interconnects = <&dram_range1>; + interconnect-names = "dma-mem"; + status = "okay"; + }; + + cpp: cpp@C02f0000 { + compatible = "spacemit,k1xcpp"; + reg = <0x0 0xC02f0000 0x0 0x7fff>; + reg-names = "cpp"; + interrupt-parent = <&intc>; + interrupts = <84>; + interrupt-names = "cpp"; + clocks = <&ccu CLK_ISP_CPP>, <&ccu CLK_ISP_BUS>, + <&ccu CLK_DPU_MCLK>; + clock-names = "cpp_func", "isp_axi", + "dpu_mclk"; + resets = <&reset RESET_ISP_AHB>, <&reset RESET_ISP_CPP>, + <&reset RESET_ISP_CI>, <&reset RESET_LCD_MCLK>; + reset-names = "isp_ahb_reset", "isp_cpp_reset", + "isp_ci_reset", "lcd_mclk_reset"; + interconnects = <&dram_range1>; + interconnect-names = "dma-mem"; + status = "okay"; + }; +}; /* soc */ diff --git a/patch/kernel/archive/spacemit-6.1/dt/k1-x-camera-sensor.dtsi b/patch/kernel/archive/spacemit-6.1/dt/k1-x-camera-sensor.dtsi new file mode 100644 index 0000000000..092101702e --- /dev/null +++ b/patch/kernel/archive/spacemit-6.1/dt/k1-x-camera-sensor.dtsi @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 SPACEMIT Micro Limited + */ +#include +#include "k1-x_pinctrl.dtsi" + +&soc { + /* imx315 */ + backsensor: cam_sensor@0 { + cell-index = <0>; + twsi-index = <0>; + dphy-index = <0>; + compatible = "spacemit,cam-sensor"; + clocks = <&ccu CLK_CAMM0>; + clock-names = "cam_mclk0"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_camera0>; + //pwdn-gpios = <&gpio 113 GPIO_ACTIVE_HIGH>; + //reset-gpios = <&gpio 111 GPIO_ACTIVE_HIGH>; + //dphy-entries = <5>; + //dphy-settings = <0x00000001 0xa2848888 0x00001500 0x000000ff 0x1001>; + /* + afvdd28-supply = <&ldo_12>; + avdd28-supply = <&ldo_10>; + dvdd12-supply = <&ldo_20>; + iovdd18-supply = <&ldo_11>; + cam-supply-names = "afvdd28", "avdd28", "dvdd12", "iovdd18"; + */ + interconnects = <&dram_range1>; + interconnect-names = "dma-mem"; + status = "okay"; + }; + + /* gc2375h */ + backsensor_aux: cam_sensor@1 { + cell-index = <1>; + twsi-index = <1>; + dphy-index = <2>; + compatible = "spacemit,cam-sensor"; + clocks = <&ccu CLK_CAMM1>; + clock-names = "cam_mclk1"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_camera1>; + //dphy-entries = <5>; + //dphy-settings = <0x00000001 0xa2848888 0x00001500 0x000000ff 0x1001>; + //pwdn-gpios = <&gpio 114 GPIO_ACTIVE_HIGH>; + //reset-gpios = <&gpio 112 GPIO_ACTIVE_HIGH>; + interconnects = <&dram_range1>; + interconnect-names = "dma-mem"; + status = "okay"; + }; + + /* S5K5E3 */ + frontsensor: cam_sensor@2 { + cell-index = <2>; + twsi-index = <1>; + dphy-index = <2>; + compatible = "spacemit,cam-sensor"; + clocks = <&ccu CLK_CAMM2>; + clock-names = "cam_mclk2"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_camera2>; + //dphy-entries = <5>; + //dphy-settings = <0x00000001 0xa2848888 0x00001500 0x000000ff 0x1001>; + //pwdn-gpios = <&gpio 122 GPIO_ACTIVE_HIGH>; + //reset-gpios = <&gpio 121 GPIO_ACTIVE_HIGH>; + interconnects = <&dram_range1>; + interconnect-names = "dma-mem"; + status = "okay"; + }; +}; diff --git a/patch/kernel/archive/spacemit-6.1/dt/k1-x-hdmi.dtsi b/patch/kernel/archive/spacemit-6.1/dt/k1-x-hdmi.dtsi new file mode 100644 index 0000000000..53bdcef5b4 --- /dev/null +++ b/patch/kernel/archive/spacemit-6.1/dt/k1-x-hdmi.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2023 Spacemit, Inc */ + +&soc { + display-subsystem-hdmi { + compatible = "spacemit,saturn-hdmi"; + reg = <0 0xc0440000 0 0x2A000>; + ports = <&dpu_online2_hdmi>; + interconnects = <&dram_range1>; + interconnect-names = "dma-mem"; + }; + + dpu_online2_hdmi: port@c0440000 { + compatible = "spacemit,dpu-online2"; + interrupt-parent = <&intc>; + interrupts = <139>, <138>; + interrupt-names = "ONLINE_IRQ", "OFFLINE_IRQ"; + interconnects = <&dram_range1>; + interconnect-names = "dma-mem"; + clocks = <&ccu CLK_HDMI>; + clock-names = "hmclk"; + resets = <&reset RESET_HDMI>; + reset-names= "hdmi_reset"; + power-domains = <&power K1X_PMU_HDMI_PWR_DOMAIN>; + pipeline-id = ; + ip = "spacemit-saturn"; + type = ; + clk,pm-runtime,no-sleep; + status = "disabled"; + + dpu_online2_hdmi_out: endpoint@0 { + remote-endpoint = <&hdmi_in>; + }; + + dpu_offline0_hdmi_out: endpoint@1 { + /* remote-endpoint = <&wb0_in>; */ + }; + }; + + hdmi: hdmi@C0400500 { + compatible = "spacemit,hdmi"; + reg = <0 0xC0400500 0 0x200>; + interrupt-parent = <&intc>; + interrupts = <136>; + clocks = <&ccu CLK_HDMI>; + clock-names = "hmclk"; + resets = <&reset RESET_HDMI>; + reset-names= "hdmi_reset"; + power-domains = <&power K1X_PMU_HDMI_PWR_DOMAIN>; + clk,pm-runtime,no-sleep; + status = "disabled"; + + port { + #address-cells = <1>; + #size-cells = <0>; + hdmi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dpu_online2_hdmi_out>; + }; + }; + }; +}; diff --git a/patch/kernel/archive/spacemit-6.1/dt/k1-x-lcd.dtsi b/patch/kernel/archive/spacemit-6.1/dt/k1-x-lcd.dtsi new file mode 100644 index 0000000000..755f032dbe --- /dev/null +++ b/patch/kernel/archive/spacemit-6.1/dt/k1-x-lcd.dtsi @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2023 Spacemit, Inc */ + +&soc { + display-subsystem-dsi { + compatible = "spacemit,saturn-le"; + reg = <0 0xC0340000 0 0x2A000>; + ports = <&dpu_online2_dsi>; + interconnects = <&dram_range1>; + interconnect-names = "dma-mem"; + }; + + dpu_online2_dsi: port@c0340000 { + compatible = "spacemit,dpu-online2"; + interrupt-parent = <&intc>; + interrupts = <90>, <89>; + interrupt-names = "ONLINE_IRQ", "OFFLINE_IRQ"; + interconnects = <&dram_range1>; + interconnect-names = "dma-mem"; + clocks = <&ccu CLK_DPU_PXCLK>, + <&ccu CLK_DPU_MCLK>, + <&ccu CLK_DPU_HCLK>, + <&ccu CLK_DPU_ESC>, + <&ccu CLK_DPU_BIT>; + clock-names = "pxclk", "mclk", "hclk", "escclk", "bitclk"; + resets = <&reset RESET_MIPI>, + <&reset RESET_LCD_MCLK>, + <&reset RESET_LCD>, + <&reset RESET_DSI_ESC>; + reset-names= "dsi_reset", "mclk_reset", "lcd_reset","esc_reset"; + power-domains = <&power K1X_PMU_LCD_PWR_DOMAIN>; + pipeline-id = ; + ip = "spacemit-saturn"; + spacemit-dpu-min-mclk = <40960000>; + type = ; + clk,pm-runtime,no-sleep; + status = "disabled"; + + dpu_online2_dsi_out: endpoint@0 { + remote-endpoint = <&dsi2_in>; + }; + + dpu_offline0_dsi_out: endpoint@1 { + remote-endpoint = <&wb0_in>; + }; + }; + + dsi2: dsi2@d421a800 { + compatible = "spacemit,dsi2-host"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0xD421A800 0 0x200>; + interrupt-parent = <&intc>; + interrupts = <95>; + ip = "synopsys-dhost"; + dev-id = <2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dsi2_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy2_in>; + }; + }; + + port@1 { + reg = <1>; + dsi2_in: endpoint { + remote-endpoint = <&dpu_online2_dsi_out>; + }; + }; + }; + }; + + dphy2: dphy2@d421a800 { + compatible = "spacemit,dsi2-phy"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0xD421A800 0 0x200>; + ip = "spacemit-dphy"; + dev-id = <2>; + status = "okay"; + + port@1 { + reg = <1>; + dphy2_in: endpoint { + remote-endpoint = <&dsi2_out>; + }; + }; + }; + + wb0 { + compatible = "spacemit,wb0"; + dev-id = <2>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + wb0_in: endpoint { + remote-endpoint = <&dpu_offline0_dsi_out>; + }; + }; + }; + }; +}; diff --git a/patch/kernel/archive/spacemit-6.1/dt/k1-x.dtsi b/patch/kernel/archive/spacemit-6.1/dt/k1-x.dtsi new file mode 100644 index 0000000000..d18fef172d --- /dev/null +++ b/patch/kernel/archive/spacemit-6.1/dt/k1-x.dtsi @@ -0,0 +1,2536 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2022 Spacemit, Inc */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + compatible = "spacemit,k1-x"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + serial6 = &uart7; + serial7 = &uart8; + serial8 = &uart9; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + mmc2 = &sdhci2; + ethernet0 = ð0; + ethernet1 = ð1; + }; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <10000000>; + cpu_0: cpu@0 { + compatible = "riscv"; + device_type = "cpu"; + model = "Spacemit(R) X60"; + reg = <0>; + status = "okay"; + riscv,isa = "rv64imafdcv_zicsr_zifencei_zicbom_zicboz_zicbop_zihintpause_zicond_zba_zbb_zbc_zbs_svpbmt_sstc_sscofpmf"; + riscv,cbom-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <512>; + next-level-cache = <&clst0_l2_cache>; + mmu-type = "riscv,sv39"; + clocks = <&ccu CLK_CPU_C0_CORE>; + cpu-idle-states = <&CPU_NONRET> /*, <&CLUSTER_NONRET>, <&TOP_NONRET> */; + operating-points-v2 = <&clst0_core_opp_table>; + #cooling-cells = <2>; + + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu_1: cpu@1 { + device_type = "cpu"; + reg = <1>; + status = "okay"; + compatible = "riscv"; + model = "Spacemit(R) X60"; + riscv,isa = "rv64imafdcv_zicsr_zifencei_zicbom_zicboz_zicbop_zihintpause_zicond_zba_zbb_zbc_zbs_svpbmt_sstc_sscofpmf"; + riscv,cbom-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <512>; + next-level-cache = <&clst0_l2_cache>; + mmu-type = "riscv,sv39"; + clocks = <&ccu CLK_CPU_C0_CORE>; + cpu-idle-states = <&CPU_NONRET> /*, <&CLUSTER_NONRET>, <&TOP_NONRET> */; + operating-points-v2 = <&clst0_core_opp_table>; + #cooling-cells = <2>; + + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu_2: cpu@2 { + device_type = "cpu"; + reg = <2>; + status = "okay"; + compatible = "riscv"; + model = "Spacemit(R) X60"; + riscv,isa = "rv64imafdcv_zicsr_zifencei_zicbom_zicboz_zicbop_zihintpause_zicond_zba_zbb_zbc_zbs_svpbmt_sstc_sscofpmf"; + riscv,cbom-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <512>; + next-level-cache = <&clst0_l2_cache>; + mmu-type = "riscv,sv39"; + clocks = <&ccu CLK_CPU_C0_CORE>; + cpu-idle-states = <&CPU_NONRET> /*, <&CLUSTER_NONRET>, <&TOP_NONRET> */; + operating-points-v2 = <&clst0_core_opp_table>; + #cooling-cells = <2>; + + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu_3: cpu@3 { + device_type = "cpu"; + reg = <3>; + status = "okay"; + compatible = "riscv"; + model = "Spacemit(R) X60"; + riscv,isa = "rv64imafdcv_zicsr_zifencei_zicbom_zicboz_zicbop_zihintpause_zicond_zba_zbb_zbc_zbs_svpbmt_sstc_sscofpmf"; + riscv,cbom-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <512>; + next-level-cache = <&clst0_l2_cache>; + mmu-type = "riscv,sv39"; + clocks = <&ccu CLK_CPU_C0_CORE>; + cpu-idle-states = <&CPU_NONRET> /*, <&CLUSTER_NONRET>, <&TOP_NONRET> */; + operating-points-v2 = <&clst0_core_opp_table>; + #cooling-cells = <2>; + + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu_4: cpu@4 { + device_type = "cpu"; + reg = <4>; + status = "okay"; + compatible = "riscv"; + model = "Spacemit(R) X60"; + riscv,isa = "rv64imafdcv_zicsr_zifencei_zicbom_zicboz_zicbop_zihintpause_zicond_zba_zbb_zbc_zbs_svpbmt_sstc_sscofpmf"; + riscv,cbom-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <512>; + next-level-cache = <&clst1_l2_cache>; + mmu-type = "riscv,sv39"; + clocks = <&ccu CLK_CPU_C1_CORE>; + cpu-idle-states = <&CPU_NONRET> /*, <&CLUSTER_NONRET>, <&TOP_NONRET> */; + operating-points-v2 = <&clst1_core_opp_table>; + #cooling-cells = <2>; + + cpu4_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu_5: cpu@5 { + device_type = "cpu"; + reg = <5>; + status = "okay"; + compatible = "riscv"; + model = "Spacemit(R) X60"; + riscv,isa = "rv64imafdcv_zicsr_zifencei_zicbom_zicboz_zicbop_zihintpause_zicond_zba_zbb_zbc_zbs_svpbmt_sstc_sscofpmf"; + riscv,cbom-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <512>; + next-level-cache = <&clst1_l2_cache>; + mmu-type = "riscv,sv39"; + clocks = <&ccu CLK_CPU_C1_CORE>; + cpu-idle-states = <&CPU_NONRET> /*, <&CLUSTER_NONRET>, <&TOP_NONRET> */; + operating-points-v2 = <&clst1_core_opp_table>; + #cooling-cells = <2>; + + cpu5_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu_6: cpu@6 { + device_type = "cpu"; + reg = <6>; + status = "okay"; + compatible = "riscv"; + model = "Spacemit(R) X60"; + riscv,isa = "rv64imafdcv_zicsr_zifencei_zicbom_zicboz_zicbop_zihintpause_zicond_zba_zbb_zbc_zbs_svpbmt_sstc_sscofpmf"; + riscv,cbom-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <512>; + next-level-cache = <&clst1_l2_cache>; + mmu-type = "riscv,sv39"; + clocks = <&ccu CLK_CPU_C1_CORE>; + cpu-idle-states = <&CPU_NONRET> /*, <&CLUSTER_NONRET>, <&TOP_NONRET> */; + operating-points-v2 = <&clst1_core_opp_table>; + #cooling-cells = <2>; + + cpu6_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu_7: cpu@7 { + device_type = "cpu"; + reg = <7>; + status = "okay"; + compatible = "riscv"; + model = "Spacemit(R) X60"; + riscv,isa = "rv64imafdcv_zicsr_zifencei_zicbom_zicboz_zicbop_zihintpause_zicond_zba_zbb_zbc_zbs_svpbmt_sstc_sscofpmf"; + riscv,cbom-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <32768>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <32768>; + d-cache-sets = <512>; + next-level-cache = <&clst1_l2_cache>; + mmu-type = "riscv,sv39"; + clocks = <&ccu CLK_CPU_C1_CORE>; + cpu-idle-states = <&CPU_NONRET> /*, <&CLUSTER_NONRET>, <&TOP_NONRET> */; + operating-points-v2 = <&clst1_core_opp_table>; + #cooling-cells = <2>; + + cpu7_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + clst0_l2_cache: l2-cache0 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <524288>; + cache-sets = <1024>; + cache-unified; + }; + + clst1_l2_cache: l2-cache1 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <524288>; + cache-sets = <1024>; + cache-unified; + }; + + idle-states { + CPU_NONRET: cpu-nonret { + compatible = "riscv,idle-state"; + idle-state-name = "riscv,cpu-nonret"; + riscv,sbi-suspend-param = <0x90000000>; + local-timer-stop; + entry-latency-us = <200>; + exit-latency-us = <500>; + min-residency-us = <950>; + }; + + CLUSTER_NONRET: cluster-nonret { + compatible = "riscv,idle-state"; + idle-state-name = "riscv,cluster-nonret"; + riscv,sbi-suspend-param = <0x91000000>; + local-timer-stop; + entry-latency-us = <600>; + exit-latency-us = <1100>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + + TOP_NONRET: top-nonret { + compatible = "riscv,idle-state"; + idle-state-name = "riscv,top-nonret"; + riscv,sbi-suspend-param = <0x92000000>; + local-timer-stop; + entry-latency-us = <700>; + exit-latency-us = <1200>; + min-residency-us = <2800>; + wakeup-latency-us = <1600>; + }; + }; + + clst0_core_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + clocks = <&ccu CLK_CPU_C0_ACE>, <&ccu CLK_CPU_C0_TCM>, <&ccu CLK_CCI550>; + clock-names = "ace","tcm", "cci"; + cci-hz = /bits/ 64 <614000000>; + + opp1600000000 { + opp-hz = /bits/ 64 <1600000000>; + tcm-hz = /bits/ 64 <800000000>; + ace-hz = /bits/ 64 <800000000>; + opp-microvolt = <950000>; + clock-latency-ns = <200000>; + }; + + opp1228800000 { + opp-hz = /bits/ 64 <1228800000>; + tcm-hz = /bits/ 64 <614400000>; + ace-hz = /bits/ 64 <614400000>; + opp-microvolt = <950000>; + clock-latency-ns = <200000>; + }; + + opp1000000000 { + opp-hz = /bits/ 64 <1000000000>; + tcm-hz = /bits/ 64 <500000000>; + ace-hz = /bits/ 64 <500000000>; + opp-microvolt = <950000>; + clock-latency-ns = <200000>; + }; + + opp819000000 { + opp-hz = /bits/ 64 <819000000>; + opp-microvolt = <950000>; + tcm-hz = /bits/ 64 <409500000>; + ace-hz = /bits/ 64 <409500000>; + clock-latency-ns = <200000>; + }; + + opp614400000 { + opp-hz = /bits/ 64 <614400000>; + tcm-hz = /bits/ 64 <307200000>; + ace-hz = /bits/ 64 <307200000>; + opp-microvolt = <950000>; + clock-latency-ns = <200000>; + }; + }; + + clst1_core_opp_table: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + clocks = <&ccu CLK_CPU_C1_ACE>, <&ccu CLK_CCI550>; + clock-names = "ace", "cci"; + cci-hz = /bits/ 64 <614000000>; + + opp1600000000 { + opp-hz = /bits/ 64 <1600000000>; + ace-hz = /bits/ 64 <800000000>; + opp-microvolt = <950000>; + clock-latency-ns = <200000>; + }; + + opp1228800000 { + opp-hz = /bits/ 64 <1228800000>; + ace-hz = /bits/ 64 <614400000>; + opp-microvolt = <950000>; + clock-latency-ns = <200000>; + }; + + opp1000000000 { + opp-hz = /bits/ 64 <1000000000>; + ace-hz = /bits/ 64 <500000000>; + opp-microvolt = <950000>; + clock-latency-ns = <200000>; + }; + + opp819000000 { + opp-hz = /bits/ 64 <819000000>; + ace-hz = /bits/ 64 <409500000>; + opp-microvolt = <950000>; + clock-latency-ns = <200000>; + }; + + opp614400000 { + opp-hz = /bits/ 64 <614400000>; + ace-hz = /bits/ 64 <307200000>; + opp-microvolt = <950000>; + clock-latency-ns = <200000>; + }; + }; + }; + + clocks { + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + + vctcxo_24: clock-vctcxo_24 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "vctcxo_24"; + }; + vctcxo_3: clock-vctcxo_3 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <3000000>; + clock-output-names = "vctcxo_3"; + }; + vctcxo_1: clock-vctcxo_1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <1000000>; + clock-output-names = "vctcxo_1"; + }; + pll1_2457p6_vco: clock-pll1_2457p6_vco { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <2457600000>; + clock-output-names = "pll1_2457p6_vco"; + }; + clk_32k: clock-clk32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32000>; + clock-output-names = "clk_32k"; + }; + + pll_clk_cluster0: clock-pll_clk_cluster0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <10000000>; + clock-output-names = "pll_clk_cluster0"; + }; + + pll_clk_cluster1: clock-pll_clk_cluster1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <10000000>; + clock-output-names = "pll_clk_cluster1"; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + area_reserved@80000000 { + /* dram area is 0~2GB, and 4GB~, the 2GB~4GB is io area */ + reg = <0x0 0x80000000 0x0 0x40800000>; + }; + + /* sram area, used for rcpu code & data & heap space */ + rcpu_mem_0: mem@c0800000 { + reg = <0x0 0xc0800000 0x0 0x40000>; + da_base = <0x0>; + no-map; + }; + + area_reserved@c0840000 { + /* dram area is 0~2GB, and 4GB~, the 2GB~4GB is io area */ + reg = <0x0 0xc0840000 0x0 0x3f7c0000>; + no-map; + }; + + /* rcpu's heap */ + rcpu_mem_1: mem@30000000 { + reg = <0x0 0x30000000 0x0 0x200000>; + no-map; + }; + + /* vring0 */ + vdev0vring0: vdev0vring0@30200000 { + reg = <0x0 0x30200000 0x0 0x3000>; + no-map; + }; + + /* vring1 */ + vdev0vring1: vdev0vring1@30203000 { + reg = <0x0 0x30203000 0x0 0x3000>; + no-map; + }; + + /* share memory buffer */ + vdev0buffer: vdev0buffer@30206000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x30206000 0x0 0xf6000>; + no-map; + }; + + /* the resource table */ + rsc_table: rsc_table@302fc000 { + reg = <0x0 0x302fc000 0x0 0x4000>; + no-map; + }; + + /* memory snapshots of rcpu when rcpu poweroff */ + rcpu_mem_snapshots: rcpu_mem_snapshots@30300000 { + reg = <0x0 0x30300000 0x0 0x40000>; + no-map; + }; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* dram mapping for dma/usb/sdh/audio/crypto for ex. */ + dram_range0: dram_range@0 { + compatible = "spacemit-dram-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>; + #interconnect-cells = <0>; + status = "okay"; + }; + + /* dram mapping for vpu/gpu/v2d/jpu for ex. */ + dram_range1: dram_range@1 { + compatible = "spacemit-dram-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, + <0x0 0x80000000 0x1 0x00000000 0x3 0x80000000>; + #interconnect-cells = <0>; + status = "okay"; + }; + + dram_range2: dram_range@2 { + compatible = "spacemit-dram-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, + <0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>; + #interconnect-cells = <0>; + status = "okay"; + }; + + clint0: clint@e4000000 { + compatible = "riscv,clint0"; + interrupts-extended = < + &cpu0_intc 3 &cpu0_intc 7 + &cpu1_intc 3 &cpu1_intc 7 + &cpu2_intc 3 &cpu2_intc 7 + &cpu3_intc 3 &cpu3_intc 7 + &cpu4_intc 3 &cpu4_intc 7 + &cpu5_intc 3 &cpu5_intc 7 + &cpu6_intc 3 &cpu6_intc 7 + &cpu7_intc 3 &cpu7_intc 7 + >; + reg = <0x0 0xE4000000 0x0 0x00010000>; + }; + + ccu: clock-controller@d4050000 { + compatible = "spacemit,k1x-clock"; + reg = <0x0 0xd4050000 0x0 0x209c>, + <0x0 0xd4282800 0x0 0x400>, + <0x0 0xd4015000 0x0 0x1000>, + <0x0 0xd4090000 0x0 0x1000>, + <0x0 0xd4282c00 0x0 0x400>, + <0x0 0xd8440000 0x0 0x98>, + <0x0 0xc0000000 0x0 0x4280>, + <0x0 0xf0610000 0x0 0x20>, + <0x0 0xc0880000 0x0 0x2050>, + <0x0 0xc0888000 0x0 0x30>; + reg-names = "mpmu", "apmu", "apbc", "apbs", "ciu", "dciu", "ddrc", "apbc2", "rcpu", "rcpu2"; + clocks = <&vctcxo_24>, <&vctcxo_3>, <&vctcxo_1>, <&pll1_2457p6_vco>, + <&clk_32k>; + clock-names = "vctcxo_24", "vctcxo_3", "vctcxo_1", "pll1_2457p6_vco", + "clk_32k"; + #clock-cells = <1>; + status = "okay"; + }; + + reset: reset-controller@d4050000 { + compatible = "spacemit,k1x-reset"; + reg = <0x0 0xd4050000 0x0 0x209c>, + <0x0 0xd4282800 0x0 0x400>, + <0x0 0xd4015000 0x0 0x1000>, + <0x0 0xd4090000 0x0 0x1000>, + <0x0 0xd4282c00 0x0 0x400>, + <0x0 0xd8440000 0x0 0x98>, + <0x0 0xc0000000 0x0 0x4280>, + <0x0 0xf0610000 0x0 0x20>, + <0x0 0xc0880000 0x0 0x2050>, + <0x0 0xc0888000 0x0 0x30>; + reg-names = "mpmu", "apmu", "apbc", "apbs", "ciu", "dciu", "ddrc", "apbc2", "rcpu", "rcpu2"; + #reset-cells = <1>; + status = "okay"; + }; + + intc: interrupt-controller@e0000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = < + &cpu0_intc 11 &cpu0_intc 9 + &cpu1_intc 11 &cpu1_intc 9 + &cpu2_intc 11 &cpu2_intc 9 + &cpu3_intc 11 &cpu3_intc 9 + &cpu4_intc 11 &cpu4_intc 9 + &cpu5_intc 11 &cpu5_intc 9 + &cpu6_intc 11 &cpu6_intc 9 + &cpu7_intc 11 &cpu7_intc 9 + >; + reg = <0x0 0xE0000000 0x0 0x04000000>; + reg-names = "control"; + riscv,max-priority = <7>; + riscv,ndev = <159>; + }; + + pinctrl: pinctrl@d401e000 { + compatible = "pinconf-single"; + reg = <0x0 0xd401e000 0x0 0x400>; + #address-cells = <1>; + #size-cells = <1>; + #pinctrl-cells = <2>; + #gpio-range-cells = <3>; + + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xff77>; + + range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; + }; + + pmu: power-management@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mpmu: mpmu@1 { + compatible = "simple-mfd", "spacemit,spacemit-mpmu", "syscon"; + reg = <0x0 0xd4050000 0x0 0x3004>; + }; + + apmu: apmu@2 { + compatible = "simple-mfd", "spacemit,spacemit-apmu", "syscon"; + reg = <0x0 0xd4282800 0x0 0x400>; + }; + + power: power-controller { + compatible = "spacemit,power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + domains = <0x9>; + + power-domain@SPT_PD_BUS { + reg = <0x0>; + pm_qos = <0x7>; + #power-domain-cells = <0>; + }; + + power-domain@SPT_PD_VPU { + reg = <0x1>; + pm_qos = <12>; + reg_pwr_ctrl = <0xa8>; + bit_sleep2 = <3>; + bit_sleep1 = <2>; + bit_isolation = <1>; + bit_pwr_stat = <1>; + bit_hw_pwr_stat = <9>; + #power-domain-cells = <0>; + }; + + power-domain@SPT_PD_GPU { + reg = <0x2>; + pm_qos = <12>; + reg_pwr_ctrl = <0xd0>; + bit_sleep2 = <3>; + bit_sleep1 = <2>; + bit_isolation = <1>; + bit_pwr_stat = <0>; + #power-domain-cells = <0>; + }; + + power-domain@SPT_PD_LCD { + reg = <0x3>; + pm_qos = <12>; + reg_pwr_ctrl = <0x380>; + bit_hw_mode = <4>; + bit_sleep2 = <3>; + bit_sleep1 = <2>; + bit_isolation = <1>; + bit_auto_pwr_on = <0>; + bit_pwr_stat = <4>; + bit_hw_pwr_stat = <12>; + use_hw = <1>; + #power-domain-cells = <0>; + }; + + power-domain@SPT_PD_ISP { + reg = <0x4>; + pm_qos = <12>; + reg_pwr_ctrl = <0x37c>; + bit_hw_mode = <4>; + bit_sleep2 = <3>; + bit_sleep1 = <2>; + bit_isolation = <1>; + bit_auto_pwr_on = <0>; + bit_pwr_stat = <2>; + bit_hw_pwr_stat = <10>; + #power-domain-cells = <0>; + }; + + power-domain@SPT_PD_AUDIO { + reg = <0x5>; + pm_qos = <15>; + reg_pwr_ctrl = <0x378>; + bit_hw_mode = <4>; + bit_sleep2 = <3>; + bit_sleep1 = <2>; + bit_isolation = <1>; + bit_auto_pwr_on = <0>; + bit_pwr_stat = <3>; + bit_hw_pwr_stat = <11>; + use_hw = <1>; + #power-domain-cells = <0>; + }; + + power-domain@SPT_PD_GNSS { + reg = <0x6>; + pm_qos = <15>; + reg_pwr_ctrl = <0x13c>; + bit_hw_mode = <4>; + bit_sleep2 = <3>; + bit_sleep1 = <2>; + bit_isolation = <1>; + bit_auto_pwr_on = <0>; + bit_pwr_stat = <6>; + bit_hw_pwr_stat = <14>; + #power-domain-cells = <0>; + }; + + power-domain@SPT_PD_HDMI { + reg = <0x7>; + pm_qos = <12>; + reg_pwr_ctrl = <0x3f4>; + bit_hw_mode = <4>; + bit_sleep2 = <3>; + bit_sleep1 = <2>; + bit_isolation = <1>; + bit_auto_pwr_on = <0>; + bit_pwr_stat = <7>; + bit_hw_pwr_stat = <15>; + use_hw = <1>; + #power-domain-cells = <0>; + }; + + power-domain@SPT_PD_DUMMY { + reg = <0x8>; + pm_qos = <15>; + #power-domain-cells = <0>; + }; + }; + }; + + uart0: serial@d4017000 { + compatible = "spacemit,pxa-uart"; + reg = <0x0 0xd4017000 0x0 0x100>; + interrupt-parent = <&intc>; + interrupts = <42>; + clocks = <&ccu CLK_UART1>, <&ccu CLK_SLOW_UART>; + clock-names = "func", "gate"; + clk-fpga = <14750000>; + resets = <&reset RESET_UART1>; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + clk,pm-runtime,no-sleep; + cpuidle,pm-runtime,sleep; + dmas = <&pdma0 DMA_UART0_RX 1 + &pdma0 DMA_UART0_TX 1>; + dma-names = "rx", "tx"; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "ok"; + }; + + uart2: uart@d4017100 { + compatible = "spacemit,pxa-uart"; + reg = <0x0 0xd4017100 0x0 0x100>; + interrupt-parent = <&intc>; + interrupts = <44>; + clocks = <&ccu CLK_UART2>, <&ccu CLK_SLOW_UART>; + clock-names = "func", "gate"; + clk-fpga = <14750000>; + resets = <&reset RESET_UART2>; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + clk,pm-runtime,no-sleep; + cpuidle,pm-runtime,sleep; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + uart3: uart@d4017200 { + compatible = "spacemit,pxa-uart"; + reg = <0x0 0xd4017200 0x0 0x100>; + interrupt-parent = <&intc>; + interrupts = <45>; + clocks = <&ccu CLK_UART3>, <&ccu CLK_SLOW_UART>; + clock-names = "func", "gate"; + clk-fpga = <14750000>; + resets = <&reset RESET_UART3>; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + clk,pm-runtime,no-sleep; + cpuidle,pm-runtime,sleep; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + uart4: uart@d4017300 { + compatible = "spacemit,pxa-uart"; + interrupt-parent = <&intc>; + reg = <0x0 0xd4017300 0x0 0x100>; + interrupts = <46>; + clocks = <&ccu CLK_UART4>, <&ccu CLK_SLOW_UART>; + clock-names = "func", "gate"; + clk-fpga = <14750000>; + resets = <&reset RESET_UART4>; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + clk,pm-runtime,no-sleep; + cpuidle,pm-runtime,sleep; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + uart5: uart@d4017400 { + compatible = "spacemit,pxa-uart"; + interrupt-parent = <&intc>; + reg = <0x0 0xd4017400 0x0 0x100>; + interrupts = <47>; + clocks = <&ccu CLK_UART5>, <&ccu CLK_SLOW_UART>; + clock-names = "func", "gate"; + clk-fpga = <14750000>; + resets = <&reset RESET_UART5>; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + clk,pm-runtime,no-sleep; + cpuidle,pm-runtime,sleep; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + uart6: uart@d4017500 { + compatible = "spacemit,pxa-uart"; + interrupt-parent = <&intc>; + reg = <0x0 0xd4017500 0x0 0x100>; + interrupts = <48>; + clocks = <&ccu CLK_UART6>, <&ccu CLK_SLOW_UART>; + clock-names = "func", "gate"; + clk-fpga = <14750000>; + resets = <&reset RESET_UART6>; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + clk,pm-runtime,no-sleep; + cpuidle,pm-runtime,sleep; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + uart7: uart@d4017600 { + compatible = "spacemit,pxa-uart"; + interrupt-parent = <&intc>; + reg = <0x0 0xd4017600 0x0 0x100>; + interrupts = <49>; + clocks = <&ccu CLK_UART7>, <&ccu CLK_SLOW_UART>; + clock-names = "func", "gate"; + clk-fpga = <14750000>; + resets = <&reset RESET_UART7>; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + clk,pm-runtime,no-sleep; + cpuidle,pm-runtime,sleep; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + uart8: uart@d4017700 { + compatible = "spacemit,pxa-uart"; + interrupt-parent = <&intc>; + reg = <0x0 0xd4017700 0x0 0x100>; + interrupts = <50>; + clocks = <&ccu CLK_UART8>, <&ccu CLK_SLOW_UART>; + clock-names = "func", "gate"; + clk-fpga = <14750000>; + resets = <&reset RESET_UART8>; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + clk,pm-runtime,no-sleep; + cpuidle,pm-runtime,sleep; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + uart9: uart@d4017800 { + compatible = "spacemit,pxa-uart"; + interrupt-parent = <&intc>; + reg = <0x0 0xd4017800 0x0 0x100>; + interrupts = <51>; + clocks = <&ccu CLK_UART9>, <&ccu CLK_SLOW_UART>; + clock-names = "func", "gate"; + clk-fpga = <14750000>; + resets = <&reset RESET_UART9>; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + clk,pm-runtime,no-sleep; + cpuidle,pm-runtime,sleep; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + mailbox: mailbox@d4013400 { + compatible = "spacemit,k1-x-mailbox"; + reg = <0x0 0xd4013400 0x0 0x100>; + interrupt-parent = <&intc>; + interrupts = <52>; + #mbox-cells = <1>; + clocks = <&ccu CLK_IPC_AP2AUD>; + clock-names = "core"; + resets = <&reset RESET_IPC_AP2AUD>; + reset-names = "core_reset"; + power-domains = <&power K1X_PMU_DUMMY_PWR_DOMAIN>; + status = "okay"; + }; + + rcpu: rcpu_rproc@0 { + compatible = "spacemit,k1-x-rproc"; + reg = <0 0xc088c000 0 0x1000>, + <0 0xc0880000 0 0x200>; + ddr-remap-base = <0x30000000>; + esos-entry-point = <0x114>; + clocks = <&ccu CLK_AUDIO>; + clock-names = "core"; + resets = <&reset RESET_AUDIO_SYS>; + reset-names = "core_reset"; + firmware-name = "esos.elf"; + power-domains = <&power K1X_PMU_AUD_PWR_DOMAIN>; + status = "okay"; + }; + + pdma0: pdma@d4000000 { + compatible = "spacemit,pdma-1.0"; + reg = <0x0 0xd4000000 0x0 0x4000>; + interrupts = <72>; + interrupt-parent = <&intc>; + clocks = <&ccu CLK_DMA>; + resets = <&reset RESET_DMA>; + #dma-cells= <2>; + #dma-channels = <16>; + max-burst-size = <64>; + reserved-channels = <15 45>; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + clk,pm-runtime,no-sleep; + cpuidle,pm-runtime,sleep; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "ok"; + }; + + hdmi_adma: adma@C0883800 { + compatible = "spacemit,k1x-adma"; + reg = <0x0 0xc0883800 0x0 0x100>, + <0x0 0xc0882050 0x0 0x4>, + <0x0 0xc08d0000 0x0 0x400>; + reg-names = "adma_reg", "ctrl_reg", "buf_addr"; + #dma-cells = <0>; + hdmi-sample; + status = "ok"; + }; + + spi0: spi@d4026000 { + compatible = "spacemit,k1x-spi"; + reg = <0x0 0xd4026000 0x0 0x30>; + k1x,ssp-id = <0>; + k1x,ssp-clock-rate = <26000000>; + dmas = <&pdma0 19 1 + &pdma0 18 1>; + dma-names = "rx", "tx"; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + cpuidle,pm-runtime,sleep; + interrupt-parent = <&intc>; + interrupts = <56>; + clocks = <&ccu CLK_SSPA0>; + resets = <&reset RESET_SSPA0>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + spi1: spi@d4026800 { + compatible = "spacemit,k1x-spi"; + reg = <0x0 0xd4026800 0x0 0x30>; + k1x,ssp-id = <1>; + k1x,ssp-clock-rate = <26000000>; + dmas = <&pdma0 21 1 + &pdma0 20 1>; + dma-names = "rx", "tx"; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + cpuidle,pm-runtime,sleep; + interrupt-parent = <&intc>; + interrupts = <57>; + clocks = <&ccu CLK_SSPA1>; + resets = <&reset RESET_SSPA1>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + spi2: spi@f0613000 { + compatible = "spacemit,k1x-spi"; + reg = <0x0 0xf0613000 0x0 0x30>; + k1x,ssp-id = <2>; + k1x,ssp-clock-rate = <26000000>; + k1x,ssp-disable-dma; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + cpuidle,pm-runtime,sleep; + interrupt-parent = <&intc>; + interrupts = <54>; + clocks = <&ccu CLK_SEC_SSP2>; + resets = <&reset RESET_SEC_SSP2>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + spi3: spi@d401c000 { + compatible = "spacemit,k1x-spi"; + reg = <0x0 0xd401c000 0x0 0x30>; + k1x,ssp-id = <3>; + k1x,ssp-clock-rate = <26000000>; + dmas = <&pdma0 17 1 + &pdma0 16 1>; + dma-names = "rx", "tx"; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + cpuidle,pm-runtime,sleep; + interrupt-parent = <&intc>; + interrupts = <55>; + clocks = <&ccu CLK_SSP3>; + resets = <&reset RESET_SSP3>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + i2c0: i2c@d4010800 { + compatible = "spacemit,k1x-i2c"; + spacemit,adapter-id = <0>; + reg = <0x0 0xd4010800 0x0 0x38>; + /* usually i2c client has only 1 reg field */ + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&intc>; + interrupts = <36>; + clocks = <&ccu CLK_TWSI0>; + resets = <&reset RESET_TWSI0>; + /* + dmas = <&pdma0 DMA_I2C0_RX 1 + &pdma0 DMA_I2C0_TX 1>; + dma-names = "rx", "tx"; + */ + spacemit,dma-disable; + /* spacemit,i2c-fast-mode; */ + /* spacemit,i2c-high-mode; */ + spacemit,i2c-master-code = /bits/ 8 <0x0e>; + spacemit,i2c-clk-rate = <32000000>; + spacemit,i2c-lcr = <0x82c469f>; + spacemit,i2c-wcr = <0x142a>; + /* apb clock: 26MHz or 52MHz */ + spacemit,apb_clock = <52000000>; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + cpuidle,pm-runtime,sleep; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + i2c1: i2c@d4011000 { + compatible = "spacemit,k1x-i2c"; + spacemit,adapter-id = <1>; + reg = <0x0 0xd4011000 0x0 0x38>; + /* usually i2c client has only 1 reg field */ + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&intc>; + interrupts = <37>; + clocks = <&ccu CLK_TWSI1>; + resets = <&reset RESET_TWSI1>; + /* + dmas = <&pdma0 DMA_I2C1_RX 1 + &pdma0 DMA_I2C1_TX 1>; + dma-names = "rx", "tx"; + */ + spacemit,dma-disable; + /* spacemit,i2c-fast-mode; */ + /* spacemit,i2c-high-mode; */ + spacemit,i2c-master-code = /bits/ 8 <0x0e>; + spacemit,i2c-clk-rate = <32000000>; + spacemit,i2c-lcr = <0x82c469f>; + spacemit,i2c-wcr = <0x142a>; + /* apb clock: 26MHz or 52MHz */ + spacemit,apb_clock = <52000000>; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + cpuidle,pm-runtime,sleep; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + i2c2: i2c@d4012000 { + compatible = "spacemit,k1x-i2c"; + spacemit,adapter-id = <2>; + reg = <0x0 0xd4012000 0x0 0x38>; + /* usually i2c client has only 1 reg field */ + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&intc>; + interrupts = <38>; + clocks = <&ccu CLK_TWSI2>; + resets = <&reset RESET_TWSI2>; + /* + dmas = <&pdma0 DMA_I2C2_RX 1 + &pdma0 DMA_I2C2_TX 1>; + dma-names = "rx", "tx"; + */ + spacemit,dma-disable; + /* spacemit,i2c-fast-mode; */ + /* spacemit,i2c-high-mode; */ + spacemit,i2c-master-code = /bits/ 8 <0x0e>; + spacemit,i2c-clk-rate = <32000000>; + spacemit,i2c-lcr = <0x82c469f>; + spacemit,i2c-wcr = <0x142a>; + /* apb clock: 26MHz or 52MHz */ + spacemit,apb_clock = <52000000>; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + cpuidle,pm-runtime,sleep; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + i2c3: i2c@f0614000 { + compatible = "spacemit,k1x-i2c"; + spacemit,adapter-id = <3>; + reg = <0x0 0xf0614000 0x0 0x38>; + /* usually i2c client has only 1 reg field */ + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&intc>; + interrupts = <39>; + spacemit,dma-disable; + /* spacemit,i2c-fast-mode; */ + /* spacemit,i2c-high-mode; */ + spacemit,i2c-master-code = /bits/ 8 <0x0e>; + spacemit,i2c-clk-rate = <32000000>; + spacemit,i2c-lcr = <0x82c469f>; + spacemit,i2c-wcr = <0x142a>; + /* apb clock: 26MHz or 52MHz */ + spacemit,apb_clock = <52000000>; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + cpuidle,pm-runtime,sleep; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + i2c4: i2c@d4012800 { + compatible = "spacemit,k1x-i2c"; + spacemit,adapter-id = <4>; + reg = <0x0 0xd4012800 0x0 0x38>; + /* usually i2c client has only 1 reg field */ + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&intc>; + interrupts = <40>; + clocks = <&ccu CLK_TWSI4>; + resets = <&reset RESET_TWSI4>; + /* + dmas = <&pdma0 DMA_I2C4_RX 1 + &pdma0 DMA_I2C4_TX 1>; + dma-names = "rx", "tx"; + */ + spacemit,dma-disable; + /* spacemit,i2c-fast-mode; */ + /* spacemit,i2c-high-mode; */ + spacemit,i2c-master-code = /bits/ 8 <0x0e>; + spacemit,i2c-clk-rate = <32000000>; + spacemit,i2c-lcr = <0x82c469f>; + spacemit,i2c-wcr = <0x142a>; + /* apb clock: 26MHz or 52MHz */ + spacemit,apb_clock = <52000000>; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + cpuidle,pm-runtime,sleep; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + i2c5: i2c@d4013800 { + compatible = "spacemit,k1x-i2c"; + spacemit,adapter-id = <5>; + reg = <0x0 0xd4013800 0x0 0x38>; + /* usually i2c client has only 1 reg field */ + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&intc>; + interrupts = <41>; + clocks = <&ccu CLK_TWSI5>; + resets = <&reset RESET_TWSI5>; + /* + dmas = <&pdma0 DMA_I2C5_RX 1 + &pdma0 DMA_I2C5_TX 1>; + dma-names = "rx", "tx"; + */ + spacemit,dma-disable; + /* spacemit,i2c-fast-mode; */ + /* spacemit,i2c-high-mode; */ + spacemit,i2c-master-code = /bits/ 8 <0x0e>; + spacemit,i2c-clk-rate = <32000000>; + spacemit,i2c-lcr = <0x82c469f>; + spacemit,i2c-wcr = <0x142a>; + /* apb clock: 26MHz or 52MHz */ + spacemit,apb_clock = <52000000>; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + cpuidle,pm-runtime,sleep; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + i2c6: i2c@d4018800 { + compatible = "spacemit,k1x-i2c"; + spacemit,adapter-id = <6>; + reg = <0x0 0xd4018800 0x0 0x38>; + /* usually i2c client has only 1 reg field */ + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&intc>; + interrupts = <70>; + clocks = <&ccu CLK_TWSI6>; + resets = <&reset RESET_TWSI6>; + /* + dmas = <&pdma0 DMA_I2C6_RX 1 + &pdma0 DMA_I2C6_TX 1>; + dma-names = "rx", "tx"; + */ + spacemit,dma-disable; + /* spacemit,i2c-fast-mode; */ + /* spacemit,i2c-high-mode; */ + spacemit,i2c-master-code = /bits/ 8 <0x0e>; + spacemit,i2c-clk-rate = <32000000>; + spacemit,i2c-lcr = <0x82c469f>; + spacemit,i2c-wcr = <0x142a>; + /* apb clock: 26MHz or 52MHz */ + spacemit,apb_clock = <52000000>; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + cpuidle,pm-runtime,sleep; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + i2c7: i2c@d401d000 { + compatible = "spacemit,k1x-i2c"; + spacemit,adapter-id = <7>; + reg = <0x0 0xd401d000 0x0 0x38>; + /* usually i2c client has only 1 reg field */ + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&intc>; + interrupts = <18>; + clocks = <&ccu CLK_TWSI7>; + resets = <&reset RESET_TWSI7>; + /* + dmas = <&pdma0 DMA_I2C7_RX 1 + &pdma0 DMA_I2C7_TX 1>; + dma-names = "rx", "tx"; + */ + spacemit,dma-disable; + /* spacemit,i2c-fast-mode; */ + /* spacemit,i2c-high-mode; */ + spacemit,i2c-master-code = /bits/ 8 <0x0e>; + spacemit,i2c-clk-rate = <32000000>; + spacemit,i2c-lcr = <0x82c469f>; + spacemit,i2c-wcr = <0x142a>; + /* apb clock: 26MHz or 52MHz */ + spacemit,apb_clock = <52000000>; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + cpuidle,pm-runtime,sleep; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + i2c8: i2c@d401d800 { + compatible = "spacemit,k1x-i2c"; + spacemit,adapter-id = <8>; + reg = <0x0 0xd401d800 0x0 0x38>; + /* usually i2c client has only 1 reg field */ + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&intc>; + interrupts = <19>; + clocks = <&ccu CLK_TWSI8>; + resets = <&reset RESET_TWSI8>; + /* + dmas = <&pdma0 DMA_I2C8_RX 1 + &pdma0 DMA_I2C8_TX 1>; + dma-names = "rx", "tx"; + */ + spacemit,dma-disable; + /* spacemit,i2c-fast-mode; */ + /* spacemit,i2c-high-mode; */ + spacemit,i2c-master-code = /bits/ 8 <0x0e>; + spacemit,i2c-clk-rate = <32000000>; + spacemit,i2c-lcr = <0x82c469f>; + spacemit,i2c-wcr = <0x142a>; + /* apb clock: 26MHz or 52MHz */ + spacemit,apb_clock = <52000000>; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + cpuidle,pm-runtime,sleep; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + pwm0: pwm@d401a000 { + compatible = "spacemit,k1x-pwm"; + reg = <0x0 0xd401a000 0x0 0x10>; + #pwm-cells = <1>; + clocks = <&ccu CLK_PWM0>; + resets = <&reset RESET_PWM0>; + k1x,pwm-disable-fd; + status = "disabled"; + }; + + pwm1: pwm@d401a400 { + compatible = "spacemit,k1x-pwm"; + reg = <0x0 0xd401a400 0x0 0x10>; + #pwm-cells = <1>; + clocks = <&ccu CLK_PWM1>; + resets = <&reset RESET_PWM1>; + k1x,pwm-disable-fd; + status = "disabled"; + }; + + pwm2: pwm@d401a800 { + compatible = "spacemit,k1x-pwm"; + reg = <0x0 0xd401a800 0x0 0x10>; + #pwm-cells = <1>; + clocks = <&ccu CLK_PWM2>; + resets = <&reset RESET_PWM2>; + k1x,pwm-disable-fd; + status = "disabled"; + }; + + pwm3: pwm@d401ac00 { + compatible = "spacemit,k1x-pwm"; + reg = <0x0 0xd401ac00 0x0 0x10>; + #pwm-cells = <1>; + clocks = <&ccu CLK_PWM3>; + resets = <&reset RESET_PWM3>; + k1x,pwm-disable-fd; + status = "disabled"; + }; + + pwm4: pwm@d401b000 { + compatible = "spacemit,k1x-pwm"; + reg = <0x0 0xd401b000 0x0 0x10>; + #pwm-cells = <1>; + clocks = <&ccu CLK_PWM4>; + resets = <&reset RESET_PWM4>; + k1x,pwm-disable-fd; + status = "disabled"; + }; + + pwm5: pwm@d401b400 { + compatible = "spacemit,k1x-pwm"; + reg = <0x0 0xd401b400 0x0 0x10>; + #pwm-cells = <1>; + clocks = <&ccu CLK_PWM5>; + resets = <&reset RESET_PWM5>; + k1x,pwm-disable-fd; + status = "disabled"; + }; + + pwm6: pwm@d401b800 { + compatible = "spacemit,k1x-pwm"; + reg = <0x0 0xd401b800 0x0 0x10>; + #pwm-cells = <1>; + clocks = <&ccu CLK_PWM6>; + resets = <&reset RESET_PWM6>; + k1x,pwm-disable-fd; + status = "disabled"; + }; + + pwm7: pwm@d401bc00 { + compatible = "spacemit,k1x-pwm"; + reg = <0x0 0xd401bc00 0x0 0x10>; + #pwm-cells = <1>; + clocks = <&ccu CLK_PWM7>; + resets = <&reset RESET_PWM7>; + k1x,pwm-disable-fd; + status = "disabled"; + }; + + pwm8: pwm@d4020000 { + compatible = "spacemit,k1x-pwm"; + reg = <0x0 0xd4020000 0x0 0x10>; + #pwm-cells = <1>; + clocks = <&ccu CLK_PWM8>; + resets = <&reset RESET_PWM8>; + k1x,pwm-disable-fd; + status = "disabled"; + }; + + pwm9: pwm@d4020400 { + compatible = "spacemit,k1x-pwm"; + reg = <0x0 0xd4020400 0x0 0x10>; + #pwm-cells = <1>; + clocks = <&ccu CLK_PWM9>; + resets = <&reset RESET_PWM9>; + k1x,pwm-disable-fd; + status = "disabled"; + }; + + pwm10: pwm@d4020800 { + compatible = "spacemit,k1x-pwm"; + reg = <0x0 0xd4020800 0x0 0x10>; + #pwm-cells = <1>; + clocks = <&ccu CLK_PWM10>; + resets = <&reset RESET_PWM10>; + k1x,pwm-disable-fd; + status = "disabled"; + }; + + pwm11: pwm@d4020c00 { + compatible = "spacemit,k1x-pwm"; + reg = <0x0 0xd4020c00 0x0 0x10>; + #pwm-cells = <1>; + clocks = <&ccu CLK_PWM11>; + resets = <&reset RESET_PWM11>; + k1x,pwm-disable-fd; + status = "disabled"; + }; + + pwm12: pwm@d4021000 { + compatible = "spacemit,k1x-pwm"; + reg = <0x0 0xd4021000 0x0 0x10>; + #pwm-cells = <1>; + clocks = <&ccu CLK_PWM12>; + resets = <&reset RESET_PWM12>; + k1x,pwm-disable-fd; + status = "disabled"; + }; + + pwm13: pwm@d4021400 { + compatible = "spacemit,k1x-pwm"; + reg = <0x0 0xd4021400 0x0 0x10>; + #pwm-cells = <1>; + clocks = <&ccu CLK_PWM13>; + resets = <&reset RESET_PWM13>; + k1x,pwm-disable-fd; + status = "disabled"; + }; + + pwm14: pwm@d4021800 { + compatible = "spacemit,k1x-pwm"; + reg = <0x0 0xd4021800 0x0 0x10>; + #pwm-cells = <1>; + clocks = <&ccu CLK_PWM14>; + resets = <&reset RESET_PWM14>; + k1x,pwm-disable-fd; + status = "disabled"; + }; + + pwm15: pwm@d4021c00 { + compatible = "spacemit,k1x-pwm"; + reg = <0x0 0xd4021c00 0x0 0x10>; + #pwm-cells = <1>; + clocks = <&ccu CLK_PWM15>; + resets = <&reset RESET_PWM15>; + k1x,pwm-disable-fd; + status = "disabled"; + }; + + pwm16: pwm@d4022000 { + compatible = "spacemit,k1x-pwm"; + reg = <0x0 0xd4022000 0x0 0x10>; + #pwm-cells = <1>; + clocks = <&ccu CLK_PWM16>; + resets = <&reset RESET_PWM16>; + k1x,pwm-disable-fd; + status = "disabled"; + }; + + pwm17: pwm@d4022400 { + compatible = "spacemit,k1x-pwm"; + reg = <0x0 0xd4022400 0x0 0x10>; + #pwm-cells = <1>; + clocks = <&ccu CLK_PWM17>; + resets = <&reset RESET_PWM17>; + k1x,pwm-disable-fd; + status = "disabled"; + }; + + pwm18: pwm@d4022800 { + compatible = "spacemit,k1x-pwm"; + reg = <0x0 0xd4022800 0x0 0x10>; + #pwm-cells = <1>; + clocks = <&ccu CLK_PWM18>; + resets = <&reset RESET_PWM18>; + k1x,pwm-disable-fd; + status = "disabled"; + }; + + pwm19: pwm@d4022c00 { + compatible = "spacemit,k1x-pwm"; + reg = <0x0 0xd4022c00 0x0 0x10>; + #pwm-cells = <1>; + clocks = <&ccu CLK_PWM19>; + resets = <&reset RESET_PWM19>; + k1x,pwm-disable-fd; + status = "disabled"; + }; + + rpwm2: pwm@c0888300 { + compatible = "spacemit,k1x-pwm"; + reg = <0x0 0xc0888300 0x0 0x10>; + #pwm-cells = <1>; + clocks = <&ccu CLK_RCPU2_PWM>; + resets = <&reset RESET_RCPU2_PWM>; + k1x,pwm-disable-fd; + rcpu-pwm; + status = "disabled"; + }; + + timer0: timer@d4014000 { + compatible = "spacemit,soc-timer"; + reg = <0x0 0xd4014000 0x0 0xc8>; + spacemit,timer-id = <0>; + spacemit,timer-fastclk-frequency = <12800000>; + spacemit,timer-apb-frequency = <52000000>; + spacemit,timer-frequency = <12800000>; + clocks = <&ccu CLK_TIMERS1>; + resets = <&reset RESET_TIMERS1>; + status = "ok"; + + counter0 { + compatible = "spacemit,timer-match"; + interrupts = <23>; + interrupt-parent = <&intc>; + spacemit,timer-broadcast; + spacemit,timer-counter-id = <0>; + status = "ok"; + }; + }; + + timer1: timer@d4016000 { + compatible = "spacemit,soc-timer"; + reg = <0x0 0xd4016000 0x0 0xc8>; + spacemit,timer-id = <1>; + spacemit,timer-fastclk-frequency = <12800000>; + spacemit,timer-apb-frequency = <52000000>; + spacemit,timer-frequency = <12800000>; + clocks = <&ccu CLK_TIMERS2>; + resets = <&reset RESET_TIMERS2>; + status = "disabled"; + + counter0 { + compatible = "spacemit,timer-match"; + interrupts = <26>; + interrupt-parent = <&intc>; + spacemit,timer-counter-id = <0>; + status = "disabled"; + }; + }; + + watchdog: watchdog@d4080000 { + compatible = "spacemit,soc-wdt"; + clocks = <&ccu CLK_WDT>; + resets = <&reset RESET_WDT>; + reg = <0x0 0xd4080000 0x0 0xff>, + <0x0 0xd4050000 0x0 0x1024>; + interrupts = <35>; + interrupt-parent = <&intc>; + spa,wdt-disabled; + status = "ok"; + }; + + reboot: handler@d4282f90 { + compatible = "spacemit,k1x-reboot"; + reg = <0x0 0xd4282f90 0x0 0x4>; + status = "ok"; + }; + + rtc: rtc@d4010000 { + compatible = "mrvl,mmp-rtc"; + reg = <0x0 0xd4010000 0x0 0x100>; + interrupt-parent = <&intc>; + interrupts = <21>, <22>; + interrupt-names = "rtc 1Hz", "rtc alarm"; + clocks = <&ccu CLK_RTC>; + resets = <&reset RESET_RTC>; + status = "disabled"; + }; + + flexcan0: fdcan@d4028000 { + compatible = "spacemit,k1x-flexcan"; + reg = <0x0 0xd4028000 0x0 0x4000>; + interrupts = <16>; + interrupt-parent = <&intc>; + clocks = <&ccu CLK_CAN0>,<&ccu CLK_CAN0_BUS>; + clock-names = "per","ipg"; + resets = <&reset RESET_CAN0>; + fsl,clk-source = <0>; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + flexcan1: fdcan@c0870000 { + compatible = "spacemit,k1x-flexcan"; + reg = <0x0 0xc0870000 0x0 0x4000>; + interrupt-parent = <&intc>; + clock-frequency = <20000000>; + fsl,clk-source = <0>; + clocks = <&ccu CLK_RCPU_CAN>,<&ccu CLK_RCPU_CAN_BUS>; + clock-names = "per","ipg"; + resets = <&reset RESET_RCPU_CAN>; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + rcpu-can; + status = "disabled"; + }; + + gpio: gpio@d4019000 { + compatible = "spacemit,k1x-gpio"; + reg = <0x0 0xd4019000 0x0 0x800>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <58>; + clocks = <&ccu CLK_GPIO>; + interrupt-names = "gpio_mux"; + interrupt-parent = <&intc>; + interrupt-controller; + #interrupt-cells = <2>; + + gcb0: gpio0 { + reg-offset = <0x0>; + }; + + gcb1: gpio1 { + reg-offset = <0x4>; + }; + + gcb2: gpio2 { + reg-offset = <0x8>; + }; + + gcb3: gpio3 { + reg-offset = <0x100>; + }; + }; + + eth0: ethernet@cac80000 { + compatible = "spacemit,k1x-emac"; + reg = <0x00000000 0xCAC80000 0x00000000 0x00000420>; + k1x,apmu-base-reg = <0xD4282800>; + ctrl-reg = <0x3e4>; + dline-reg = <0x3e8>; + clocks = <&ccu CLK_EMAC0_BUS>, + <&ccu CLK_EMAC0_PTP>; + clock-names = "emac-clk", "ptp-clk"; + resets = <&reset RESET_EMAC0>; + reset-names = "emac-reset"; + interrupts = <131>; + interrupt-parent = <&intc>; + mac-address = [ 00 00 00 00 00 00 ]; + ptp-support; + ptp-clk-rate = <10000000>; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + clk,pm-runtime,no-sleep; + cpuidle,pm-runtime,sleep; + interconnects = <&dram_range1>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + eth1: ethernet@cac81000 { + compatible = "spacemit,k1x-emac"; + reg = <0x00000000 0xCAC81000 0x00000000 0x00000420>; + k1x,apmu-base-reg = <0xD4282800>; + ctrl-reg = <0x3ec>; + dline-reg = <0x3f0>; + clocks = <&ccu CLK_EMAC1_BUS>, + <&ccu CLK_EMAC1_PTP>; + clock-names = "emac-clk", "ptp-clk"; + resets = <&reset RESET_EMAC1>; + reset-names = "emac-reset"; + interrupts = <133>; + interrupt-parent = <&intc>; + mac-address = [ 00 00 00 00 00 00 ]; + ptp-support; + ptp-clk-rate = <10000000>; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + clk,pm-runtime,no-sleep; + cpuidle,pm-runtime,sleep; + interconnects = <&dram_range1>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + extcon: extcon@d428287c { + compatible = "spacemit,vbus-id"; + reg = <0x0 0xd428287c 0x0 0x4>, + <0x0 0xd4282918 0x0 0x4>; + reg-names = "reg_pmuap", "pin_state"; + interrupts = <106>; + interrupt-parent = <&intc>; + clocks = <&ccu CLK_USB_AXI>; + status = "disabled"; + }; + + usbphy: usbphy@c0940000 { + compatible = "spacemit,usb2-phy"; + reg = <0x0 0xc0940000 0x0 0x200>; + clocks = <&ccu CLK_USB_AXI>; + status = "disabled"; + }; + + otg: otg@c0900100 { + compatible = "spacemit,mv-otg"; + reg = <0x0 0xc0900100 0x0 0x4000>; + interrupts = <105>; + interrupt-parent = <&intc>; + spacemit,otg-name = "mv-otg"; + spacemit,otg-force-a-bus-req; + clocks = <&ccu CLK_USB_AXI>; + resets = <&reset RESET_USB_AXI>; + usb-phy = <&usbphy>; + extcon = <&extcon>; + status = "disabled"; + }; + + udc: udc@c0900100 { + compatible = "spacemit,mv-udc"; + reg = <0x0 0xc0900100 0x0 0x4000>; + interrupts = <105>; + interrupt-parent = <&intc>; + spacemit,udc-name = "mv-udc"; + spacemit,otg-force-a-bus-req; + resets = <&reset RESET_USB_AXI>; + clocks = <&ccu CLK_USB_AXI>; + usb-phy = <&usbphy>; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + usb-otg = <&otg>; + status = "disabled"; + }; + + ehci: ehci@c0900100 { + compatible = "spacemit,mv-ehci"; + reg = <0x0 0xc0900100 0x0 0x4000>; + interrupts = <105>; + interrupt-parent = <&intc>; + spacemit,ehci-name = "mv-ehci"; + spacemit,otg-force-a-bus-req; + resets = <&reset RESET_USB_AXI>; + clocks = <&ccu CLK_USB_AXI>; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + clk,pm-runtime,no-sleep; + regulator,pm-runtime,no-sleep; + cpuidle,pm-runtime,sleep; + usb-phy = <&usbphy>; + usb-otg = <&otg>; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + usbphy1: usbphy1@c09c0000 { + compatible = "spacemit,usb2-phy"; + reg = <0x0 0xc09c0000 0x0 0x200>; + clocks = <&ccu CLK_USB_P1>; + status = "disabled"; + }; + + ehci1: ehci1@c0980100 { + compatible = "spacemit,mv-ehci"; + reg = <0x0 0xc0980100 0x0 0x4000>; + interrupts = <118>; + interrupt-parent = <&intc>; + spacemit,ehci-name = "mv-ehci"; + spacemit,otg-force-a-bus-req; + resets = <&reset RESET_USBP1_AXI>; + clocks = <&ccu CLK_USB_P1>; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + clk,pm-runtime,no-sleep; + regulator,pm-runtime,no-sleep; + cpuidle,pm-runtime,sleep; + usb-phy = <&usbphy1>; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + combphy: phy@c0b10000{ + compatible = "spacemit,k1x-combphy"; + reg = <0x0 0xc0b10000 0x0 0x800>, + <0x0 0xd4282910 0x0 0x400>; + reg-names = "puphy", "phy_sel"; + resets = <&reset RESET_PCIE0>; + reset-names = "phy_rst"; + #phy-cells = <1>; + status = "disabled"; + }; + + usb2phy: usb2phy@0xc0a30000 { + compatible = "spacemit,usb2-phy"; + reg = <0x0 0xc0a30000 0x0 0x200>; + spacemit,handle_connect_change; + clocks = <&ccu CLK_USB30>; + status = "disabled"; + }; + + usb3hub: usb3hub@0 { + compatible = "spacemit,usb3-hub"; + status = "disabled"; + }; + + usbdrd3: usb3@0 { + compatible = "spacemit,k1-x-dwc3"; + #address-cells = <2>; + #size-cells = <2>; + resets = <&reset RESET_USB3_0>; + reset-names = "ctl_rst"; + clocks = <&ccu CLK_USB30>; + clock-names = "usbdrd30"; + phys = <&combphy PHY_TYPE_USB3>; + phy-names = "usb3-phy"; + usb-phy = <&usb2phy>; + interrupt-parent = <&intc>; + interrupts = <149>; + ranges; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; + + dwc3@c0a00000 { + compatible = "snps,dwc3"; + reg = <0x0 0xc0a00000 0x0 0x10000>; + interrupt-parent = <&intc>; + interrupts = <125>; + }; + }; + + sdhci0: sdh@d4280000 { + compatible = "spacemit,k1-x-sdhci"; + reg = <0x0 0xd4280000 0x0 0x200>; + interrupts = <99>; + interrupt-parent = <&intc>; + resets = <&reset RESET_SDH_AXI>, + <&reset RESET_SDH0>; + reset-names = "sdh_axi", "sdh0"; + clocks = <&ccu CLK_SDH0>, + <&ccu CLK_SDH_AXI>, + <&ccu CLK_AIB>; + clock-names = "sdh-io", "sdh-core","aib-clk"; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + clk,pm-runtime,no-sleep; + regulator,pm-runtime,no-sleep; + cpuidle,pm-runtime,sleep; + status = "disabled"; + }; + + sdhci1: sdh@d4280800 { + compatible = "spacemit,k1-x-sdhci"; + reg = <0x0 0xd4280800 0x0 0x200>; + interrupts = <100>; + interrupt-parent = <&intc>; + resets = <&reset RESET_SDH_AXI>, + <&reset RESET_SDH1>; + reset-names = "sdh_axi", "sdh1"; + clocks = <&ccu CLK_SDH1>, + <&ccu CLK_SDH_AXI>; + clock-names = "sdh-io", "sdh-core"; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + clk,pm-runtime,no-sleep; + regulator,pm-runtime,no-sleep; + cpuidle,pm-runtime,sleep; + status = "disabled"; + }; + + sdhci2: sdh@d4281000 { + compatible = "spacemit,k1-x-sdhci"; + reg = <0x0 0xd4281000 0x0 0x200>; + interrupts = <101>; + interrupt-parent = <&intc>; + resets = <&reset RESET_SDH_AXI>, + <&reset RESET_SDH2>; + reset-names = "sdh_axi", "sdh2"; + clocks = <&ccu CLK_SDH2>, + <&ccu CLK_SDH_AXI>; + clock-names = "sdh-io", "sdh-core"; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + clk,pm-runtime,no-sleep; + regulator,pm-runtime,no-sleep; + cpuidle,pm-runtime,sleep; + status = "disabled"; + }; + + pcie0_rc: pcie@ca000000 { + compatible = "k1x,dwc-pcie"; + reg = <0x0 0xca000000 0x0 0x00001000>, /* dbi */ + <0x0 0xca300000 0x0 0x0001ff24>, /* atu registers */ + <0x0 0x8f000000 0x0 0x00002000>, /* config space */ + <0x0 0xd4282bcc 0x0 0x00000008>, /* k1x soc config addr */ + <0x0 0xc0b20000 0x0 0x00001000>, /* phy ahb */ + <0x0 0xc0b10000 0x0 0x00001000>, /* phy addr */ + <0x0 0xd4282bcc 0x0 0x00000008>, /* conf0 addr */ + <0x0 0xc0b10000 0x0 0x00001000>; /* phy0 addr */ + reg-names = "dbi", "atu", "config", "k1x_conf", "phy_ahb", "phy_addr", "conf0_addr", "phy0_addr"; + + k1x,pcie-port = <0>; + clocks = <&ccu CLK_PCIE0>; + clock-names = "pcie-clk"; + resets = <&reset RESET_PCIE0>; + reset-names = "pcie-reset"; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + + bus-range = <0x00 0xff>; + max-link-speed = <2>; + num-lanes = <1>; + num-viewport = <8>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x8f002000 0 0x8f002000 0x0 0x100000>, + <0x02000000 0x0 0x80000000 0 0x80000000 0x0 0x0f000000>; + interconnects = <&dram_range2>; + interconnect-names = "dma-mem"; + + interrupts = <141>, <145>; + interrupt-parent = <&intc>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0000 0 0 1 &pcie0_intc 1>, /* int_a */ + <0000 0 0 2 &pcie0_intc 2>, /* int_b */ + <0000 0 0 3 &pcie0_intc 3>, /* int_c */ + <0000 0 0 4 &pcie0_intc 4>; /* int_d */ + linux,pci-domain = <0>; + status = "disabled"; + pcie0_intc: interrupt-controller@0 { + interrupt-controller; + reg = <0 0 0 0 0>; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pcie1_rc: pcie@ca400000 { + compatible = "k1x,dwc-pcie"; + reg = <0x0 0xca400000 0x0 0x00001000>, /* dbi */ + <0x0 0xca700000 0x0 0x0001ff24>, /* atu registers */ + <0x0 0x9f000000 0x0 0x00002000>, /* config space */ + <0x0 0xd4282bd4 0x0 0x00000008>, /* k1x soc config addr */ + <0x0 0xc0c20000 0x0 0x00001000>, /* phy ahb */ + <0x0 0xc0c10000 0x0 0x00001000>, /* phy addr */ + <0x0 0xd4282bcc 0x0 0x00000008>, /* conf0 addr */ + <0x0 0xc0b10000 0x0 0x00001000>; /* phy0 addr */ + reg-names = "dbi", "atu", "config", "k1x_conf", "phy_ahb", "phy_addr", "conf0_addr", "phy0_addr"; + + k1x,pcie-port = <1>; + clocks = <&ccu CLK_PCIE1>; + clock-names = "pcie-clk"; + resets = <&reset RESET_PCIE1>; + reset-names = "pcie-reset"; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + + bus-range = <0x00 0xff>; + max-link-speed = <2>; + num-lanes = <2>; + num-viewport = <8>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x9f002000 0 0x9f002000 0x0 0x100000>, + <0x02000000 0x0 0x90000000 0 0x90000000 0x0 0x0f000000>; + interconnects = <&dram_range2>; + interconnect-names = "dma-mem"; + + interrupts = <142>, <146>; + interrupt-parent = <&intc>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0000 0 0 1 &pcie1_intc 1>, /* int_a */ + <0000 0 0 2 &pcie1_intc 2>, /* int_b */ + <0000 0 0 3 &pcie1_intc 3>, /* int_c */ + <0000 0 0 4 &pcie1_intc 4>; /* int_d */ + linux,pci-domain = <1>; + status = "disabled"; + pcie1_intc: interrupt-controller@0 { + interrupt-controller; + reg = <0 0 0 0 0>; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pcie2_rc: pcie@ca800000 { + compatible = "k1x,dwc-pcie"; + reg = <0x0 0xca800000 0x0 0x00001000>, /* dbi */ + <0x0 0xcab00000 0x0 0x0001ff24>, /* atu registers */ + <0x0 0xb7000000 0x0 0x00002000>, /* config space */ + <0x0 0xd4282bdc 0x0 0x00000008>, /* k1x soc config addr */ + <0x0 0xc0d20000 0x0 0x00001000>, /* phy ahb */ + <0x0 0xc0d10000 0x0 0x00001000>, /* phy addr */ + <0x0 0xd4282bcc 0x0 0x00000008>, /* conf0 addr */ + <0x0 0xc0b10000 0x0 0x00001000>; /* phy0 addr */ + reg-names = "dbi", "atu", "config", "k1x_conf", "phy_ahb", "phy_addr", "conf0_addr", "phy0_addr"; + + k1x,pcie-port = <2>; + clocks = <&ccu CLK_PCIE2>; + clock-names = "pcie-clk"; + resets = <&reset RESET_PCIE2>; + reset-names = "pcie-reset"; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + + bus-range = <0x00 0xff>; + max-link-speed = <2>; + num-lanes = <2>; + num-viewport = <8>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0xb7002000 0 0xb7002000 0x0 0x100000>, + <0x02000000 0x0 0xa0000000 0 0xa0000000 0x0 0x17000000>; + interconnects = <&dram_range2>; + interconnect-names = "dma-mem"; + + interrupts = <143>, <147>; + interrupt-parent = <&intc>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0000 0 0 1 &pcie2_intc 1>, /* int_a */ + <0000 0 0 2 &pcie2_intc 2>, /* int_b */ + <0000 0 0 3 &pcie2_intc 3>, /* int_c */ + <0000 0 0 4 &pcie2_intc 4>; /* int_d */ + linux,pci-domain = <2>; + status = "disabled"; + pcie2_intc: interrupt-controller@0 { + interrupt-controller; + reg = <0 0 0 0 0>; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + qspi: spi@d420c000 { + compatible = "spacemit,k1x-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0xd420c000 0x0 0x1000>, + <0x0 0xb8000000 0x0 0xc00000>; + reg-names = "qspi-base", "qspi-mmap"; + k1x,qspi-sfa1ad = <0x4000000>; + k1x,qspi-sfa2ad = <0x100000>; + k1x,qspi-sfb1ad = <0x100000>; + k1x,qspi-sfb2ad = <0x100000>; + clocks = <&ccu CLK_QSPI>, + <&ccu CLK_QSPI_BUS>; + clock-names = "qspi_clk", "qspi_bus_clk"; + resets = <&reset RESET_QSPI>, + <&reset RESET_QSPI_BUS>; + reset-names = "qspi_reset", "qspi_bus_reset"; + k1x,qspi-pmuap-reg = <0xd4282860>; + k1x,qspi-mpmu-acgr-reg = <0xd4051024>; + k1x,qspi-freq = <26500000>; + k1x,qspi-id = <4>; + power-domains = <&power K1X_PMU_BUS_PWR_DOMAIN>; + cpuidle,pm-runtime,sleep; + interrupts = <117>; + interrupt-parent = <&intc>; + k1x,qspi-tx-dma = <1>; + k1x,qspi-rx-dma = <1>; + dmas = <&pdma0 45 1>; + dma-names = "tx-dma"; + interconnects = <&dram_range0>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + thermal: thermal@d4018000 { + compatible = "spacemit,k1x-tsensor"; + reg = <0x0 0xd4018000 0x0 0x100>; + interrupt-parent = <&intc>; + interrupts = <61>; + clocks = <&ccu CLK_TSEN>; + clock-names = "thermal_core"; + resets = <&reset RESET_TSEN>; + reset-names = "tsen_reset"; + /* bjt-tsensor map: + * bjt0: local, bjt1: top, + * bjt2: gpu, bjt3: cluster0, + * bjt4: cluster1, + */ + sensor_range = <0x3 0x4>; + /* emergent_reboot_threshold = <110>; */ + #thermal-sensor-cells = <1>; + status = "okay"; + }; + + thermal_zones: thermal-zones { + cluster0_thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&thermal 3>; + + trips { + cls0_trip0: cls0-trip-point0 { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + + cls0_trip1: cls0-trip-point1 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + cls0_trip2: cls0-trip-point2 { + temperature = <115000>; + hysteresis = <5000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cls0_trip0>; +/* + cooling-device = <&{/cpus/cpu@3/thermal-hotplug} 0 1>; +*/ + cooling-device = <&cpu_0 1 2>, + <&cpu_1 1 2>, + <&cpu_2 1 2>, + <&cpu_3 1 2>; + }; + + map1 { + trip = <&cls0_trip1>; +/* + cooling-device = <&{/cpus/cpu@3/thermal-hotplug} 0 1>; +*/ + cooling-device = <&cpu_0 3 3>, + <&cpu_1 3 3>, + <&cpu_2 3 3>, + <&cpu_3 3 3>; + }; + }; + }; + + cluster1_thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&thermal 4>; + + trips { + cls1_trip0: cls1-trip-point0 { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + + cls1_trip1: cls1-trip-point1 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + + cls1_trip2: cls1-trip-point2 { + temperature = <115000>; + hysteresis = <5000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cls1_trip0>; +/* + cooling-device = <&{/cpus/cpu@7/thermal-hotplug} 0 1>; +*/ + cooling-device = <&cpu_4 1 2>, + <&cpu_5 1 2>, + <&cpu_6 1 2>, + <&cpu_7 1 2>; + }; + + map1 { + trip = <&cls1_trip1>; +/* + cooling-device = <&{/cpus/cpu@7/thermal-hotplug} 0 1>; +*/ + cooling-device = <&cpu_4 3 3>, + <&cpu_5 3 3>, + <&cpu_6 3 3>, + <&cpu_7 3 3>; + }; + }; + }; + }; + + tcm: tcm@0xd8000000 { + compatible = "spacemit,k1-x-tcm"; + reg = <0x0 0xd8000000 0x0 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xd8000000 0x80000>; + no-memory-wc; + + core0_tcm@0 { + reg = <0x00000 0x20000>; + pool; + }; + core1_tcm@20000 { + reg = <0x20000 0x20000>; + pool; + }; + core2_tcm@40000 { + reg = <0x40000 0x20000>; + pool; + }; + core3_tcm@60000 { + reg = <0x60000 0x20000>; + pool; + }; + }; + + linlon-v5@c0500000 { + compatible = "arm china,linlon-v5"; + reg = <0x0 0xC0500000 0x0 0x10000>; + interrupt-parent = <&intc>; + interrupts = <74>; + clocks = <&ccu CLK_VPU>; + clock-names = "vpu_clk"; + power-domains = <&power K1X_PMU_VPU_PWR_DOMAIN>; + resets = <&reset RESET_VPU>; + interconnects = <&dram_range1>; + interconnect-names = "dma-mem"; + clk,pm-runtime,no-sleep; + status = "okay"; + }; + + v2d@c0100000 { + compatible = "spacemit,v2d"; + reg = <0x0 0xc0100000 0x0 0x1000>; + reg-names = "v2dreg"; + clocks = <&ccu CLK_DPU_MCLK>, + <&ccu CLK_V2D>; + clock-names = "v2d-io", "v2d-core"; + resets = <&reset RESET_V2D>; + reset-names= "v2d_reset"; + interrupt-parent = <&intc>; + interrupts = <86>; + interconnects = <&dram_range1>; + interconnect-names = "dma-mem"; + status = "ok"; + }; + jpu@c02f8000 { + compatible = "chip-media, jpu"; + reg = <0 0xc02f8000 0 0x700>; + interrupt-parent = <&intc>; + interrupts = <87>; + jpu,chip-id = <0>; + clocks = <&ccu CLK_JPG>, + <&ccu CLK_DPU_MCLK>, + <&ccu CLK_ISP_BUS>; + clock-names ="cclk", "aclk", "iclk"; + power-domains = <&power K1X_PMU_ISP_PWR_DOMAIN>; + resets = <&reset RESET_JPG>, + <&reset RESET_LCD_MCLK>, + <&reset RESET_ISP_CI>, + <&reset RESET_ISP>, + <&reset RESET_ISP_AHB>; + reset-names = "jpg_reset", "lcd_mclk_reset", "isp_ci_reset", "freset", "sreset"; + + jpu,cclk-max-frequency = /bits/ 64 <1000000000>; + jpu,cclk-min-frequency = <409000000>; + jpu,cclk-default-frequency = <614000000>; + page-size = <4>; + interconnects = <&dram_range1>; + interconnect-names = "dma-mem"; + clk,pm-runtime,no-sleep; + status = "okay"; + }; + + pwm_bl: lcd_backlight { + compatible = "pwm-backlight"; + status = "disabled"; + }; + + imggpu: imggpu@cac00000 { + compatible = "img,rgx"; + interrupt-names = "rgxirq"; + interrupt-parent = <&intc>; + interrupts = <75>; + reg = <0x0 0xcac00000 0x0 0x100000>; + reg-names = "rgxregs"; + clocks = <&ccu CLK_GPU>; + clock-names = "gpu_clk"; + resets = <&reset RESET_GPU>; + power-domains = <&power K1X_PMU_GPU_PWR_DOMAIN>; + interconnects = <&dram_range1>; + interconnect-names = "dma-mem"; + status = "ok"; + }; + + spacemit_crypto_engine@d8600000 { + compatible = "spacemit,crypto_engine"; + spacemit-crypto-engine-0 = <0xd8600000 0x00100000>; + interrupt-parent = <&intc>; + interrupts = <113>; + num-engines = <1>; + clocks = <&ccu CLK_AES>; + resets = <&reset RESET_AES>; + status = "okay"; + }; + + ciu: ciu@d4282c00 { + compatible = "spacemit,aquila-ciu", "spacemit,ciu", "syscon"; + reg = <0x0 0xd4282c00 0x0 0x2d0>; + }; + }; + + pmu { + compatible = "riscv,pmu"; + + riscv,event-to-mhpmevent = + /* BRANCH_INSTRUCTIONS */ + <0x00005 0x0 0x01>, + /* BRANCH_MISSES */ + <0x00006 0x0 0x02>, + /* STALLED_CYCLES_FRONTEND */ + <0x00008 0x0 0x03>, + /* STALLED_CYCLES_BACKEND */ + <0x00009 0x0 0x04>, + /* L1D_READ_ACCESS */ + <0x10000 0x0 0x06>, + /* L1D_READ_MISS */ + <0x10001 0x0 0x05>, + /* L1D_WRITE_ACCESS */ + <0x10002 0x0 0x0a>, + /* L1D_WRITE_MISS */ + <0x10003 0x0 0x09>, + /* L1I_READ_ACCESS */ + <0x10008 0x0 0x0c>, + /* L1I_READ_MISS */ + <0x10009 0x0 0x0b>, + /* L1I_PREFETCH_ACCESS */ + <0x1000c 0x0 0x0e>, + /* L1I_PREFETCH_MISS */ + <0x1000d 0x0 0x0d>, + /* DTLB_READ_MISS */ + <0x10019 0x0 0x15>, + /* DTLB_WRITE_MISS */ + <0x1001b 0x0 0x19>, + /* ITLB_READ_MISS */ + <0x10021 0x0 0x1b>; + + /* 16 valid counters: mhpmcounter3 ~ mhpmcounter18 */ + riscv,event-to-mhpmcounters = + <0x00005 0x00006 0x0007fff8>, + <0x00008 0x00009 0x0007fff8>, + <0x10000 0x10003 0x0007fff8>, + <0x10008 0x10009 0x0007fff8>, + <0x1000c 0x1000d 0x0007fff8>, + <0x10019 0x10019 0x0007fff8>, + <0x1001b 0x1001b 0x0007fff8>, + <0x10021 0x10021 0x0007fff8>; + + riscv,raw-event-to-mhpmcounters = + /* + * For convenience, we treat 0x1~0xff as valid indexes, + * but actually in hardware the valid indexes are 0x1~0xbd. + */ + <0x0 0x0 0xffffffff 0xffffff00 0x0007fff8>; + }; + + hdmi_dma: spacemit_snd_dma_hdmi { + compatible = "spacemit,spacemit-snd-dma-hdmi"; + reg = <0 0xc08d0400 0 0x3c00>; + dmas = <&hdmi_adma>; + dma-names = "tx"; + #sound-dai-cells = <0>; + status = "okay"; + }; + + hdmi_sspa: spacemit_snd_sspa { + compatible = "spacemit,spacemit-snd-sspa"; + reg = <0 0xc0883900 0 0x300>, + <0 0xc0882000 0 0x50>; + clocks = <&ccu CLK_RCPU_HDMIAUDIO>; + resets = <&reset RESET_RCPU_HDMIAUDIO>; + assigned-clocks = <&ccu CLK_RCPU_HDMIAUDIO>; + assigned-clock-rates = <48000>; + power-domains = <&power K1X_PMU_DUMMY_PWR_DOMAIN>; + #sound-dai-cells = <0>; + status = "okay"; + }; + + dummy_codec: dummy_codec{ + compatible = "spacemit,dummy-codec"; + #sound-dai-cells = <0>; + status = "okay"; + }; + + i2s0: i2s0@d4026000 { + compatible = "spacemit,spacemit-i2s0"; + reg = <0x0 0xD4026000 0x0 0x30>; + reg-names = "i2s0"; + #sound-dai-cells = <0>; + clocks = <&ccu CLK_SSPA0>; + clock-names = "sspa-clk"; + resets = <&reset RESET_SSPA0>; + reset-names = "sspa-rst"; + assigned-clocks = <&ccu CLK_SSPA0>; + assigned-clock-rates = <1536000>; + power-domains = <&power K1X_PMU_DUMMY_PWR_DOMAIN>; + status = "disabled"; + }; + + i2s1: i2s1@d4026800 { + compatible = "spacemit,spacemit-i2s1"; + reg = <0x0 0xD4026800 0x0 0x30>; + reg-names = "i2s1"; + #sound-dai-cells = <0>; + clocks = <&ccu CLK_SSPA1>; + clock-names = "sspa-clk"; + resets = <&reset RESET_SSPA1>; + reset-names = "sspa-rst"; + assigned-clocks = <&ccu CLK_SSPA1>; + assigned-clock-rates = <1536000>; + power-domains = <&power K1X_PMU_DUMMY_PWR_DOMAIN>; + status = "disabled"; + }; + + i2s0_dma: spacemit-snd-dma0 { + compatible = "spacemit,spacemit-snd-dma0"; + dmas = <&pdma0 22 1 + &pdma0 21 1>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "okay"; + }; + + i2s1_dma: spacemit-snd-dma1 { + compatible = "spacemit,spacemit-snd-dma1"; + dmas = <&pdma0 24 1 + &pdma0 23 1>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "okay"; + }; + + sound_hdmi: snd-card@0 { + compatible = "spacemit,simple-audio-card"; + simple-audio-card,name = "snd-hdmi"; + status = "disabled"; + simple-audio-card,cpu { + sound-dai = <&hdmi_sspa>; + }; + simple-audio-card,plat { + sound-dai = <&hdmi_dma>; + }; + simple-audio-card,codec { + sound-dai = <&dummy_codec>; + }; + }; + + sound_codec: snd-card@1 { + compatible = "spacemit,simple-audio-card"; + simple-audio-card,format = "i2s"; + status = "disabled"; + spacemit,init-jack; + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + simple-audio-card,plat { + sound-dai = <&i2s0_dma>; + }; + }; +}; diff --git a/patch/kernel/archive/spacemit-6.1/dt/k1-x_deb1.dts b/patch/kernel/archive/spacemit-6.1/dt/k1-x_deb1.dts new file mode 100644 index 0000000000..5898fae7ad --- /dev/null +++ b/patch/kernel/archive/spacemit-6.1/dt/k1-x_deb1.dts @@ -0,0 +1,1129 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2023 Spacemit, Inc */ + +/dts-v1/; + +#include "k1-x.dtsi" +#include "k1-x_pinctrl.dtsi" +#include "lcd_gx09inx101_mipi.dtsi" +#include "k1-x-hdmi.dtsi" +#include "k1-x-lcd.dtsi" +#include "k1-x-camera-sdk.dtsi" + +/ { + model = "spacemit k1-x deb1 board"; + modules_usrload = "8852bs"; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <24000000>; + + cpu_0: cpu@0 { + cpu-ai = "true"; + }; + + cpu_1: cpu@1 { + cpu-ai = "true"; + }; + + cpu_2: cpu@2 { + reg = <2>; + cpu-ai = "true"; + }; + + cpu_3: cpu@3 { + reg = <3>; + cpu-ai = "true"; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_0>; + }; + + core1 { + cpu = <&cpu_1>; + }; + + core2 { + cpu = <&cpu_2>; + }; + + core3 { + cpu = <&cpu_3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu_4>; + }; + + core1 { + cpu = <&cpu_5>; + }; + + core2 { + cpu = <&cpu_6>; + }; + + core3 { + cpu = <&cpu_7>; + }; + }; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x00000000 0x0 0x80000000>; + }; + + memory@100000000 { + device_type = "memory"; + reg = <0x1 0x00000000 0x0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + /* alloc memory from 0x40000000~0x80000000 */ + alloc-ranges = <0 0x40000000 0 0x40000000>; + /* size of cma buffer is 384MByte */ + size = <0 0x18000000>; + /* start address is 1Mbyte aligned */ + alignment = <0x0 0x100000>; + linux,cma-default; + /* besides hardware, dma for ex. buffer can be used by memory management */ + reusable; + }; + + /* reserved 384K for dpu, including mmu table(256K) and cmdlist(128K) */ + dpu_resv: dpu_reserved@2ff40000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x2ff40000 0x0 0x000C0000>; + no-map; + }; + }; + + chosen { + bootargs = "earlycon=sbi console=ttyS0,115200n8 debug loglevel=8 swiotlb=65536 rdinit=/init"; + stdout-path = "serial0:115200n8"; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc4v0_baseboard: vcc4v0-baseboard { + compatible = "regulator-fixed"; + regulator-name = "vcc4v0_baseboard"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + vin-supply = <&dc_12v>; + }; + + rf_pwrseq: rf-pwrseq { + compatible = "spacemit,rf-pwrseq"; + //vdd-supply = <&ldo_7>; + //vdd_voltage = <3300000>; + io-supply = <&dcdc_3>; + io_voltage = <1800000>; + pwr-gpios = <&gpio 67 0>; + status = "okay"; + + wlan_pwrseq: wlan-pwrseq { + compatible = "spacemit,wlan-pwrseq"; + regon-gpios = <&gpio 116 0>; + hostwake-gpios = <&gpio 66 0>; + }; + + bt_pwrseq: bt-pwrseq { + compatible = "spacemit,bt-pwrseq"; + reset-gpios = <&gpio 63 0>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led1 { + label = "sys-led"; + gpios = <&gpio 96 0>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + status = "okay"; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + pwms = <&rpwm2 10000>; + #cooling-cells = <2>; + cooling-levels = <0 64 128 192 255>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0_2>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&pwm14 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm14_1>; + status = "okay"; +}; + +&dpu_online2_dsi { + memory-region = <&dpu_resv>; + spacemit-dpu-bitclk = <1000000000>; + spacemit-dpu-escclk = <76800000>; + dsi_1v2-supply = <&ldo_5>; + vin-supply-names = "dsi_1v2"; + status = "disabled"; +}; + +&dsi2 { + status = "disabled"; + + panel2: panel2@0 { + status = "ok"; + compatible = "spacemit,mipi-panel2"; + reg = <0>; + + gpios-reset = <81>; + gpios-dc = <82 83>; + id = <2>; + delay-after-reset = <10>; + force-attached = "lcd_gx09inx101_mipi"; + }; +}; + +&lcds { + status = "disabled"; +}; + +&dpu_online2_hdmi { + memory-region = <&dpu_resv>; + status = "okay"; +}; + +&hdmi{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_0>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + spacemit,i2c-fast-mode; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + spacemit,i2c-fast-mode; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_0>; + spacemit,i2c-fast-mode; + status = "okay"; + + eeprom@50{ + compatible = "atmel,24c02"; + reg = <0x50>; + #address-cells = <1>; + #size-cells = <1>; + + power-domains = <&power K1X_PMU_DUMMY_PWR_DOMAIN>; + status = "disabled"; + + mac_address0: mac_address0@0 { + reg = <0x0 6>; + }; + + mac_address1: mac_address1@6 { + reg = <0x6 6>; + }; + }; + + es8326: es8326@19{ + compatible = "everest,es8326"; + reg = <0x19>; + #sound-dai-cells = <0>; + interrupt-parent = <&gpio>; + interrupts = <126 1>; + spk-ctl-gpio = <&gpio 127 0>; + everest,mic1-src = [44]; + everest,mic2-src = [66]; + status = "okay"; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_2>; + status = "disabled"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_2>; + status = "disabled"; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6_2>; + status = "disabled"; + + gt9xx@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + + reset-gpios = <&gpio 114 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio 58 GPIO_ACTIVE_HIGH>; + irq-flags = <2>; + + touchscreen-max-id = <11>; + touchscreen-size-x = <1200>; + touchscreen-size-y = <1920>; + touchscreen-max-w = <512>; + touchscreen-max-p = <512>; + + goodix,int-sync = <1>; + status = "disabled"; + }; + +}; + +&i2c7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c7>; + status = "disabled"; +}; + +&i2c8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c8>; + status = "okay"; + + spm8821@41 { + compatible = "spacemit,spm8821"; + reg = <0x41>; + interrupt-parent = <&intc>; + interrupts = <64>; + status = "okay"; + + vcc_sys-supply = <&vcc4v0_baseboard>; + dcdc5-supply = <&dcdc_5>; + + regulators { + compatible = "pmic,regulator,spm8821"; + + /* buck */ + dcdc_1: DCDC_REG1 { + regulator-name = "dcdc1"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <650000>; + }; + }; + + dcdc_2: DCDC_REG2 { + regulator-name = "dcdc2"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + dcdc_3: DCDC_REG3 { + regulator-name = "dcdc3"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + dcdc_4: DCDC_REG4 { + regulator-name = "dcdc4"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + dcdc_5: DCDC_REG5 { + regulator-name = "dcdc5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + dcdc_6: DCDC_REG6 { + regulator-name = "dcdc6"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + /* aldo */ + ldo_1: LDO_REG1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + + /* set the min voltage means will disable this vol in suspend for ldo */ + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <500000>; + }; + }; + + ldo_2: LDO_REG2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <500000>; + }; + }; + + ldo_3: LDO_REG3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <500000>; + }; + }; + + ldo_4: LDO_REG4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <500000>; + }; + }; + + /* dldo */ + ldo_5: LDO_REG5 { + regulator-name = "ldo5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <500000>; + }; + }; + + ldo_6: LDO_REG6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <500000>; + }; + }; + + ldo_7: LDO_REG7 { + regulator-name = "ldo7"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <500000>; + }; + }; + + ldo_8: LDO_REG8 { + regulator-name = "ldo8"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + ldo_9: LDO_REG9 { + regulator-name = "ldo9"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + ldo_10: LDO_REG10 { + regulator-name = "ldo10"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + ldo_11: LDO_REG11 { + regulator-name = "ldo11"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + sw_1: SWITCH_REG1 { + regulator-name = "switch1"; + }; + }; + + pmic_pinctrl: pinctrl { + compatible = "pmic,pinctrl,spm8821"; + gpio-controller; + #gpio-cells = <2>; + spacemit,npins = <6>; +/** + * led_pins: led-pins { + * pins = "PIN3"; + * function = "sleep"; + * bias-disable = <0>; + * drive-open-drain = <0x1>; + * }; + */ + }; + + pwr_key: key { + compatible = "pmic,pwrkey,spm8821"; + }; + + ext_rtc: rtc { + compatible = "pmic,rtc,spm8821"; + }; + }; +}; + +&pinctrl { + pinctrl-single,gpio-range = < + &range GPIO_49 2 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_3V_DS4) + &range GPIO_58 1 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_1V8_DS2) + &range GPIO_63 2 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_1V8_DS2) + &range GPIO_65 1 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_1V8_DS2) + &range GPIO_66 2 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_3V_DS4) + &range PRI_TDI 2 (MUX_MODE1 | EDGE_NONE | PULL_UP | PAD_1V8_DS2) + &range PRI_TCK 1 (MUX_MODE1 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2) + &range PRI_TDO 1 (MUX_MODE1 | EDGE_NONE | PULL_UP | PAD_1V8_DS2) + &range GPIO_74 1 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_1V8_DS2) + &range GPIO_80 1 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_3V_DS4) + &range GPIO_81 3 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_1V8_DS2) + &range GPIO_90 1 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2) + &range GPIO_91 2 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_1V8_DS2) + &range DVL0 1 (MUX_MODE1 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2) + &range DVL1 1 (MUX_MODE1 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS0) + &range GPIO_110 1 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2) + &range GPIO_111 1 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2) + &range GPIO_113 1 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2) + &range GPIO_114 1 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2) + &range GPIO_115 1 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2) + &range GPIO_116 1 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_1V8_DS2) + &range GPIO_118 1 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_1V8_DS2) + &range GPIO_123 1 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS0) + &range GPIO_124 1 (MUX_MODE0 | EDGE_NONE | PULL_UP | PAD_1V8_DS2) + &range GPIO_125 3 (MUX_MODE0 | EDGE_NONE | PULL_DOWN | PAD_1V8_DS2) + >; + + pinctrl_rcpu: pinctrl_rcpu_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_47, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* r_uart0_tx */ + K1X_PADCONF(GPIO_48, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* r_uart0_rx */ + >; + }; + + pinctrl_gmac0: gmac0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_00, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_rxdv */ + K1X_PADCONF(GPIO_01, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_rx_d0 */ + K1X_PADCONF(GPIO_02, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_rx_d1 */ + K1X_PADCONF(GPIO_03, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_rx_clk */ + K1X_PADCONF(GPIO_04, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_rx_d2 */ + K1X_PADCONF(GPIO_05, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_rx_d3 */ + K1X_PADCONF(GPIO_06, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_tx_d0 */ + K1X_PADCONF(GPIO_07, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_tx_d1 */ + K1X_PADCONF(GPIO_08, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_tx */ + K1X_PADCONF(GPIO_09, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_tx_d2 */ + K1X_PADCONF(GPIO_10, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_tx_d3 */ + K1X_PADCONF(GPIO_11, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_tx_en */ + K1X_PADCONF(GPIO_12, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS0)) /* gmac0_mdc */ + K1X_PADCONF(GPIO_13, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS0)) /* gmac0_mdio */ + K1X_PADCONF(GPIO_14, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_int_n */ + K1X_PADCONF(GPIO_45, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_clk_ref */ + >; + }; + + pinctrl_gmac1: gmac1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_29, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_rxdv */ + K1X_PADCONF(GPIO_30, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_rx_d0 */ + K1X_PADCONF(GPIO_31, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_rx_d1 */ + K1X_PADCONF(GPIO_32, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_rx_clk */ + K1X_PADCONF(GPIO_33, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_rx_d2 */ + K1X_PADCONF(GPIO_34, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_rx_d3 */ + K1X_PADCONF(GPIO_35, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS0)) /* gmac1_tx_d0 */ + K1X_PADCONF(GPIO_36, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS0)) /* gmac1_tx_d1 */ + K1X_PADCONF(GPIO_37, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_tx */ + K1X_PADCONF(GPIO_38, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS0)) /* gmac1_tx_d2 */ + K1X_PADCONF(GPIO_39, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS0)) /* gmac1_tx_d3 */ + K1X_PADCONF(GPIO_40, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS0)) /* gmac1_tx_en */ + K1X_PADCONF(GPIO_41, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS0)) /* gmac1_mdc */ + K1X_PADCONF(GPIO_42, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS0)) /* gmac1_mdio */ + K1X_PADCONF(GPIO_43, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_int_n */ + K1X_PADCONF(GPIO_46, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_clk_ref */ + >; + }; +}; + +&gpio{ + gpio-ranges = < + &pinctrl 49 GPIO_49 2 + &pinctrl 58 GPIO_58 1 + &pinctrl 63 GPIO_63 5 + &pinctrl 70 PRI_TDI 4 + &pinctrl 74 GPIO_74 1 + &pinctrl 80 GPIO_80 4 + &pinctrl 90 GPIO_90 3 + &pinctrl 96 DVL0 2 + &pinctrl 110 GPIO_110 1 + &pinctrl 111 GPIO_111 1 + &pinctrl 113 GPIO_113 1 + &pinctrl 114 GPIO_114 3 + &pinctrl 118 GPIO_118 1 + &pinctrl 123 GPIO_123 5 + >; +}; + +/* SD */ +&sdhci0 { + pinctrl-names = "default","fast"; + pinctrl-0 = <&pinctrl_mmc1>; + pinctrl-1 = <&pinctrl_mmc1_fast>; + bus-width = <4>; + cd-gpios = <&gpio 80 0>; + cd-inverted; + vmmc-supply = <&dcdc_4>; + vqmmc-supply = <&ldo_1>; + no-mmc; + no-sdio; + spacemit,sdh-host-caps-disable = <( + MMC_CAP_UHS_SDR12 | + MMC_CAP_UHS_SDR25 + )>; + spacemit,sdh-quirks = <( + SDHCI_QUIRK_BROKEN_CARD_DETECTION | + SDHCI_QUIRK_INVERTED_WRITE_PROTECT | + SDHCI_QUIRK_BROKEN_TIMEOUT_VAL + )>; + spacemit,sdh-quirks2 = <( + SDHCI_QUIRK2_PRESET_VALUE_BROKEN | + SDHCI_QUIRK2_BROKEN_PHY_MODULE | + SDHCI_QUIRK2_SET_AIB_MMC + )>; + spacemit,aib_mmc1_io_reg = <0xD401E81C>; + spacemit,apbc_asfar_reg = <0xD4015050>; + spacemit,apbc_assar_reg = <0xD4015054>; + spacemit,rx_dline_reg = <0x0>; + spacemit,tx_dline_reg = <0x0>; + spacemit,tx_delaycode = <0x7f>; + spacemit,rx_tuning_limit = <50>; + spacemit,sdh-freq = <204800000>; + status = "okay"; +}; + +/* SDIO */ +&sdhci1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc2>; + bus-width = <4>; + non-removable; + vqmmc-supply = <&dcdc_3>; + no-mmc; + no-sd; + keep-power-in-suspend; + /* bcmdhd use private oob solution rather than dat1/standard wakeup */ + /delete-property/ enable-sdio-wakeup; + spacemit,sdh-host-caps-disable = <( + MMC_CAP_UHS_DDR50 | + MMC_CAP_NEEDS_POLL + )>; + spacemit,sdh-quirks = <( + SDHCI_QUIRK_BROKEN_CARD_DETECTION | + SDHCI_QUIRK_BROKEN_TIMEOUT_VAL + )>; + spacemit,sdh-quirks2 = <( + SDHCI_QUIRK2_PRESET_VALUE_BROKEN | + SDHCI_QUIRK2_BROKEN_PHY_MODULE + )>; + spacemit,rx_dline_reg = <0x0>; + spacemit,rx_tuning_limit = <50>; + spacemit,sdh-freq = <375000000>; + status = "okay"; +}; + +/* eMMC */ +&sdhci2 { + bus-width = <8>; + non-removable; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sd; + no-sdio; + spacemit,sdh-quirks = <( + SDHCI_QUIRK_BROKEN_CARD_DETECTION | + SDHCI_QUIRK_BROKEN_TIMEOUT_VAL + )>; + spacemit,sdh-quirks2 = <( + SDHCI_QUIRK2_PRESET_VALUE_BROKEN + )>; + spacemit,sdh-freq = <375000000>; + status = "okay"; +}; + +ð0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gmac0>; + + emac,reset-gpio = <&gpio 110 0>; + emac,reset-active-low; + emac,reset-delays-us = <0 10000 100000>; + + /* store forward mode */ + tx-threshold = <1518>; + rx-threshold = <12>; + tx-ring-num = <1024>; + rx-ring-num = <1024>; + dma-burst-len = <5>; + + ref-clock-from-phy; + + clk-tuning-enable; + clk-tuning-by-delayline; + tx-phase = <60>; + rx-phase = <73>; + + nvmem-cells = <&mac_address0>; + nvmem-cell-names = "mac-address"; + + phy-handle = <&rgmii0>; + + status = "okay"; + + mdio-bus { + #address-cells = <0x1>; + #size-cells = <0x0>; + rgmii0: phy@0 { + compatible = "ethernet-phy-id001c.c916"; + device_type = "ethernet-phy"; + reg = <0x1>; + phy-mode = "rgmii"; + }; + }; +}; + +ð1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gmac1>; + + emac,reset-gpio = <&gpio 115 0>; + emac,reset-active-low; + emac,reset-delays-us = <0 10000 100000>; + + /* store forward mode */ + tx-threshold = <1518>; + rx-threshold = <12>; + tx-ring-num = <1024>; + rx-ring-num = <1024>; + dma-burst-len = <5>; + + ref-clock-from-phy; + + clk-tuning-enable; + clk-tuning-by-delayline; + tx-phase = <90>; + rx-phase = <73>; + nvmem-cells = <&mac_address1>; + nvmem-cell-names = "mac-address"; + + phy-handle = <&rgmii1>; + + status = "okay"; + + mdio-bus { + #address-cells = <0x1>; + #size-cells = <0x0>; + rgmii1: phy@1 { + compatible = "ethernet-phy-id001c.c916"; + device_type = "ethernet-phy"; + reg = <0x1>; + phy-mode = "rgmii"; + }; + }; +}; + +&usbphy { + status = "okay"; +}; + +&udc { + /*spacemit,udc-mode = ; + spacemit,extern-attr = ;*/ + spacemit,udc-mode = ; + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; + +&ehci1 { + spacemit,reset-on-resume; + status = "okay"; +}; + +&usb2phy { + status = "okay"; +}; + +&combphy { + status = "okay"; +}; + +&usb3hub { + hub-gpios = < + &gpio 123 0 /* usb3 hub en */ + &gpio 124 0>; /* usb3 hub rst*/ + vbus-gpios = <&gpio 97 0>; /* gpio_97 for usb3 hub output vbus */ + status = "okay"; +}; + +&usbdrd3 { + status = "okay"; + reset-on-resume; + dwc3@c0a00000 { + dr_mode = "host"; + phy_type = "utmi"; + snps,hsphy_interface = "utmi"; + snps,dis_enblslpm_quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-ss-quirk; + }; +}; + +&pcie1_rc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1_3>; + status = "okay"; +}; + +&pcie2_rc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie2_4>; + status = "okay"; +}; + +&imggpu { + status = "okay"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <26500000>; + m25p,fast-read; + broken-flash-reset; + status = "okay"; + }; +}; + +&pwm_bl { + pwms = <&pwm14 2000>; + brightness-levels = < + 0 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 + 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 + 40 40 40 40 40 40 40 40 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <100>; + + status = "okay"; +}; + +/* ov16a10 */ +&backsensor { + af_2v8-supply = <&ldo_3>; + avdd_2v8-supply = <&ldo_2>; + dovdd_1v8-supply = <&ldo_7>; + dvdd_1v2-supply = <&ldo_6>; + + pwdn-gpios = <&gpio 113 0>; + reset-gpios = <&gpio 111 0>; + + status = "okay"; +}; + +&backsensor_aux { + avdd_2v8-supply = <&ldo_2>; + dovdd_1v8-supply = <&ldo_7>; + + status = "disabled"; +}; + +&frontsensor { + af_2v8-supply = <&ldo_3>; + avdd_2v8-supply = <&ldo_2>; + dovdd_1v8-supply = <&ldo_7>; + dvdd_1v2-supply = <&ldo_6>; + + clocks = <&ccu CLK_CAMM1>; + clock-names = "cam_mclk1"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_camera1>; + + pwdn-gpios = <&gpio 114 0>; + reset-gpios = <&gpio 112 0>; + + status = "disabled"; +}; +&csiphy0 { + + status = "okay"; +}; +&csiphy1 { + + status = "disabled"; +}; +&csiphy2 { + + status = "okay"; +}; + +&ccic0 { + power-domains = <&power K1X_PMU_ISP_PWR_DOMAIN>; + + status = "okay"; +}; +&ccic1 { + power-domains = <&power K1X_PMU_ISP_PWR_DOMAIN>; + + status = "okay"; +}; +&ccic2 { + power-domains = <&power K1X_PMU_ISP_PWR_DOMAIN>; + + status = "okay"; +}; +&isp { + power-domains = <&power K1X_PMU_ISP_PWR_DOMAIN>; +}; + +&cpp { + power-domains = <&power K1X_PMU_ISP_PWR_DOMAIN>; +}; + +&vi { + power-domains = <&power K1X_PMU_ISP_PWR_DOMAIN>; +}; + +&cpu_0 { + clst0-supply = <&dcdc_1>; + vin-supply-names = "clst0"; +}; + +&clst0_core_opp_table { + opp1600000000 { + opp-microvolt = <1050000>; + }; +}; + +&clst1_core_opp_table { + opp1600000000 { + opp-microvolt = <1050000>; + }; +}; + +&rcpu { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rcpu>; + mboxes = <&mailbox 0>, <&mailbox 1>; + mbox-names = "vq0", "vq1"; + memory-region = <&rcpu_mem_0>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, <&rsc_table>, <&rcpu_mem_snapshots>; + status = "okay"; +}; + +&thermal { + sensor_range = <0x1 0x4>; +}; + +&thermal_zones { + top_thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&thermal 1>; + + trips { + top_trip0: top-trip0 { + temperature = <40000>; + hysteresis = <5000>; + type = "passive"; + }; + + top_trip1: top-trip1 { + temperature = <55000>; + hysteresis = <5000>; + type = "passive"; + }; + + top_trip2: top-trip2 { + temperature = <70000>; + hysteresis = <5000>; + type = "passive"; + }; + + top_trip3: top-trip3 { + temperature = <85000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&top_trip0>; + cooling-device = <&fan 0 1>; + }; + + map1 { + trip = <&top_trip1>; + cooling-device = <&fan 1 2>; + }; + + map2 { + trip = <&top_trip2>; + cooling-device = <&fan 2 3>; + }; + + map3 { + trip = <&top_trip3>; + cooling-device = <&fan 3 4>; + }; + }; + }; + + gpu_thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&thermal 2>; + + /* Just a placeholder */ + trips { + gpu_trip0: gpu-trip0 { + temperature = <40000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; +}; + +&cls0_trip2 { + temperature = <115000>; +}; + +&cls1_trip2 { + temperature = <115000>; +}; + +&i2s0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sspa0_0>; + status = "okay"; +}; + +&sound_hdmi { + status = "okay"; +}; + +&sound_codec { + status = "okay"; + simple-audio-card,name = "snd-es8326"; + spacemit,mclk-fs = <64>; + simple-audio-card,codec { + sound-dai = <&es8326>; + }; +}; + +&rpwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rpwm2_0>; + status = "okay"; +}; diff --git a/patch/kernel/archive/spacemit-6.1/dt/k1-x_pinctrl.dtsi b/patch/kernel/archive/spacemit-6.1/dt/k1-x_pinctrl.dtsi new file mode 100644 index 0000000000..f6ed1d7158 --- /dev/null +++ b/patch/kernel/archive/spacemit-6.1/dt/k1-x_pinctrl.dtsi @@ -0,0 +1,1157 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2022 Spacemit, Inc */ + +#include +/* Pin Configuration Node: */ +/* Format: */ +&pinctrl { + pinctrl_uart0_0: uart0_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(MMC1_DAT3, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* uart0_txd */ + K1X_PADCONF(MMC1_DAT2, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* uart0_rxd */ + >; + }; + + pinctrl_uart0_1: uart0_1_grp { + pinctrl-single,pins = < + K1X_PADCONF(MMC1_CMD, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* uart0_txd */ + K1X_PADCONF(GPIO_80, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_3V_DS4)) /* uart0_rxd */ + >; + }; + + pinctrl_uart0_2: uart0_2_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_68, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart0_txd */ + K1X_PADCONF(GPIO_69, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart0_rxd */ + >; + }; + + pinctrl_uart2: uart2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_21, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* uart2_txd */ + K1X_PADCONF(GPIO_22, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* uart2_rxd */ + K1X_PADCONF(GPIO_23, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* uart2_cts_n */ + K1X_PADCONF(GPIO_24, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* uart2_rts_n */ + >; + }; + + pinctrl_uart3_0: uart3_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_81, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart3_txd */ + K1X_PADCONF(GPIO_82, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart3_rxd */ + K1X_PADCONF(GPIO_83, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart3_cts_n */ + K1X_PADCONF(GPIO_84, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart3_rts_n */ + >; + }; + + pinctrl_uart3_1: uart3_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_18, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart3_txd */ + K1X_PADCONF(GPIO_19, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart3_rxd */ + K1X_PADCONF(GPIO_20, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart3_cts_n */ + K1X_PADCONF(GPIO_21, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart3_rts_n */ + >; + }; + + pinctrl_uart3_2: uart3_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_53, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart3_txd */ + K1X_PADCONF(GPIO_54, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart3_rxd */ + K1X_PADCONF(GPIO_55, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart3_cts_n */ + K1X_PADCONF(GPIO_56, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart3_rts_n */ + >; + }; + + pinctrl_uart4_0: uart4_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(QSPI_DAT1, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_3V_DS4)) /* uart4_txd */ + K1X_PADCONF(QSPI_DAT0, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_3V_DS4)) /* uart4_rxd */ + >; + }; + + pinctrl_uart4_1: uart4_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_81, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart4_cts_n */ + K1X_PADCONF(GPIO_82, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart4_rts_n */ + K1X_PADCONF(GPIO_83, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart4_txd */ + K1X_PADCONF(GPIO_84, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart4_rxd */ + >; + }; + + pinctrl_uart4_2: uart4_2_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_23, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart4_txd */ + K1X_PADCONF(GPIO_24, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart4_rxd */ + >; + }; + + pinctrl_uart4_3: uart4_3_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_33, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart4_txd */ + K1X_PADCONF(GPIO_34, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart4_rxd */ + K1X_PADCONF(GPIO_35, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart4_cts_n */ + K1X_PADCONF(GPIO_36, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart4_rts_n */ + >; + }; + + pinctrl_uart4_4: uart4_4_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_111, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart4_txd */ + K1X_PADCONF(GPIO_112, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart4_rxd */ + K1X_PADCONF(GPIO_113, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart4_cts_n */ + K1X_PADCONF(GPIO_114, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart4_rts_n */ + >; + }; + + pinctrl_uart5_0: uart5_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(QSPI_CLK, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_3V_DS4)) /* uart5_txd */ + K1X_PADCONF(QSPI_CSI, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_3V_DS4)) /* uart5_rxd */ + >; + }; + + pinctrl_uart5_1: uart5_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_25, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart5_txd */ + K1X_PADCONF(GPIO_26, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart5_rxd */ + K1X_PADCONF(GPIO_27, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart5_cts_n */ + K1X_PADCONF(GPIO_28, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart5_rts_n */ + >; + }; + + pinctrl_uart5_2: uart5_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_42, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart5_txd */ + K1X_PADCONF(GPIO_43, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart5_rxd */ + K1X_PADCONF(GPIO_44, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart5_cts_n */ + K1X_PADCONF(GPIO_45, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart5_rts_n */ + >; + }; + + pinctrl_uart5_3: uart5_3_grp { + pinctrl-single,pins =< + K1X_PADCONF(PRI_TDI, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart5_txd */ + K1X_PADCONF(PRI_TMS, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart5_rxd */ + K1X_PADCONF(PRI_TCK, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart5_cts_n */ + K1X_PADCONF(PRI_TDO, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart5_rts_n */ + >; + }; + + pinctrl_uart6_0: uart6_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_85, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart6_cts_n */ + K1X_PADCONF(GPIO_86, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart6_txd */ + K1X_PADCONF(GPIO_87, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart6_rxd */ + K1X_PADCONF(GPIO_90, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart6_rts_n */ + >; + }; + + pinctrl_uart6_1: uart6_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_00, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart6_txd */ + K1X_PADCONF(GPIO_01, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart6_rxd */ + K1X_PADCONF(GPIO_02, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart6_cts_n */ + K1X_PADCONF(GPIO_03, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart6_rts_n */ + >; + }; + + pinctrl_uart6_2: uart6_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_56, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart6_txd */ + K1X_PADCONF(GPIO_57, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart6_rxd */ + >; + }; + + pinctrl_uart7_0: uart7_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_88, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart7_txd */ + K1X_PADCONF(GPIO_89, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart7_rxd */ + >; + }; + + pinctrl_uart7_1: uart7_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_04, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart7_txd */ + K1X_PADCONF(GPIO_05, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart7_rxd */ + K1X_PADCONF(GPIO_06, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart7_cts_n */ + K1X_PADCONF(GPIO_07, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart7_rts_n */ + >; + }; + + pinctrl_uart8_0: uart8_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_82, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart8_txd */ + K1X_PADCONF(GPIO_83, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart8_rxd */ + >; + }; + + pinctrl_uart8_1: uart8_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_08, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart8_txd */ + K1X_PADCONF(GPIO_09, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart8_rxd */ + K1X_PADCONF(GPIO_10, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart8_cts_n */ + K1X_PADCONF(GPIO_11, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart8_rts_n */ + >; + }; + + pinctrl_uart8_2: uart8_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_75, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* uart8_txd */ + K1X_PADCONF(GPIO_76, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* uart8_rxd */ + K1X_PADCONF(GPIO_77, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* uart8_cts_n */ + K1X_PADCONF(GPIO_78, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* uart8_rts_n */ + >; + }; + + pinctrl_uart9_0: uart9_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_12, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart9_txd */ + K1X_PADCONF(GPIO_13, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart9_rxd */ + >; + }; + + pinctrl_uart9_1: uart9_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_110, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart9_cts_n */ + K1X_PADCONF(GPIO_115, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart9_rts_n */ + K1X_PADCONF(GPIO_116, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart9_txd */ + K1X_PADCONF(GPIO_117, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart9_rxd */ + >; + }; + + pinctrl_uart9_2: uart9_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(PRI_TCK, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* uart9_txd */ + K1X_PADCONF(PRI_TDO, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* uart9_rxd */ + >; + }; + + pinctrl_i2c0: i2c0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_54, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c0_scl */ + K1X_PADCONF(GPIO_55, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c0_sda */ + >; + }; + + pinctrl_i2c1: i2c1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_56, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c1_scl */ + K1X_PADCONF(GPIO_57, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c1_sda */ + >; + }; + + pinctrl_i2c2_0: i2c2_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_84, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c2_scl */ + K1X_PADCONF(GPIO_85, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c2_sda */ + >; + }; + + pinctrl_i2c2_1: i2c2_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(PRI_TDI, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c2_scl */ + K1X_PADCONF(PRI_TMS, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c2_sda */ + >; + }; + + pinctrl_i2c2_2: i2c2_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_68, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c2_scl */ + K1X_PADCONF(GPIO_69, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c2_sda */ + >; + }; + + pinctrl_i2c3_0: i2c3_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_38, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c3_scl */ + K1X_PADCONF(GPIO_39, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c3_sda */ + >; + }; + + pinctrl_i2c3_1: i2c3_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_47, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c3_scl */ + K1X_PADCONF(GPIO_48, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c3_sda */ + >; + }; + + pinctrl_i2c3_2: i2c3_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_77, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c3_scl */ + K1X_PADCONF(GPIO_78, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c3_sda */ + >; + }; + + pinctrl_i2c4_0: i2c4_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_40, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c4_scl */ + K1X_PADCONF(GPIO_41, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c4_sda */ + >; + }; + + pinctrl_i2c4_1: i2c4_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_75, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_3V_DS0)) /* i2c4_scl */ + K1X_PADCONF(GPIO_76, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_3V_DS0)) /* i2c4_sda */ + >; + }; + + pinctrl_i2c4_2: i2c4_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_51, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_3V_DS0)) /* i2c4_scl */ + K1X_PADCONF(GPIO_52, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_3V_DS0)) /* i2c4_sda */ + >; + }; + + pinctrl_i2c5_0: i2c5_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_81, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c5_scl */ + K1X_PADCONF(GPIO_82, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c5_sda */ + >; + }; + + pinctrl_i2c5_1: i2c5_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_54, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c5_scl */ + K1X_PADCONF(GPIO_55, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c5_sda */ + >; + }; + + pinctrl_i2c6_0: i2c6_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_83, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c6_scl */ + K1X_PADCONF(GPIO_90, MUX_MODE5, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* i2c6_sda */ + >; + }; + + pinctrl_i2c6_1: i2c6_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_118, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c6_scl */ + K1X_PADCONF(GPIO_119, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c6_sda */ + >; + }; + + pinctrl_i2c6_2: i2c6_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_56, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c6_scl */ + K1X_PADCONF(GPIO_57, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c6_sda */ + >; + }; + + pinctrl_i2c7: i2c7_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_118, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* i2c6_scl */ + K1X_PADCONF(GPIO_119, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* i2c6_sda */ + >; + }; + + pinctrl_i2c8: i2c8_grp { + pinctrl-single,pins =< + K1X_PADCONF(PWR_SCL, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* pwr_scl */ + K1X_PADCONF(PWR_SDA, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* pwr_sda */ + >; + }; + + pinctrl_one_wire_0: one_wire_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_110, MUX_MODE5, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* one_wire */ + >; + }; + + pinctrl_one_wire_1: one_wire_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_47, MUX_MODE5, (EDGE_NONE | PULL_DOWN | PAD_3V_DS4)) /* one_wire */ + >; + }; + + pinctrl_ir_rx_0: ir_rx_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(DVL1, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* ir_rx */ + >; + }; + + pinctrl_ir_rx_1: ir_rx_1_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_79, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_3V_DS4)) /* ir_rx */ + >; + }; + + pinctrl_ir_rx_2: ir_rx_2_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_58, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* ir_rx */ + >; + }; + + pinctrl_pwm0_0: pwm0_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(MMC1_DAT3, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* pwm0 */ + >; + }; + + pinctrl_pwm0_1: pwm0_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_14, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm0 */ + >; + }; + + pinctrl_pwm0_2: pwm0_2_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_22, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm0 */ + >; + }; + + pinctrl_pwm1_0: pwm1_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(MMC1_DAT2, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* pwm1 */ + >; + }; + + pinctrl_pwm1_1: pwm1_1_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_29, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm1 */ + >; + }; + + pinctrl_pwm1_2: pwm1_2_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_23, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm1 */ + >; + }; + + pinctrl_pwm2_0: pwm2_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(MMC1_DAT1, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* pwm2 */ + >; + }; + + pinctrl_pwm2_1: pwm2_1_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_22, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm2 */ + >; + }; + + pinctrl_pwm2_2: pwm2_2_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_30, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm2 */ + >; + }; + + pinctrl_pwm2_3: pwm2_3_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_24, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm2 */ + >; + }; + + pinctrl_pwm3_0: pwm3_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(MMC1_DAT0, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* pwm3 */ + >; + }; + + pinctrl_pwm3_1: pwm3_1_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_33, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm3 */ + >; + }; + + pinctrl_pwm3_2: pwm3_2_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_25, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm3 */ + >; + }; + + pinctrl_pwm4_0: pwm4_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(MMC1_CMD, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* pwm4 */ + >; + }; + + pinctrl_pwm4_1: pwm4_1_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_34, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm4 */ + >; + }; + + pinctrl_pwm5_0: pwm5_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(MMC1_CLK, MUX_MODE5, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* pwm5 */ + >; + }; + + pinctrl_pwm5_1: pwm5_1_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_35, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm5 */ + >; + }; + + pinctrl_pwm6_0: pwm6_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_88, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm6 */ + >; + }; + + pinctrl_pwm6_1: pwm6_1_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_36, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm6 */ + >; + }; + + pinctrl_pwm7_0: pwm7_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_92, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* pwm7 */ + >; + }; + + pinctrl_pwm7_1: pwm7_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_37, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm7 */ + >; + }; + + pinctrl_pwm8_0: pwm8_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_00, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm8 */ + >; + }; + + pinctrl_pwm8_1: pwm8_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_38, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* pwm8 */ + >; + }; + + pinctrl_pwm9_0: pwm9_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_01, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm9 */ + >; + }; + + pinctrl_pwm9_1: pwm9_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_39, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* pwm9 */ + >; + }; + + pinctrl_pwm9_2: pwm9_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_74, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* pwm9 */ + >; + }; + + pinctrl_pwm10_0: pwm10_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_02, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm10 */ + >; + }; + + pinctrl_pwm10_1: pwm10_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_40, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* pwm10 */ + >; + }; + + pinctrl_pwm11_0: pwm11_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_03, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm11 */ + >; + }; + + pinctrl_pwm11_1: pwm11_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_41, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* pwm11 */ + >; + }; + + pinctrl_pwm12_0: pwm12_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_04, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm12 */ + >; + }; + + pinctrl_pwm12_1: pwm12_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_42, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm12 */ + >; + }; + + pinctrl_pwm13_0: pwm13_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_05, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm13 */ + >; + }; + + pinctrl_pwm13_1: pwm13_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_43, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm13 */ + >; + }; + + pinctrl_pwm14_0: pwm14_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_06, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm14 */ + >; + }; + + pinctrl_pwm14_1: pwm14_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_44, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm14 */ + >; + }; + + pinctrl_pwm15_0: pwm15_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_07, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm15 */ + >; + }; + + pinctrl_pwm15_1: pwm15_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_45, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm15 */ + >; + }; + + pinctrl_pwm16_0: pwm16_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_09, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm16 */ + >; + }; + + pinctrl_pwm16_1: pwm16_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_46, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm16 */ + >; + }; + + pinctrl_pwm17_0: pwm17_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_10, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm17 */ + >; + }; + + pinctrl_pwm17_1: pwm17_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_53, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm17 */ + >; + }; + + pinctrl_pwm18_0: pwm18_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_11, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm18 */ + >; + }; + + pinctrl_pwm18_1: pwm18_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_57, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* pwm18 */ + >; + }; + + pinctrl_pwm19_0: pwm19_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_13, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm19 */ + >; + }; + + pinctrl_pwm19_1: pwm19_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_63, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pwm19 */ + >; + }; + + pinctrl_rpwm2_0: rpwm2_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_79, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_3V_DS4)) /* rcpu_pwm2 */ + >; + }; + + pinctrl_sspa0_0: sspa0_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_118, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* sspa0_clk */ + K1X_PADCONF(GPIO_119, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS0)) /* sspa0_frm */ + K1X_PADCONF(GPIO_120, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* sspa0_txd */ + K1X_PADCONF(GPIO_121, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* sspa0_rxd */ + K1X_PADCONF(GPIO_122, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* sspa0_sysclk */ + >; + }; + + pinctrl_sspa0_1: sspa0_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_58, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* sspa0_sysclk */ + K1X_PADCONF(GPIO_111, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* sspa0_clk */ + K1X_PADCONF(GPIO_112, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* sspa0_frm */ + K1X_PADCONF(GPIO_113, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* sspa0_txd */ + K1X_PADCONF(GPIO_114, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* sspa0_rxd */ + >; + }; + + pinctrl_sspa1: sspa1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_24, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* sspa1_sysclk */ + K1X_PADCONF(GPIO_25, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* sspa1_sclk */ + K1X_PADCONF(GPIO_26, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* sspa1_frm */ + K1X_PADCONF(GPIO_27, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* sspa1_txd */ + K1X_PADCONF(GPIO_28, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS0)) /* sspa1_rxd */ + >; + }; + + pinctrl_ssp2_0: ssp2_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_75, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* ssp2_sclk */ + K1X_PADCONF(GPIO_76, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* ssp2_frm */ + K1X_PADCONF(GPIO_77, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* ssp2_txd */ + K1X_PADCONF(GPIO_78, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* ssp2_rxd */ + >; + }; + + pinctrl_ssp2_1: ssp2_1_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_64, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* ssp2_sclk */ + K1X_PADCONF(GPIO_65, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* ssp2_frm */ + K1X_PADCONF(GPIO_66, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* ssp2_txd */ + K1X_PADCONF(GPIO_67, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* ssp2_rxd */ + >; + }; + + pinctrl_ssp3_0: ssp3_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_75, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* ssp3_sclk */ + K1X_PADCONF(GPIO_76, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* ssp3_frm */ + K1X_PADCONF(GPIO_77, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* ssp3_txd */ + K1X_PADCONF(GPIO_78, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* ssp3_rxd */ + >; + }; + + pinctrl_ssp3_1: ssp3_1_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_59, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* ssp3_sclk */ + K1X_PADCONF(GPIO_60, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* ssp3_frm */ + K1X_PADCONF(GPIO_61, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* ssp3_txd */ + K1X_PADCONF(GPIO_62, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* ssp3_rxd */ + >; + }; + + pinctrl_qspi: qspi_grp { + pinctrl-single,pins = < + K1X_PADCONF(QSPI_DAT3, MUX_MODE0, (EDGE_NONE | PULL_DOWN | PAD_3V_DS4)) /* qspi_d3 */ + K1X_PADCONF(QSPI_DAT2, MUX_MODE0, (EDGE_NONE | PULL_DOWN | PAD_3V_DS4)) /* qspi_d2 */ + K1X_PADCONF(QSPI_DAT1, MUX_MODE0, (EDGE_NONE | PULL_DOWN | PAD_3V_DS4)) /* qspi_d1 */ + K1X_PADCONF(QSPI_DAT0, MUX_MODE0, (EDGE_NONE | PULL_DOWN | PAD_3V_DS4)) /* qspi_d1 */ + K1X_PADCONF(QSPI_CLK, MUX_MODE0, (EDGE_NONE | PULL_DOWN | PAD_3V_DS4)) /* qspi_clk */ + K1X_PADCONF(QSPI_CSI, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* qspi_csi */ + >; + }; + + pinctrl_mmc1: mmc1_grp { + pinctrl-single,pins = < + K1X_PADCONF(MMC1_DAT3, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* mmc1_d3 */ + K1X_PADCONF(MMC1_DAT2, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* mmc1_d2 */ + K1X_PADCONF(MMC1_DAT1, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* mmc1_d1 */ + K1X_PADCONF(MMC1_DAT0, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* mmc1_d0 */ + K1X_PADCONF(MMC1_CMD, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* mmc1_cmd */ + K1X_PADCONF(MMC1_CLK, MUX_MODE0, (EDGE_NONE | PULL_DOWN | PAD_3V_DS4)) /* mmc1_clk */ + >; + }; + + pinctrl_mmc1_fast: mmc1_fast_grp { + pinctrl-single,pins = < + K1X_PADCONF(MMC1_DAT3, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_1V8_DS3)) /* mmc1_d3 */ + K1X_PADCONF(MMC1_DAT2, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_1V8_DS3)) /* mmc1_d2 */ + K1X_PADCONF(MMC1_DAT1, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_1V8_DS3)) /* mmc1_d1 */ + K1X_PADCONF(MMC1_DAT0, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_1V8_DS3)) /* mmc1_d0 */ + K1X_PADCONF(MMC1_CMD, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_1V8_DS3)) /* mmc1_cmd */ + K1X_PADCONF(MMC1_CLK, MUX_MODE0, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS3)) /* mmc1_clk */ + >; + }; + + pinctrl_mmc2: mmc2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_15, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* mmc2_data3 */ + K1X_PADCONF(GPIO_16, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* mmc2_data2 */ + K1X_PADCONF(GPIO_17, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* mmc2_data1 */ + K1X_PADCONF(GPIO_18, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* mmc2_data0 */ + K1X_PADCONF(GPIO_19, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* mmc2_cmd */ + K1X_PADCONF(GPIO_20, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* mmc2_clk */ + >; + }; + + pinctrl_usb0_0: usb0_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_125, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* vbus_on0 */ + K1X_PADCONF(GPIO_126, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* usb_id0 */ + K1X_PADCONF(GPIO_127, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* drive_vbus0_iso */ + >; + }; + + pinctrl_usb0_1: usb0_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_64, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* vbus_on0 */ + K1X_PADCONF(GPIO_65, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* usb_id0 */ + K1X_PADCONF(GPIO_63, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* drive_vbus0_iso */ + >; + }; + + pinctrl_usb1_0: usb1_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_124, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* drive_vbus1_iso */ + >; + }; + + pinctrl_usb1_1: usb1_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_66, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* drive_vbus1_iso */ + >; + }; + + pinctrl_usb2_0: usb2_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_121, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* vbus_on2 */ + K1X_PADCONF(GPIO_122, MUX_MODE2, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* usb_id2 */ + K1X_PADCONF(GPIO_123, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* drive_vbus2_iso */ + >; + }; + + pinctrl_usb2_1: usb2_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_68, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* vbus_on2 */ + K1X_PADCONF(GPIO_69, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* usb_id2 */ + K1X_PADCONF(GPIO_67, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* drive_vbus2_iso */ + >; + }; + + pinctrl_pcie0_0: pcie0_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_15, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe0_perstn */ + K1X_PADCONF(GPIO_16, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe0_waken */ + K1X_PADCONF(GPIO_17, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe0_clkreqn */ + >; + }; + + pinctrl_pcie0_1: pcie0_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_29, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe0_perstn */ + K1X_PADCONF(GPIO_30, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe0_waken */ + K1X_PADCONF(GPIO_31, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe0_clkreqn */ + >; + }; + + pinctrl_pcie0_2: pcie0_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_110, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe0_perstn */ + K1X_PADCONF(GPIO_115, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe0_waken */ + K1X_PADCONF(GPIO_116, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe0_clkreqn */ + >; + }; + + pinctrl_pcie0_3: pcie0_3_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_53, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe0_perstn */ + K1X_PADCONF(GPIO_54, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe0_waken */ + K1X_PADCONF(GPIO_55, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe0_clkreqn */ + >; + }; + + pinctrl_pcie1_0: pcie1_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_15, MUX_MODE4, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* PCIe1_perstn */ + K1X_PADCONF(GPIO_16, MUX_MODE4, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* PCIe1_waken */ + K1X_PADCONF(GPIO_17, MUX_MODE4, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* PCIe1_clkreqn */ + >; + }; + + pinctrl_pcie1_1: pcie1_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_32, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe1_perstn */ + K1X_PADCONF(GPIO_33, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe1_waken */ + K1X_PADCONF(GPIO_34, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe1_clkreqn */ + >; + }; + + pinctrl_pcie1_2: pcie1_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_56, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe1_perstn */ + K1X_PADCONF(GPIO_57, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe1_waken */ + K1X_PADCONF(GPIO_58, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe1_clkreqn */ + >; + }; + + pinctrl_pcie1_3: pcie1_3_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_59, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe1_perstn */ + K1X_PADCONF(GPIO_60, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe1_waken */ + K1X_PADCONF(GPIO_61, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe1_clkreqn */ + >; + }; + + pinctrl_pcie2_0: pcie2_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_18, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe2_perstn */ + K1X_PADCONF(GPIO_19, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe2_waken */ + K1X_PADCONF(GPIO_20, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe2_clkreqn */ + >; + }; + + pinctrl_pcie2_1: pcie2_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_35, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe2_perstn */ + K1X_PADCONF(GPIO_36, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe2_waken */ + K1X_PADCONF(GPIO_37, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe2_clkreqn */ + >; + }; + + pinctrl_pcie2_2: pcie2_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_62, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe2_perstn */ + K1X_PADCONF(GPIO_74, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe2_waken */ + K1X_PADCONF(GPIO_117, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe2_clkreqn */ + >; + }; + + pinctrl_pcie2_3: pcie2_3_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_111, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe2_perstn */ + K1X_PADCONF(GPIO_112, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe2_waken */ + K1X_PADCONF(GPIO_113, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe2_clkreqn */ + >; + }; + + pinctrl_pcie2_4: pcie2_4_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_62, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe2_perstn */ + K1X_PADCONF(GPIO_112, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* PCIe2_waken */ + K1X_PADCONF(GPIO_117, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* PCIe2_clkreqn */ + >; + }; + + pinctrl_gmac0: gmac0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_00, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_rxdv */ + K1X_PADCONF(GPIO_01, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_rx_d0 */ + K1X_PADCONF(GPIO_02, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_rx_d1 */ + K1X_PADCONF(GPIO_03, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_rx_clk */ + K1X_PADCONF(GPIO_04, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_rx_d2 */ + K1X_PADCONF(GPIO_05, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_rx_d3 */ + K1X_PADCONF(GPIO_06, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_tx_d0 */ + K1X_PADCONF(GPIO_07, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_tx_d1 */ + K1X_PADCONF(GPIO_08, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_tx */ + K1X_PADCONF(GPIO_09, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_tx_d2 */ + K1X_PADCONF(GPIO_10, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_tx_d3 */ + K1X_PADCONF(GPIO_11, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_tx_en */ + K1X_PADCONF(GPIO_12, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_mdc */ + K1X_PADCONF(GPIO_13, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_mdio */ + K1X_PADCONF(GPIO_14, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_int_n */ + K1X_PADCONF(GPIO_45, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac0_clk_ref */ + >; + }; + + pinctrl_gmac1: gmac1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_29, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_rxdv */ + K1X_PADCONF(GPIO_30, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_rx_d0 */ + K1X_PADCONF(GPIO_31, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_rx_d1 */ + K1X_PADCONF(GPIO_32, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_rx_clk */ + K1X_PADCONF(GPIO_33, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_rx_d2 */ + K1X_PADCONF(GPIO_34, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_rx_d3 */ + K1X_PADCONF(GPIO_35, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_tx_d0 */ + K1X_PADCONF(GPIO_36, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_tx_d1 */ + K1X_PADCONF(GPIO_37, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_tx */ + K1X_PADCONF(GPIO_38, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_tx_d2 */ + K1X_PADCONF(GPIO_39, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_tx_d3 */ + K1X_PADCONF(GPIO_40, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_tx_en */ + K1X_PADCONF(GPIO_41, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_mdc */ + K1X_PADCONF(GPIO_42, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_mdio */ + K1X_PADCONF(GPIO_43, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_int_n */ + K1X_PADCONF(GPIO_46, MUX_MODE1, (EDGE_NONE | PULL_DIS | PAD_1V8_DS2)) /* gmac1_clk_ref */ + >; + }; + + pinctrl_can_0: can_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_75, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* can_tx0 */ + K1X_PADCONF(GPIO_76, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_3V_DS4)) /* can_rx0 */ + >; + }; + + pinctrl_can_1: can_1_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_54, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* can_tx0 */ + K1X_PADCONF(GPIO_55, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* can_rx0 */ + >; + }; + + pinctrl_hdmi_0: hdmi_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_86, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* hdmi_tx_hscl */ + K1X_PADCONF(GPIO_87, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* hdmi_tx_hsda */ + K1X_PADCONF(GPIO_88, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* hdmi_tx_hcec */ + K1X_PADCONF(GPIO_89, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* hdmi_tx_pdp */ + >; + }; + + pinctrl_hdmi_1: hdmi_1_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_59, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* hdmi_tx_hscl */ + K1X_PADCONF(GPIO_60, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* hdmi_tx_hsda */ + K1X_PADCONF(GPIO_61, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* hdmi_tx_hcec */ + K1X_PADCONF(GPIO_62, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* hdmi_tx_pdp */ + >; + }; + + pinctrl_spi_lcd_0: spi_lcd_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_86, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* dclk */ + K1X_PADCONF(GPIO_87, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* dcx */ + K1X_PADCONF(GPIO_88, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* din */ + K1X_PADCONF(GPIO_89, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* dout0 */ + K1X_PADCONF(GPIO_90, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* dout1 */ + K1X_PADCONF(GPIO_91, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* dsi_te */ + K1X_PADCONF(GPIO_92, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* smpn_rstb */ + >; + }; + + pinctrl_spi_lcd_1: spi_lcd_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(PRI_TDI, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* dclk */ + K1X_PADCONF(PRI_TMS, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* dcx */ + K1X_PADCONF(PRI_TCK, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* din */ + K1X_PADCONF(PRI_TDO, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* dout0 */ + K1X_PADCONF(GPIO_74, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* dout1 */ + K1X_PADCONF(GPIO_114, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* dsi_te */ + K1X_PADCONF(GPIO_63, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* smpn_rstb */ + >; + }; + + pinctrl_camera0: camera0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_53, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* cam_mclk0 */ + >; + }; + + pinctrl_camera1: camera1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_58, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* cam_mclk1 */ + >; + }; + + pinctrl_camera2: camera2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_120, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* cam_mclk2 */ + >; + }; + + pinctrl_pmic: pmic_grp { + pinctrl-single,pins = < + K1X_PADCONF(VCXO_EN, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* vcxo_en */ + K1X_PADCONF(DVL0, MUX_MODE0, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* dvl0 */ + K1X_PADCONF(DVL1, MUX_MODE0, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* dvl1 */ + >; + }; + + pinctrl_mn_clk_0: mn_clk_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_92, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* mn_clk */ + >; + }; + + pinctrl_mn_clk_1: mn_clk_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_81, MUX_MODE4, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* mn_clk */ + >; + }; + + pinctrl_mn_clk_2: mn_clk_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_44, MUX_MODE1, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* mn_clk */ + >; + }; + + pinctrl_mn_clk_3: mn_clk_3_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_20, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* mn_clk */ + >; + }; + + pinctrl_mn_clk_4: mn_clk_4_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_23, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* mn_clk */ + >; + }; + + pinctrl_mn_clk_5: mn_clk_5_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_32, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* mn_clk */ + >; + }; + + pinctrl_mn_clk2_0: mn_clk2_0_grp { + pinctrl-single,pins = < + K1X_PADCONF(GPIO_91, MUX_MODE1, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* mn_clk2 */ + >; + }; + + pinctrl_mn_clk2_1: mn_clk2_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_85, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* mn_clk2 */ + >; + }; + + pinctrl_vcxo_0: vcxo_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(DVL0, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* vcxo_req */ + K1X_PADCONF(DVL1, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* vcxo_out */ + >; + }; + + pinctrl_vcxo_1: vcxo_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_16, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* vcxo_req */ + K1X_PADCONF(GPIO_17, MUX_MODE3, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* vcxo_out */ + >; + }; + + pinctrl_vcxo_2: vcxo_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_89, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* vcxo_req */ + K1X_PADCONF(GPIO_90, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* vcxo_out */ + >; + }; + + pinctrl_vcxo_out_0: vcxo_out_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_91, MUX_MODE2, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* vcxo_out_0 */ + >; + }; + + pinctrl_vcxo_out_1: vcxo_out_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_12, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* vcxo_out */ + >; + }; + + pinctrl_32k_out_0: 32k_out_0_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_21, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* 32k_out */ + >; + }; + + pinctrl_32k_out_1: 32k_out_1_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_31, MUX_MODE3, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* 32k_out */ + >; + }; + + pinctrl_32k_out_2: 32k_out_2_grp { + pinctrl-single,pins =< + K1X_PADCONF(GPIO_28, MUX_MODE4, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* 32k_out */ + >; + }; + + pinctrl_pri: pri_grp { + pinctrl-single,pins =< + K1X_PADCONF(PRI_TDI, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* pri_tdi */ + K1X_PADCONF(PRI_TMS, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* pri_tms */ + K1X_PADCONF(PRI_TCK, MUX_MODE0, (EDGE_NONE | PULL_DOWN | PAD_1V8_DS2)) /* pri_tck */ + K1X_PADCONF(PRI_TDO, MUX_MODE0, (EDGE_NONE | PULL_UP | PAD_1V8_DS2)) /* pri_tck */ + >; + }; +}; + diff --git a/patch/kernel/archive/spacemit-6.1/dt/lcd_gx09inx101_mipi.dtsi b/patch/kernel/archive/spacemit-6.1/dt/lcd_gx09inx101_mipi.dtsi new file mode 100644 index 0000000000..5fac6d4a9a --- /dev/null +++ b/patch/kernel/archive/spacemit-6.1/dt/lcd_gx09inx101_mipi.dtsi @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { lcds: lcds { + lcd_gx09inx101_mipi: lcd_gx09inx101_mipi { + dsi-work-mode = <1>; /* video burst mode*/ + dsi-lane-number = <4>; + dsi-color-format = "rgb888"; + width-mm = <142>; + height-mm = <228>; + use-dcs-write; + + /*mipi info*/ + height = <1920>; + width = <1200>; + hfp = <80>; + hbp = <40>; + hsync = <10>; + vfp = <20>; + vbp = <16>; + vsync = <4>; + fps = <60>; + work-mode = <0>; + rgb-mode = <3>; + lane-number = <4>; + phy-bit-clock = <1000000000>; + phy-esc-clock = <76800000>; + split-enable = <0>; + eotp-enable = <0>; + burst-mode = <2>; + esd-check-enable = <0>; + + /* DSI_CMD, DSI_MODE, timeout, len, cmd */ + initial-command = [ + 39 01 00 02 B0 01 + 39 01 00 02 C3 4F + 39 01 00 02 C4 40 + 39 01 00 02 C5 40 + 39 01 00 02 C6 40 + 39 01 00 02 C7 40 + 39 01 00 02 C8 4D + 39 01 00 02 C9 52 + 39 01 00 02 CA 51 + 39 01 00 02 CD 5D + 39 01 00 02 CE 5B + 39 01 00 02 CF 4B + 39 01 00 02 D0 49 + 39 01 00 02 D1 47 + 39 01 00 02 D2 45 + 39 01 00 02 D3 41 + 39 01 00 02 D7 50 + 39 01 00 02 D8 40 + 39 01 00 02 D9 40 + 39 01 00 02 DA 40 + 39 01 00 02 DB 40 + 39 01 00 02 DC 4E + 39 01 00 02 DD 52 + 39 01 00 02 DE 51 + 39 01 00 02 E1 5E + 39 01 00 02 E2 5C + 39 01 00 02 E3 4C + 39 01 00 02 E4 4A + 39 01 00 02 E5 48 + 39 01 00 02 E6 46 + 39 01 00 02 E7 42 + 39 01 00 02 B0 03 + 39 01 00 02 BE 03 + 39 01 00 02 CC 44 + 39 01 00 02 C8 07 + 39 01 00 02 C9 05 + 39 01 00 02 CA 42 + 39 01 00 02 CD 3E + 39 01 00 02 CF 60 + 39 01 00 02 D2 04 + 39 01 00 02 D3 04 + 39 01 00 02 D4 01 + 39 01 00 02 D5 00 + 39 01 00 02 D6 03 + 39 01 00 02 D7 04 + 39 01 00 02 D9 01 + 39 01 00 02 DB 01 + 39 01 00 02 E4 F0 + 39 01 00 02 E5 0A + 39 01 00 02 B0 00 + 39 01 00 02 BD 50 + 39 01 00 02 C2 08 + 39 01 00 02 C4 10 + 39 01 00 02 CC 00 + // 39 01 00 02 B2 41 // BIST pattern + 39 01 00 02 B0 02 + 39 01 00 02 C0 00 + 39 01 00 02 C1 0A + 39 01 00 02 C2 20 + 39 01 00 02 C3 24 + 39 01 00 02 C4 23 + 39 01 00 02 C5 29 + 39 01 00 02 C6 23 + 39 01 00 02 C7 1C + 39 01 00 02 C8 19 + 39 01 00 02 C9 17 + 39 01 00 02 CA 17 + 39 01 00 02 CB 18 + 39 01 00 02 CC 1A + 39 01 00 02 CD 1E + 39 01 00 02 CE 20 + 39 01 00 02 CF 23 + 39 01 00 02 D0 07 + 39 01 00 02 D1 00 + 39 01 00 02 D2 00 + 39 01 00 02 D3 0A + 39 01 00 02 D4 13 + 39 01 00 02 D5 1C + 39 01 00 02 D6 1A + 39 01 00 02 D7 13 + 39 01 00 02 D8 17 + 39 01 00 02 D9 1C + 39 01 00 02 DA 19 + 39 01 00 02 DB 17 + 39 01 00 02 DC 17 + 39 01 00 02 DD 18 + 39 01 00 02 DE 1A + 39 01 00 02 DF 1E + 39 01 00 02 E0 20 + 39 01 00 02 E1 23 + 39 01 00 02 E2 07 + 39 01 F0 01 11 + 39 01 28 01 29 + ]; + sleep-in-command = [ + 39 01 78 01 28 + 39 01 78 01 10 + ]; + sleep-out-command = [ + 39 01 96 01 11 + 39 01 32 01 29 + ]; + read-id-command = [ + 37 01 00 01 05 + 14 01 00 05 fb fc fd fe ff + ]; + + display-timings { + timing0 { + clock-frequency = <143000000>; + hactive = <1200>; + hfront-porch = <80>; + hback-porch = <40>; + hsync-len = <10>; + vactive = <1920>; + vfront-porch = <20>; + vback-porch = <16>; + vsync-len = <4>; + vsync-active = <1>; + hsync-active = <1>; + }; + }; + }; +};};