From c51857b67a28593d086746532caa85c8fa46d907 Mon Sep 17 00:00:00 2001 From: Oleg Date: Mon, 14 Feb 2022 21:05:37 +0300 Subject: [PATCH] fix USB and SATA p2 (#3486) --- patch/kernel/media-edge/00-v90-rk356x.patch | 662 ++++++++++-------- patch/kernel/media-edge/00-v91-rk3566.patch | 26 + patch/kernel/media-edge/00-v91-rk3568.patch | 69 ++ .../kernel/media-edge/00-v91-rk356x-vpu.patch | 32 - patch/kernel/media-edge/00-v92-rk356x.patch | 184 +++++ ...tch => 00-v95-rk3566-firefly-roc-pc.patch} | 279 +++++--- ...tch => 00-v95-rk3568-firefly-roc-pc.patch} | 462 ++++++++++-- 7 files changed, 1195 insertions(+), 519 deletions(-) create mode 100644 patch/kernel/media-edge/00-v91-rk3566.patch create mode 100644 patch/kernel/media-edge/00-v91-rk3568.patch delete mode 100644 patch/kernel/media-edge/00-v91-rk356x-vpu.patch create mode 100644 patch/kernel/media-edge/00-v92-rk356x.patch rename patch/kernel/media-edge/{00-v99-rk3566-firefly-roc-pc.patch => 00-v95-rk3566-firefly-roc-pc.patch} (78%) rename patch/kernel/media-edge/{00-v99-rk3568-firefly-roc-pc.patch => 00-v95-rk3568-firefly-roc-pc.patch} (58%) diff --git a/patch/kernel/media-edge/00-v90-rk356x.patch b/patch/kernel/media-edge/00-v90-rk356x.patch index 5898c05bc1..00ff6a1b37 100644 --- a/patch/kernel/media-edge/00-v90-rk356x.patch +++ b/patch/kernel/media-edge/00-v90-rk356x.patch @@ -1,9 +1,75 @@ --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -247,6 +247,98 @@ +@@ -39,6 +39,10 @@ + serial7 = &uart7; + serial8 = &uart8; + serial9 = &uart9; ++ spi0 = &spi0; ++ spi1 = &spi1; ++ spi2 = &spi2; ++ spi3 = &spi3; + }; + + cpus { +@@ -89,39 +93,45 @@ + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; +- opp-microvolt = <900000 900000 1150000>; ++ opp-microvolt = <825000 825000 1150000>; + clock-latency-ns = <40000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; +- opp-microvolt = <900000 900000 1150000>; ++ opp-microvolt = <825000 825000 1150000>; ++ clock-latency-ns = <40000>; + }; + + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; +- opp-microvolt = <900000 900000 1150000>; ++ opp-microvolt = <825000 825000 1150000>; ++ clock-latency-ns = <40000>; + opp-suspend; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; +- opp-microvolt = <900000 900000 1150000>; ++ opp-microvolt = <825000 825000 1150000>; ++ clock-latency-ns = <40000>; + }; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; +- opp-microvolt = <900000 900000 1150000>; ++ opp-microvolt = <925000 925000 1150000>; ++ clock-latency-ns = <40000>; + }; + + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; +- opp-microvolt = <975000 975000 1150000>; ++ opp-microvolt = <1000000 1000000 1150000>; ++ clock-latency-ns = <40000>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1050000 1050000 1150000>; ++ clock-latency-ns = <40000>; }; }; +@@ -244,6 +254,105 @@ + scmi_shmem: sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x100>; ++ }; ++ }; ++ + sata1: sata@fc400000 { + compatible = "snps,dwc-ahci"; + reg = <0 0xfc400000 0 0x1000>; @@ -49,15 +115,20 @@ + compatible = "snps,dwc3"; + reg = <0x0 0xfcc00000 0x0 0x400000>; + interrupts = ; -+ dr_mode = "host"; ++// dr_mode = "host"; ++ dr_mode = "otg"; ++ phys = <&u2phy0_otg>, <&combphy0 PHY_TYPE_USB3>; ++ phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3568_PD_PIPE>; + resets = <&cru SRST_USB3OTG0>; + reset-names = "usb3-otg"; + snps,dis_enblslpm_quirk; ++ snps,dis-u1u2-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; ++ snps,dis_rxdet_inp3_quirk; + snps,xhci-trb-ent-quirk; + status = "disabled"; + }; @@ -71,8 +142,8 @@ + "bus_clk", "pipe_clk"; + #address-cells = <2>; + #size-cells = <2>; -+ assigned-clocks = <&cru CLK_PCIEPHY1_REF>; -+ assigned-clock-rates = <25000000>; ++// assigned-clocks = <&cru CLK_PCIEPHY1_REF>; ++// assigned-clock-rates = <25000000>; + ranges; + status = "disabled"; + @@ -89,21 +160,21 @@ + reset-names = "usb3-host"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; -+ snps,dis_u2_susphy_quirk; ++// snps,dis_u2_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; ++ snps,dis_rxdet_inp3_quirk; ++ snps,xhci-trb-ent-quirk; + status = "disabled"; -+ }; -+ }; -+ - gic: interrupt-controller@fd400000 { - compatible = "arm,gic-v3"; - reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ -@@ -313,10 +405,25 @@ + }; + }; + +@@ -313,11 +422,32 @@ }; }; + pipegrf: syscon@fdc50000 { ++ compatible = "rockchip,rk3568-pipe-grf", "syscon"; + reg = <0x0 0xfdc50000 0x0 0x1000>; + }; + @@ -111,6 +182,11 @@ compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; reg = <0x0 0xfdc60000 0x0 0x10000>; }; + ++ pipe_phy_grf0: syscon@fdc70000 { ++ compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; ++ reg = <0x0 0xfdc70000 0x0 0x1000>; ++ }; + + pipe_phy_grf1: syscon@fdc80000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; @@ -122,10 +198,23 @@ + reg = <0x0 0xfdc90000 0x0 0x1000>; + }; + - ++ usb2phy0_grf: syscon@fdca0000 { compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; -@@ -365,6 +472,7 @@ + reg = <0x0 0xfdca0000 0x0 0x8000>; +@@ -326,6 +456,11 @@ + usb2phy1_grf: syscon@fdca8000 { + compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; + reg = <0x0 0xfdca8000 0x0 0x8000>; ++ }; ++ ++ pcie30_phy_grf: syscon@fdcb8000 { ++ compatible = "rockchip,pcie30-phy-grf", "syscon"; ++ reg = <0x0 0xfdcb8000 0x0 0x10000>; + }; + + pmucru: clock-controller@fdd00000 { +@@ -365,6 +500,7 @@ clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac0 0>, <&dmac0 1>; @@ -133,7 +222,49 @@ pinctrl-0 = <&uart0_xfer>; pinctrl-names = "default"; reg-io-width = <4>; -@@ -573,7 +681,8 @@ +@@ -498,17 +634,38 @@ + gpu: gpu@fde60000 { + compatible = "rockchip,rk3568-mali", "arm,mali-bifrost"; + reg = <0x0 0xfde60000 0x0 0x4000>; +- + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + clocks = <&scmi_clk 1>, <&cru CLK_GPU>; +- clock-names = "core", "bus"; ++ clock-names = "gpu", "bus"; ++ #cooling-cells = <2>; + operating-points-v2 = <&gpu_opp_table>; +- #cooling-cells = <2>; + power-domains = <&power RK3568_PD_GPU>; + status = "disabled"; ++ }; ++ ++ vpu: video-codec@fdea0400 { ++ compatible = "rockchip,rk3328-vpu"; ++ reg = <0x0 0xfdea0000 0x0 0x800>; ++ interrupts = ; ++ interrupt-names = "vdpu"; ++ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; ++ clock-names = "aclk", "hclk"; ++ iommus = <&vdpu_mmu>; ++ power-domains = <&power RK3568_PD_VPU>; ++ }; ++ ++ vdpu_mmu: iommu@fdea0800 { ++ compatible = "rockchip,rk3568-iommu"; ++ reg = <0x0 0xfdea0800 0x0 0x40>; ++ interrupts = ; ++ interrupt-names = "vdpu_mmu"; ++ clock-names = "aclk", "iface"; ++ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; ++ power-domains = <&power RK3568_PD_VPU>; ++ #iommu-cells = <0>; + }; + + sdmmc2: mmc@fe000000 { +@@ -573,7 +730,8 @@ }; vop: vop@fe040000 { @@ -143,7 +274,7 @@ interrupts = ; clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2"; -@@ -770,6 +879,61 @@ +@@ -770,6 +928,164 @@ qos_vop_m1: qos@fe1a8100 { compatible = "rockchip,rk3568-qos", "syscon"; reg = <0x0 0xfe1a8100 0x0 0x20>; @@ -201,11 +332,114 @@ + interrupt-parent = <&gic>; + interrupts = ; + }; ++ }; + ++ pcie3x1: pcie@fe270000 { ++ compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ bus-range = <0x10 0x1f>; ++ clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, ++ <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, ++ <&cru CLK_PCIE30X1_AUX_NDFT>; ++ clock-names = "aclk_mst", "aclk_slv", ++ "aclk_dbi", "pclk", "aux"; ++ device_type = "pci"; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "sys", "pmc", "msi", "legacy", "err"; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie3x1_intc 0>, ++ <0 0 0 2 &pcie3x1_intc 1>, ++ <0 0 0 3 &pcie3x1_intc 2>, ++ <0 0 0 4 &pcie3x1_intc 3>; ++ linux,pci-domain = <1>; ++ num-ib-windows = <6>; ++ num-ob-windows = <2>; ++ max-link-speed = <3>; ++ msi-map = <0x1000 &gic 0x1000 0x1000>; ++ num-lanes = <1>; ++ phys = <&pcie30phy>; ++ phy-names = "pcie-phy"; ++ power-domains = <&power RK3568_PD_PIPE>; ++ ranges = <0x00000800 0x0 0x40000000 0x3 0x40000000 0x0 0x800000 ++ 0x81000000 0x0 0x40800000 0x3 0x40800000 0x0 0x100000 ++ 0x83000000 0x0 0x40900000 0x3 0x40900000 0x0 0x3f700000>; ++ reg = <0x3 0xc0400000 0x0 0x400000>, ++ <0x0 0xfe270000 0x0 0x10000>; ++ reg-names = "dbi", "apb", "config"; ++ resets = <&cru SRST_PCIE30X1_POWERUP>; ++ reset-names = "pipe"; ++ /* rockchip,bifurcation; lane1 when using 1+1 */ ++ status = "disabled"; ++ ++ pcie3x1_intc: legacy-interrupt-controller { ++ interrupt-controller; ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-parent = <&gic>; ++ interrupts = ; ++ }; ++ }; ++ ++ pcie3x2: pcie@fe280000 { ++ compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ bus-range = <0x20 0x2f>; ++ clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, ++ <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, ++ <&cru CLK_PCIE30X2_AUX_NDFT>; ++ clock-names = "aclk_mst", "aclk_slv", ++ "aclk_dbi", "pclk", "aux"; ++ device_type = "pci"; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "sys", "pmc", "msi", "legacy", "err"; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, ++ <0 0 0 2 &pcie3x2_intc 1>, ++ <0 0 0 3 &pcie3x2_intc 2>, ++ <0 0 0 4 &pcie3x2_intc 3>; ++ linux,pci-domain = <2>; ++ num-ib-windows = <6>; ++ num-ob-windows = <2>; ++ max-link-speed = <3>; ++ msi-map = <0x2000 &gic 0x2000 0x1000>; ++ num-lanes = <2>; ++ phys = <&pcie30phy>; ++ phy-names = "pcie-phy"; ++ power-domains = <&power RK3568_PD_PIPE>; ++ ranges = <0x00000800 0x0 0x80000000 0x3 0x80000000 0x0 0x800000 ++ 0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000 ++ 0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>; ++ reg = <0x3 0xc0800000 0x0 0x400000>, ++ <0x0 0xfe280000 0x0 0x10000>; ++ reg-names = "dbi", "apb", "config"; ++ resets = <&cru SRST_PCIE30X2_POWERUP>; ++ reset-names = "pipe"; ++ /* rockchip,bifurcation; lane0 when using 1+1 */ ++ status = "disabled"; ++ ++ pcie3x2_intc: legacy-interrupt-controller { ++ interrupt-controller; ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-parent = <&gic>; ++ interrupts = ; ++ }; }; sdmmc0: mmc@fe2b0000 { -@@ -797,6 +961,17 @@ +@@ -797,6 +1113,17 @@ max-frequency = <150000000>; resets = <&cru SRST_SDMMC1>; reset-names = "reset"; @@ -223,7 +457,74 @@ status = "disabled"; }; -@@ -971,6 +1146,7 @@ +@@ -964,6 +1291,66 @@ + clock-names = "tclk", "pclk"; + }; + ++ spi0: spi@fe610000 { ++ compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; ++ reg = <0x0 0xfe610000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; ++ clock-names = "spiclk", "apb_pclk"; ++ dmas = <&dmac0 20>, <&dmac0 21>; ++ dma-names = "tx", "rx"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi1: spi@fe620000 { ++ compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; ++ reg = <0x0 0xfe620000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; ++ clock-names = "spiclk", "apb_pclk"; ++ dmas = <&dmac0 22>, <&dmac0 23>; ++ dma-names = "tx", "rx"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi2: spi@fe630000 { ++ compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; ++ reg = <0x0 0xfe630000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; ++ clock-names = "spiclk", "apb_pclk"; ++ dmas = <&dmac0 24>, <&dmac0 25>; ++ dma-names = "tx", "rx"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi3: spi@fe640000 { ++ compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; ++ reg = <0x0 0xfe640000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; ++ clock-names = "spiclk", "apb_pclk"; ++ dmas = <&dmac0 26>, <&dmac0 27>; ++ dma-names = "tx", "rx"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + uart1: serial@fe650000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe650000 0x0 0x100>; +@@ -971,6 +1358,7 @@ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac0 2>, <&dmac0 3>; @@ -231,7 +532,7 @@ pinctrl-0 = <&uart1m0_xfer>; pinctrl-names = "default"; reg-io-width = <4>; -@@ -985,6 +1161,7 @@ +@@ -985,6 +1373,7 @@ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac0 4>, <&dmac0 5>; @@ -239,7 +540,7 @@ pinctrl-0 = <&uart2m0_xfer>; pinctrl-names = "default"; reg-io-width = <4>; -@@ -999,6 +1176,7 @@ +@@ -999,6 +1388,7 @@ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac0 6>, <&dmac0 7>; @@ -247,7 +548,7 @@ pinctrl-0 = <&uart3m0_xfer>; pinctrl-names = "default"; reg-io-width = <4>; -@@ -1013,6 +1191,7 @@ +@@ -1013,6 +1403,7 @@ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac0 8>, <&dmac0 9>; @@ -255,7 +556,7 @@ pinctrl-0 = <&uart4m0_xfer>; pinctrl-names = "default"; reg-io-width = <4>; -@@ -1027,6 +1206,7 @@ +@@ -1027,6 +1418,7 @@ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac0 10>, <&dmac0 11>; @@ -263,7 +564,7 @@ pinctrl-0 = <&uart5m0_xfer>; pinctrl-names = "default"; reg-io-width = <4>; -@@ -1041,6 +1221,7 @@ +@@ -1041,6 +1433,7 @@ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac0 12>, <&dmac0 13>; @@ -271,7 +572,7 @@ pinctrl-0 = <&uart6m0_xfer>; pinctrl-names = "default"; reg-io-width = <4>; -@@ -1055,6 +1236,7 @@ +@@ -1055,6 +1448,7 @@ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac0 14>, <&dmac0 15>; @@ -279,7 +580,7 @@ pinctrl-0 = <&uart7m0_xfer>; pinctrl-names = "default"; reg-io-width = <4>; -@@ -1069,6 +1251,7 @@ +@@ -1069,6 +1463,7 @@ clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac0 16>, <&dmac0 17>; @@ -287,7 +588,7 @@ pinctrl-0 = <&uart8m0_xfer>; pinctrl-names = "default"; reg-io-width = <4>; -@@ -1083,6 +1266,7 @@ +@@ -1083,6 +1478,7 @@ clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac0 18>, <&dmac0 19>; @@ -295,10 +596,39 @@ pinctrl-0 = <&uart9m0_xfer>; pinctrl-names = "default"; reg-io-width = <4>; -@@ -1370,6 +1554,38 @@ +@@ -1370,6 +1766,67 @@ }; }; ++ pcie30phy: phy@fe8c0000 { ++ compatible = "rockchip,rk3568-pcie3-phy"; ++ reg = <0x0 0xfe8c0000 0x0 0x20000>; ++ #phy-cells = <0>; ++ clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>, ++ <&cru PCLK_PCIE30PHY>; ++ clock-names = "refclk_m", "refclk_n", "pclk"; ++ resets = <&cru SRST_PCIE30PHY>; ++ reset-names = "phy"; ++ rockchip,phy-grf = <&pcie30_phy_grf>; ++ status = "disabled"; ++ }; ++ ++ combphy0: phy@fe820000 { ++ compatible = "rockchip,rk3568-naneng-combphy"; ++ reg = <0x0 0xfe820000 0x0 0x100>; ++ #phy-cells = <1>; ++ assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; ++ assigned-clock-rates = <100000000>; ++ clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>, ++ <&cru PCLK_PIPE>; ++ clock-names = "ref", "apb", "pipe"; ++ resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; ++ reset-names = "combphy-apb", "combphy"; ++ rockchip,pipe-grf = <&pipegrf>; ++ rockchip,pipe-phy-grf = <&pipe_phy_grf0>; ++ status = "disabled"; ++ }; ++ + combphy1: phy@fe830000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe830000 0x0 0x100>; @@ -335,281 +665,3 @@ compatible = "rockchip,rk3568-pinctrl"; rockchip,grf = <&grf>; ---- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi -@@ -7,6 +7,21 @@ - - / { - compatible = "rockchip,rk3568"; -+ -+ sata0: sata@fc000000 { -+ compatible = "snps,dwc-ahci"; -+ reg = <0 0xfc000000 0 0x1000>; -+ clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>, -+ <&cru CLK_SATA0_RXOOB>; -+ clock-names = "sata", "pmalive", "rxoob"; -+ interrupts = ; -+ interrupt-names = "hostc"; -+ phys = <&combphy0 PHY_TYPE_SATA>; -+ phy-names = "sata-phy"; -+ ports-implemented = <0x1>; -+ power-domains = <&power RK3568_PD_PIPE>; -+ status = "disabled"; -+ }; - - qos_pcie3x1: qos@fe190080 { - compatible = "rockchip,rk3568-qos", "syscon"; -@@ -71,6 +86,22 @@ - queue0 {}; - }; - }; -+ -+// combphy0: phy@fe820000 { -+// compatible = "rockchip,rk3568-naneng-combphy"; -+// reg = <0x0 0xfe820000 0x0 0x100>; -+// #phy-cells = <1>; -+// assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; -+// assigned-clock-rates = <100000000>; -+// clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>, -+// <&cru PCLK_PIPE>; -+// clock-names = "ref", "apb", "pipe"; -+// resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; -+// reset-names = "combphy-apb", "combphy"; -+// rockchip,pipe-grf = <&pipegrf>; -+// rockchip,pipe-phy-grf = <&pipe_phy_grf0>; -+// status = "disabled"; -+// }; - }; - - &cpu0_opp_table { -@@ -78,6 +109,10 @@ - opp-hz = /bits/ 64 <1992000000>; - opp-microvolt = <1150000 1150000 1150000>; - }; -+}; -+ -+&pipegrf { -+ compatible = "rockchip,rk3568-pipegrf", "syscon"; - }; - - &power { -@@ -95,3 +130,8 @@ - #power-domain-cells = <0>; - }; - }; -+ -+&usbdrd_dwc3 { -+ phys = <&u2phy0_otg>, <&combphy0 PHY_TYPE_USB3>; -+ phy-names = "usb2-phy", "usb3-phy"; -+}; - ---- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi -@@ -4,6 +4,10 @@ - - / { - compatible = "rockchip,rk3566"; -+}; -+ -+&pipegrf { -+ compatible = "rockchip,rk3566-pipegrf", "syscon"; - }; - - &power { -@@ -18,3 +22,11 @@ - #power-domain-cells = <0>; - }; - }; -+ -+&usbdrd_dwc3 { -+ phys = <&u2phy0_otg>; -+ phy-names = "usb2-phy"; -+ extcon = <&u2phy0>; -+ maximum-speed = "high-speed"; -+ snps,dis_u2_susphy_quirk; -+}; - ---- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c -+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c -@@ -16,6 +16,7 @@ - #include - #include - #include -+#include - #include - - #define BIT_WRITEABLE_SHIFT 16 - ---- a/drivers/usb/dwc3/core.h -+++ b/drivers/usb/dwc3/core.h -@@ -258,6 +258,7 @@ - /* Global User Control 1 Register */ - #define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT BIT(31) - #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) -+#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT(26) - #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) - #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17) - - ---- a/drivers/usb/dwc3/core.c -+++ b/drivers/usb/dwc3/core.c -@@ -1087,6 +1087,10 @@ - - if (dwc->parkmode_disable_ss_quirk) - reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; -+ -+ if (dwc->maximum_speed == USB_SPEED_HIGH || -+ dwc->maximum_speed == USB_SPEED_FULL) -+ reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; - - dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); - } - ---- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c -+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c -@@ -10,9 +10,12 @@ - - #include - #include -+#include -+#include - #include - #include - #include -+#include - #include - #include - #include -@@ -36,10 +39,12 @@ - #define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) - #define PCIE_L0S_ENTRY 0x11 - #define PCIE_CLIENT_GENERAL_CONTROL 0x0 -+#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c - #define PCIE_CLIENT_GENERAL_DEBUG 0x104 --#define PCIE_CLIENT_HOT_RESET_CTRL 0x180 -+#define PCIE_CLIENT_HOT_RESET_CTRL 0x180 - #define PCIE_CLIENT_LTSSM_STATUS 0x300 --#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) -+#define PCIE_LEGACY_INT_ENABLE GENMASK(7, 0) -+#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) - #define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) - - struct rockchip_pcie { -@@ -51,6 +56,7 @@ - struct reset_control *rst; - struct gpio_desc *rst_gpio; - struct regulator *vpcie3v3; -+ struct irq_domain *irq_domain; - }; - - static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, -@@ -63,6 +69,68 @@ - u32 val, u32 reg) - { - writel_relaxed(val, rockchip->apb_base + reg); -+} -+ -+static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc) -+{ -+ struct irq_chip *chip = irq_desc_get_chip(desc); -+ struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc); -+ struct device *dev = rockchip->pci.dev; -+ u32 reg; -+ u32 hwirq; -+ u32 virq; -+ -+ chained_irq_enter(chip, desc); -+ -+ reg = rockchip_pcie_readl_apb(rockchip, 0x8); -+ -+ while (reg) { -+ hwirq = ffs(reg) - 1; -+ reg &= ~BIT(hwirq); -+ -+ virq = irq_find_mapping(rockchip->irq_domain, hwirq); -+ if (virq) -+ generic_handle_irq(virq); -+ else -+ dev_err(dev, "unexpected IRQ, INT%d\n", hwirq); -+ } -+ -+ chained_irq_exit(chip, desc); -+} -+ -+static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq, -+ irq_hw_number_t hwirq) -+{ -+ irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); -+ irq_set_chip_data(irq, domain->host_data); -+ -+ return 0; -+} -+ -+static const struct irq_domain_ops intx_domain_ops = { -+ .map = rockchip_pcie_intx_map, -+}; -+ -+static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip) -+{ -+ struct device *dev = rockchip->pci.dev; -+ struct device_node *intc; -+ -+ intc = of_get_child_by_name(dev->of_node, "legacy-interrupt-controller"); -+ if (!intc) { -+ dev_err(dev, "missing child interrupt-controller node\n"); -+ return -EINVAL; -+ } -+ -+ rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX, -+ &intx_domain_ops, rockchip); -+ of_node_put(intc); -+ if (!rockchip->irq_domain) { -+ dev_err(dev, "failed to get a INTx IRQ domain\n"); -+ return -EINVAL; -+ } -+ -+ return 0; - } - - static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) -@@ -111,9 +179,27 @@ - { - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); -- u32 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); -+ struct device *dev = rockchip->pci.dev; -+ int irq, ret; -+ u32 val; -+ -+ irq = of_irq_get_byname(dev->of_node, "legacy"); -+ if (irq < 0) -+ return irq; -+ -+ irq_set_chained_handler_and_data(irq, rockchip_pcie_legacy_int_handler, rockchip); -+ -+ ret = rockchip_pcie_init_irq_domain(rockchip); -+ if (ret < 0) -+ dev_err(dev, "failed to init irq domain\n"); -+ -+ /* enable legacy interrupts */ -+ val = HIWORD_UPDATE_BIT(PCIE_LEGACY_INT_ENABLE); -+ val &= ~PCIE_LEGACY_INT_ENABLE; -+ rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_INTR_MASK_LEGACY); - - /* LTSSM enable control mode */ -+ val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); - rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); - - rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_RC_MODE, -@@ -214,6 +300,10 @@ - - rockchip->pci.dev = dev; - rockchip->pci.ops = &dw_pcie_ops; -+ -+ ret = dma_set_mask(rockchip->pci.dev, DMA_BIT_MASK(32)); -+ if (ret) -+ dev_warn(rockchip->pci.dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); - - pp = &rockchip->pci.pp; - pp->ops = &rockchip_pcie_host_ops; - diff --git a/patch/kernel/media-edge/00-v91-rk3566.patch b/patch/kernel/media-edge/00-v91-rk3566.patch new file mode 100644 index 0000000000..12a9c1f637 --- /dev/null +++ b/patch/kernel/media-edge/00-v91-rk3566.patch @@ -0,0 +1,26 @@ +--- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi +@@ -4,6 +4,10 @@ + + / { + compatible = "rockchip,rk3566"; ++}; ++ ++&pipegrf { ++ compatible = "rockchip,rk3566-pipegrf", "syscon"; + }; + + &power { +@@ -22,3 +26,11 @@ + &vop { + compatible = "rockchip,rk3566-vop"; + }; ++ ++&usbdrd_dwc3 { ++ phys = <&u2phy0_otg>; ++ phy-names = "usb2-phy"; ++ extcon = <&u2phy0>; ++ maximum-speed = "high-speed"; ++ snps,dis_u2_susphy_quirk; ++}; + diff --git a/patch/kernel/media-edge/00-v91-rk3568.patch b/patch/kernel/media-edge/00-v91-rk3568.patch new file mode 100644 index 0000000000..fc23fc9a62 --- /dev/null +++ b/patch/kernel/media-edge/00-v91-rk3568.patch @@ -0,0 +1,69 @@ +--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +@@ -8,9 +8,19 @@ + / { + compatible = "rockchip,rk3568"; + +- pipe_phy_grf0: syscon@fdc70000 { +- compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; +- reg = <0x0 0xfdc70000 0x0 0x1000>; ++ sata0: sata@fc000000 { ++ compatible = "snps,dwc-ahci"; ++ reg = <0 0xfc000000 0 0x1000>; ++ clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>, ++ <&cru CLK_SATA0_RXOOB>; ++ clock-names = "sata", "pmalive", "rxoob"; ++ interrupts = ; ++ interrupt-names = "hostc"; ++ phys = <&combphy0 PHY_TYPE_SATA>; ++ phy-names = "sata-phy"; ++ ports-implemented = <0x1>; ++ power-domains = <&power RK3568_PD_PIPE>; ++ status = "disabled"; + }; + + qos_pcie3x1: qos@fe190080 { +@@ -76,22 +86,6 @@ + queue0 {}; + }; + }; +- +- combphy0: phy@fe820000 { +- compatible = "rockchip,rk3568-naneng-combphy"; +- reg = <0x0 0xfe820000 0x0 0x100>; +- clocks = <&pmucru CLK_PCIEPHY0_REF>, +- <&cru PCLK_PIPEPHY0>, +- <&cru PCLK_PIPE>; +- clock-names = "ref", "apb", "pipe"; +- assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; +- assigned-clock-rates = <100000000>; +- resets = <&cru SRST_PIPEPHY0>; +- rockchip,pipe-grf = <&pipegrf>; +- rockchip,pipe-phy-grf = <&pipe_phy_grf0>; +- #phy-cells = <1>; +- status = "disabled"; +- }; + }; + + &cpu0_opp_table { +@@ -99,6 +93,10 @@ + opp-hz = /bits/ 64 <1992000000>; + opp-microvolt = <1150000 1150000 1150000>; + }; ++}; ++ ++&pipegrf { ++ compatible = "rockchip,rk3568-pipegrf", "syscon"; + }; + + &power { +@@ -120,3 +118,8 @@ + &vop { + compatible = "rockchip,rk3568-vop"; + }; ++ ++&usbdrd_dwc3 { ++ phys = <&u2phy0_otg>, <&combphy0 PHY_TYPE_USB3>; ++ phy-names = "usb2-phy", "usb3-phy"; ++}; + diff --git a/patch/kernel/media-edge/00-v91-rk356x-vpu.patch b/patch/kernel/media-edge/00-v91-rk356x-vpu.patch deleted file mode 100644 index 491f196ab9..0000000000 --- a/patch/kernel/media-edge/00-v91-rk356x-vpu.patch +++ /dev/null @@ -1,32 +0,0 @@ ---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi -@@ -617,6 +617,28 @@ - #cooling-cells = <2>; - power-domains = <&power RK3568_PD_GPU>; - status = "disabled"; -+ }; -+ -+ vpu: video-codec@fdea0400 { -+ compatible = "rockchip,rk3328-vpu"; -+ reg = <0x0 0xfdea0000 0x0 0x800>; -+ interrupts = ; -+ interrupt-names = "vdpu"; -+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; -+ clock-names = "aclk", "hclk"; -+ iommus = <&vdpu_mmu>; -+ power-domains = <&power RK3568_PD_VPU>; -+ }; -+ -+ vdpu_mmu: iommu@fdea0800 { -+ compatible = "rockchip,rk3568-iommu"; -+ reg = <0x0 0xfdea0800 0x0 0x40>; -+ interrupts = ; -+ interrupt-names = "vdpu_mmu"; -+ clock-names = "aclk", "iface"; -+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; -+ power-domains = <&power RK3568_PD_VPU>; -+ #iommu-cells = <0>; - }; - - sdmmc2: mmc@fe000000 { - diff --git a/patch/kernel/media-edge/00-v92-rk356x.patch b/patch/kernel/media-edge/00-v92-rk356x.patch new file mode 100644 index 0000000000..89197412f2 --- /dev/null +++ b/patch/kernel/media-edge/00-v92-rk356x.patch @@ -0,0 +1,184 @@ +--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c ++++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +@@ -16,6 +16,7 @@ + #include + #include + #include ++#include + #include + + #define BIT_WRITEABLE_SHIFT 16 + +--- a/drivers/usb/dwc3/core.h ++++ b/drivers/usb/dwc3/core.h +@@ -258,6 +258,7 @@ + /* Global User Control 1 Register */ + #define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT BIT(31) + #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) ++#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT(26) + #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) + #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17) + + +--- a/drivers/usb/dwc3/core.c ++++ b/drivers/usb/dwc3/core.c +@@ -1087,6 +1087,10 @@ + + if (dwc->parkmode_disable_ss_quirk) + reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; ++ ++ if (dwc->maximum_speed == USB_SPEED_HIGH || ++ dwc->maximum_speed == USB_SPEED_FULL) ++ reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; + + dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); + } + +--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c ++++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c +@@ -10,9 +10,12 @@ + + #include + #include ++#include ++#include + #include + #include + #include ++#include + #include + #include + #include +@@ -36,10 +39,12 @@ + #define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) + #define PCIE_L0S_ENTRY 0x11 + #define PCIE_CLIENT_GENERAL_CONTROL 0x0 ++#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c + #define PCIE_CLIENT_GENERAL_DEBUG 0x104 +-#define PCIE_CLIENT_HOT_RESET_CTRL 0x180 ++#define PCIE_CLIENT_HOT_RESET_CTRL 0x180 + #define PCIE_CLIENT_LTSSM_STATUS 0x300 +-#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) ++#define PCIE_LEGACY_INT_ENABLE GENMASK(7, 0) ++#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) + #define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) + + struct rockchip_pcie { +@@ -51,6 +56,7 @@ + struct reset_control *rst; + struct gpio_desc *rst_gpio; + struct regulator *vpcie3v3; ++ struct irq_domain *irq_domain; + }; + + static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, +@@ -63,6 +69,68 @@ + u32 val, u32 reg) + { + writel_relaxed(val, rockchip->apb_base + reg); ++} ++ ++static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc) ++{ ++ struct irq_chip *chip = irq_desc_get_chip(desc); ++ struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc); ++ struct device *dev = rockchip->pci.dev; ++ u32 reg; ++ u32 hwirq; ++ u32 virq; ++ ++ chained_irq_enter(chip, desc); ++ ++ reg = rockchip_pcie_readl_apb(rockchip, 0x8); ++ ++ while (reg) { ++ hwirq = ffs(reg) - 1; ++ reg &= ~BIT(hwirq); ++ ++ virq = irq_find_mapping(rockchip->irq_domain, hwirq); ++ if (virq) ++ generic_handle_irq(virq); ++ else ++ dev_err(dev, "unexpected IRQ, INT%d\n", hwirq); ++ } ++ ++ chained_irq_exit(chip, desc); ++} ++ ++static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq, ++ irq_hw_number_t hwirq) ++{ ++ irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); ++ irq_set_chip_data(irq, domain->host_data); ++ ++ return 0; ++} ++ ++static const struct irq_domain_ops intx_domain_ops = { ++ .map = rockchip_pcie_intx_map, ++}; ++ ++static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip) ++{ ++ struct device *dev = rockchip->pci.dev; ++ struct device_node *intc; ++ ++ intc = of_get_child_by_name(dev->of_node, "legacy-interrupt-controller"); ++ if (!intc) { ++ dev_err(dev, "missing child interrupt-controller node\n"); ++ return -EINVAL; ++ } ++ ++ rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX, ++ &intx_domain_ops, rockchip); ++ of_node_put(intc); ++ if (!rockchip->irq_domain) { ++ dev_err(dev, "failed to get a INTx IRQ domain\n"); ++ return -EINVAL; ++ } ++ ++ return 0; + } + + static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) +@@ -111,9 +179,27 @@ + { + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); +- u32 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); ++ struct device *dev = rockchip->pci.dev; ++ int irq, ret; ++ u32 val; ++ ++ irq = of_irq_get_byname(dev->of_node, "legacy"); ++ if (irq < 0) ++ return irq; ++ ++ irq_set_chained_handler_and_data(irq, rockchip_pcie_legacy_int_handler, rockchip); ++ ++ ret = rockchip_pcie_init_irq_domain(rockchip); ++ if (ret < 0) ++ dev_err(dev, "failed to init irq domain\n"); ++ ++ /* enable legacy interrupts */ ++ val = HIWORD_UPDATE_BIT(PCIE_LEGACY_INT_ENABLE); ++ val &= ~PCIE_LEGACY_INT_ENABLE; ++ rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_INTR_MASK_LEGACY); + + /* LTSSM enable control mode */ ++ val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); + rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); + + rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_RC_MODE, +@@ -214,6 +300,10 @@ + + rockchip->pci.dev = dev; + rockchip->pci.ops = &dw_pcie_ops; ++ ++ ret = dma_set_mask(rockchip->pci.dev, DMA_BIT_MASK(32)); ++ if (ret) ++ dev_warn(rockchip->pci.dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); + + pp = &rockchip->pci.pp; + pp->ops = &rockchip_pcie_host_ops; + diff --git a/patch/kernel/media-edge/00-v99-rk3566-firefly-roc-pc.patch b/patch/kernel/media-edge/00-v95-rk3566-firefly-roc-pc.patch similarity index 78% rename from patch/kernel/media-edge/00-v99-rk3566-firefly-roc-pc.patch rename to patch/kernel/media-edge/00-v95-rk3566-firefly-roc-pc.patch index 600f2d457b..25aa8b7c8a 100644 --- a/patch/kernel/media-edge/00-v99-rk3566-firefly-roc-pc.patch +++ b/patch/kernel/media-edge/00-v95-rk3566-firefly-roc-pc.patch @@ -2,7 +2,7 @@ new file mode 100644 index 000000000..fac2db500 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-firefly-roc-pc.dts -@@ -0,0 +1,685 @@ +@@ -0,0 +1,742 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. @@ -11,6 +11,7 @@ index 000000000..fac2db500 + +/dts-v1/; +#include ++#include +#include +#include +#include "rk3566.dtsi" @@ -48,6 +49,27 @@ index 000000000..fac2db500 + }; + }; + ++ firefly_leds: leds { ++ compatible = "gpio-leds"; ++ power_led: power { ++ label = "firefly:blue:power"; ++ linux,default-trigger = "ir-power-click"; ++ default-state = "on"; ++ gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_power>; ++ }; ++ ++ user_led: user { ++ label = "firefly:yellow:user"; ++ linux,default-trigger = "ir-user-click"; ++ default-state = "off"; ++ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_user>; ++ }; ++ }; ++ + sdio_pwrseq: sdio-pwrseq { + status = "okay"; + compatible = "mmc-pwrseq-simple"; @@ -60,6 +82,38 @@ index 000000000..fac2db500 + power-off-delay-us = <5000000>; + }; + ++ pcie30_avdd0v9: pcie30-avdd0v9 { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie30_avdd0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ pcie30_avdd1v8: pcie30-avdd1v8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie30_avdd1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ pcie30_3v3: gpio-regulator { ++ compatible = "regulator-gpio"; ++ regulator-name = "pcie30_3v3"; ++ regulator-min-microvolt = <100000>; ++ regulator-max-microvolt = <3300000>; ++ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; ++ gpios-states = <0x1>; ++ states = <100000 0x0 ++ 3300000 0x1>; ++ }; ++ ++ + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; @@ -89,42 +143,23 @@ index 000000000..fac2db500 + vin-supply = <&vcc5v0_in>; + }; + -+ vcc5v0_usb30_host: vcc5v0_usb30_host { ++ vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_usb30_host"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_usb30_host_en_h>; -+ regulator-always-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc5v0_usb_otg: vcc5v0_usb_otg { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_usb_otg"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_usb_otg_en_h>; -+ regulator-always-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc3v3_pcie: vcc3v3_pcie { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_pcie"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; -+ pinctrl-0 = <&vcc3v3_pcie_en_h>; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_3v3>; ++ pinctrl-0 = <&vcc5v0_host_en>; ++ regulator-name = "vcc5v0_host"; ++ regulator-always-on; ++ }; ++ ++ vcc5v0_otg: vcc5v0-otg-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_otg_en>; ++ regulator-name = "vcc5v0_otg"; + }; +}; + @@ -186,9 +221,9 @@ index 000000000..fac2db500 +}; + +&hdmi { -+ status = "okay"; + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; ++ status = "okay"; +}; + +&hdmi_in { @@ -270,6 +305,8 @@ index 000000000..fac2db500 + }; + + vdd_gpu: DCDC_REG2 { ++ regulator-always-on; ++ regulator-boot-on; + regulator-name = "vdd_gpu"; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; @@ -306,19 +343,9 @@ index 000000000..fac2db500 + }; + }; + -+ vcc_1v8: DCDC_REG5 { -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ + vdda0v9_image: LDO_REG1 { ++ regulator-boot-on; ++ regulator-always-on; + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; @@ -354,6 +381,8 @@ index 000000000..fac2db500 + }; + + vccio_acodec: LDO_REG4 { ++ regulator-always-on; ++ regulator-boot-on; + regulator-name = "vccio_acodec"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; @@ -414,6 +443,8 @@ index 000000000..fac2db500 + }; + + vcca1v8_image: LDO_REG9 { ++ regulator-always-on; ++ regulator-boot-on; + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; @@ -423,6 +454,17 @@ index 000000000..fac2db500 + }; + }; + ++ vcc_1v8: DCDC_REG5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; @@ -468,35 +510,30 @@ index 000000000..fac2db500 +}; + +&pcie2x1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_reset_h>; -+ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_reset_gpio>; ++ vpcie3v3-supply = <&pcie30_3v3>; ++ status = "okay"; ++}; ++ ++&pcie30_3v3 { + status = "okay"; -+ vpcie3v3-supply = <&vcc3v3_pcie>; ++ gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; ++}; ++ ++&gic { ++ status = "okay"; +}; + +&pinctrl { -+ bt { -+ bt_enable_h: bt-enable-h { -+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_host_wake_l: bt-host-wake-l { -+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ bt_wake_l: bt-wake-l { -+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pcie { -+ vcc3v3_pcie_en_h: vcc3v3-pcie-en-h { ++ usb { ++ vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + -+ pcie_reset_h: pcie-reset-h { -+ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; ++ vcc5v0_otg_en: vcc5v0-otg-en { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + @@ -513,22 +550,27 @@ index 000000000..fac2db500 + }; + }; + -+ usb { -+ vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h { -+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; ++ pcie { ++ pcie_reset_gpio: pcie-reset-gpio { ++ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; ++ }; ++ leds { ++ led_power: led-power { ++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ led_user: led-user { ++ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; + -+ vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en_h { -+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; -+ vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; @@ -544,23 +586,24 @@ index 000000000..fac2db500 + +&sdhci { + bus-width = <8>; -+ mmc-hs200-1_8v; ++ supports-emmc; + non-removable; -+ vmmc-supply = <&vcc_3v3>; -+ vqmmc-supply = <&vcc_1v8>; ++ max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc0 { ++ max-frequency = <150000000>; ++ supports-sd; + bus-width = <4>; ++ cap-mmc-highspeed; + cap-sd-highspeed; -+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + @@ -580,18 +623,25 @@ index 000000000..fac2db500 +}; + +&sdmmc2 { ++// max-frequency = <150000000>; ++ max-frequency = <100000000>; ++ supports-sdio; ++ bus-width = <4>; ++ disable-wp; + cap-sd-highspeed; + cap-sdio-irq; -+ bus-width = <4>; -+ vmmc-supply = <&vcc_3v3>; -+ vqmmc-supply = <&vcca1v8_pmu>; ++ keep-power-in-suspend; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; ++ mmc-pwrseq = <&sdio_pwrseq>; ++ non-removable; + status = "okay"; +}; + +&tsadc { ++ rockchip,hw-tshut-mode = <1>; ++ rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + @@ -601,42 +651,27 @@ index 000000000..fac2db500 + status = "okay"; +}; + -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; -+ status = "okay"; -+ uart-has-rtscts; -+ -+ bluetooth { -+ compatible = "brcm,bcm4345c5"; -+ clocks = <&rk809 1>; -+ clock-names = "lpo"; -+ device-wake-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; -+ host-wake-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; -+ shutdown-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; -+ vbat-supply = <&vcc3v3_sys>; -+ vddio-supply = <&vcca1v8_pmu>; -+ }; -+}; -+ +&uart2 { + status = "okay"; +}; + +&u2phy0_host { -+ phy-supply = <&vcc5v0_usb30_host>; ++ phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { -+ vbus-supply = <&vcc5v0_usb_otg>; ++ vbus-supply = <&vcc5v0_otg>; ++ status = "okay"; ++}; ++ ++&u2phy1_host { ++ phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1_otg { -+ phy-supply = <&vcc5v0_usb30_host>; ++ phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + @@ -648,7 +683,25 @@ index 000000000..fac2db500 + status = "okay"; +}; + ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ +&usbdrd_dwc3 { ++ dr_mode = "otg"; ++ extcon = <&u2phy0>; + status = "okay"; +}; + @@ -664,18 +717,22 @@ index 000000000..fac2db500 + status = "okay"; +}; + -+&usb_host0_ehci { ++&pwm4 { + status = "okay"; +}; + -+&usb_host0_ohci { ++&pwm5 { ++ status = "okay"; ++}; ++ ++&pwm7 { + status = "okay"; +}; + +&vop { -+ status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; +}; + +&vop_mmu { diff --git a/patch/kernel/media-edge/00-v99-rk3568-firefly-roc-pc.patch b/patch/kernel/media-edge/00-v95-rk3568-firefly-roc-pc.patch similarity index 58% rename from patch/kernel/media-edge/00-v99-rk3568-firefly-roc-pc.patch rename to patch/kernel/media-edge/00-v95-rk3568-firefly-roc-pc.patch index 5dcba60710..7887a4cecb 100644 --- a/patch/kernel/media-edge/00-v99-rk3568-firefly-roc-pc.patch +++ b/patch/kernel/media-edge/00-v95-rk3568-firefly-roc-pc.patch @@ -2,7 +2,7 @@ new file mode 100644 index 000000000..fac2db500 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-firefly-roc-pc.dts -@@ -0,0 +1,640 @@ +@@ -0,0 +1,960 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. @@ -11,6 +11,7 @@ index 000000000..fac2db500 + +/dts-v1/; +#include ++#include +#include +#include +#include "rk3568.dtsi" @@ -40,6 +41,14 @@ index 000000000..fac2db500 + regulator-max-microvolt = <12000000>; + }; + ++ fan: gpio_fan { ++ compatible = "gpio-fan"; ++ gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; ++ gpio-fan,speed-map = <0 0 ++ 4500 1>; ++ #cooling-cells = <2>; ++ }; ++ + hdmi-con { + compatible = "hdmi-connector"; + type = "c"; @@ -51,6 +60,67 @@ index 000000000..fac2db500 + }; + }; + ++ vcc2v5_sys: vcc2v5-ddr { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc2v5-sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <2500000>; ++ regulator-max-microvolt = <2500000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ vcc3v3_vga: vcc3v3-vga { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_vga"; ++ regulator-always-on; ++ regulator-boot-on; ++ gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ pcie30_avdd0v9: pcie30-avdd0v9 { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie30_avdd0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ pcie30_avdd1v8: pcie30-avdd1v8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie30_avdd1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ pcie30_3v3: gpio-regulator { ++ compatible = "regulator-gpio"; ++ regulator-name = "pcie30_3v3"; ++ regulator-min-microvolt = <100000>; ++ regulator-max-microvolt = <3300000>; ++ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; ++ gpios-states = <0x1>; ++ states = <100000 0x0 ++ 3300000 0x1>; ++ }; ++ ++ vcc3v3_bu: vcc3v3-bu { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_bu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; @@ -91,43 +161,141 @@ index 000000000..fac2db500 + }; + }; + -+ vcc5v0_usb30_host: vcc5v0_usb30_host { ++ vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_usb30_host"; + enable-active-high; -+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; ++ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_usb30_host_en_h>; ++ pinctrl-0 = <&vcc5v0_host_en>; ++ regulator-name = "vcc5v0_host"; + regulator-always-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_sys>; + }; + -+ vcc5v0_usb_otg: vcc5v0_usb_otg { ++ vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_usb_otg"; + enable-active-high; -+ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; ++ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_usb_otg_en_h>; -+ regulator-always-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_sys>; ++ pinctrl-0 = <&vcc5v0_otg_en>; ++ regulator-name = "vcc5v0_otg"; + }; + -+ vcc3v3_pcie: vcc3v3_pcie { ++ vcc_hub_power: vcc-hub-power-regulator { + compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_pcie"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; -+ pinctrl-0 = <&vcc3v3_pcie_en_h>; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_3v3>; ++ pinctrl-0 = <&vcc_hub_power_en>; ++ regulator-name = "vcc_hub_power_en"; ++ regulator-always-on; + }; ++ ++ vcc_hub_reset: vcc-hub-reset-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc_hub_reset_en>; ++ regulator-name = "vcc_hub_reset_en"; ++ regulator-always-on; ++ }; ++ ++ pcie_pi6c_oe: pcie-pi6c-oe-regulator { ++ compatible = "regulator-fixed"; ++ //enable-active-high; ++ gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_pi6c_oe_en>; ++ regulator-name = "pcie_pi6c_oe_en"; ++ regulator-always-on; ++ }; ++ ++ firefly_leds: leds { ++ status = "okay"; ++ compatible = "gpio-leds"; ++ ++ power_led: power { ++ label = "firefly:blue:power"; ++ linux,default-trigger = "ir-power-click"; ++ default-state = "on"; ++ gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_power>; ++ }; ++ ++ user_led: user { ++ label = "firefly:yellow:user"; ++ linux,default-trigger = "ir-user-click"; ++ default-state = "off"; ++ gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_user>; ++ }; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rk809 1>; ++ clock-names = "ext_clock"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_enable_h>; ++ /* ++ * On the module itself this is one of these (depending ++ * on the actual card populated): ++ * - SDIO_RESET_L_WL_REG_ON ++ * - PDN (power down when low) ++ */ ++ reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; ++ }; ++ ++ wireless_wlan: wireless-wlan { ++ compatible = "wlan-platdata"; ++ rockchip,grf = <&grf>; ++ wifi_chip_type = "ap6398s"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_host_wake_irq>; ++ WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; ++ status = "disabled"; ++ }; ++ ++ wireless_bluetooth: wireless-bluetooth { ++ compatible = "bluetooth-platdata"; ++ clocks = <&rk809 1>; ++ clock-names = "ext_clock"; ++ //wifi-bt-power-toggle; ++ uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; ++ pinctrl-names = "default", "rts_gpio"; ++ pinctrl-0 = <&uart8m0_rtsn>; ++ pinctrl-1 = <&uart8_gpios>; ++ BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; ++ BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; ++ BT,wake_host_irq = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; ++ status = "disabled"; ++ }; ++ ++ flash_led: flash-led { ++ compatible = "led,rgb13h"; ++ label = "pwm-flash-led"; ++ led-max-microamp = <20000>; ++ flash-max-microamp = <20000>; ++ flash-max-timeout-us = <1000000>; ++ pwms = <&pwm11 0 25000 0>; ++ rockchip,camera-module-index = <1>; ++ rockchip,camera-module-facing = "front"; ++ status = "disabled"; ++ }; ++ ++// vcc3v3_pcie: vcc3v3_pcie { ++// compatible = "regulator-fixed"; ++// regulator-name = "vcc3v3_pcie"; ++// enable-active-high; ++// gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; ++// pinctrl-names = "default"; ++// pinctrl-0 = <&vcc3v3_pcie_en_h>; ++// regulator-min-microvolt = <3300000>; ++// regulator-max-microvolt = <3300000>; ++// vin-supply = <&vcc_3v3>; ++// }; +}; + +&combphy1 { @@ -154,6 +322,23 @@ index 000000000..fac2db500 + cpu-supply = <&vdd_cpu>; +}; + ++&cpu_thermal { ++ trips { ++ cpu_hot: cpu_hot { ++ temperature = <55000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ }; ++ ++ cooling-maps { ++ map1 { ++ trip = <&cpu_hot>; ++ cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ }; ++ }; ++}; ++ +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru SCLK_GMAC0>; @@ -199,9 +384,9 @@ index 000000000..fac2db500 +}; + +&hdmi { -+ status = "okay"; + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; ++ status = "okay"; +}; + +&hdmi_in { @@ -229,17 +414,29 @@ index 000000000..fac2db500 +&i2c0 { + status = "okay"; + ++ fusb0: fusb30x@22 { ++ compatible = "fairchild,fusb302"; ++ reg = <0x22>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&fusb0_int>; ++ int-n-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; ++ fusb340-switch-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; ++ vbus-5v-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++ }; ++ + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu"; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1150000>; -+ regulator-ramp-delay = <2300>; -+ regulator-always-on; -+ regulator-boot-on; + vin-supply = <&vcc5v0_sys>; ++ regulator-compatible = "fan53555-reg"; ++ regulator-name = "vdd_cpu"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1390000>; ++ regulator-ramp-delay = <2300>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-boot-on; ++ regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; @@ -283,6 +480,8 @@ index 000000000..fac2db500 + }; + + vdd_gpu: DCDC_REG2 { ++ regulator-always-on; ++ regulator-boot-on; + regulator-name = "vdd_gpu"; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; @@ -319,19 +518,9 @@ index 000000000..fac2db500 + }; + }; + -+ vcc_1v8: DCDC_REG5 { -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ + vdda0v9_image: LDO_REG1 { ++ regulator-boot-on; ++ regulator-always-on; + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; @@ -367,6 +556,8 @@ index 000000000..fac2db500 + }; + + vccio_acodec: LDO_REG4 { ++ regulator-always-on; ++ regulator-boot-on; + regulator-name = "vccio_acodec"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; @@ -427,6 +618,8 @@ index 000000000..fac2db500 + }; + + vcca1v8_image: LDO_REG9 { ++ regulator-always-on; ++ regulator-boot-on; + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; @@ -436,6 +629,17 @@ index 000000000..fac2db500 + }; + }; + ++ vcc_1v8: DCDC_REG5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; @@ -487,22 +691,63 @@ index 000000000..fac2db500 + }; +}; + -+&pcie2x1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_reset_h>; -+ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; ++//&pcie30phy { ++// status = "okay"; ++//}; ++ ++//&pcie3x2 { ++// reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; ++// vpcie3v3-supply = <&pcie30_3v3>; ++ ++// status = "okay"; ++//}; ++ ++&gic { ++ status = "okay"; ++}; ++ ++&sata2 { + status = "okay"; -+ vpcie3v3-supply = <&vcc3v3_pcie>; +}; + +&pinctrl { -+ pcie { -+ vcc3v3_pcie_en_h: vcc3v3-pcie-en-h { ++ sdio-pwrseq { ++ wifi_enable_h: wifi-enable-h { ++ rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ wireless-wlan { ++ wifi_host_wake_irq: wifi-host-wake-irq { ++ rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ wireless-bluetooth { ++ uart8_gpios: uart8-gpios { ++ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb { ++ vcc_hub_power_en: vcc-hub-power-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + -+ pcie_reset_h: pcie-reset-h { -+ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; ++ vcc_hub_reset_en: vcc-hub-reset-en { ++ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ fusb30x { ++ fusb0_int: fusb0-int { ++ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ pcie { ++ pcie_pi6c_oe_en: pcie-pi6c-oe-en { ++ rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + @@ -514,21 +759,30 @@ index 000000000..fac2db500 + }; + + usb { -+ vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h { -+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; ++ vcc5v0_host_en: vcc5v0-host-en { ++ rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + -+ vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en_h { -+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; ++ vcc5v0_otg_en: vcc5v0-otg-en { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; ++ ++ leds { ++ led_power: led-power { ++ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ led_user: led-user { ++ rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; -+ vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; @@ -544,35 +798,62 @@ index 000000000..fac2db500 + +&sdhci { + bus-width = <8>; -+ mmc-hs200-1_8v; ++ supports-emmc; + non-removable; -+ vmmc-supply = <&vcc_3v3>; -+ vqmmc-supply = <&vcc_1v8>; ++ max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc0 { ++ max-frequency = <150000000>; ++ supports-sd; + bus-width = <4>; ++ cap-mmc-highspeed; + cap-sd-highspeed; -+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + ++&sdio_pwrseq { ++ status = "okay"; ++ reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; ++ post-power-on-delay-ms = <100>; ++}; ++ +&sdmmc2 { ++// max-frequency = <150000000>; ++ max-frequency = <100000000>; ++ supports-sdio; ++ bus-width = <4>; ++ disable-wp; + cap-sd-highspeed; + cap-sdio-irq; -+ bus-width = <4>; -+ vmmc-supply = <&vcc_3v3>; -+ vqmmc-supply = <&vcca1v8_pmu>; ++ keep-power-in-suspend; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; ++ mmc-pwrseq = <&sdio_pwrseq>; ++ non-removable; ++ status = "okay"; ++}; ++ ++&wireless_wlan { ++ wifi_chip_type = "ap6275s"; ++ status = "okay"; ++}; ++ ++&wireless_bluetooth { ++ status = "okay"; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <1>; ++ rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + @@ -580,18 +861,35 @@ index 000000000..fac2db500 + status = "okay"; +}; + ++&uart3 { ++ status = "okay"; ++}; ++ ++&uart4 { ++ status = "okay"; ++}; ++ ++&uart8 { ++ status = "okay"; ++}; ++ +&u2phy0_host { -+ phy-supply = <&vcc5v0_usb30_host>; ++ phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { -+ vbus-supply = <&vcc5v0_usb_otg>; ++ vbus-supply = <&vcc5v0_otg>; ++ status = "okay"; ++}; ++ ++&u2phy1_host { ++ phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1_otg { -+ phy-supply = <&vcc5v0_usb30_host>; ++ phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + @@ -603,7 +901,25 @@ index 000000000..fac2db500 + status = "okay"; +}; + ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ +&usbdrd_dwc3 { ++ dr_mode = "otg"; ++ extcon = <&u2phy0>; + status = "okay"; +}; + @@ -619,18 +935,22 @@ index 000000000..fac2db500 + status = "okay"; +}; + -+&usb_host0_ehci { ++&pwm4 { + status = "okay"; +}; + -+&usb_host0_ohci { ++&pwm5 { ++ status = "okay"; ++}; ++ ++&pwm7 { + status = "okay"; +}; + +&vop { -+ status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; +}; + +&vop_mmu {