From be8176a3ad90bb2a55adce8d061b1703261ff3f2 Mon Sep 17 00:00:00 2001 From: amazingfate Date: Sun, 10 Nov 2024 19:08:23 +0800 Subject: [PATCH] rockchip-rk3588-6.12: drop patches which cannot get applied --- .../0025-RK3588-Add-HW-RNG-Support.patch | 663 ----- ...588-Add-VPU121-H.264-Decoder-Support.patch | 395 --- ...64-dts-rockchip-rk3588-add-RGA2-node.patch | 34 - ...chip-samsung-hdptx-Enable-runtime-PM.patch | 91 - ...hip-samsung-hdptx-Add-clock-provider.patch | 323 -- ...itial-support-for-DW-HDMI-Controller.patch | 2603 ----------------- ...ip-add-PCIe-for-M.2-E-Key-to-rock-5a.patch | 39 - ...s-rockchip-nanopct6-lts-and-fixes-v6.patch | 2540 ---------------- 8 files changed, 6688 deletions(-) delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.12/0025-RK3588-Add-HW-RNG-Support.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.12/0026-RK3588-Add-VPU121-H.264-Decoder-Support.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.12/0029-arm64-dts-rockchip-rk3588-add-RGA2-node.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.12/0130-phy-phy-rockchip-samsung-hdptx-Enable-runtime-PM.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.12/0131-phy-phy-rockchip-samsung-hdptx-Add-clock-provider.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.12/0134-drm-bridge-synopsys-Add-initial-support-for-DW-HDMI-Controller.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.12/1023-arm64-dts-rockchip-add-PCIe-for-M.2-E-Key-to-rock-5a.patch delete mode 100644 patch/kernel/archive/rockchip-rk3588-6.12/1051-arm64-dts-rockchip-nanopct6-lts-and-fixes-v6.patch diff --git a/patch/kernel/archive/rockchip-rk3588-6.12/0025-RK3588-Add-HW-RNG-Support.patch b/patch/kernel/archive/rockchip-rk3588-6.12/0025-RK3588-Add-HW-RNG-Support.patch deleted file mode 100644 index ef9b779112..0000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.12/0025-RK3588-Add-HW-RNG-Support.patch +++ /dev/null @@ -1,663 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Thu, 16 Nov 2023 17:49:42 +0300 -Subject: hwrng: rockchip: Add support for Rockchip HW RNG - ---- - drivers/char/hw_random/Kconfig | 13 + - drivers/char/hw_random/Makefile | 1 + - drivers/char/hw_random/rockchip-rng.c | 574 ++++++++++ - 3 files changed, 588 insertions(+) - -diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig -index 111111111111..222222222222 100644 ---- a/drivers/char/hw_random/Kconfig -+++ b/drivers/char/hw_random/Kconfig -@@ -538,6 +538,19 @@ config HW_RANDOM_XIPHERA - To compile this driver as a module, choose M here: the - module will be called xiphera-trng. - -+config HW_RANDOM_ROCKCHIP -+ tristate "Rockchip Random Number Generator support" -+ depends on ARCH_ROCKCHIP -+ default HW_RANDOM -+ help -+ This driver provides kernel-side support for the Random Number -+ Generator hardware found on Rockchip cpus. -+ -+ To compile this driver as a module, choose M here: the -+ module will be called rockchip-rng. -+ -+ If unsure, say Y. -+ - config HW_RANDOM_ARM_SMCCC_TRNG - tristate "Arm SMCCC TRNG firmware interface support" - depends on HAVE_ARM_SMCCC_DISCOVERY -diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile -index 111111111111..222222222222 100644 ---- a/drivers/char/hw_random/Makefile -+++ b/drivers/char/hw_random/Makefile -@@ -35,6 +35,7 @@ obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) += iproc-rng200.o - obj-$(CONFIG_HW_RANDOM_ST) += st-rng.o - obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o - obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o -+obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o - obj-$(CONFIG_HW_RANDOM_PIC32) += pic32-rng.o - obj-$(CONFIG_HW_RANDOM_MESON) += meson-rng.o - obj-$(CONFIG_HW_RANDOM_CAVIUM) += cavium-rng.o cavium-rng-vf.o -diff --git a/drivers/char/hw_random/rockchip-rng.c b/drivers/char/hw_random/rockchip-rng.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/char/hw_random/rockchip-rng.c -@@ -0,0 +1,574 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * rockchip-rng.c Random Number Generator driver for the Rockchip -+ * -+ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd. -+ * Author: Lin Jinhan -+ * -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define _SBF(s, v) ((v) << (s)) -+#define HIWORD_UPDATE(val, mask, shift) \ -+ ((val) << (shift) | (mask) << ((shift) + 16)) -+ -+#define ROCKCHIP_AUTOSUSPEND_DELAY 100 -+#define ROCKCHIP_POLL_PERIOD_US 100 -+#define ROCKCHIP_POLL_TIMEOUT_US 50000 -+#define RK_MAX_RNG_BYTE (32) -+ -+/* start of CRYPTO V1 register define */ -+#define CRYPTO_V1_CTRL 0x0008 -+#define CRYPTO_V1_RNG_START BIT(8) -+#define CRYPTO_V1_RNG_FLUSH BIT(9) -+ -+#define CRYPTO_V1_TRNG_CTRL 0x0200 -+#define CRYPTO_V1_OSC_ENABLE BIT(16) -+#define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x) (x) -+ -+#define CRYPTO_V1_TRNG_DOUT_0 0x0204 -+/* end of CRYPTO V1 register define */ -+ -+/* start of CRYPTO V2 register define */ -+#define CRYPTO_V2_RNG_DEFAULT_OFFSET 0x0400 -+#define CRYPTO_V2_RNG_CTL 0x0 -+#define CRYPTO_V2_RNG_64_BIT_LEN _SBF(4, 0x00) -+#define CRYPTO_V2_RNG_128_BIT_LEN _SBF(4, 0x01) -+#define CRYPTO_V2_RNG_192_BIT_LEN _SBF(4, 0x02) -+#define CRYPTO_V2_RNG_256_BIT_LEN _SBF(4, 0x03) -+#define CRYPTO_V2_RNG_FATESY_SOC_RING _SBF(2, 0x00) -+#define CRYPTO_V2_RNG_SLOWER_SOC_RING_0 _SBF(2, 0x01) -+#define CRYPTO_V2_RNG_SLOWER_SOC_RING_1 _SBF(2, 0x02) -+#define CRYPTO_V2_RNG_SLOWEST_SOC_RING _SBF(2, 0x03) -+#define CRYPTO_V2_RNG_ENABLE BIT(1) -+#define CRYPTO_V2_RNG_START BIT(0) -+#define CRYPTO_V2_RNG_SAMPLE_CNT 0x0004 -+#define CRYPTO_V2_RNG_DOUT_0 0x0010 -+/* end of CRYPTO V2 register define */ -+ -+/* start of TRNG_V1 register define */ -+/* TRNG is no longer subordinate to the Crypto module */ -+#define TRNG_V1_CTRL 0x0000 -+#define TRNG_V1_CTRL_NOP _SBF(0, 0x00) -+#define TRNG_V1_CTRL_RAND _SBF(0, 0x01) -+#define TRNG_V1_CTRL_SEED _SBF(0, 0x02) -+ -+#define TRNG_V1_STAT 0x0004 -+#define TRNG_V1_STAT_SEEDED BIT(9) -+#define TRNG_V1_STAT_GENERATING BIT(30) -+#define TRNG_V1_STAT_RESEEDING BIT(31) -+ -+#define TRNG_V1_MODE 0x0008 -+#define TRNG_V1_MODE_128_BIT _SBF(3, 0x00) -+#define TRNG_V1_MODE_256_BIT _SBF(3, 0x01) -+ -+#define TRNG_V1_IE 0x0010 -+#define TRNG_V1_IE_GLBL_EN BIT(31) -+#define TRNG_V1_IE_SEED_DONE_EN BIT(1) -+#define TRNG_V1_IE_RAND_RDY_EN BIT(0) -+ -+#define TRNG_V1_ISTAT 0x0014 -+#define TRNG_V1_ISTAT_RAND_RDY BIT(0) -+ -+/* RAND0 ~ RAND7 */ -+#define TRNG_V1_RAND0 0x0020 -+#define TRNG_V1_RAND7 0x003C -+ -+#define TRNG_V1_AUTO_RQSTS 0x0060 -+ -+#define TRNG_V1_VERSION 0x00F0 -+#define TRNG_v1_VERSION_CODE 0x46bc -+/* end of TRNG_V1 register define */ -+ -+/* start of RKRNG register define */ -+#define RKRNG_CTRL 0x0010 -+#define RKRNG_CTRL_INST_REQ BIT(0) -+#define RKRNG_CTRL_RESEED_REQ BIT(1) -+#define RKRNG_CTRL_TEST_REQ BIT(2) -+#define RKRNG_CTRL_SW_DRNG_REQ BIT(3) -+#define RKRNG_CTRL_SW_TRNG_REQ BIT(4) -+ -+#define RKRNG_STATE 0x0014 -+#define RKRNG_STATE_INST_ACK BIT(0) -+#define RKRNG_STATE_RESEED_ACK BIT(1) -+#define RKRNG_STATE_TEST_ACK BIT(2) -+#define RKRNG_STATE_SW_DRNG_ACK BIT(3) -+#define RKRNG_STATE_SW_TRNG_ACK BIT(4) -+ -+/* DRNG_DATA_0 ~ DNG_DATA_7 */ -+#define RKRNG_DRNG_DATA_0 0x0070 -+#define RKRNG_DRNG_DATA_7 0x008C -+ -+/* end of RKRNG register define */ -+ -+struct rk_rng_soc_data { -+ u32 default_offset; -+ -+ int (*rk_rng_init)(struct hwrng *rng); -+ int (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait); -+}; -+ -+struct rk_rng { -+ struct device *dev; -+ struct hwrng rng; -+ void __iomem *mem; -+ struct rk_rng_soc_data *soc_data; -+ int clk_num; -+ struct clk_bulk_data *clk_bulks; -+}; -+ -+static void rk_rng_writel(struct rk_rng *rng, u32 val, u32 offset) -+{ -+ __raw_writel(val, rng->mem + offset); -+} -+ -+static u32 rk_rng_readl(struct rk_rng *rng, u32 offset) -+{ -+ return __raw_readl(rng->mem + offset); -+} -+ -+static int rk_rng_init(struct hwrng *rng) -+{ -+ int ret; -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ -+ dev_dbg(rk_rng->dev, "clk_bulk_prepare_enable.\n"); -+ -+ ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks); -+ if (ret < 0) { -+ dev_err(rk_rng->dev, "failed to enable clks %d\n", ret); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static void rk_rng_cleanup(struct hwrng *rng) -+{ -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ -+ dev_dbg(rk_rng->dev, "clk_bulk_disable_unprepare.\n"); -+ clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks); -+} -+ -+static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait) -+{ -+ int ret; -+ int read_len = 0; -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ -+ if (!rk_rng->soc_data->rk_rng_read) -+ return -EFAULT; -+ -+ ret = pm_runtime_get_sync(rk_rng->dev); -+ if (ret < 0) { -+ pm_runtime_put_noidle(rk_rng->dev); -+ return ret; -+ } -+ -+ ret = 0; -+ while (max > ret) { -+ read_len = rk_rng->soc_data->rk_rng_read(rng, buf + ret, -+ max - ret, wait); -+ if (read_len < 0) { -+ ret = read_len; -+ break; -+ } -+ ret += read_len; -+ } -+ -+ pm_runtime_mark_last_busy(rk_rng->dev); -+ pm_runtime_put_sync_autosuspend(rk_rng->dev); -+ -+ return ret; -+} -+ -+static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf, -+ size_t size) -+{ -+ u32 i; -+ -+ for (i = 0; i < size; i += 4) -+ *(u32 *)(buf + i) = be32_to_cpu(rk_rng_readl(rng, offset + i)); -+} -+ -+static int crypto_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait) -+{ -+ int ret = 0; -+ u32 reg_ctrl = 0; -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ -+ /* enable osc_ring to get entropy, sample period is set as 100 */ -+ reg_ctrl = CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100); -+ rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_TRNG_CTRL); -+ -+ reg_ctrl = HIWORD_UPDATE(CRYPTO_V1_RNG_START, CRYPTO_V1_RNG_START, 0); -+ -+ rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_CTRL); -+ -+ ret = read_poll_timeout(rk_rng_readl, reg_ctrl, -+ !(reg_ctrl & CRYPTO_V1_RNG_START), -+ ROCKCHIP_POLL_PERIOD_US, -+ ROCKCHIP_POLL_TIMEOUT_US, false, -+ rk_rng, CRYPTO_V1_CTRL); -+ -+ if (ret < 0) -+ goto out; -+ -+ ret = min_t(size_t, max, RK_MAX_RNG_BYTE); -+ -+ rk_rng_read_regs(rk_rng, CRYPTO_V1_TRNG_DOUT_0, buf, ret); -+ -+out: -+ /* close TRNG */ -+ rk_rng_writel(rk_rng, HIWORD_UPDATE(0, CRYPTO_V1_RNG_START, 0), -+ CRYPTO_V1_CTRL); -+ -+ return ret; -+} -+ -+static int crypto_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait) -+{ -+ int ret = 0; -+ u32 reg_ctrl = 0; -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ -+ /* enable osc_ring to get entropy, sample period is set as 100 */ -+ rk_rng_writel(rk_rng, 100, CRYPTO_V2_RNG_SAMPLE_CNT); -+ -+ reg_ctrl |= CRYPTO_V2_RNG_256_BIT_LEN; -+ reg_ctrl |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0; -+ reg_ctrl |= CRYPTO_V2_RNG_ENABLE; -+ reg_ctrl |= CRYPTO_V2_RNG_START; -+ -+ rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0), -+ CRYPTO_V2_RNG_CTL); -+ -+ ret = read_poll_timeout(rk_rng_readl, reg_ctrl, -+ !(reg_ctrl & CRYPTO_V2_RNG_START), -+ ROCKCHIP_POLL_PERIOD_US, -+ ROCKCHIP_POLL_TIMEOUT_US, false, -+ rk_rng, CRYPTO_V2_RNG_CTL); -+ if (ret < 0) -+ goto out; -+ -+ ret = min_t(size_t, max, RK_MAX_RNG_BYTE); -+ -+ rk_rng_read_regs(rk_rng, CRYPTO_V2_RNG_DOUT_0, buf, ret); -+ -+out: -+ /* close TRNG */ -+ rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), CRYPTO_V2_RNG_CTL); -+ -+ return ret; -+} -+ -+static int trng_v1_init(struct hwrng *rng) -+{ -+ int ret; -+ uint32_t auto_reseed_cnt = 1000; -+ uint32_t reg_ctrl, status, version; -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ -+ version = rk_rng_readl(rk_rng, TRNG_V1_VERSION); -+ if (version != TRNG_v1_VERSION_CODE) { -+ dev_err(rk_rng->dev, -+ "wrong trng version, expected = %08x, actual = %08x\n", -+ TRNG_V1_VERSION, version); -+ ret = -EFAULT; -+ goto exit; -+ } -+ -+ status = rk_rng_readl(rk_rng, TRNG_V1_STAT); -+ -+ /* TRNG should wait RAND_RDY triggered if it is busy or not seeded */ -+ if (!(status & TRNG_V1_STAT_SEEDED) || -+ (status & TRNG_V1_STAT_GENERATING) || -+ (status & TRNG_V1_STAT_RESEEDING)) { -+ uint32_t mask = TRNG_V1_STAT_SEEDED | -+ TRNG_V1_STAT_GENERATING | -+ TRNG_V1_STAT_RESEEDING; -+ -+ udelay(10); -+ -+ /* wait for GENERATING and RESEEDING flag to clear */ -+ read_poll_timeout(rk_rng_readl, reg_ctrl, -+ (reg_ctrl & mask) == TRNG_V1_STAT_SEEDED, -+ ROCKCHIP_POLL_PERIOD_US, -+ ROCKCHIP_POLL_TIMEOUT_US, false, -+ rk_rng, TRNG_V1_STAT); -+ } -+ -+ /* clear ISTAT flag because trng may auto reseeding when power on */ -+ reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT); -+ rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT); -+ -+ /* auto reseed after (auto_reseed_cnt * 16) byte rand generate */ -+ rk_rng_writel(rk_rng, auto_reseed_cnt, TRNG_V1_AUTO_RQSTS); -+ -+ ret = 0; -+exit: -+ -+ return ret; -+} -+ -+static int trng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait) -+{ -+ int ret = 0; -+ u32 reg_ctrl = 0; -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ -+ /* clear ISTAT anyway */ -+ reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT); -+ rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT); -+ -+ /* generate 256bit random */ -+ rk_rng_writel(rk_rng, TRNG_V1_MODE_256_BIT, TRNG_V1_MODE); -+ rk_rng_writel(rk_rng, TRNG_V1_CTRL_RAND, TRNG_V1_CTRL); -+ -+ /* -+ * Generate2 56 bit random data will cost 1024 clock cycles. -+ * Estimated at 150M RNG module frequency, it takes 6.7 microseconds. -+ */ -+ udelay(10); -+ reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT); -+ if (!(reg_ctrl & TRNG_V1_ISTAT_RAND_RDY)) { -+ /* wait RAND_RDY triggered */ -+ ret = read_poll_timeout(rk_rng_readl, reg_ctrl, -+ (reg_ctrl & TRNG_V1_ISTAT_RAND_RDY), -+ ROCKCHIP_POLL_PERIOD_US, -+ ROCKCHIP_POLL_TIMEOUT_US, false, -+ rk_rng, TRNG_V1_ISTAT); -+ if (ret < 0) -+ goto out; -+ } -+ -+ ret = min_t(size_t, max, RK_MAX_RNG_BYTE); -+ -+ rk_rng_read_regs(rk_rng, TRNG_V1_RAND0, buf, ret); -+ -+ /* clear all status flag */ -+ rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT); -+out: -+ /* close TRNG */ -+ rk_rng_writel(rk_rng, TRNG_V1_CTRL_NOP, TRNG_V1_CTRL); -+ -+ return ret; -+} -+ -+static int rkrng_init(struct hwrng *rng) -+{ -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ u32 reg = 0; -+ -+ rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), RKRNG_CTRL); -+ -+ reg = rk_rng_readl(rk_rng, RKRNG_STATE); -+ rk_rng_writel(rk_rng, reg, RKRNG_STATE); -+ -+ return 0; -+} -+ -+static int rkrng_read(struct hwrng *rng, void *buf, size_t max, bool wait) -+{ -+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); -+ u32 reg_ctrl = 0; -+ int ret; -+ -+ reg_ctrl = RKRNG_CTRL_SW_DRNG_REQ; -+ -+ rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0), RKRNG_CTRL); -+ -+ ret = readl_poll_timeout(rk_rng->mem + RKRNG_STATE, reg_ctrl, -+ (reg_ctrl & RKRNG_STATE_SW_DRNG_ACK), -+ ROCKCHIP_POLL_PERIOD_US, -+ ROCKCHIP_POLL_TIMEOUT_US); -+ -+ if (ret) -+ goto exit; -+ -+ rk_rng_writel(rk_rng, reg_ctrl, RKRNG_STATE); -+ -+ ret = min_t(size_t, max, RK_MAX_RNG_BYTE); -+ -+ rk_rng_read_regs(rk_rng, RKRNG_DRNG_DATA_0, buf, ret); -+ -+exit: -+ /* close TRNG */ -+ rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), RKRNG_CTRL); -+ -+ return ret; -+} -+ -+static const struct rk_rng_soc_data crypto_v1_soc_data = { -+ .default_offset = 0, -+ -+ .rk_rng_read = crypto_v1_read, -+}; -+ -+static const struct rk_rng_soc_data crypto_v2_soc_data = { -+ .default_offset = CRYPTO_V2_RNG_DEFAULT_OFFSET, -+ -+ .rk_rng_read = crypto_v2_read, -+}; -+ -+static const struct rk_rng_soc_data trng_v1_soc_data = { -+ .default_offset = 0, -+ -+ .rk_rng_init = trng_v1_init, -+ .rk_rng_read = trng_v1_read, -+}; -+ -+static const struct rk_rng_soc_data rkrng_soc_data = { -+ .default_offset = 0, -+ -+ .rk_rng_init = rkrng_init, -+ .rk_rng_read = rkrng_read, -+}; -+ -+static const struct of_device_id rk_rng_dt_match[] = { -+ { -+ .compatible = "rockchip,cryptov1-rng", -+ .data = (void *)&crypto_v1_soc_data, -+ }, -+ { -+ .compatible = "rockchip,cryptov2-rng", -+ .data = (void *)&crypto_v2_soc_data, -+ }, -+ { -+ .compatible = "rockchip,trngv1", -+ .data = (void *)&trng_v1_soc_data, -+ }, -+ { -+ .compatible = "rockchip,rkrng", -+ .data = (void *)&rkrng_soc_data, -+ }, -+ { }, -+}; -+ -+MODULE_DEVICE_TABLE(of, rk_rng_dt_match); -+ -+static int rk_rng_probe(struct platform_device *pdev) -+{ -+ int ret; -+ struct rk_rng *rk_rng; -+ struct device_node *np = pdev->dev.of_node; -+ const struct of_device_id *match; -+ resource_size_t map_size; -+ -+ dev_dbg(&pdev->dev, "probing...\n"); -+ rk_rng = devm_kzalloc(&pdev->dev, sizeof(struct rk_rng), GFP_KERNEL); -+ if (!rk_rng) -+ return -ENOMEM; -+ -+ match = of_match_node(rk_rng_dt_match, np); -+ rk_rng->soc_data = (struct rk_rng_soc_data *)match->data; -+ -+ rk_rng->dev = &pdev->dev; -+ rk_rng->rng.name = "rockchip"; -+#ifndef CONFIG_PM -+ rk_rng->rng.init = rk_rng_init; -+ rk_rng->rng.cleanup = rk_rng_cleanup, -+#endif -+ rk_rng->rng.read = rk_rng_read; -+ rk_rng->rng.quality = 999; -+ -+ rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, &map_size); -+ if (IS_ERR(rk_rng->mem)) -+ return PTR_ERR(rk_rng->mem); -+ -+ /* compatible with crypto v2 module */ -+ /* -+ * With old dtsi configurations, the RNG base was equal to the crypto -+ * base, so both drivers could not be enabled at the same time. -+ * RNG base = CRYPTO base + RNG offset -+ * (Since RK356X, RNG module is no longer belongs to CRYPTO module) -+ * -+ * With new dtsi configurations, CRYPTO regs is divided into two parts -+ * |---cipher---|---rng---|---pka---|, and RNG base is real RNG base. -+ * RNG driver and CRYPTO driver could be enabled at the same time. -+ */ -+ if (map_size > rk_rng->soc_data->default_offset) -+ rk_rng->mem += rk_rng->soc_data->default_offset; -+ -+ rk_rng->clk_num = devm_clk_bulk_get_all(&pdev->dev, &rk_rng->clk_bulks); -+ if (rk_rng->clk_num < 0) { -+ dev_err(&pdev->dev, "failed to get clks property\n"); -+ return -ENODEV; -+ } -+ -+ platform_set_drvdata(pdev, rk_rng); -+ -+ pm_runtime_set_autosuspend_delay(&pdev->dev, -+ ROCKCHIP_AUTOSUSPEND_DELAY); -+ pm_runtime_use_autosuspend(&pdev->dev); -+ pm_runtime_enable(&pdev->dev); -+ -+ ret = devm_hwrng_register(&pdev->dev, &rk_rng->rng); -+ if (ret) { -+ pm_runtime_dont_use_autosuspend(&pdev->dev); -+ pm_runtime_disable(&pdev->dev); -+ } -+ -+ /* for some platform need hardware operation when probe */ -+ if (rk_rng->soc_data->rk_rng_init) { -+ pm_runtime_get_sync(rk_rng->dev); -+ -+ ret = rk_rng->soc_data->rk_rng_init(&rk_rng->rng); -+ -+ pm_runtime_mark_last_busy(rk_rng->dev); -+ pm_runtime_put_sync_autosuspend(rk_rng->dev); -+ } -+ -+ return ret; -+} -+ -+#ifdef CONFIG_PM -+static int rk_rng_runtime_suspend(struct device *dev) -+{ -+ struct rk_rng *rk_rng = dev_get_drvdata(dev); -+ -+ rk_rng_cleanup(&rk_rng->rng); -+ -+ return 0; -+} -+ -+static int rk_rng_runtime_resume(struct device *dev) -+{ -+ struct rk_rng *rk_rng = dev_get_drvdata(dev); -+ -+ return rk_rng_init(&rk_rng->rng); -+} -+ -+static const struct dev_pm_ops rk_rng_pm_ops = { -+ SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend, -+ rk_rng_runtime_resume, NULL) -+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, -+ pm_runtime_force_resume) -+}; -+ -+#endif -+ -+static struct platform_driver rk_rng_driver = { -+ .driver = { -+ .name = "rockchip-rng", -+#ifdef CONFIG_PM -+ .pm = &rk_rng_pm_ops, -+#endif -+ .of_match_table = rk_rng_dt_match, -+ }, -+ .probe = rk_rng_probe, -+}; -+ -+module_platform_driver(rk_rng_driver); -+ -+MODULE_DESCRIPTION("ROCKCHIP H/W Random Number Generator driver"); -+MODULE_AUTHOR("Lin Jinhan "); -+MODULE_LICENSE("GPL v2"); --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Fri, 2 Aug 2024 00:10:39 +0300 -Subject: arm64: dts: rockchip: rk3588: enable RNG node - ---- - arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -1774,6 +1774,16 @@ crypto: crypto@fe370000 { - reset-names = "core"; - }; - -+ rng: rng@fe378000 { -+ compatible = "rockchip,trngv1"; -+ reg = <0x0 0xfe378000 0x0 0x200>; -+ interrupts = ; -+ clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>; -+ clock-names = "hclk_trng"; -+ resets = <&scmi_reset SRST_H_TRNG_NS>; -+ reset-names = "reset"; -+ }; -+ - i2s0_8ch: i2s@fe470000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfe470000 0x0 0x1000>; --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.12/0026-RK3588-Add-VPU121-H.264-Decoder-Support.patch b/patch/kernel/archive/rockchip-rk3588-6.12/0026-RK3588-Add-VPU121-H.264-Decoder-Support.patch deleted file mode 100644 index 35298c4c46..0000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.12/0026-RK3588-Add-VPU121-H.264-Decoder-Support.patch +++ /dev/null @@ -1,395 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Emmanuel Gil Peyrot -Date: Thu, 18 Apr 2024 16:15:05 +0200 -Subject: media: dt-bindings: rk3568-vepu: Add RK3588 VEPU121 - -This encoder-only device is present four times on this SoC, and should -support everything the rk3568 vepu supports (so JPEG, H.264 and VP8 -encoding). No fallback compatible has been added, since the operating -systems might already support RK3568 VEPU and want to avoid registering -four of them separately considering they can be used as a cluster. - -Signed-off-by: Emmanuel Gil Peyrot -Acked-by: Conor Dooley -Signed-off-by: Sebastian Reichel ---- - Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml b/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml -index 111111111111..222222222222 100644 ---- a/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml -+++ b/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml -@@ -17,6 +17,7 @@ properties: - compatible: - enum: - - rockchip,rk3568-vepu -+ - rockchip,rk3588-vepu121 - - reg: - maxItems: 1 --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jianfeng Liu -Date: Tue, 30 Apr 2024 10:40:01 +0800 -Subject: media: dt-bindings: rockchip-vpu: Add RK3588 VPU121 - -RK3588 has four Hantro H1 VEPUs (encoder-only) modules and one combined -Hantro H1/G1 VPU (decoder and encoder). These are not described as -separate IP, since they are sharing an internal cache. This adds the -RK3588 specific compatible string for the combined VPU, which seems to -be identical to the version found in the RK3568. - -Signed-off-by: Jianfeng Liu -Acked-by: Conor Dooley -Signed-off-by: Sebastian Reichel ---- - Documentation/devicetree/bindings/media/rockchip-vpu.yaml | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml -index 111111111111..222222222222 100644 ---- a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml -+++ b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml -@@ -31,6 +31,9 @@ properties: - - items: - - const: rockchip,rk3228-vpu - - const: rockchip,rk3399-vpu -+ - items: -+ - const: rockchip,rk3588-vpu121 -+ - const: rockchip,rk3568-vpu - - reg: - maxItems: 1 --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Thu, 13 Jun 2024 14:29:55 +0200 -Subject: media: hantro: Disable multicore support - -Avoid exposing equal Hantro video codecs to userspace. Equal video -codecs allow scheduling work between the cores. For that kernel support -is required, which does not yet exist. Until that is implemented avoid -exposing each core separately to userspace so that multicore can be -added in the future without breaking userspace ABI. - -This was written with Rockchip RK3588 in mind (which has 4 Hantro H1 -cores), but applies to all SoCs. - -Signed-off-by: Sebastian Reichel ---- - drivers/media/platform/verisilicon/hantro_drv.c | 47 ++++++++++ - 1 file changed, 47 insertions(+) - -diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/verisilicon/hantro_drv.c -+++ b/drivers/media/platform/verisilicon/hantro_drv.c -@@ -992,6 +992,49 @@ static const struct media_device_ops hantro_m2m_media_ops = { - .req_queue = v4l2_m2m_request_queue, - }; - -+/* -+ * Some SoCs, like RK3588 have multiple identical Hantro cores, but the -+ * kernel is currently missing support for multi-core handling. Exposing -+ * separate devices for each core to userspace is bad, since that does -+ * not allow scheduling tasks properly (and creates ABI). With this workaround -+ * the driver will only probe for the first core and early exit for the other -+ * cores. Once the driver gains multi-core support, the same technique -+ * for detecting the main core can be used to cluster all cores together. -+ */ -+static int hantro_disable_multicore(struct hantro_dev *vpu) -+{ -+ struct device_node *node = NULL; -+ const char *compatible; -+ bool is_main_core; -+ int ret; -+ -+ /* Intentionally ignores the fallback strings */ -+ ret = of_property_read_string(vpu->dev->of_node, "compatible", &compatible); -+ if (ret) -+ return ret; -+ -+ /* The first compatible and available node found is considered the main core */ -+ do { -+ node = of_find_compatible_node(node, NULL, compatible); -+ if (of_device_is_available(node)) -+ break; -+ } while (node); -+ -+ if (!node) -+ return -EINVAL; -+ -+ is_main_core = (vpu->dev->of_node == node); -+ -+ of_node_put(node); -+ -+ if (!is_main_core) { -+ dev_info(vpu->dev, "missing multi-core support, ignoring this instance\n"); -+ return -ENODEV; -+ } -+ -+ return 0; -+} -+ - static int hantro_probe(struct platform_device *pdev) - { - const struct of_device_id *match; -@@ -1011,6 +1054,10 @@ static int hantro_probe(struct platform_device *pdev) - match = of_match_node(of_hantro_match, pdev->dev.of_node); - vpu->variant = match->data; - -+ ret = hantro_disable_multicore(vpu); -+ if (ret) -+ return ret; -+ - /* - * Support for nxp,imx8mq-vpu is kept for backwards compatibility - * but it's deprecated. Please update your DTS file to use --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Thu, 13 Jun 2024 14:48:43 +0200 -Subject: media: hantro: Add RK3588 VEPU121 - -RK3588 handling is exactly the same as RK3568. This is not -handled using fallback compatibles to avoid exposing multiple -video devices on kernels not having the multicore disable -patch. - -Signed-off-by: Sebastian Reichel ---- - drivers/media/platform/verisilicon/hantro_drv.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/verisilicon/hantro_drv.c -+++ b/drivers/media/platform/verisilicon/hantro_drv.c -@@ -722,6 +722,7 @@ static const struct of_device_id of_hantro_match[] = { - { .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, }, - { .compatible = "rockchip,rk3568-vepu", .data = &rk3568_vepu_variant, }, - { .compatible = "rockchip,rk3568-vpu", .data = &rk3568_vpu_variant, }, -+ { .compatible = "rockchip,rk3588-vepu121", .data = &rk3568_vepu_variant, }, - { .compatible = "rockchip,rk3588-av1-vpu", .data = &rk3588_vpu981_variant, }, - #endif - #ifdef CONFIG_VIDEO_HANTRO_IMX8M --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Emmanuel Gil Peyrot -Date: Wed, 5 Jun 2024 15:28:33 +0200 -Subject: arm64: dts: rockchip: Add VEPU121 to RK3588 - -RK3588 has 4 Hantro G1 encoder-only cores. They are all independent IP, -but can be used as a cluster (i.e. sharing work between the cores). -These cores are called VEPU121 in the TRM. The TRM describes one more -VEPU121, but that is combined with a Hantro H1. That one will be handled -using the VPU binding instead. - -Signed-off-by: Emmanuel Gil Peyrot -Signed-off-by: Sebastian Reichel ---- - arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 80 ++++++++++ - 1 file changed, 80 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -1122,6 +1122,86 @@ power-domain@RK3588_PD_SDMMC { - }; - }; - -+ vepu121_0: video-codec@fdba0000 { -+ compatible = "rockchip,rk3588-vepu121"; -+ reg = <0x0 0xfdba0000 0x0 0x800>; -+ interrupts = ; -+ clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; -+ clock-names = "aclk", "hclk"; -+ iommus = <&vepu121_0_mmu>; -+ power-domains = <&power RK3588_PD_VDPU>; -+ }; -+ -+ vepu121_0_mmu: iommu@fdba0800 { -+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; -+ reg = <0x0 0xfdba0800 0x0 0x40>; -+ interrupts = ; -+ clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; -+ clock-names = "aclk", "iface"; -+ power-domains = <&power RK3588_PD_VDPU>; -+ #iommu-cells = <0>; -+ }; -+ -+ vepu121_1: video-codec@fdba4000 { -+ compatible = "rockchip,rk3588-vepu121"; -+ reg = <0x0 0xfdba4000 0x0 0x800>; -+ interrupts = ; -+ clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; -+ clock-names = "aclk", "hclk"; -+ iommus = <&vepu121_1_mmu>; -+ power-domains = <&power RK3588_PD_VDPU>; -+ }; -+ -+ vepu121_1_mmu: iommu@fdba4800 { -+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; -+ reg = <0x0 0xfdba4800 0x0 0x40>; -+ interrupts = ; -+ clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; -+ clock-names = "aclk", "iface"; -+ power-domains = <&power RK3588_PD_VDPU>; -+ #iommu-cells = <0>; -+ }; -+ -+ vepu121_2: video-codec@fdba8000 { -+ compatible = "rockchip,rk3588-vepu121"; -+ reg = <0x0 0xfdba8000 0x0 0x800>; -+ interrupts = ; -+ clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; -+ clock-names = "aclk", "hclk"; -+ iommus = <&vepu121_2_mmu>; -+ power-domains = <&power RK3588_PD_VDPU>; -+ }; -+ -+ vepu121_2_mmu: iommu@fdba8800 { -+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; -+ reg = <0x0 0xfdba8800 0x0 0x40>; -+ interrupts = ; -+ clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; -+ clock-names = "aclk", "iface"; -+ power-domains = <&power RK3588_PD_VDPU>; -+ #iommu-cells = <0>; -+ }; -+ -+ vepu121_3: video-codec@fdbac000 { -+ compatible = "rockchip,rk3588-vepu121"; -+ reg = <0x0 0xfdbac000 0x0 0x800>; -+ interrupts = ; -+ clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; -+ clock-names = "aclk", "hclk"; -+ iommus = <&vepu121_3_mmu>; -+ power-domains = <&power RK3588_PD_VDPU>; -+ }; -+ -+ vepu121_3_mmu: iommu@fdbac800 { -+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; -+ reg = <0x0 0xfdbac800 0x0 0x40>; -+ interrupts = ; -+ clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; -+ clock-names = "aclk", "iface"; -+ power-domains = <&power RK3588_PD_VDPU>; -+ #iommu-cells = <0>; -+ }; -+ - av1d: video-codec@fdc70000 { - compatible = "rockchip,rk3588-av1-vpu"; - reg = <0x0 0xfdc70000 0x0 0x800>; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jianfeng Liu -Date: Tue, 30 Apr 2024 10:40:02 +0800 -Subject: arm64: dts: rockchip: Add VPU121 support for RK3588 - -Enable Hantro G1 video decoder in RK3588's devicetree. - -Tested with FFmpeg v4l2_request code taken from [1] -with MPEG2, H.264 and VP8 samples. - -[1] https://github.com/LibreELEC/LibreELEC.tv/blob/master/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch - -Signed-off-by: Jianfeng Liu -Tested-by: Hugh Cole-Baker -Signed-off-by: Sebastian Reichel ---- - arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 21 ++++++++++ - 1 file changed, 21 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -1122,6 +1122,27 @@ power-domain@RK3588_PD_SDMMC { - }; - }; - -+ vpu121: video-codec@fdb50000 { -+ compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu"; -+ reg = <0x0 0xfdb50000 0x0 0x800>; -+ interrupts = ; -+ interrupt-names = "vdpu"; -+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; -+ clock-names = "aclk", "hclk"; -+ iommus = <&vpu121_mmu>; -+ power-domains = <&power RK3588_PD_VDPU>; -+ }; -+ -+ vpu121_mmu: iommu@fdb50800 { -+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; -+ reg = <0x0 0xfdb50800 0x0 0x40>; -+ interrupts = ; -+ clock-names = "aclk", "iface"; -+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; -+ power-domains = <&power RK3588_PD_VDPU>; -+ #iommu-cells = <0>; -+ }; -+ - vepu121_0: video-codec@fdba0000 { - compatible = "rockchip,rk3588-vepu121"; - reg = <0x0 0xfdba0000 0x0 0x800>; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Mon, 29 Jul 2024 23:21:19 +0300 -Subject: arm64: dts: rockchip: rk3588: disable H264 decoding on Hantro decoder - ---- - Documentation/devicetree/bindings/media/rockchip-vpu.yaml | 2 +- - arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 7 ++++--- - 2 files changed, 5 insertions(+), 4 deletions(-) - -diff --git a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml -index 111111111111..222222222222 100644 ---- a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml -+++ b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml -@@ -33,7 +33,7 @@ properties: - - const: rockchip,rk3399-vpu - - items: - - const: rockchip,rk3588-vpu121 -- - const: rockchip,rk3568-vpu -+ - const: rockchip,rk3399-vpu - - reg: - maxItems: 1 -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -1123,10 +1123,11 @@ power-domain@RK3588_PD_SDMMC { - }; - - vpu121: video-codec@fdb50000 { -- compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu"; -+ compatible = "rockchip,rk3588-vpu121", "rockchip,rk3399-vpu"; - reg = <0x0 0xfdb50000 0x0 0x800>; -- interrupts = ; -- interrupt-names = "vdpu"; -+ interrupts = , -+ ; -+ interrupt-names = "vepu", "vdpu"; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "hclk"; - iommus = <&vpu121_mmu>; --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.12/0029-arm64-dts-rockchip-rk3588-add-RGA2-node.patch b/patch/kernel/archive/rockchip-rk3588-6.12/0029-arm64-dts-rockchip-rk3588-add-RGA2-node.patch deleted file mode 100644 index abb8d16837..0000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.12/0029-arm64-dts-rockchip-rk3588-add-RGA2-node.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Muhammed Efe Cetin -Date: Mon, 13 May 2024 20:29:49 +0300 -Subject: arm64: dts: rockchip: rk3588: add VDPU and RGA2 nodes - ---- - arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 11 ++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -566,6 +566,17 @@ mmu600_php: iommu@fcb00000 { - status = "disabled"; - }; - -+ rga: rga@fdb80000 { -+ compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga"; -+ reg = <0x0 0xfdb80000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru ACLK_RGA2>, <&cru HCLK_RGA2>, <&cru CLK_RGA2_CORE>; -+ clock-names = "aclk", "hclk", "sclk"; -+ resets = <&cru SRST_RGA2_CORE>, <&cru SRST_A_RGA2>, <&cru SRST_H_RGA2>; -+ reset-names = "core", "axi", "ahb"; -+ power-domains = <&power RK3588_PD_VDPU>; -+ }; -+ - pmu1grf: syscon@fd58a000 { - compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; - reg = <0x0 0xfd58a000 0x0 0x10000>; --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.12/0130-phy-phy-rockchip-samsung-hdptx-Enable-runtime-PM.patch b/patch/kernel/archive/rockchip-rk3588-6.12/0130-phy-phy-rockchip-samsung-hdptx-Enable-runtime-PM.patch deleted file mode 100644 index 387f39d1df..0000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.12/0130-phy-phy-rockchip-samsung-hdptx-Enable-runtime-PM.patch +++ /dev/null @@ -1,91 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Tue, 11 Jun 2024 02:28:26 +0300 -Subject: phy: phy-rockchip-samsung-hdptx: Enable runtime PM at PHY core level - -When a new PHY is created via [devm_]phy_create(), the runtime PM for it -is not enabled unless the parent device (which creates the PHY) has its -own runtime PM already enabled. - -Move the call to devm_pm_runtime_enable() before devm_phy_create() to -enable runtime PM at PHY core level. - -With this change the ->power_on() and ->power_off() callbacks do not -require explicit runtime PM management anymore, since the PHY core -handles that via phy_pm_runtime_{get,put}_sync() when phy_power_on() and -phy_power_off() are invoked. - -Hence drop the now unnecessary calls to pm_runtime_resume_and_get() and -pm_runtime_put() helpers. - -Signed-off-by: Cristian Ciocaltea ---- - drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 24 +++------- - 1 file changed, 6 insertions(+), 18 deletions(-) - -diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c -index 111111111111..222222222222 100644 ---- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c -+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c -@@ -860,7 +860,7 @@ static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx, - static int rk_hdptx_phy_power_on(struct phy *phy) - { - struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy); -- int ret, bus_width = phy_get_bus_width(hdptx->phy); -+ int bus_width = phy_get_bus_width(hdptx->phy); - /* - * FIXME: Temporary workaround to pass pixel_clk_rate - * from the HDMI bridge driver until phy_configure_opts_hdmi -@@ -871,17 +871,7 @@ static int rk_hdptx_phy_power_on(struct phy *phy) - dev_dbg(hdptx->dev, "%s bus_width=%x rate=%u\n", - __func__, bus_width, rate); - -- ret = pm_runtime_resume_and_get(hdptx->dev); -- if (ret) { -- dev_err(hdptx->dev, "Failed to resume phy: %d\n", ret); -- return ret; -- } -- -- ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate); -- if (ret) -- pm_runtime_put(hdptx->dev); -- -- return ret; -+ return rk_hdptx_ropll_tmds_mode_config(hdptx, rate); - } - - static int rk_hdptx_phy_power_off(struct phy *phy) -@@ -894,8 +884,6 @@ static int rk_hdptx_phy_power_off(struct phy *phy) - if (ret == 0 && (val & HDPTX_O_PLL_LOCK_DONE)) - rk_hdptx_phy_disable(hdptx); - -- pm_runtime_put(hdptx->dev); -- - return ret; - } - -@@ -977,6 +965,10 @@ static int rk_hdptx_phy_probe(struct platform_device *pdev) - return dev_err_probe(dev, PTR_ERR(hdptx->grf), - "Could not get GRF syscon\n"); - -+ ret = devm_pm_runtime_enable(dev); -+ if (ret) -+ return dev_err_probe(dev, ret, "Failed to enable runtime PM\n"); -+ - hdptx->phy = devm_phy_create(dev, NULL, &rk_hdptx_phy_ops); - if (IS_ERR(hdptx->phy)) - return dev_err_probe(dev, PTR_ERR(hdptx->phy), -@@ -986,10 +978,6 @@ static int rk_hdptx_phy_probe(struct platform_device *pdev) - phy_set_drvdata(hdptx->phy, hdptx); - phy_set_bus_width(hdptx->phy, 8); - -- ret = devm_pm_runtime_enable(dev); -- if (ret) -- return dev_err_probe(dev, ret, "Failed to enable runtime PM\n"); -- - phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); - if (IS_ERR(phy_provider)) - return dev_err_probe(dev, PTR_ERR(phy_provider), --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.12/0131-phy-phy-rockchip-samsung-hdptx-Add-clock-provider.patch b/patch/kernel/archive/rockchip-rk3588-6.12/0131-phy-phy-rockchip-samsung-hdptx-Add-clock-provider.patch deleted file mode 100644 index 721cf796ee..0000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.12/0131-phy-phy-rockchip-samsung-hdptx-Add-clock-provider.patch +++ /dev/null @@ -1,323 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Mon, 19 Feb 2024 21:53:24 +0200 -Subject: dt-bindings: phy: rockchip,rk3588-hdptx-phy: Add #clock-cells - -The HDMI PHY can be used as a clock provider on RK3588 SoC, hence add -the necessary '#clock-cells' property. - -Signed-off-by: Cristian Ciocaltea ---- - Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml -index 111111111111..222222222222 100644 ---- a/Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml -+++ b/Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml -@@ -27,6 +27,9 @@ properties: - - const: ref - - const: apb - -+ "#clock-cells": -+ const: 0 -+ - "#phy-cells": - const: 0 - --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Tue, 16 Jan 2024 19:27:40 +0200 -Subject: phy: phy-rockchip-samsung-hdptx: Add clock provider support - -The HDMI PHY PLL can be used as an alternative dclk source to RK3588 SoC -CRU. It provides more accurate clock rates required by VOP2 to improve -existing support for display modes handling, which is known to be -problematic when dealing with non-integer refresh rates, among others. - -It is worth noting this only works for HDMI 2.0 or below, e.g. cannot be -used to support HDMI 2.1 4K@120Hz mode. - -Signed-off-by: Cristian Ciocaltea ---- - drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 195 ++++++++-- - 1 file changed, 173 insertions(+), 22 deletions(-) - -diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c -index 111111111111..222222222222 100644 ---- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c -+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c -@@ -8,6 +8,7 @@ - */ - #include - #include -+#include - #include - #include - #include -@@ -191,6 +192,8 @@ - #define LN3_TX_SER_RATE_SEL_HBR2 BIT(3) - #define LN3_TX_SER_RATE_SEL_HBR3 BIT(2) - -+#define HDMI20_MAX_RATE 600000000 -+ - struct lcpll_config { - u32 bit_rate; - u8 lcvco_mode_en; -@@ -273,6 +276,12 @@ struct rk_hdptx_phy { - struct clk_bulk_data *clks; - int nr_clks; - struct reset_control_bulk_data rsts[RST_MAX]; -+ -+ /* clk provider */ -+ struct clk_hw hw; -+ unsigned long rate; -+ -+ atomic_t usage_count; - }; - - static const struct ropll_config ropll_tmds_cfg[] = { -@@ -760,6 +769,8 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx, - struct ropll_config rc = {0}; - int i; - -+ hdptx->rate = rate * 100; -+ - for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) - if (rate == ropll_tmds_cfg[i].bit_rate) { - cfg = &ropll_tmds_cfg[i]; -@@ -823,19 +834,6 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx, - static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx, - unsigned int rate) - { -- u32 val; -- int ret; -- -- ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val); -- if (ret) -- return ret; -- -- if (!(val & HDPTX_O_PLL_LOCK_DONE)) { -- ret = rk_hdptx_ropll_tmds_cmn_config(hdptx, rate); -- if (ret) -- return ret; -- } -- - rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq); - - regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06); -@@ -857,10 +855,68 @@ static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx, - return rk_hdptx_post_enable_lane(hdptx); - } - -+static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx, -+ unsigned int rate) -+{ -+ u32 status; -+ int ret; -+ -+ if (atomic_inc_return(&hdptx->usage_count) > 1) -+ return 0; -+ -+ ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status); -+ if (ret) -+ goto dec_usage; -+ -+ if (status & HDPTX_O_PLL_LOCK_DONE) -+ dev_warn(hdptx->dev, "PLL locked by unknown consumer!\n"); -+ -+ if (rate) { -+ ret = rk_hdptx_ropll_tmds_cmn_config(hdptx, rate); -+ if (ret) -+ goto dec_usage; -+ } -+ -+ return 0; -+ -+dec_usage: -+ atomic_dec(&hdptx->usage_count); -+ return ret; -+} -+ -+static int rk_hdptx_phy_consumer_put(struct rk_hdptx_phy *hdptx, bool force) -+{ -+ u32 status; -+ int ret; -+ -+ ret = atomic_dec_return(&hdptx->usage_count); -+ if (ret > 0) -+ return 0; -+ -+ if (ret < 0) { -+ dev_warn(hdptx->dev, "Usage count underflow!\n"); -+ ret = -EINVAL; -+ } else { -+ ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status); -+ if (!ret) { -+ if (status & HDPTX_O_PLL_LOCK_DONE) -+ rk_hdptx_phy_disable(hdptx); -+ return 0; -+ } else if (force) { -+ return 0; -+ } -+ } -+ -+ atomic_inc(&hdptx->usage_count); -+ return ret; -+} -+ - static int rk_hdptx_phy_power_on(struct phy *phy) - { - struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy); - int bus_width = phy_get_bus_width(hdptx->phy); -+ int ret; -+ - /* - * FIXME: Temporary workaround to pass pixel_clk_rate - * from the HDMI bridge driver until phy_configure_opts_hdmi -@@ -871,20 +927,22 @@ static int rk_hdptx_phy_power_on(struct phy *phy) - dev_dbg(hdptx->dev, "%s bus_width=%x rate=%u\n", - __func__, bus_width, rate); - -- return rk_hdptx_ropll_tmds_mode_config(hdptx, rate); -+ ret = rk_hdptx_phy_consumer_get(hdptx, rate); -+ if (ret) -+ return ret; -+ -+ ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate); -+ if (ret) -+ rk_hdptx_phy_consumer_put(hdptx, true); -+ -+ return ret; - } - - static int rk_hdptx_phy_power_off(struct phy *phy) - { - struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy); -- u32 val; -- int ret; - -- ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val); -- if (ret == 0 && (val & HDPTX_O_PLL_LOCK_DONE)) -- rk_hdptx_phy_disable(hdptx); -- -- return ret; -+ return rk_hdptx_phy_consumer_put(hdptx, false); - } - - static const struct phy_ops rk_hdptx_phy_ops = { -@@ -893,6 +951,99 @@ static const struct phy_ops rk_hdptx_phy_ops = { - .owner = THIS_MODULE, - }; - -+static struct rk_hdptx_phy *to_rk_hdptx_phy(struct clk_hw *hw) -+{ -+ return container_of(hw, struct rk_hdptx_phy, hw); -+} -+ -+static int rk_hdptx_phy_clk_prepare(struct clk_hw *hw) -+{ -+ struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); -+ -+ return rk_hdptx_phy_consumer_get(hdptx, hdptx->rate / 100); -+} -+ -+static void rk_hdptx_phy_clk_unprepare(struct clk_hw *hw) -+{ -+ struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); -+ -+ rk_hdptx_phy_consumer_put(hdptx, true); -+} -+ -+static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); -+ -+ return hdptx->rate; -+} -+ -+static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long *parent_rate) -+{ -+ u32 bit_rate = rate / 100; -+ int i; -+ -+ if (rate > HDMI20_MAX_RATE) -+ return rate; -+ -+ for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) -+ if (bit_rate == ropll_tmds_cfg[i].bit_rate) -+ break; -+ -+ if (i == ARRAY_SIZE(ropll_tmds_cfg) && -+ !rk_hdptx_phy_clk_pll_calc(bit_rate, NULL)) -+ return -EINVAL; -+ -+ return rate; -+} -+ -+static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate, -+ unsigned long parent_rate) -+{ -+ struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); -+ -+ return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate / 100); -+} -+ -+static const struct clk_ops hdptx_phy_clk_ops = { -+ .prepare = rk_hdptx_phy_clk_prepare, -+ .unprepare = rk_hdptx_phy_clk_unprepare, -+ .recalc_rate = rk_hdptx_phy_clk_recalc_rate, -+ .round_rate = rk_hdptx_phy_clk_round_rate, -+ .set_rate = rk_hdptx_phy_clk_set_rate, -+}; -+ -+static int rk_hdptx_phy_clk_register(struct rk_hdptx_phy *hdptx) -+{ -+ struct device *dev = hdptx->dev; -+ const char *name, *pname; -+ struct clk *refclk; -+ int ret, id; -+ -+ refclk = devm_clk_get(dev, "ref"); -+ if (IS_ERR(refclk)) -+ return dev_err_probe(dev, PTR_ERR(refclk), -+ "Failed to get ref clock\n"); -+ -+ id = of_alias_get_id(dev->of_node, "hdptxphy"); -+ name = id > 0 ? "clk_hdmiphy_pixel1" : "clk_hdmiphy_pixel0"; -+ pname = __clk_get_name(refclk); -+ -+ hdptx->hw.init = CLK_HW_INIT(name, pname, &hdptx_phy_clk_ops, -+ CLK_GET_RATE_NOCACHE); -+ -+ ret = devm_clk_hw_register(dev, &hdptx->hw); -+ if (ret) -+ return dev_err_probe(dev, ret, "Failed to register clock\n"); -+ -+ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &hdptx->hw); -+ if (ret) -+ return dev_err_probe(dev, ret, -+ "Failed to register clk provider\n"); -+ return 0; -+} -+ - static int rk_hdptx_phy_runtime_suspend(struct device *dev) - { - struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev); -@@ -987,7 +1138,7 @@ static int rk_hdptx_phy_probe(struct platform_device *pdev) - reset_control_deassert(hdptx->rsts[RST_CMN].rstc); - reset_control_deassert(hdptx->rsts[RST_INIT].rstc); - -- return 0; -+ return rk_hdptx_phy_clk_register(hdptx); - } - - static const struct dev_pm_ops rk_hdptx_phy_pm_ops = { --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.12/0134-drm-bridge-synopsys-Add-initial-support-for-DW-HDMI-Controller.patch b/patch/kernel/archive/rockchip-rk3588-6.12/0134-drm-bridge-synopsys-Add-initial-support-for-DW-HDMI-Controller.patch deleted file mode 100644 index 35f16d8ba3..0000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.12/0134-drm-bridge-synopsys-Add-initial-support-for-DW-HDMI-Controller.patch +++ /dev/null @@ -1,2603 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Fri, 26 Jul 2024 02:54:52 +0300 -Subject: dt-bindings: display: bridge: Add schema for Synopsys DW HDMI QP TX - IP - -Add dt-binding schema containing the common properties for the Synopsys -DesignWare HDMI QP TX controller. - -Note this is not a full dt-binding specification, but is meant to be -referenced by platform-specific bindings for this IP core. - -Signed-off-by: Cristian Ciocaltea ---- - Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi-qp.yaml | 66 ++++++++++ - 1 file changed, 66 insertions(+) - -diff --git a/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi-qp.yaml b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi-qp.yaml -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi-qp.yaml -@@ -0,0 +1,66 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi-qp.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Common Properties for Synopsys DesignWare HDMI QP TX Controller IP -+ -+maintainers: -+ - Cristian Ciocaltea -+ -+description: | -+ This document defines device tree properties for the Synopsys DesignWare -+ HDMI 2.1 Quad-Pixel (QP) TX controller IP core. -+ It doesn't constitute a device tree binding specification by itself, but -+ is meant to be referenced by platform-specific device tree bindings. -+ -+ When referenced from platform device tree bindings, the properties defined -+ in this document are defined as follows. The platform device tree bindings -+ are responsible for defining whether each property is required or optional. -+ -+properties: -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ minItems: 4 -+ maxItems: 6 -+ items: -+ - description: Peripheral/APB bus clock -+ - description: EARC RX biphase clock -+ - description: Reference clock -+ - description: Audio interface clock -+ additionalItems: true -+ -+ clock-names: -+ minItems: 4 -+ maxItems: 6 -+ items: -+ - const: pclk -+ - const: earc -+ - const: ref -+ - const: aud -+ additionalItems: true -+ -+ interrupts: -+ minItems: 4 -+ maxItems: 5 -+ items: -+ - description: AVP Unit interrupt -+ - description: CEC interrupt -+ - description: eARC RX interrupt -+ - description: Main Unit interrupt -+ additionalItems: true -+ -+ interrupt-names: -+ minItems: 4 -+ maxItems: 5 -+ items: -+ - const: avp -+ - const: cec -+ - const: earc -+ - const: main -+ additionalItems: true -+ -+additionalProperties: true --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Mon, 20 May 2024 14:49:50 +0300 -Subject: drm/bridge: synopsys: Add DW HDMI QP TX Controller driver - -The Synopsys DesignWare HDMI 2.1 Quad-Pixel (QP) TX Controller supports -the following features, among others: - -* Fixed Rate Link (FRL) -* Display Stream Compression (DSC) -* 4K@120Hz and 8K@60Hz video modes -* Variable Refresh Rate (VRR) including Quick Media Switching (QMS), aka - Cinema VRR -* Fast Vactive (FVA), aka Quick Frame Transport (QFT) -* SCDC I2C DDC access -* TMDS Scrambler enabling 2160p@60Hz with RGB/YCbCr4:4:4 -* YCbCr4:2:0 enabling 2160p@60Hz at lower HDMI link speeds -* Multi-stream audio -* Enhanced Audio Return Channel (EARC) - -Add driver to enable basic support, i.e. RGB output up to 4K@60Hz, -without audio, CEC or any HDMI 2.1 specific features. - -Co-developed-by: Algea Cao -Signed-off-by: Algea Cao -Signed-off-by: Cristian Ciocaltea ---- - drivers/gpu/drm/bridge/synopsys/Kconfig | 8 + - drivers/gpu/drm/bridge/synopsys/Makefile | 2 + - drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 748 +++++++++ - drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h | 834 ++++++++++ - include/drm/bridge/dw_hdmi_qp.h | 37 + - 5 files changed, 1629 insertions(+) - -diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig b/drivers/gpu/drm/bridge/synopsys/Kconfig -index 111111111111..222222222222 100644 ---- a/drivers/gpu/drm/bridge/synopsys/Kconfig -+++ b/drivers/gpu/drm/bridge/synopsys/Kconfig -@@ -46,6 +46,14 @@ config DRM_DW_HDMI_CEC - Support the CE interface which is part of the Synopsys - Designware HDMI block. - -+config DRM_DW_HDMI_QP -+ tristate -+ select DRM_DISPLAY_HDMI_HELPER -+ select DRM_DISPLAY_HDMI_STATE_HELPER -+ select DRM_DISPLAY_HELPER -+ select DRM_KMS_HELPER -+ select REGMAP_MMIO -+ - config DRM_DW_MIPI_DSI - tristate - select DRM_KMS_HELPER -diff --git a/drivers/gpu/drm/bridge/synopsys/Makefile b/drivers/gpu/drm/bridge/synopsys/Makefile -index 111111111111..222222222222 100644 ---- a/drivers/gpu/drm/bridge/synopsys/Makefile -+++ b/drivers/gpu/drm/bridge/synopsys/Makefile -@@ -5,4 +5,6 @@ obj-$(CONFIG_DRM_DW_HDMI_GP_AUDIO) += dw-hdmi-gp-audio.o - obj-$(CONFIG_DRM_DW_HDMI_I2S_AUDIO) += dw-hdmi-i2s-audio.o - obj-$(CONFIG_DRM_DW_HDMI_CEC) += dw-hdmi-cec.o - -+obj-$(CONFIG_DRM_DW_HDMI_QP) += dw-hdmi-qp.o -+ - obj-$(CONFIG_DRM_DW_MIPI_DSI) += dw-mipi-dsi.o -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c -@@ -0,0 +1,748 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* -+ * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd. -+ * Copyright (c) 2024 Collabora Ltd. -+ * -+ * Author: Algea Cao -+ * Author: Cristian Ciocaltea -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "dw-hdmi-qp.h" -+ -+#define DDC_CI_ADDR 0x37 -+#define DDC_SEGMENT_ADDR 0x30 -+ -+#define SCDC_MIN_SOURCE_VERSION 0x1 -+ -+#define HDMI14_MAX_TMDSCLK 340000000 -+ -+struct dw_hdmi_qp_i2c { -+ struct i2c_adapter adap; -+ -+ struct mutex lock; /* used to serialize data transfers */ -+ struct completion cmp; -+ u8 stat; -+ -+ u8 slave_reg; -+ bool is_regaddr; -+ bool is_segment; -+}; -+ -+struct dw_hdmi_qp { -+ struct drm_bridge bridge; -+ -+ struct device *dev; -+ struct dw_hdmi_qp_i2c *i2c; -+ -+ struct { -+ const struct dw_hdmi_qp_phy_ops *ops; -+ void *data; -+ } phy; -+ -+ struct clk *ref_clk; -+ -+ struct drm_connector *curr_conn; -+ unsigned long long pix_clock; -+ -+ struct regmap *regm; -+}; -+ -+/* Filter out invalid setups to avoid configuring SCDC and scrambling */ -+static bool dw_hdmi_qp_support_scdc(struct dw_hdmi_qp *hdmi, -+ const struct drm_display_info *display) -+{ -+ /* Disable if no DDC bus */ -+ if (!hdmi->bridge.ddc) -+ return false; -+ -+ /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */ -+ if (!display->hdmi.scdc.supported || -+ !display->hdmi.scdc.scrambling.supported) -+ return false; -+ -+ /* -+ * Disable if display only support low TMDS rates and scrambling -+ * for low rates is not supported either -+ */ -+ if (!display->hdmi.scdc.scrambling.low_rates && -+ display->max_tmds_clock <= 340000) -+ return false; -+ -+ return true; -+} -+ -+int dw_hdmi_qp_set_refclk_rate(struct dw_hdmi_qp *hdmi, unsigned long rate) -+{ -+ return clk_set_rate(hdmi->ref_clk, rate); -+} -+EXPORT_SYMBOL_GPL(dw_hdmi_qp_set_refclk_rate); -+ -+/* -+ * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates: -+ * - The Source shall suspend transmission of the TMDS clock and data -+ * -+ * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it -+ * from a 0 to a 1 or from a 1 to a 0 -+ * -+ * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from -+ * the time the TMDS_Bit_Clock_Ratio bit is written until resuming -+ * transmission of TMDS clock and data -+ * -+ * To respect the 100ms max delay, the dw_hdmi_qp_set_high_tmds_clock_ratio() -+ * helper should be called right before enabling the TMDS Clock and Data in -+ * the PHY configuration callback. -+ */ -+void dw_hdmi_qp_set_high_tmds_clock_ratio(struct dw_hdmi_qp *hdmi, -+ const struct drm_display_info *display) -+{ -+ bool set; -+ -+ if (hdmi->curr_conn && dw_hdmi_qp_support_scdc(hdmi, display)) { -+ set = (hdmi->pix_clock > HDMI14_MAX_TMDSCLK); -+ drm_scdc_set_high_tmds_clock_ratio(hdmi->curr_conn, set); -+ } -+} -+EXPORT_SYMBOL_GPL(dw_hdmi_qp_set_high_tmds_clock_ratio); -+ -+static void dw_hdmi_qp_write(struct dw_hdmi_qp *hdmi, unsigned int val, -+ int offset) -+{ -+ regmap_write(hdmi->regm, offset, val); -+} -+ -+static unsigned int dw_hdmi_qp_read(struct dw_hdmi_qp *hdmi, int offset) -+{ -+ unsigned int val = 0; -+ -+ regmap_read(hdmi->regm, offset, &val); -+ -+ return val; -+} -+ -+static void dw_hdmi_qp_mod(struct dw_hdmi_qp *hdmi, unsigned int data, -+ unsigned int mask, unsigned int reg) -+{ -+ regmap_update_bits(hdmi->regm, reg, mask, data); -+} -+ -+static int dw_hdmi_qp_i2c_read(struct dw_hdmi_qp *hdmi, -+ unsigned char *buf, unsigned int length) -+{ -+ struct dw_hdmi_qp_i2c *i2c = hdmi->i2c; -+ int stat; -+ -+ if (!i2c->is_regaddr) { -+ dev_dbg(hdmi->dev, "set read register address to 0\n"); -+ i2c->slave_reg = 0x00; -+ i2c->is_regaddr = true; -+ } -+ -+ while (length--) { -+ reinit_completion(&i2c->cmp); -+ -+ dw_hdmi_qp_mod(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR, -+ I2CM_INTERFACE_CONTROL0); -+ -+ if (i2c->is_segment) -+ dw_hdmi_qp_mod(hdmi, I2CM_EXT_READ, I2CM_WR_MASK, -+ I2CM_INTERFACE_CONTROL0); -+ else -+ dw_hdmi_qp_mod(hdmi, I2CM_FM_READ, I2CM_WR_MASK, -+ I2CM_INTERFACE_CONTROL0); -+ -+ stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); -+ if (!stat) { -+ dev_err(hdmi->dev, "i2c read timed out\n"); -+ dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); -+ return -EAGAIN; -+ } -+ -+ /* Check for error condition on the bus */ -+ if (i2c->stat & I2CM_NACK_RCVD_IRQ) { -+ dev_err(hdmi->dev, "i2c read error\n"); -+ dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); -+ return -EIO; -+ } -+ -+ *buf++ = dw_hdmi_qp_read(hdmi, I2CM_INTERFACE_RDDATA_0_3) & 0xff; -+ dw_hdmi_qp_mod(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0); -+ } -+ -+ i2c->is_segment = false; -+ -+ return 0; -+} -+ -+static int dw_hdmi_qp_i2c_write(struct dw_hdmi_qp *hdmi, -+ unsigned char *buf, unsigned int length) -+{ -+ struct dw_hdmi_qp_i2c *i2c = hdmi->i2c; -+ int stat; -+ -+ if (!i2c->is_regaddr) { -+ /* Use the first write byte as register address */ -+ i2c->slave_reg = buf[0]; -+ length--; -+ buf++; -+ i2c->is_regaddr = true; -+ } -+ -+ while (length--) { -+ reinit_completion(&i2c->cmp); -+ -+ dw_hdmi_qp_write(hdmi, *buf++, I2CM_INTERFACE_WRDATA_0_3); -+ dw_hdmi_qp_mod(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR, -+ I2CM_INTERFACE_CONTROL0); -+ dw_hdmi_qp_mod(hdmi, I2CM_FM_WRITE, I2CM_WR_MASK, -+ I2CM_INTERFACE_CONTROL0); -+ -+ stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); -+ if (!stat) { -+ dev_err(hdmi->dev, "i2c write time out!\n"); -+ dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); -+ return -EAGAIN; -+ } -+ -+ /* Check for error condition on the bus */ -+ if (i2c->stat & I2CM_NACK_RCVD_IRQ) { -+ dev_err(hdmi->dev, "i2c write nack!\n"); -+ dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); -+ return -EIO; -+ } -+ -+ dw_hdmi_qp_mod(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0); -+ } -+ -+ return 0; -+} -+ -+static int dw_hdmi_qp_i2c_xfer(struct i2c_adapter *adap, -+ struct i2c_msg *msgs, int num) -+{ -+ struct dw_hdmi_qp *hdmi = i2c_get_adapdata(adap); -+ struct dw_hdmi_qp_i2c *i2c = hdmi->i2c; -+ u8 addr = msgs[0].addr; -+ int i, ret = 0; -+ -+ if (addr == DDC_CI_ADDR) -+ /* -+ * The internal I2C controller does not support the multi-byte -+ * read and write operations needed for DDC/CI. -+ * FIXME: Blacklist the DDC/CI address until we filter out -+ * unsupported I2C operations. -+ */ -+ return -EOPNOTSUPP; -+ -+ for (i = 0; i < num; i++) { -+ if (msgs[i].len == 0) { -+ dev_err(hdmi->dev, -+ "unsupported transfer %d/%d, no data\n", -+ i + 1, num); -+ return -EOPNOTSUPP; -+ } -+ } -+ -+ mutex_lock(&i2c->lock); -+ -+ /* Unmute DONE and ERROR interrupts */ -+ dw_hdmi_qp_mod(hdmi, I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N, -+ I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N, -+ MAINUNIT_1_INT_MASK_N); -+ -+ /* Set slave device address taken from the first I2C message */ -+ if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1) -+ addr = DDC_ADDR; -+ -+ dw_hdmi_qp_mod(hdmi, addr << 5, I2CM_SLVADDR, I2CM_INTERFACE_CONTROL0); -+ -+ /* Set slave device register address on transfer */ -+ i2c->is_regaddr = false; -+ -+ /* Set segment pointer for I2C extended read mode operation */ -+ i2c->is_segment = false; -+ -+ for (i = 0; i < num; i++) { -+ if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { -+ i2c->is_segment = true; -+ dw_hdmi_qp_mod(hdmi, DDC_SEGMENT_ADDR, I2CM_SEG_ADDR, -+ I2CM_INTERFACE_CONTROL1); -+ dw_hdmi_qp_mod(hdmi, *msgs[i].buf << 7, I2CM_SEG_PTR, -+ I2CM_INTERFACE_CONTROL1); -+ } else { -+ if (msgs[i].flags & I2C_M_RD) -+ ret = dw_hdmi_qp_i2c_read(hdmi, msgs[i].buf, -+ msgs[i].len); -+ else -+ ret = dw_hdmi_qp_i2c_write(hdmi, msgs[i].buf, -+ msgs[i].len); -+ } -+ if (ret < 0) -+ break; -+ } -+ -+ if (!ret) -+ ret = num; -+ -+ /* Mute DONE and ERROR interrupts */ -+ dw_hdmi_qp_mod(hdmi, 0, I2CM_OP_DONE_MASK_N | I2CM_NACK_RCVD_MASK_N, -+ MAINUNIT_1_INT_MASK_N); -+ -+ mutex_unlock(&i2c->lock); -+ -+ return ret; -+} -+ -+static u32 dw_hdmi_qp_i2c_func(struct i2c_adapter *adapter) -+{ -+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; -+} -+ -+static const struct i2c_algorithm dw_hdmi_qp_algorithm = { -+ .master_xfer = dw_hdmi_qp_i2c_xfer, -+ .functionality = dw_hdmi_qp_i2c_func, -+}; -+ -+static struct i2c_adapter *dw_hdmi_qp_i2c_adapter(struct dw_hdmi_qp *hdmi) -+{ -+ struct dw_hdmi_qp_i2c *i2c; -+ struct i2c_adapter *adap; -+ int ret; -+ -+ i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); -+ if (!i2c) -+ return ERR_PTR(-ENOMEM); -+ -+ mutex_init(&i2c->lock); -+ init_completion(&i2c->cmp); -+ -+ adap = &i2c->adap; -+ adap->owner = THIS_MODULE; -+ adap->dev.parent = hdmi->dev; -+ adap->algo = &dw_hdmi_qp_algorithm; -+ strscpy(adap->name, "DesignWare HDMI QP", sizeof(adap->name)); -+ -+ i2c_set_adapdata(adap, hdmi); -+ -+ ret = devm_i2c_add_adapter(hdmi->dev, adap); -+ if (ret) { -+ dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); -+ devm_kfree(hdmi->dev, i2c); -+ return ERR_PTR(ret); -+ } -+ -+ hdmi->i2c = i2c; -+ dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name); -+ -+ return adap; -+} -+ -+static int dw_hdmi_qp_config_avi_infoframe(struct dw_hdmi_qp *hdmi, -+ const u8 *buffer, size_t len) -+{ -+ u32 val, i, j; -+ -+ if (len != HDMI_INFOFRAME_SIZE(AVI)) { -+ dev_err(hdmi->dev, "failed to configure avi infoframe\n"); -+ return -EINVAL; -+ } -+ -+ /* -+ * DW HDMI QP IP uses a different byte format from standard AVI info -+ * frames, though generally the bits are in the correct bytes. -+ */ -+ val = buffer[1] << 8 | buffer[2] << 16; -+ dw_hdmi_qp_write(hdmi, val, PKT_AVI_CONTENTS0); -+ -+ for (i = 0; i < 4; i++) { -+ for (j = 0; j < 4; j++) { -+ if (i * 4 + j >= 14) -+ break; -+ if (!j) -+ val = buffer[i * 4 + j + 3]; -+ val |= buffer[i * 4 + j + 3] << (8 * j); -+ } -+ -+ dw_hdmi_qp_write(hdmi, val, PKT_AVI_CONTENTS1 + i * 4); -+ } -+ -+ dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_AVI_FIELDRATE, PKTSCHED_PKT_CONFIG1); -+ -+ dw_hdmi_qp_mod(hdmi, PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, -+ PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, PKTSCHED_PKT_EN); -+ -+ return 0; -+} -+ -+static int dw_hdmi_qp_config_drm_infoframe(struct dw_hdmi_qp *hdmi, -+ const u8 *buffer, size_t len) -+{ -+ u32 val, i; -+ -+ if (len != HDMI_INFOFRAME_SIZE(DRM)) { -+ dev_err(hdmi->dev, "failed to configure drm infoframe\n"); -+ return -EINVAL; -+ } -+ -+ dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN); -+ -+ val = buffer[1] << 8 | buffer[2] << 16; -+ dw_hdmi_qp_write(hdmi, val, PKT_DRMI_CONTENTS0); -+ -+ for (i = 0; i <= buffer[2]; i++) { -+ if (i % 4 == 0) -+ val = buffer[3 + i]; -+ val |= buffer[3 + i] << ((i % 4) * 8); -+ -+ if ((i % 4 == 3) || i == buffer[2]) -+ dw_hdmi_qp_write(hdmi, val, -+ PKT_DRMI_CONTENTS1 + ((i / 4) * 4)); -+ } -+ -+ dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_DRMI_FIELDRATE, PKTSCHED_PKT_CONFIG1); -+ dw_hdmi_qp_mod(hdmi, PKTSCHED_DRMI_TX_EN, PKTSCHED_DRMI_TX_EN, -+ PKTSCHED_PKT_EN); -+ -+ return 0; -+} -+ -+static void dw_hdmi_qp_setup(struct dw_hdmi_qp *hdmi, -+ struct drm_connector *connector) -+{ -+ bool scramb; -+ u8 ver; -+ -+ if (!connector->display_info.is_hdmi) { -+ dev_dbg(hdmi->dev, "%s DVI mode\n", __func__); -+ -+ dw_hdmi_qp_mod(hdmi, HDCP2_BYPASS, HDCP2_BYPASS, -+ HDCP2LOGIC_CONFIG0); -+ dw_hdmi_qp_mod(hdmi, OPMODE_DVI, OPMODE_DVI, LINK_CONFIG0); -+ -+ return; -+ } -+ -+ dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__); -+ -+ dw_hdmi_qp_mod(hdmi, 0, OPMODE_DVI, LINK_CONFIG0); -+ dw_hdmi_qp_mod(hdmi, HDCP2_BYPASS, HDCP2_BYPASS, HDCP2LOGIC_CONFIG0); -+ -+ scramb = (hdmi->pix_clock > HDMI14_MAX_TMDSCLK); -+ -+ if (dw_hdmi_qp_support_scdc(hdmi, &connector->display_info)) { -+ if (scramb) { -+ drm_scdc_readb(hdmi->bridge.ddc, SCDC_SINK_VERSION, &ver); -+ drm_scdc_writeb(hdmi->bridge.ddc, SCDC_SOURCE_VERSION, -+ min_t(u8, ver, SCDC_MIN_SOURCE_VERSION)); -+ } -+ -+ drm_scdc_set_high_tmds_clock_ratio(connector, scramb); -+ drm_scdc_set_scrambling(connector, scramb); -+ } -+ -+ dw_hdmi_qp_write(hdmi, scramb, SCRAMB_CONFIG0); -+} -+ -+static int dw_hdmi_qp_bridge_atomic_check(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state, -+ struct drm_crtc_state *crtc_state, -+ struct drm_connector_state *conn_state) -+{ -+ struct dw_hdmi_qp *hdmi = bridge->driver_private; -+ int ret; -+ -+ ret = drm_atomic_helper_connector_hdmi_check(conn_state->connector, -+ conn_state->state); -+ if (ret) -+ dev_dbg(hdmi->dev, "%s failed: %d\n", __func__, ret); -+ -+ return ret; -+} -+ -+static void dw_hdmi_qp_bridge_atomic_enable(struct drm_bridge *bridge, -+ struct drm_bridge_state *old_state) -+{ -+ struct dw_hdmi_qp *hdmi = bridge->driver_private; -+ struct drm_atomic_state *state = old_state->base.state; -+ struct drm_connector *connector; -+ struct drm_connector_state *conn_state; -+ -+ connector = drm_atomic_get_new_connector_for_encoder(state, -+ bridge->encoder); -+ conn_state = drm_atomic_get_new_connector_state(state, connector); -+ -+ hdmi->pix_clock = conn_state->hdmi.tmds_char_rate; -+ hdmi->curr_conn = connector; -+ -+ hdmi->phy.ops->init(hdmi, hdmi->phy.data, &connector->display_info); -+ -+ dw_hdmi_qp_setup(hdmi, connector); -+ -+ drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); -+} -+ -+static void dw_hdmi_qp_bridge_atomic_disable(struct drm_bridge *bridge, -+ struct drm_bridge_state *old_state) -+{ -+ struct dw_hdmi_qp *hdmi = bridge->driver_private; -+ -+ hdmi->curr_conn = NULL; -+ hdmi->phy.ops->disable(hdmi, hdmi->phy.data); -+} -+ -+static enum drm_connector_status -+dw_hdmi_qp_bridge_detect(struct drm_bridge *bridge) -+{ -+ struct dw_hdmi_qp *hdmi = bridge->driver_private; -+ -+ return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); -+} -+ -+static const struct drm_edid * -+dw_hdmi_qp_bridge_edid_read(struct drm_bridge *bridge, -+ struct drm_connector *connector) -+{ -+ struct dw_hdmi_qp *hdmi = bridge->driver_private; -+ const struct drm_edid *drm_edid; -+ -+ if (!bridge->ddc) -+ return NULL; -+ -+ drm_edid = drm_edid_read_ddc(connector, bridge->ddc); -+ if (!drm_edid) -+ dev_dbg(hdmi->dev, "failed to get edid\n"); -+ -+ return drm_edid; -+} -+ -+static int dw_hdmi_qp_bridge_clear_infoframe(struct drm_bridge *bridge, -+ enum hdmi_infoframe_type type) -+{ -+ struct dw_hdmi_qp *hdmi = bridge->driver_private; -+ -+ switch (type) { -+ case HDMI_INFOFRAME_TYPE_AVI: -+ dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, -+ PKTSCHED_PKT_EN); -+ break; -+ -+ case HDMI_INFOFRAME_TYPE_DRM: -+ dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN); -+ break; -+ -+ default: -+ dev_dbg(hdmi->dev, "Unsupported infoframe type %x\n", type); -+ } -+ -+ return 0; -+} -+ -+static int dw_hdmi_qp_bridge_write_infoframe(struct drm_bridge *bridge, -+ enum hdmi_infoframe_type type, -+ const u8 *buffer, size_t len) -+{ -+ struct dw_hdmi_qp *hdmi = bridge->driver_private; -+ -+ dw_hdmi_qp_bridge_clear_infoframe(bridge, type); -+ -+ switch (type) { -+ case HDMI_INFOFRAME_TYPE_AVI: -+ return dw_hdmi_qp_config_avi_infoframe(hdmi, buffer, len); -+ -+ case HDMI_INFOFRAME_TYPE_DRM: -+ return dw_hdmi_qp_config_drm_infoframe(hdmi, buffer, len); -+ -+ default: -+ dev_dbg(hdmi->dev, "Unsupported infoframe type %x\n", type); -+ return 0; -+ } -+} -+ -+static const struct drm_bridge_funcs dw_hdmi_qp_bridge_funcs = { -+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, -+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, -+ .atomic_reset = drm_atomic_helper_bridge_reset, -+ .atomic_check = dw_hdmi_qp_bridge_atomic_check, -+ .atomic_enable = dw_hdmi_qp_bridge_atomic_enable, -+ .atomic_disable = dw_hdmi_qp_bridge_atomic_disable, -+ .detect = dw_hdmi_qp_bridge_detect, -+ .edid_read = dw_hdmi_qp_bridge_edid_read, -+ .hdmi_clear_infoframe = dw_hdmi_qp_bridge_clear_infoframe, -+ .hdmi_write_infoframe = dw_hdmi_qp_bridge_write_infoframe, -+}; -+ -+static irqreturn_t dw_hdmi_qp_main_hardirq(int irq, void *dev_id) -+{ -+ struct dw_hdmi_qp *hdmi = dev_id; -+ struct dw_hdmi_qp_i2c *i2c = hdmi->i2c; -+ u32 stat; -+ -+ stat = dw_hdmi_qp_read(hdmi, MAINUNIT_1_INT_STATUS); -+ -+ i2c->stat = stat & (I2CM_OP_DONE_IRQ | I2CM_READ_REQUEST_IRQ | -+ I2CM_NACK_RCVD_IRQ); -+ -+ if (i2c->stat) { -+ dw_hdmi_qp_write(hdmi, i2c->stat, MAINUNIT_1_INT_CLEAR); -+ complete(&i2c->cmp); -+ } -+ -+ if (stat) -+ return IRQ_HANDLED; -+ -+ return IRQ_NONE; -+} -+ -+static const struct regmap_config dw_hdmi_qp_regmap_config = { -+ .reg_bits = 32, -+ .val_bits = 32, -+ .reg_stride = 4, -+ .max_register = EARCRX_1_INT_FORCE, -+}; -+ -+static void dw_hdmi_qp_init_hw(struct dw_hdmi_qp *hdmi) -+{ -+ dw_hdmi_qp_write(hdmi, 0, MAINUNIT_0_INT_MASK_N); -+ dw_hdmi_qp_write(hdmi, 0, MAINUNIT_1_INT_MASK_N); -+ dw_hdmi_qp_write(hdmi, 428571429, TIMER_BASE_CONFIG0); -+ -+ /* Software reset */ -+ dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); -+ -+ dw_hdmi_qp_write(hdmi, 0x085c085c, I2CM_FM_SCL_CONFIG0); -+ -+ dw_hdmi_qp_mod(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0); -+ -+ /* Clear DONE and ERROR interrupts */ -+ dw_hdmi_qp_write(hdmi, I2CM_OP_DONE_CLEAR | I2CM_NACK_RCVD_CLEAR, -+ MAINUNIT_1_INT_CLEAR); -+ -+ if (hdmi->phy.ops->setup_hpd) -+ hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); -+} -+ -+struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev, -+ struct drm_encoder *encoder, -+ const struct dw_hdmi_qp_plat_data *plat_data) -+{ -+ static const char * const clk_names[] = { -+ "pclk", "earc", "aud", "ref" /* keep "ref" last */ -+ }; -+ struct device *dev = &pdev->dev; -+ struct dw_hdmi_qp *hdmi; -+ void __iomem *regs; -+ struct clk *clk; -+ int irq, ret, i; -+ -+ if (!plat_data->phy_ops || !plat_data->phy_ops->init || -+ !plat_data->phy_ops->disable || !plat_data->phy_ops->read_hpd) { -+ dev_err(dev, "Missing platform PHY ops\n"); -+ return ERR_PTR(-ENODEV); -+ } -+ -+ hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); -+ if (!hdmi) -+ return ERR_PTR(-ENOMEM); -+ -+ hdmi->dev = dev; -+ -+ regs = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(regs)) -+ return regs; -+ -+ hdmi->regm = devm_regmap_init_mmio(dev, regs, &dw_hdmi_qp_regmap_config); -+ if (IS_ERR(hdmi->regm)) { -+ dev_err(dev, "Failed to configure regmap\n"); -+ return ERR_CAST(hdmi->regm); -+ } -+ -+ for (i = 0; i < ARRAY_SIZE(clk_names); i++) { -+ clk = devm_clk_get_enabled(hdmi->dev, clk_names[i]); -+ -+ if (IS_ERR(clk)) { -+ if (PTR_ERR(clk) != -EPROBE_DEFER) -+ dev_err(dev, "Failed to get %s clock\n", -+ clk_names[i]); -+ return ERR_CAST(clk); -+ } -+ } -+ hdmi->ref_clk = clk; -+ -+ hdmi->phy.ops = plat_data->phy_ops; -+ hdmi->phy.data = plat_data->phy_data; -+ -+ dw_hdmi_qp_init_hw(hdmi); -+ -+ irq = platform_get_irq_byname(pdev, "main"); -+ if (irq < 0) -+ return ERR_PTR(irq); -+ -+ ret = devm_request_threaded_irq(dev, irq, -+ dw_hdmi_qp_main_hardirq, NULL, -+ IRQF_SHARED, dev_name(dev), hdmi); -+ if (ret) -+ return ERR_PTR(ret); -+ -+ hdmi->bridge.driver_private = hdmi; -+ hdmi->bridge.funcs = &dw_hdmi_qp_bridge_funcs; -+ hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | -+ DRM_BRIDGE_OP_EDID | -+ DRM_BRIDGE_OP_HDMI | -+ DRM_BRIDGE_OP_HPD; -+ hdmi->bridge.of_node = pdev->dev.of_node; -+ hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA; -+ hdmi->bridge.vendor = "Synopsys"; -+ hdmi->bridge.product = "DW HDMI QP TX"; -+ -+ hdmi->bridge.ddc = dw_hdmi_qp_i2c_adapter(hdmi); -+ if (IS_ERR(hdmi->bridge.ddc)) -+ hdmi->bridge.ddc = NULL; -+ -+ ret = devm_drm_bridge_add(dev, &hdmi->bridge); -+ if (ret) -+ return ERR_PTR(ret); -+ -+ ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, -+ DRM_BRIDGE_ATTACH_NO_CONNECTOR); -+ if (ret) -+ return ERR_PTR(ret); -+ -+ return hdmi; -+} -+EXPORT_SYMBOL_GPL(dw_hdmi_qp_bind); -+ -+void dw_hdmi_qp_unbind(struct dw_hdmi_qp *hdmi) -+{ -+} -+EXPORT_SYMBOL_GPL(dw_hdmi_qp_unbind); -+ -+void dw_hdmi_qp_resume(struct device *dev, struct dw_hdmi_qp *hdmi) -+{ -+ dw_hdmi_qp_init_hw(hdmi); -+} -+EXPORT_SYMBOL_GPL(dw_hdmi_qp_resume); -+ -+MODULE_AUTHOR("Algea Cao "); -+MODULE_AUTHOR("Cristian Ciocaltea "); -+MODULE_DESCRIPTION("DW HDMI QP transmitter driver"); -+MODULE_LICENSE("GPL"); -+MODULE_ALIAS("platform:dw-hdmi-qp"); -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h -@@ -0,0 +1,834 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright (C) Rockchip Electronics Co.Ltd -+ * Author: -+ * Algea Cao -+ */ -+#ifndef __DW_HDMI_QP_H__ -+#define __DW_HDMI_QP_H__ -+ -+#include -+ -+/* Main Unit Registers */ -+#define CORE_ID 0x0 -+#define VER_NUMBER 0x4 -+#define VER_TYPE 0x8 -+#define CONFIG_REG 0xc -+#define CONFIG_CEC BIT(28) -+#define CONFIG_AUD_UD BIT(23) -+#define CORE_TIMESTAMP_HHMM 0x14 -+#define CORE_TIMESTAMP_MMDD 0x18 -+#define CORE_TIMESTAMP_YYYY 0x1c -+/* Reset Manager Registers */ -+#define GLOBAL_SWRESET_REQUEST 0x40 -+#define EARCRX_CMDC_SWINIT_P BIT(27) -+#define AVP_DATAPATH_PACKET_AUDIO_SWINIT_P BIT(10) -+#define GLOBAL_SWDISABLE 0x44 -+#define CEC_SWDISABLE BIT(17) -+#define AVP_DATAPATH_PACKET_AUDIO_SWDISABLE BIT(10) -+#define AVP_DATAPATH_VIDEO_SWDISABLE BIT(6) -+#define RESET_MANAGER_CONFIG0 0x48 -+#define RESET_MANAGER_STATUS0 0x50 -+#define RESET_MANAGER_STATUS1 0x54 -+#define RESET_MANAGER_STATUS2 0x58 -+/* Timer Base Registers */ -+#define TIMER_BASE_CONFIG0 0x80 -+#define TIMER_BASE_STATUS0 0x84 -+/* CMU Registers */ -+#define CMU_CONFIG0 0xa0 -+#define CMU_CONFIG1 0xa4 -+#define CMU_CONFIG2 0xa8 -+#define CMU_CONFIG3 0xac -+#define CMU_STATUS 0xb0 -+#define DISPLAY_CLK_MONITOR 0x3f -+#define DISPLAY_CLK_LOCKED 0X15 -+#define EARC_BPCLK_OFF BIT(9) -+#define AUDCLK_OFF BIT(7) -+#define LINKQPCLK_OFF BIT(5) -+#define VIDQPCLK_OFF BIT(3) -+#define IPI_CLK_OFF BIT(1) -+#define CMU_IPI_CLK_FREQ 0xb4 -+#define CMU_VIDQPCLK_FREQ 0xb8 -+#define CMU_LINKQPCLK_FREQ 0xbc -+#define CMU_AUDQPCLK_FREQ 0xc0 -+#define CMU_EARC_BPCLK_FREQ 0xc4 -+/* I2CM Registers */ -+#define I2CM_SM_SCL_CONFIG0 0xe0 -+#define I2CM_FM_SCL_CONFIG0 0xe4 -+#define I2CM_CONFIG0 0xe8 -+#define I2CM_CONTROL0 0xec -+#define I2CM_STATUS0 0xf0 -+#define I2CM_INTERFACE_CONTROL0 0xf4 -+#define I2CM_ADDR 0xff000 -+#define I2CM_SLVADDR 0xfe0 -+#define I2CM_WR_MASK 0x1e -+#define I2CM_EXT_READ BIT(4) -+#define I2CM_SHORT_READ BIT(3) -+#define I2CM_FM_READ BIT(2) -+#define I2CM_FM_WRITE BIT(1) -+#define I2CM_FM_EN BIT(0) -+#define I2CM_INTERFACE_CONTROL1 0xf8 -+#define I2CM_SEG_PTR 0x7f80 -+#define I2CM_SEG_ADDR 0x7f -+#define I2CM_INTERFACE_WRDATA_0_3 0xfc -+#define I2CM_INTERFACE_WRDATA_4_7 0x100 -+#define I2CM_INTERFACE_WRDATA_8_11 0x104 -+#define I2CM_INTERFACE_WRDATA_12_15 0x108 -+#define I2CM_INTERFACE_RDDATA_0_3 0x10c -+#define I2CM_INTERFACE_RDDATA_4_7 0x110 -+#define I2CM_INTERFACE_RDDATA_8_11 0x114 -+#define I2CM_INTERFACE_RDDATA_12_15 0x118 -+/* SCDC Registers */ -+#define SCDC_CONFIG0 0x140 -+#define SCDC_I2C_FM_EN BIT(12) -+#define SCDC_UPD_FLAGS_AUTO_CLR BIT(6) -+#define SCDC_UPD_FLAGS_POLL_EN BIT(4) -+#define SCDC_CONTROL0 0x148 -+#define SCDC_STATUS0 0x150 -+#define STATUS_UPDATE BIT(0) -+#define FRL_START BIT(4) -+#define FLT_UPDATE BIT(5) -+/* FLT Registers */ -+#define FLT_CONFIG0 0x160 -+#define FLT_CONFIG1 0x164 -+#define FLT_CONFIG2 0x168 -+#define FLT_CONTROL0 0x170 -+/* Main Unit 2 Registers */ -+#define MAINUNIT_STATUS0 0x180 -+/* Video Interface Registers */ -+#define VIDEO_INTERFACE_CONFIG0 0x800 -+#define VIDEO_INTERFACE_CONFIG1 0x804 -+#define VIDEO_INTERFACE_CONFIG2 0x808 -+#define VIDEO_INTERFACE_CONTROL0 0x80c -+#define VIDEO_INTERFACE_STATUS0 0x814 -+/* Video Packing Registers */ -+#define VIDEO_PACKING_CONFIG0 0x81c -+/* Audio Interface Registers */ -+#define AUDIO_INTERFACE_CONFIG0 0x820 -+#define AUD_IF_SEL_MSK 0x3 -+#define AUD_IF_SPDIF 0x2 -+#define AUD_IF_I2S 0x1 -+#define AUD_IF_PAI 0x0 -+#define AUD_FIFO_INIT_ON_OVF_MSK BIT(2) -+#define AUD_FIFO_INIT_ON_OVF_EN BIT(2) -+#define I2S_LINES_EN_MSK GENMASK(7, 4) -+#define I2S_LINES_EN(x) BIT((x) + 4) -+#define I2S_BPCUV_RCV_MSK BIT(12) -+#define I2S_BPCUV_RCV_EN BIT(12) -+#define I2S_BPCUV_RCV_DIS 0 -+#define SPDIF_LINES_EN GENMASK(19, 16) -+#define AUD_FORMAT_MSK GENMASK(26, 24) -+#define AUD_3DOBA (0x7 << 24) -+#define AUD_3DASP (0x6 << 24) -+#define AUD_MSOBA (0x5 << 24) -+#define AUD_MSASP (0x4 << 24) -+#define AUD_HBR (0x3 << 24) -+#define AUD_DST (0x2 << 24) -+#define AUD_OBA (0x1 << 24) -+#define AUD_ASP (0x0 << 24) -+#define AUDIO_INTERFACE_CONFIG1 0x824 -+#define AUDIO_INTERFACE_CONTROL0 0x82c -+#define AUDIO_FIFO_CLR_P BIT(0) -+#define AUDIO_INTERFACE_STATUS0 0x834 -+/* Frame Composer Registers */ -+#define FRAME_COMPOSER_CONFIG0 0x840 -+#define FRAME_COMPOSER_CONFIG1 0x844 -+#define FRAME_COMPOSER_CONFIG2 0x848 -+#define FRAME_COMPOSER_CONFIG3 0x84c -+#define FRAME_COMPOSER_CONFIG4 0x850 -+#define FRAME_COMPOSER_CONFIG5 0x854 -+#define FRAME_COMPOSER_CONFIG6 0x858 -+#define FRAME_COMPOSER_CONFIG7 0x85c -+#define FRAME_COMPOSER_CONFIG8 0x860 -+#define FRAME_COMPOSER_CONFIG9 0x864 -+#define FRAME_COMPOSER_CONTROL0 0x86c -+/* Video Monitor Registers */ -+#define VIDEO_MONITOR_CONFIG0 0x880 -+#define VIDEO_MONITOR_STATUS0 0x884 -+#define VIDEO_MONITOR_STATUS1 0x888 -+#define VIDEO_MONITOR_STATUS2 0x88c -+#define VIDEO_MONITOR_STATUS3 0x890 -+#define VIDEO_MONITOR_STATUS4 0x894 -+#define VIDEO_MONITOR_STATUS5 0x898 -+#define VIDEO_MONITOR_STATUS6 0x89c -+/* HDCP2 Logic Registers */ -+#define HDCP2LOGIC_CONFIG0 0x8e0 -+#define HDCP2_BYPASS BIT(0) -+#define HDCP2LOGIC_ESM_GPIO_IN 0x8e4 -+#define HDCP2LOGIC_ESM_GPIO_OUT 0x8e8 -+/* HDCP14 Registers */ -+#define HDCP14_CONFIG0 0x900 -+#define HDCP14_CONFIG1 0x904 -+#define HDCP14_CONFIG2 0x908 -+#define HDCP14_CONFIG3 0x90c -+#define HDCP14_KEY_SEED 0x914 -+#define HDCP14_KEY_H 0x918 -+#define HDCP14_KEY_L 0x91c -+#define HDCP14_KEY_STATUS 0x920 -+#define HDCP14_AKSV_H 0x924 -+#define HDCP14_AKSV_L 0x928 -+#define HDCP14_AN_H 0x92c -+#define HDCP14_AN_L 0x930 -+#define HDCP14_STATUS0 0x934 -+#define HDCP14_STATUS1 0x938 -+/* Scrambler Registers */ -+#define SCRAMB_CONFIG0 0x960 -+/* Video Configuration Registers */ -+#define LINK_CONFIG0 0x968 -+#define OPMODE_FRL_4LANES BIT(8) -+#define OPMODE_DVI BIT(4) -+#define OPMODE_FRL BIT(0) -+/* TMDS FIFO Registers */ -+#define TMDS_FIFO_CONFIG0 0x970 -+#define TMDS_FIFO_CONTROL0 0x974 -+/* FRL RSFEC Registers */ -+#define FRL_RSFEC_CONFIG0 0xa20 -+#define FRL_RSFEC_STATUS0 0xa30 -+/* FRL Packetizer Registers */ -+#define FRL_PKTZ_CONFIG0 0xa40 -+#define FRL_PKTZ_CONTROL0 0xa44 -+#define FRL_PKTZ_CONTROL1 0xa50 -+#define FRL_PKTZ_STATUS1 0xa54 -+/* Packet Scheduler Registers */ -+#define PKTSCHED_CONFIG0 0xa80 -+#define PKTSCHED_PRQUEUE0_CONFIG0 0xa84 -+#define PKTSCHED_PRQUEUE1_CONFIG0 0xa88 -+#define PKTSCHED_PRQUEUE2_CONFIG0 0xa8c -+#define PKTSCHED_PRQUEUE2_CONFIG1 0xa90 -+#define PKTSCHED_PRQUEUE2_CONFIG2 0xa94 -+#define PKTSCHED_PKT_CONFIG0 0xa98 -+#define PKTSCHED_PKT_CONFIG1 0xa9c -+#define PKTSCHED_DRMI_FIELDRATE BIT(13) -+#define PKTSCHED_AVI_FIELDRATE BIT(12) -+#define PKTSCHED_PKT_CONFIG2 0xaa0 -+#define PKTSCHED_PKT_CONFIG3 0xaa4 -+#define PKTSCHED_PKT_EN 0xaa8 -+#define PKTSCHED_DRMI_TX_EN BIT(17) -+#define PKTSCHED_AUDI_TX_EN BIT(15) -+#define PKTSCHED_AVI_TX_EN BIT(13) -+#define PKTSCHED_EMP_CVTEM_TX_EN BIT(10) -+#define PKTSCHED_AMD_TX_EN BIT(8) -+#define PKTSCHED_GCP_TX_EN BIT(3) -+#define PKTSCHED_AUDS_TX_EN BIT(2) -+#define PKTSCHED_ACR_TX_EN BIT(1) -+#define PKTSCHED_NULL_TX_EN BIT(0) -+#define PKTSCHED_PKT_CONTROL0 0xaac -+#define PKTSCHED_PKT_SEND 0xab0 -+#define PKTSCHED_PKT_STATUS0 0xab4 -+#define PKTSCHED_PKT_STATUS1 0xab8 -+#define PKT_NULL_CONTENTS0 0xb00 -+#define PKT_NULL_CONTENTS1 0xb04 -+#define PKT_NULL_CONTENTS2 0xb08 -+#define PKT_NULL_CONTENTS3 0xb0c -+#define PKT_NULL_CONTENTS4 0xb10 -+#define PKT_NULL_CONTENTS5 0xb14 -+#define PKT_NULL_CONTENTS6 0xb18 -+#define PKT_NULL_CONTENTS7 0xb1c -+#define PKT_ACP_CONTENTS0 0xb20 -+#define PKT_ACP_CONTENTS1 0xb24 -+#define PKT_ACP_CONTENTS2 0xb28 -+#define PKT_ACP_CONTENTS3 0xb2c -+#define PKT_ACP_CONTENTS4 0xb30 -+#define PKT_ACP_CONTENTS5 0xb34 -+#define PKT_ACP_CONTENTS6 0xb38 -+#define PKT_ACP_CONTENTS7 0xb3c -+#define PKT_ISRC1_CONTENTS0 0xb40 -+#define PKT_ISRC1_CONTENTS1 0xb44 -+#define PKT_ISRC1_CONTENTS2 0xb48 -+#define PKT_ISRC1_CONTENTS3 0xb4c -+#define PKT_ISRC1_CONTENTS4 0xb50 -+#define PKT_ISRC1_CONTENTS5 0xb54 -+#define PKT_ISRC1_CONTENTS6 0xb58 -+#define PKT_ISRC1_CONTENTS7 0xb5c -+#define PKT_ISRC2_CONTENTS0 0xb60 -+#define PKT_ISRC2_CONTENTS1 0xb64 -+#define PKT_ISRC2_CONTENTS2 0xb68 -+#define PKT_ISRC2_CONTENTS3 0xb6c -+#define PKT_ISRC2_CONTENTS4 0xb70 -+#define PKT_ISRC2_CONTENTS5 0xb74 -+#define PKT_ISRC2_CONTENTS6 0xb78 -+#define PKT_ISRC2_CONTENTS7 0xb7c -+#define PKT_GMD_CONTENTS0 0xb80 -+#define PKT_GMD_CONTENTS1 0xb84 -+#define PKT_GMD_CONTENTS2 0xb88 -+#define PKT_GMD_CONTENTS3 0xb8c -+#define PKT_GMD_CONTENTS4 0xb90 -+#define PKT_GMD_CONTENTS5 0xb94 -+#define PKT_GMD_CONTENTS6 0xb98 -+#define PKT_GMD_CONTENTS7 0xb9c -+#define PKT_AMD_CONTENTS0 0xba0 -+#define PKT_AMD_CONTENTS1 0xba4 -+#define PKT_AMD_CONTENTS2 0xba8 -+#define PKT_AMD_CONTENTS3 0xbac -+#define PKT_AMD_CONTENTS4 0xbb0 -+#define PKT_AMD_CONTENTS5 0xbb4 -+#define PKT_AMD_CONTENTS6 0xbb8 -+#define PKT_AMD_CONTENTS7 0xbbc -+#define PKT_VSI_CONTENTS0 0xbc0 -+#define PKT_VSI_CONTENTS1 0xbc4 -+#define PKT_VSI_CONTENTS2 0xbc8 -+#define PKT_VSI_CONTENTS3 0xbcc -+#define PKT_VSI_CONTENTS4 0xbd0 -+#define PKT_VSI_CONTENTS5 0xbd4 -+#define PKT_VSI_CONTENTS6 0xbd8 -+#define PKT_VSI_CONTENTS7 0xbdc -+#define PKT_AVI_CONTENTS0 0xbe0 -+#define HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT BIT(4) -+#define HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR 0x04 -+#define HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR 0x08 -+#define HDMI_FC_AVICONF2_IT_CONTENT_VALID 0x80 -+#define PKT_AVI_CONTENTS1 0xbe4 -+#define PKT_AVI_CONTENTS2 0xbe8 -+#define PKT_AVI_CONTENTS3 0xbec -+#define PKT_AVI_CONTENTS4 0xbf0 -+#define PKT_AVI_CONTENTS5 0xbf4 -+#define PKT_AVI_CONTENTS6 0xbf8 -+#define PKT_AVI_CONTENTS7 0xbfc -+#define PKT_SPDI_CONTENTS0 0xc00 -+#define PKT_SPDI_CONTENTS1 0xc04 -+#define PKT_SPDI_CONTENTS2 0xc08 -+#define PKT_SPDI_CONTENTS3 0xc0c -+#define PKT_SPDI_CONTENTS4 0xc10 -+#define PKT_SPDI_CONTENTS5 0xc14 -+#define PKT_SPDI_CONTENTS6 0xc18 -+#define PKT_SPDI_CONTENTS7 0xc1c -+#define PKT_AUDI_CONTENTS0 0xc20 -+#define PKT_AUDI_CONTENTS1 0xc24 -+#define PKT_AUDI_CONTENTS2 0xc28 -+#define PKT_AUDI_CONTENTS3 0xc2c -+#define PKT_AUDI_CONTENTS4 0xc30 -+#define PKT_AUDI_CONTENTS5 0xc34 -+#define PKT_AUDI_CONTENTS6 0xc38 -+#define PKT_AUDI_CONTENTS7 0xc3c -+#define PKT_NVI_CONTENTS0 0xc40 -+#define PKT_NVI_CONTENTS1 0xc44 -+#define PKT_NVI_CONTENTS2 0xc48 -+#define PKT_NVI_CONTENTS3 0xc4c -+#define PKT_NVI_CONTENTS4 0xc50 -+#define PKT_NVI_CONTENTS5 0xc54 -+#define PKT_NVI_CONTENTS6 0xc58 -+#define PKT_NVI_CONTENTS7 0xc5c -+#define PKT_DRMI_CONTENTS0 0xc60 -+#define PKT_DRMI_CONTENTS1 0xc64 -+#define PKT_DRMI_CONTENTS2 0xc68 -+#define PKT_DRMI_CONTENTS3 0xc6c -+#define PKT_DRMI_CONTENTS4 0xc70 -+#define PKT_DRMI_CONTENTS5 0xc74 -+#define PKT_DRMI_CONTENTS6 0xc78 -+#define PKT_DRMI_CONTENTS7 0xc7c -+#define PKT_GHDMI1_CONTENTS0 0xc80 -+#define PKT_GHDMI1_CONTENTS1 0xc84 -+#define PKT_GHDMI1_CONTENTS2 0xc88 -+#define PKT_GHDMI1_CONTENTS3 0xc8c -+#define PKT_GHDMI1_CONTENTS4 0xc90 -+#define PKT_GHDMI1_CONTENTS5 0xc94 -+#define PKT_GHDMI1_CONTENTS6 0xc98 -+#define PKT_GHDMI1_CONTENTS7 0xc9c -+#define PKT_GHDMI2_CONTENTS0 0xca0 -+#define PKT_GHDMI2_CONTENTS1 0xca4 -+#define PKT_GHDMI2_CONTENTS2 0xca8 -+#define PKT_GHDMI2_CONTENTS3 0xcac -+#define PKT_GHDMI2_CONTENTS4 0xcb0 -+#define PKT_GHDMI2_CONTENTS5 0xcb4 -+#define PKT_GHDMI2_CONTENTS6 0xcb8 -+#define PKT_GHDMI2_CONTENTS7 0xcbc -+/* EMP Packetizer Registers */ -+#define PKT_EMP_CONFIG0 0xce0 -+#define PKT_EMP_CONTROL0 0xcec -+#define PKT_EMP_CONTROL1 0xcf0 -+#define PKT_EMP_CONTROL2 0xcf4 -+#define PKT_EMP_VTEM_CONTENTS0 0xd00 -+#define PKT_EMP_VTEM_CONTENTS1 0xd04 -+#define PKT_EMP_VTEM_CONTENTS2 0xd08 -+#define PKT_EMP_VTEM_CONTENTS3 0xd0c -+#define PKT_EMP_VTEM_CONTENTS4 0xd10 -+#define PKT_EMP_VTEM_CONTENTS5 0xd14 -+#define PKT_EMP_VTEM_CONTENTS6 0xd18 -+#define PKT_EMP_VTEM_CONTENTS7 0xd1c -+#define PKT0_EMP_CVTEM_CONTENTS0 0xd20 -+#define PKT0_EMP_CVTEM_CONTENTS1 0xd24 -+#define PKT0_EMP_CVTEM_CONTENTS2 0xd28 -+#define PKT0_EMP_CVTEM_CONTENTS3 0xd2c -+#define PKT0_EMP_CVTEM_CONTENTS4 0xd30 -+#define PKT0_EMP_CVTEM_CONTENTS5 0xd34 -+#define PKT0_EMP_CVTEM_CONTENTS6 0xd38 -+#define PKT0_EMP_CVTEM_CONTENTS7 0xd3c -+#define PKT1_EMP_CVTEM_CONTENTS0 0xd40 -+#define PKT1_EMP_CVTEM_CONTENTS1 0xd44 -+#define PKT1_EMP_CVTEM_CONTENTS2 0xd48 -+#define PKT1_EMP_CVTEM_CONTENTS3 0xd4c -+#define PKT1_EMP_CVTEM_CONTENTS4 0xd50 -+#define PKT1_EMP_CVTEM_CONTENTS5 0xd54 -+#define PKT1_EMP_CVTEM_CONTENTS6 0xd58 -+#define PKT1_EMP_CVTEM_CONTENTS7 0xd5c -+#define PKT2_EMP_CVTEM_CONTENTS0 0xd60 -+#define PKT2_EMP_CVTEM_CONTENTS1 0xd64 -+#define PKT2_EMP_CVTEM_CONTENTS2 0xd68 -+#define PKT2_EMP_CVTEM_CONTENTS3 0xd6c -+#define PKT2_EMP_CVTEM_CONTENTS4 0xd70 -+#define PKT2_EMP_CVTEM_CONTENTS5 0xd74 -+#define PKT2_EMP_CVTEM_CONTENTS6 0xd78 -+#define PKT2_EMP_CVTEM_CONTENTS7 0xd7c -+#define PKT3_EMP_CVTEM_CONTENTS0 0xd80 -+#define PKT3_EMP_CVTEM_CONTENTS1 0xd84 -+#define PKT3_EMP_CVTEM_CONTENTS2 0xd88 -+#define PKT3_EMP_CVTEM_CONTENTS3 0xd8c -+#define PKT3_EMP_CVTEM_CONTENTS4 0xd90 -+#define PKT3_EMP_CVTEM_CONTENTS5 0xd94 -+#define PKT3_EMP_CVTEM_CONTENTS6 0xd98 -+#define PKT3_EMP_CVTEM_CONTENTS7 0xd9c -+#define PKT4_EMP_CVTEM_CONTENTS0 0xda0 -+#define PKT4_EMP_CVTEM_CONTENTS1 0xda4 -+#define PKT4_EMP_CVTEM_CONTENTS2 0xda8 -+#define PKT4_EMP_CVTEM_CONTENTS3 0xdac -+#define PKT4_EMP_CVTEM_CONTENTS4 0xdb0 -+#define PKT4_EMP_CVTEM_CONTENTS5 0xdb4 -+#define PKT4_EMP_CVTEM_CONTENTS6 0xdb8 -+#define PKT4_EMP_CVTEM_CONTENTS7 0xdbc -+#define PKT5_EMP_CVTEM_CONTENTS0 0xdc0 -+#define PKT5_EMP_CVTEM_CONTENTS1 0xdc4 -+#define PKT5_EMP_CVTEM_CONTENTS2 0xdc8 -+#define PKT5_EMP_CVTEM_CONTENTS3 0xdcc -+#define PKT5_EMP_CVTEM_CONTENTS4 0xdd0 -+#define PKT5_EMP_CVTEM_CONTENTS5 0xdd4 -+#define PKT5_EMP_CVTEM_CONTENTS6 0xdd8 -+#define PKT5_EMP_CVTEM_CONTENTS7 0xddc -+/* Audio Packetizer Registers */ -+#define AUDPKT_CONTROL0 0xe20 -+#define AUDPKT_PBIT_FORCE_EN_MASK BIT(12) -+#define AUDPKT_PBIT_FORCE_EN BIT(12) -+#define AUDPKT_CHSTATUS_OVR_EN_MASK BIT(0) -+#define AUDPKT_CHSTATUS_OVR_EN BIT(0) -+#define AUDPKT_CONTROL1 0xe24 -+#define AUDPKT_ACR_CONTROL0 0xe40 -+#define AUDPKT_ACR_N_VALUE 0xfffff -+#define AUDPKT_ACR_CONTROL1 0xe44 -+#define AUDPKT_ACR_CTS_OVR_VAL_MSK GENMASK(23, 4) -+#define AUDPKT_ACR_CTS_OVR_VAL(x) ((x) << 4) -+#define AUDPKT_ACR_CTS_OVR_EN_MSK BIT(1) -+#define AUDPKT_ACR_CTS_OVR_EN BIT(1) -+#define AUDPKT_ACR_STATUS0 0xe4c -+#define AUDPKT_CHSTATUS_OVR0 0xe60 -+#define AUDPKT_CHSTATUS_OVR1 0xe64 -+/* IEC60958 Byte 3: Sampleing frenuency Bits 24 to 27 */ -+#define AUDPKT_CHSTATUS_SR_MASK GENMASK(3, 0) -+#define AUDPKT_CHSTATUS_SR_22050 0x4 -+#define AUDPKT_CHSTATUS_SR_24000 0x6 -+#define AUDPKT_CHSTATUS_SR_32000 0x3 -+#define AUDPKT_CHSTATUS_SR_44100 0x0 -+#define AUDPKT_CHSTATUS_SR_48000 0x2 -+#define AUDPKT_CHSTATUS_SR_88200 0x8 -+#define AUDPKT_CHSTATUS_SR_96000 0xa -+#define AUDPKT_CHSTATUS_SR_176400 0xc -+#define AUDPKT_CHSTATUS_SR_192000 0xe -+#define AUDPKT_CHSTATUS_SR_768000 0x9 -+#define AUDPKT_CHSTATUS_SR_NOT_INDICATED 0x1 -+/* IEC60958 Byte 4: Original Sampleing frenuency Bits 36 to 39 */ -+#define AUDPKT_CHSTATUS_0SR_MASK GENMASK(15, 12) -+#define AUDPKT_CHSTATUS_OSR_8000 0x6 -+#define AUDPKT_CHSTATUS_OSR_11025 0xa -+#define AUDPKT_CHSTATUS_OSR_12000 0x2 -+#define AUDPKT_CHSTATUS_OSR_16000 0x8 -+#define AUDPKT_CHSTATUS_OSR_22050 0xb -+#define AUDPKT_CHSTATUS_OSR_24000 0x9 -+#define AUDPKT_CHSTATUS_OSR_32000 0xc -+#define AUDPKT_CHSTATUS_OSR_44100 0xf -+#define AUDPKT_CHSTATUS_OSR_48000 0xd -+#define AUDPKT_CHSTATUS_OSR_88200 0x7 -+#define AUDPKT_CHSTATUS_OSR_96000 0x5 -+#define AUDPKT_CHSTATUS_OSR_176400 0x3 -+#define AUDPKT_CHSTATUS_OSR_192000 0x1 -+#define AUDPKT_CHSTATUS_OSR_NOT_INDICATED 0x0 -+#define AUDPKT_CHSTATUS_OVR2 0xe68 -+#define AUDPKT_CHSTATUS_OVR3 0xe6c -+#define AUDPKT_CHSTATUS_OVR4 0xe70 -+#define AUDPKT_CHSTATUS_OVR5 0xe74 -+#define AUDPKT_CHSTATUS_OVR6 0xe78 -+#define AUDPKT_CHSTATUS_OVR7 0xe7c -+#define AUDPKT_CHSTATUS_OVR8 0xe80 -+#define AUDPKT_CHSTATUS_OVR9 0xe84 -+#define AUDPKT_CHSTATUS_OVR10 0xe88 -+#define AUDPKT_CHSTATUS_OVR11 0xe8c -+#define AUDPKT_CHSTATUS_OVR12 0xe90 -+#define AUDPKT_CHSTATUS_OVR13 0xe94 -+#define AUDPKT_CHSTATUS_OVR14 0xe98 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC0 0xea0 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC1 0xea4 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC2 0xea8 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC3 0xeac -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC4 0xeb0 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC5 0xeb4 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC6 0xeb8 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC7 0xebc -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC8 0xec0 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC9 0xec4 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC10 0xec8 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC11 0xecc -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC12 0xed0 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC13 0xed4 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC14 0xed8 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC15 0xedc -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC16 0xee0 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC17 0xee4 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC18 0xee8 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC19 0xeec -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC20 0xef0 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC21 0xef4 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC22 0xef8 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC23 0xefc -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC24 0xf00 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC25 0xf04 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC26 0xf08 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC27 0xf0c -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC28 0xf10 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC29 0xf14 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC30 0xf18 -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC31 0xf1c -+#define AUDPKT_USRDATA_OVR_MSG_GENERIC32 0xf20 -+#define AUDPKT_VBIT_OVR0 0xf24 -+/* CEC Registers */ -+#define CEC_TX_CONTROL 0x1000 -+#define CEC_STATUS 0x1004 -+#define CEC_CONFIG 0x1008 -+#define CEC_ADDR 0x100c -+#define CEC_TX_COUNT 0x1020 -+#define CEC_TX_DATA3_0 0x1024 -+#define CEC_TX_DATA7_4 0x1028 -+#define CEC_TX_DATA11_8 0x102c -+#define CEC_TX_DATA15_12 0x1030 -+#define CEC_RX_COUNT_STATUS 0x1040 -+#define CEC_RX_DATA3_0 0x1044 -+#define CEC_RX_DATA7_4 0x1048 -+#define CEC_RX_DATA11_8 0x104c -+#define CEC_RX_DATA15_12 0x1050 -+#define CEC_LOCK_CONTROL 0x1054 -+#define CEC_RXQUAL_BITTIME_CONFIG 0x1060 -+#define CEC_RX_BITTIME_CONFIG 0x1064 -+#define CEC_TX_BITTIME_CONFIG 0x1068 -+/* eARC RX CMDC Registers */ -+#define EARCRX_CMDC_CONFIG0 0x1800 -+#define EARCRX_XACTREAD_STOP_CFG BIT(26) -+#define EARCRX_XACTREAD_RETRY_CFG BIT(25) -+#define EARCRX_CMDC_DSCVR_EARCVALID0_TO_DISC1 BIT(24) -+#define EARCRX_CMDC_XACT_RESTART_EN BIT(18) -+#define EARCRX_CMDC_CONFIG1 0x1804 -+#define EARCRX_CMDC_CONTROL 0x1808 -+#define EARCRX_CMDC_HEARTBEAT_LOSS_EN BIT(4) -+#define EARCRX_CMDC_DISCOVERY_EN BIT(3) -+#define EARCRX_CONNECTOR_HPD BIT(1) -+#define EARCRX_CMDC_WHITELIST0_CONFIG 0x180c -+#define EARCRX_CMDC_WHITELIST1_CONFIG 0x1810 -+#define EARCRX_CMDC_WHITELIST2_CONFIG 0x1814 -+#define EARCRX_CMDC_WHITELIST3_CONFIG 0x1818 -+#define EARCRX_CMDC_STATUS 0x181c -+#define EARCRX_CMDC_XACT_INFO 0x1820 -+#define EARCRX_CMDC_XACT_ACTION 0x1824 -+#define EARCRX_CMDC_HEARTBEAT_RXSTAT_SE 0x1828 -+#define EARCRX_CMDC_HEARTBEAT_STATUS 0x182c -+#define EARCRX_CMDC_XACT_WR0 0x1840 -+#define EARCRX_CMDC_XACT_WR1 0x1844 -+#define EARCRX_CMDC_XACT_WR2 0x1848 -+#define EARCRX_CMDC_XACT_WR3 0x184c -+#define EARCRX_CMDC_XACT_WR4 0x1850 -+#define EARCRX_CMDC_XACT_WR5 0x1854 -+#define EARCRX_CMDC_XACT_WR6 0x1858 -+#define EARCRX_CMDC_XACT_WR7 0x185c -+#define EARCRX_CMDC_XACT_WR8 0x1860 -+#define EARCRX_CMDC_XACT_WR9 0x1864 -+#define EARCRX_CMDC_XACT_WR10 0x1868 -+#define EARCRX_CMDC_XACT_WR11 0x186c -+#define EARCRX_CMDC_XACT_WR12 0x1870 -+#define EARCRX_CMDC_XACT_WR13 0x1874 -+#define EARCRX_CMDC_XACT_WR14 0x1878 -+#define EARCRX_CMDC_XACT_WR15 0x187c -+#define EARCRX_CMDC_XACT_WR16 0x1880 -+#define EARCRX_CMDC_XACT_WR17 0x1884 -+#define EARCRX_CMDC_XACT_WR18 0x1888 -+#define EARCRX_CMDC_XACT_WR19 0x188c -+#define EARCRX_CMDC_XACT_WR20 0x1890 -+#define EARCRX_CMDC_XACT_WR21 0x1894 -+#define EARCRX_CMDC_XACT_WR22 0x1898 -+#define EARCRX_CMDC_XACT_WR23 0x189c -+#define EARCRX_CMDC_XACT_WR24 0x18a0 -+#define EARCRX_CMDC_XACT_WR25 0x18a4 -+#define EARCRX_CMDC_XACT_WR26 0x18a8 -+#define EARCRX_CMDC_XACT_WR27 0x18ac -+#define EARCRX_CMDC_XACT_WR28 0x18b0 -+#define EARCRX_CMDC_XACT_WR29 0x18b4 -+#define EARCRX_CMDC_XACT_WR30 0x18b8 -+#define EARCRX_CMDC_XACT_WR31 0x18bc -+#define EARCRX_CMDC_XACT_WR32 0x18c0 -+#define EARCRX_CMDC_XACT_WR33 0x18c4 -+#define EARCRX_CMDC_XACT_WR34 0x18c8 -+#define EARCRX_CMDC_XACT_WR35 0x18cc -+#define EARCRX_CMDC_XACT_WR36 0x18d0 -+#define EARCRX_CMDC_XACT_WR37 0x18d4 -+#define EARCRX_CMDC_XACT_WR38 0x18d8 -+#define EARCRX_CMDC_XACT_WR39 0x18dc -+#define EARCRX_CMDC_XACT_WR40 0x18e0 -+#define EARCRX_CMDC_XACT_WR41 0x18e4 -+#define EARCRX_CMDC_XACT_WR42 0x18e8 -+#define EARCRX_CMDC_XACT_WR43 0x18ec -+#define EARCRX_CMDC_XACT_WR44 0x18f0 -+#define EARCRX_CMDC_XACT_WR45 0x18f4 -+#define EARCRX_CMDC_XACT_WR46 0x18f8 -+#define EARCRX_CMDC_XACT_WR47 0x18fc -+#define EARCRX_CMDC_XACT_WR48 0x1900 -+#define EARCRX_CMDC_XACT_WR49 0x1904 -+#define EARCRX_CMDC_XACT_WR50 0x1908 -+#define EARCRX_CMDC_XACT_WR51 0x190c -+#define EARCRX_CMDC_XACT_WR52 0x1910 -+#define EARCRX_CMDC_XACT_WR53 0x1914 -+#define EARCRX_CMDC_XACT_WR54 0x1918 -+#define EARCRX_CMDC_XACT_WR55 0x191c -+#define EARCRX_CMDC_XACT_WR56 0x1920 -+#define EARCRX_CMDC_XACT_WR57 0x1924 -+#define EARCRX_CMDC_XACT_WR58 0x1928 -+#define EARCRX_CMDC_XACT_WR59 0x192c -+#define EARCRX_CMDC_XACT_WR60 0x1930 -+#define EARCRX_CMDC_XACT_WR61 0x1934 -+#define EARCRX_CMDC_XACT_WR62 0x1938 -+#define EARCRX_CMDC_XACT_WR63 0x193c -+#define EARCRX_CMDC_XACT_WR64 0x1940 -+#define EARCRX_CMDC_XACT_RD0 0x1960 -+#define EARCRX_CMDC_XACT_RD1 0x1964 -+#define EARCRX_CMDC_XACT_RD2 0x1968 -+#define EARCRX_CMDC_XACT_RD3 0x196c -+#define EARCRX_CMDC_XACT_RD4 0x1970 -+#define EARCRX_CMDC_XACT_RD5 0x1974 -+#define EARCRX_CMDC_XACT_RD6 0x1978 -+#define EARCRX_CMDC_XACT_RD7 0x197c -+#define EARCRX_CMDC_XACT_RD8 0x1980 -+#define EARCRX_CMDC_XACT_RD9 0x1984 -+#define EARCRX_CMDC_XACT_RD10 0x1988 -+#define EARCRX_CMDC_XACT_RD11 0x198c -+#define EARCRX_CMDC_XACT_RD12 0x1990 -+#define EARCRX_CMDC_XACT_RD13 0x1994 -+#define EARCRX_CMDC_XACT_RD14 0x1998 -+#define EARCRX_CMDC_XACT_RD15 0x199c -+#define EARCRX_CMDC_XACT_RD16 0x19a0 -+#define EARCRX_CMDC_XACT_RD17 0x19a4 -+#define EARCRX_CMDC_XACT_RD18 0x19a8 -+#define EARCRX_CMDC_XACT_RD19 0x19ac -+#define EARCRX_CMDC_XACT_RD20 0x19b0 -+#define EARCRX_CMDC_XACT_RD21 0x19b4 -+#define EARCRX_CMDC_XACT_RD22 0x19b8 -+#define EARCRX_CMDC_XACT_RD23 0x19bc -+#define EARCRX_CMDC_XACT_RD24 0x19c0 -+#define EARCRX_CMDC_XACT_RD25 0x19c4 -+#define EARCRX_CMDC_XACT_RD26 0x19c8 -+#define EARCRX_CMDC_XACT_RD27 0x19cc -+#define EARCRX_CMDC_XACT_RD28 0x19d0 -+#define EARCRX_CMDC_XACT_RD29 0x19d4 -+#define EARCRX_CMDC_XACT_RD30 0x19d8 -+#define EARCRX_CMDC_XACT_RD31 0x19dc -+#define EARCRX_CMDC_XACT_RD32 0x19e0 -+#define EARCRX_CMDC_XACT_RD33 0x19e4 -+#define EARCRX_CMDC_XACT_RD34 0x19e8 -+#define EARCRX_CMDC_XACT_RD35 0x19ec -+#define EARCRX_CMDC_XACT_RD36 0x19f0 -+#define EARCRX_CMDC_XACT_RD37 0x19f4 -+#define EARCRX_CMDC_XACT_RD38 0x19f8 -+#define EARCRX_CMDC_XACT_RD39 0x19fc -+#define EARCRX_CMDC_XACT_RD40 0x1a00 -+#define EARCRX_CMDC_XACT_RD41 0x1a04 -+#define EARCRX_CMDC_XACT_RD42 0x1a08 -+#define EARCRX_CMDC_XACT_RD43 0x1a0c -+#define EARCRX_CMDC_XACT_RD44 0x1a10 -+#define EARCRX_CMDC_XACT_RD45 0x1a14 -+#define EARCRX_CMDC_XACT_RD46 0x1a18 -+#define EARCRX_CMDC_XACT_RD47 0x1a1c -+#define EARCRX_CMDC_XACT_RD48 0x1a20 -+#define EARCRX_CMDC_XACT_RD49 0x1a24 -+#define EARCRX_CMDC_XACT_RD50 0x1a28 -+#define EARCRX_CMDC_XACT_RD51 0x1a2c -+#define EARCRX_CMDC_XACT_RD52 0x1a30 -+#define EARCRX_CMDC_XACT_RD53 0x1a34 -+#define EARCRX_CMDC_XACT_RD54 0x1a38 -+#define EARCRX_CMDC_XACT_RD55 0x1a3c -+#define EARCRX_CMDC_XACT_RD56 0x1a40 -+#define EARCRX_CMDC_XACT_RD57 0x1a44 -+#define EARCRX_CMDC_XACT_RD58 0x1a48 -+#define EARCRX_CMDC_XACT_RD59 0x1a4c -+#define EARCRX_CMDC_XACT_RD60 0x1a50 -+#define EARCRX_CMDC_XACT_RD61 0x1a54 -+#define EARCRX_CMDC_XACT_RD62 0x1a58 -+#define EARCRX_CMDC_XACT_RD63 0x1a5c -+#define EARCRX_CMDC_XACT_RD64 0x1a60 -+#define EARCRX_CMDC_SYNC_CONFIG 0x1b00 -+/* eARC RX DMAC Registers */ -+#define EARCRX_DMAC_PHY_CONTROL 0x1c00 -+#define EARCRX_DMAC_CONFIG 0x1c08 -+#define EARCRX_DMAC_CONTROL0 0x1c0c -+#define EARCRX_DMAC_AUDIO_EN BIT(1) -+#define EARCRX_DMAC_EN BIT(0) -+#define EARCRX_DMAC_CONTROL1 0x1c10 -+#define EARCRX_DMAC_STATUS 0x1c14 -+#define EARCRX_DMAC_CHSTATUS0 0x1c18 -+#define EARCRX_DMAC_CHSTATUS1 0x1c1c -+#define EARCRX_DMAC_CHSTATUS2 0x1c20 -+#define EARCRX_DMAC_CHSTATUS3 0x1c24 -+#define EARCRX_DMAC_CHSTATUS4 0x1c28 -+#define EARCRX_DMAC_CHSTATUS5 0x1c2c -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC0 0x1c30 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC1 0x1c34 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC2 0x1c38 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC3 0x1c3c -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC4 0x1c40 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC5 0x1c44 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC6 0x1c48 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC7 0x1c4c -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC8 0x1c50 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC9 0x1c54 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC10 0x1c58 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC11 0x1c5c -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT0 0x1c60 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT1 0x1c64 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT2 0x1c68 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT3 0x1c6c -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT4 0x1c70 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT5 0x1c74 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT6 0x1c78 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT7 0x1c7c -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT8 0x1c80 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT9 0x1c84 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT10 0x1c88 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT11 0x1c8c -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT0 0x1c90 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT1 0x1c94 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT2 0x1c98 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT3 0x1c9c -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT4 0x1ca0 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT5 0x1ca4 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT6 0x1ca8 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT7 0x1cac -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT8 0x1cb0 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT9 0x1cb4 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT10 0x1cb8 -+#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT11 0x1cbc -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC0 0x1cc0 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC1 0x1cc4 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC2 0x1cc8 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC3 0x1ccc -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC4 0x1cd0 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC5 0x1cd4 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC6 0x1cd8 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC7 0x1cdc -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC8 0x1ce0 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC9 0x1ce4 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC10 0x1ce8 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC11 0x1cec -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC12 0x1cf0 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC13 0x1cf4 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC14 0x1cf8 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC15 0x1cfc -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC16 0x1d00 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC17 0x1d04 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC18 0x1d08 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC19 0x1d0c -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC20 0x1d10 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC21 0x1d14 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC22 0x1d18 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC23 0x1d1c -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC24 0x1d20 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC25 0x1d24 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC26 0x1d28 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC27 0x1d2c -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC28 0x1d30 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC29 0x1d34 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC30 0x1d38 -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC31 0x1d3c -+#define EARCRX_DMAC_USRDATA_MSG_GENERIC32 0x1d40 -+#define EARCRX_DMAC_CHSTATUS_STREAMER0 0x1d44 -+#define EARCRX_DMAC_CHSTATUS_STREAMER1 0x1d48 -+#define EARCRX_DMAC_CHSTATUS_STREAMER2 0x1d4c -+#define EARCRX_DMAC_CHSTATUS_STREAMER3 0x1d50 -+#define EARCRX_DMAC_CHSTATUS_STREAMER4 0x1d54 -+#define EARCRX_DMAC_CHSTATUS_STREAMER5 0x1d58 -+#define EARCRX_DMAC_CHSTATUS_STREAMER6 0x1d5c -+#define EARCRX_DMAC_CHSTATUS_STREAMER7 0x1d60 -+#define EARCRX_DMAC_CHSTATUS_STREAMER8 0x1d64 -+#define EARCRX_DMAC_CHSTATUS_STREAMER9 0x1d68 -+#define EARCRX_DMAC_CHSTATUS_STREAMER10 0x1d6c -+#define EARCRX_DMAC_CHSTATUS_STREAMER11 0x1d70 -+#define EARCRX_DMAC_CHSTATUS_STREAMER12 0x1d74 -+#define EARCRX_DMAC_CHSTATUS_STREAMER13 0x1d78 -+#define EARCRX_DMAC_CHSTATUS_STREAMER14 0x1d7c -+#define EARCRX_DMAC_USRDATA_STREAMER0 0x1d80 -+/* Main Unit Interrupt Registers */ -+#define MAIN_INTVEC_INDEX 0x3000 -+#define MAINUNIT_0_INT_STATUS 0x3010 -+#define MAINUNIT_0_INT_MASK_N 0x3014 -+#define MAINUNIT_0_INT_CLEAR 0x3018 -+#define MAINUNIT_0_INT_FORCE 0x301c -+#define MAINUNIT_1_INT_STATUS 0x3020 -+#define FLT_EXIT_TO_LTSL_IRQ BIT(22) -+#define FLT_EXIT_TO_LTS4_IRQ BIT(21) -+#define FLT_EXIT_TO_LTSP_IRQ BIT(20) -+#define SCDC_NACK_RCVD_IRQ BIT(12) -+#define SCDC_RR_REPLY_STOP_IRQ BIT(11) -+#define SCDC_UPD_FLAGS_CLR_IRQ BIT(10) -+#define SCDC_UPD_FLAGS_CHG_IRQ BIT(9) -+#define SCDC_UPD_FLAGS_RD_IRQ BIT(8) -+#define I2CM_NACK_RCVD_IRQ BIT(2) -+#define I2CM_READ_REQUEST_IRQ BIT(1) -+#define I2CM_OP_DONE_IRQ BIT(0) -+#define MAINUNIT_1_INT_MASK_N 0x3024 -+#define I2CM_NACK_RCVD_MASK_N BIT(2) -+#define I2CM_READ_REQUEST_MASK_N BIT(1) -+#define I2CM_OP_DONE_MASK_N BIT(0) -+#define MAINUNIT_1_INT_CLEAR 0x3028 -+#define I2CM_NACK_RCVD_CLEAR BIT(2) -+#define I2CM_READ_REQUEST_CLEAR BIT(1) -+#define I2CM_OP_DONE_CLEAR BIT(0) -+#define MAINUNIT_1_INT_FORCE 0x302c -+/* AVPUNIT Interrupt Registers */ -+#define AVP_INTVEC_INDEX 0x3800 -+#define AVP_0_INT_STATUS 0x3810 -+#define AVP_0_INT_MASK_N 0x3814 -+#define AVP_0_INT_CLEAR 0x3818 -+#define AVP_0_INT_FORCE 0x381c -+#define AVP_1_INT_STATUS 0x3820 -+#define AVP_1_INT_MASK_N 0x3824 -+#define HDCP14_AUTH_CHG_MASK_N BIT(6) -+#define AVP_1_INT_CLEAR 0x3828 -+#define AVP_1_INT_FORCE 0x382c -+#define AVP_2_INT_STATUS 0x3830 -+#define AVP_2_INT_MASK_N 0x3834 -+#define AVP_2_INT_CLEAR 0x3838 -+#define AVP_2_INT_FORCE 0x383c -+#define AVP_3_INT_STATUS 0x3840 -+#define AVP_3_INT_MASK_N 0x3844 -+#define AVP_3_INT_CLEAR 0x3848 -+#define AVP_3_INT_FORCE 0x384c -+#define AVP_4_INT_STATUS 0x3850 -+#define AVP_4_INT_MASK_N 0x3854 -+#define AVP_4_INT_CLEAR 0x3858 -+#define AVP_4_INT_FORCE 0x385c -+#define AVP_5_INT_STATUS 0x3860 -+#define AVP_5_INT_MASK_N 0x3864 -+#define AVP_5_INT_CLEAR 0x3868 -+#define AVP_5_INT_FORCE 0x386c -+#define AVP_6_INT_STATUS 0x3870 -+#define AVP_6_INT_MASK_N 0x3874 -+#define AVP_6_INT_CLEAR 0x3878 -+#define AVP_6_INT_FORCE 0x387c -+/* CEC Interrupt Registers */ -+#define CEC_INT_STATUS 0x4000 -+#define CEC_INT_MASK_N 0x4004 -+#define CEC_INT_CLEAR 0x4008 -+#define CEC_INT_FORCE 0x400c -+/* eARC RX Interrupt Registers */ -+#define EARCRX_INTVEC_INDEX 0x4800 -+#define EARCRX_0_INT_STATUS 0x4810 -+#define EARCRX_CMDC_DISCOVERY_TIMEOUT_IRQ BIT(9) -+#define EARCRX_CMDC_DISCOVERY_DONE_IRQ BIT(8) -+#define EARCRX_0_INT_MASK_N 0x4814 -+#define EARCRX_0_INT_CLEAR 0x4818 -+#define EARCRX_0_INT_FORCE 0x481c -+#define EARCRX_1_INT_STATUS 0x4820 -+#define EARCRX_1_INT_MASK_N 0x4824 -+#define EARCRX_1_INT_CLEAR 0x4828 -+#define EARCRX_1_INT_FORCE 0x482c -+ -+#endif /* __DW_HDMI_QP_H__ */ -diff --git a/include/drm/bridge/dw_hdmi_qp.h b/include/drm/bridge/dw_hdmi_qp.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/include/drm/bridge/dw_hdmi_qp.h -@@ -0,0 +1,37 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+/* -+ * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd. -+ * Copyright (c) 2024 Collabora Ltd. -+ */ -+ -+#ifndef __DW_HDMI_QP__ -+#define __DW_HDMI_QP__ -+ -+struct device; -+struct drm_display_info; -+struct drm_encoder; -+struct dw_hdmi_qp; -+struct platform_device; -+ -+struct dw_hdmi_qp_phy_ops { -+ int (*init)(struct dw_hdmi_qp *hdmi, void *data, -+ const struct drm_display_info *display); -+ void (*disable)(struct dw_hdmi_qp *hdmi, void *data); -+ enum drm_connector_status (*read_hpd)(struct dw_hdmi_qp *hdmi, void *data); -+ void (*setup_hpd)(struct dw_hdmi_qp *hdmi, void *data); -+}; -+ -+struct dw_hdmi_qp_plat_data { -+ const struct dw_hdmi_qp_phy_ops *phy_ops; -+ void *phy_data; -+}; -+ -+int dw_hdmi_qp_set_refclk_rate(struct dw_hdmi_qp *hdmi, unsigned long rate); -+void dw_hdmi_qp_set_high_tmds_clock_ratio(struct dw_hdmi_qp *hdmi, -+ const struct drm_display_info *display); -+void dw_hdmi_qp_unbind(struct dw_hdmi_qp *hdmi); -+struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev, -+ struct drm_encoder *encoder, -+ const struct dw_hdmi_qp_plat_data *plat_data); -+void dw_hdmi_qp_resume(struct device *dev, struct dw_hdmi_qp *hdmi); -+#endif /* __DW_HDMI_QP__ */ --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Fri, 26 Jul 2024 03:07:04 +0300 -Subject: dt-bindings: display: rockchip: Add schema for RK3588 HDMI TX - Controller - -Rockchip RK3588 SoC integrates the Synopsys DesignWare HDMI 2.1 -Quad-Pixel (QP) TX controller IP. - -Since this is a new IP block, quite different from those used in the -previous generations of Rockchip SoCs, add a dedicated binding file. - -Signed-off-by: Cristian Ciocaltea ---- - Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi-qp.yaml | 188 ++++++++++ - 1 file changed, 188 insertions(+) - -diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi-qp.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi-qp.yaml -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi-qp.yaml -@@ -0,0 +1,188 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi-qp.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Rockchip DW HDMI QP TX Encoder -+ -+maintainers: -+ - Cristian Ciocaltea -+ -+description: -+ Rockchip RK3588 SoC integrates the Synopsys DesignWare HDMI QP TX controller -+ IP and a HDMI/eDP TX Combo PHY based on a Samsung IP block. -+ -+allOf: -+ - $ref: ../bridge/synopsys,dw-hdmi-qp.yaml# -+ - $ref: /schemas/sound/dai-common.yaml# -+ -+properties: -+ compatible: -+ enum: -+ - rockchip,rk3588-dw-hdmi-qp -+ -+ clocks: -+ minItems: 4 -+ items: -+ - {} -+ - {} -+ - {} -+ - {} -+ # The next clocks are optional, but shall be specified in this -+ # order when present. -+ - description: TMDS/FRL link clock -+ - description: Video datapath clock -+ -+ clock-names: -+ minItems: 4 -+ items: -+ - {} -+ - {} -+ - {} -+ - {} -+ - enum: [hdp, hclk_vo1] -+ - const: hclk_vo1 -+ -+ interrupts: -+ items: -+ - {} -+ - {} -+ - {} -+ - {} -+ - description: HPD interrupt -+ -+ interrupt-names: -+ items: -+ - {} -+ - {} -+ - {} -+ - {} -+ - const: hpd -+ -+ phys: -+ maxItems: 1 -+ description: The HDMI/eDP PHY. -+ -+ phy-names: -+ const: hdmi -+ -+ ports: -+ $ref: /schemas/graph.yaml#/properties/ports -+ -+ properties: -+ port@0: -+ $ref: /schemas/graph.yaml#/properties/port -+ description: -+ Port node with one endpoint connected to a vop node. -+ -+ port@1: -+ $ref: /schemas/graph.yaml#/properties/port -+ description: -+ Port node with one endpoint connected to a hdmi-connector node. -+ -+ required: -+ - port@0 -+ - port@1 -+ -+ power-domains: -+ maxItems: 1 -+ -+ resets: -+ minItems: 2 -+ maxItems: 2 -+ -+ reset-names: -+ items: -+ - const: ref -+ - const: hdp -+ -+ "#sound-dai-cells": -+ const: 0 -+ -+ rockchip,grf: -+ $ref: /schemas/types.yaml#/definitions/phandle -+ description: -+ Most HDMI QP related data is accessed through SYS GRF regs. -+ -+ rockchip,vo1_grf: -+ $ref: /schemas/types.yaml#/definitions/phandle -+ description: -+ Additional HDMI QP related data is accessed through VO1 GRF regs. -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - clock-names -+ - interrupts -+ - interrupt-names -+ - phys -+ - phy-names -+ - ports -+ - resets -+ - reset-names -+ - rockchip,grf -+ - rockchip,vo1_grf -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ #include -+ #include -+ #include -+ #include -+ #include -+ -+ soc { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ hdmi@fde80000 { -+ compatible = "rockchip,rk3588-dw-hdmi-qp"; -+ reg = <0x0 0xfde80000 0x0 0x20000>; -+ clocks = <&cru PCLK_HDMITX0>, -+ <&cru CLK_HDMITX0_EARC>, -+ <&cru CLK_HDMITX0_REF>, -+ <&cru MCLK_I2S5_8CH_TX>, -+ <&cru CLK_HDMIHDP0>, -+ <&cru HCLK_VO1>; -+ clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "avp", "cec", "earc", "main", "hpd"; -+ phys = <&hdptxphy_hdmi0>; -+ phy-names = "hdmi"; -+ power-domains = <&power RK3588_PD_VO1>; -+ resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>; -+ reset-names = "ref", "hdp"; -+ rockchip,grf = <&sys_grf>; -+ rockchip,vo1_grf = <&vo1_grf>; -+ #sound-dai-cells = <0>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ -+ hdmi0_in_vp0: endpoint { -+ remote-endpoint = <&vp0_out_hdmi0>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ -+ hdmi0_out_con0: endpoint { -+ remote-endpoint = <&hdmi_con0_in>; -+ }; -+ }; -+ }; -+ }; -+ }; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Wed, 17 Jul 2024 03:34:36 +0300 -Subject: drm/rockchip: Explicitly include bits header - -Driver makes use of the BIT() macro, but relies on the bits header being -implicitly included. - -Explicitly pull the header in to avoid potential build failures in some -configurations. - -While at it, reorder include directives alphabetically. - -Fixes: 8c8546546f25 ("drm/rockchip: move output interface related definition to rockchip_drm_drv.h") -Signed-off-by: Cristian Ciocaltea ---- - drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -index 111111111111..222222222222 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -@@ -12,9 +12,10 @@ - #include - #include - -+#include -+#include - #include - #include --#include - - #define ROCKCHIP_MAX_FB_BUFFER 3 - #define ROCKCHIP_MAX_CONNECTOR 2 --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Sat, 6 Jul 2024 03:22:35 +0300 -Subject: drm/rockchip: Add basic RK3588 HDMI output support - -The RK3588 SoC family integrates the newer Synopsys DesignWare HDMI 2.1 -Quad-Pixel (QP) TX controller IP and a HDMI/eDP TX Combo PHY based on a -Samsung IP block. - -Add just the basic support for now, i.e. RGB output up to 4K@60Hz, -without audio, CEC or any of the HDMI 2.1 specific features. - -Co-developed-by: Algea Cao -Signed-off-by: Algea Cao -Signed-off-by: Cristian Ciocaltea ---- - drivers/gpu/drm/rockchip/Kconfig | 8 + - drivers/gpu/drm/rockchip/Makefile | 1 + - drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 430 ++++++++++ - drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 2 + - drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 1 + - 5 files changed, 442 insertions(+) - -diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig -index 111111111111..222222222222 100644 ---- a/drivers/gpu/drm/rockchip/Kconfig -+++ b/drivers/gpu/drm/rockchip/Kconfig -@@ -8,6 +8,7 @@ config DRM_ROCKCHIP - select VIDEOMODE_HELPERS - select DRM_ANALOGIX_DP if ROCKCHIP_ANALOGIX_DP - select DRM_DW_HDMI if ROCKCHIP_DW_HDMI -+ select DRM_DW_HDMI_QP if ROCKCHIP_DW_HDMI_QP - select DRM_DW_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI - select GENERIC_PHY if ROCKCHIP_DW_MIPI_DSI - select GENERIC_PHY_MIPI_DPHY if ROCKCHIP_DW_MIPI_DSI -@@ -63,6 +64,13 @@ config ROCKCHIP_DW_HDMI - enable HDMI on RK3288 or RK3399 based SoC, you should select - this option. - -+config ROCKCHIP_DW_HDMI_QP -+ bool "Rockchip specific extensions for Synopsys DW HDMI QP" -+ help -+ This selects support for Rockchip SoC specific extensions -+ for the Synopsys DesignWare HDMI QP driver. If you want to -+ enable HDMI on RK3588 based SoC, you should select this option. -+ - config ROCKCHIP_DW_MIPI_DSI - bool "Rockchip specific extensions for Synopsys DW MIPI DSI" - select GENERIC_PHY_MIPI_DPHY -diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile -index 111111111111..222222222222 100644 ---- a/drivers/gpu/drm/rockchip/Makefile -+++ b/drivers/gpu/drm/rockchip/Makefile -@@ -11,6 +11,7 @@ rockchipdrm-$(CONFIG_ROCKCHIP_VOP) += rockchip_drm_vop.o rockchip_vop_reg.o - rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o - rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o - rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o -+rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI_QP) += dw_hdmi_qp-rockchip.o - rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi-rockchip.o - rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o - rockchipdrm-$(CONFIG_ROCKCHIP_LVDS) += rockchip_lvds.o -diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c -@@ -0,0 +1,430 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* -+ * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd. -+ * Copyright (c) 2024 Collabora Ltd. -+ * -+ * Author: Algea Cao -+ * Author: Cristian Ciocaltea -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "rockchip_drm_drv.h" -+ -+#define RK3588_GRF_SOC_CON2 0x0308 -+#define RK3588_HDMI0_HPD_INT_MSK BIT(13) -+#define RK3588_HDMI0_HPD_INT_CLR BIT(12) -+#define RK3588_GRF_SOC_CON7 0x031c -+#define RK3588_SET_HPD_PATH_MASK GENMASK(13, 12) -+#define RK3588_GRF_SOC_STATUS1 0x0384 -+#define RK3588_HDMI0_LEVEL_INT BIT(16) -+#define RK3588_GRF_VO1_CON3 0x000c -+#define RK3588_SCLIN_MASK BIT(9) -+#define RK3588_SDAIN_MASK BIT(10) -+#define RK3588_MODE_MASK BIT(11) -+#define RK3588_I2S_SEL_MASK BIT(13) -+#define RK3588_GRF_VO1_CON9 0x0024 -+#define RK3588_HDMI0_GRANT_SEL BIT(10) -+ -+#define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16) -+ -+struct rockchip_hdmi_qp { -+ struct device *dev; -+ struct regmap *regmap; -+ struct regmap *vo1_regmap; -+ struct rockchip_encoder encoder; -+ struct dw_hdmi_qp *hdmi; -+ struct phy *phy; -+ struct gpio_desc *enable_gpio; -+ struct delayed_work hpd_work; -+}; -+ -+static struct rockchip_hdmi_qp *to_rockchip_hdmi_qp(struct drm_encoder *encoder) -+{ -+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -+ -+ return container_of(rkencoder, struct rockchip_hdmi_qp, encoder); -+} -+ -+static void -+dw_hdmi_qp_rockchip_encoder_mode_set(struct drm_encoder *encoder, -+ struct drm_display_mode *mode, -+ struct drm_display_mode *adj_mode) -+{ -+ struct rockchip_hdmi_qp *hdmi = to_rockchip_hdmi_qp(encoder); -+ -+ dw_hdmi_qp_set_refclk_rate(hdmi->hdmi, adj_mode->clock * 1000); -+} -+ -+static void dw_hdmi_qp_rockchip_encoder_enable(struct drm_encoder *encoder) -+{ -+ struct rockchip_hdmi_qp *hdmi = to_rockchip_hdmi_qp(encoder); -+ struct drm_crtc *crtc = encoder->crtc; -+ int rate; -+ -+ /* Unconditionally switch to TMDS as FRL is not yet supported */ -+ gpiod_set_value(hdmi->enable_gpio, 1); -+ -+ if (crtc && crtc->state) { -+ dw_hdmi_qp_set_refclk_rate(hdmi->hdmi, -+ crtc->state->adjusted_mode.crtc_clock * 1000); -+ /* -+ * FIXME: Temporary workaround to pass pixel clock rate -+ * to the PHY driver until phy_configure_opts_hdmi -+ * becomes available in the PHY API. See also the related -+ * comment in rk_hdptx_phy_power_on() from -+ * drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c -+ */ -+ rate = crtc->state->mode.clock * 10; -+ phy_set_bus_width(hdmi->phy, rate); -+ drm_dbg(hdmi, "%s set bus_width=%u\n", __func__, rate); -+ } -+} -+ -+static int -+dw_hdmi_qp_rockchip_encoder_atomic_check(struct drm_encoder *encoder, -+ struct drm_crtc_state *crtc_state, -+ struct drm_connector_state *conn_state) -+{ -+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); -+ -+ s->output_mode = ROCKCHIP_OUT_MODE_AAAA; -+ s->output_type = DRM_MODE_CONNECTOR_HDMIA; -+ -+ return 0; -+} -+ -+static const struct -+drm_encoder_helper_funcs dw_hdmi_qp_rockchip_encoder_helper_funcs = { -+ .mode_set = dw_hdmi_qp_rockchip_encoder_mode_set, -+ .enable = dw_hdmi_qp_rockchip_encoder_enable, -+ .atomic_check = dw_hdmi_qp_rockchip_encoder_atomic_check, -+}; -+ -+static int dw_hdmi_qp_rk3588_phy_init(struct dw_hdmi_qp *dw_hdmi, void *data, -+ const struct drm_display_info *display) -+{ -+ struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; -+ -+ dw_hdmi_qp_set_high_tmds_clock_ratio(dw_hdmi, display); -+ -+ return phy_power_on(hdmi->phy); -+} -+ -+static void dw_hdmi_qp_rk3588_phy_disable(struct dw_hdmi_qp *dw_hdmi, -+ void *data) -+{ -+ struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; -+ -+ phy_power_off(hdmi->phy); -+} -+ -+static enum drm_connector_status -+dw_hdmi_qp_rk3588_read_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) -+{ -+ struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; -+ u32 val; -+ -+ regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &val); -+ -+ return val & RK3588_HDMI0_LEVEL_INT ? -+ connector_status_connected : connector_status_disconnected; -+} -+ -+static void dw_hdmi_qp_rk3588_setup_hpd(struct dw_hdmi_qp *dw_hdmi, void *data) -+{ -+ struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; -+ -+ regmap_write(hdmi->regmap, -+ RK3588_GRF_SOC_CON2, -+ HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR, -+ RK3588_HDMI0_HPD_INT_CLR | -+ RK3588_HDMI0_HPD_INT_MSK)); -+} -+ -+static const struct dw_hdmi_qp_phy_ops rk3588_hdmi_phy_ops = { -+ .init = dw_hdmi_qp_rk3588_phy_init, -+ .disable = dw_hdmi_qp_rk3588_phy_disable, -+ .read_hpd = dw_hdmi_qp_rk3588_read_hpd, -+ .setup_hpd = dw_hdmi_qp_rk3588_setup_hpd, -+}; -+ -+static void dw_hdmi_qp_rk3588_hpd_work(struct work_struct *work) -+{ -+ struct rockchip_hdmi_qp *hdmi = container_of(work, -+ struct rockchip_hdmi_qp, -+ hpd_work.work); -+ struct drm_device *drm = hdmi->encoder.encoder.dev; -+ bool changed; -+ -+ if (drm) { -+ changed = drm_helper_hpd_irq_event(drm); -+ if (changed) -+ drm_dbg(hdmi, "connector status changed\n"); -+ } -+} -+ -+static irqreturn_t dw_hdmi_qp_rk3588_hardirq(int irq, void *dev_id) -+{ -+ struct rockchip_hdmi_qp *hdmi = dev_id; -+ u32 intr_stat, val; -+ -+ regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &intr_stat); -+ -+ if (intr_stat) { -+ val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_MSK, -+ RK3588_HDMI0_HPD_INT_MSK); -+ regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); -+ return IRQ_WAKE_THREAD; -+ } -+ -+ return IRQ_NONE; -+} -+ -+static irqreturn_t dw_hdmi_qp_rk3588_irq(int irq, void *dev_id) -+{ -+ struct rockchip_hdmi_qp *hdmi = dev_id; -+ u32 intr_stat, val; -+ int debounce_ms; -+ -+ regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &intr_stat); -+ if (!intr_stat) -+ return IRQ_NONE; -+ -+ val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR, -+ RK3588_HDMI0_HPD_INT_CLR); -+ regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); -+ -+ debounce_ms = intr_stat & RK3588_HDMI0_LEVEL_INT ? 150 : 20; -+ mod_delayed_work(system_wq, &hdmi->hpd_work, -+ msecs_to_jiffies(debounce_ms)); -+ -+ val |= HIWORD_UPDATE(0, RK3588_HDMI0_HPD_INT_MSK); -+ regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); -+ -+ return IRQ_HANDLED; -+} -+ -+static const struct of_device_id dw_hdmi_qp_rockchip_dt_ids[] = { -+ { .compatible = "rockchip,rk3588-dw-hdmi-qp", -+ .data = &rk3588_hdmi_phy_ops }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, dw_hdmi_qp_rockchip_dt_ids); -+ -+static int dw_hdmi_qp_rockchip_bind(struct device *dev, struct device *master, -+ void *data) -+{ -+ static const char * const clk_names[] = { "hdp", "hclk_vo1" }; -+ struct platform_device *pdev = to_platform_device(dev); -+ struct dw_hdmi_qp_plat_data plat_data; -+ struct drm_device *drm = data; -+ struct drm_connector *connector; -+ struct drm_encoder *encoder; -+ struct rockchip_hdmi_qp *hdmi; -+ struct clk *clk; -+ int ret, irq, i; -+ u32 val; -+ -+ if (!pdev->dev.of_node) -+ return -ENODEV; -+ -+ hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); -+ if (!hdmi) -+ return -ENOMEM; -+ -+ plat_data.phy_ops = of_device_get_match_data(dev); -+ if (!plat_data.phy_ops) -+ return -ENODEV; -+ -+ plat_data.phy_data = hdmi; -+ hdmi->dev = &pdev->dev; -+ -+ encoder = &hdmi->encoder.encoder; -+ encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); -+ -+ rockchip_drm_encoder_set_crtc_endpoint_id(&hdmi->encoder, -+ dev->of_node, 0, 0); -+ /* -+ * If we failed to find the CRTC(s) which this encoder is -+ * supposed to be connected to, it's because the CRTC has -+ * not been registered yet. Defer probing, and hope that -+ * the required CRTC is added later. -+ */ -+ if (encoder->possible_crtcs == 0) -+ return -EPROBE_DEFER; -+ -+ hdmi->regmap = syscon_regmap_lookup_by_phandle(dev->of_node, -+ "rockchip,grf"); -+ if (IS_ERR(hdmi->regmap)) { -+ drm_err(hdmi, "Unable to get rockchip,grf\n"); -+ return PTR_ERR(hdmi->regmap); -+ } -+ -+ hdmi->vo1_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, -+ "rockchip,vo1_grf"); -+ if (IS_ERR(hdmi->vo1_regmap)) { -+ drm_err(hdmi, "Unable to get rockchip,vo1_grf\n"); -+ return PTR_ERR(hdmi->vo1_regmap); -+ } -+ -+ for (i = 0; i < ARRAY_SIZE(clk_names); i++) { -+ clk = devm_clk_get_optional_enabled(hdmi->dev, clk_names[i]); -+ -+ if (IS_ERR(clk)) { -+ ret = PTR_ERR(clk); -+ if (ret != -EPROBE_DEFER) -+ drm_err(hdmi, "Failed to get %s clock: %d\n", -+ clk_names[i], ret); -+ return ret; -+ } -+ } -+ -+ hdmi->enable_gpio = devm_gpiod_get_optional(hdmi->dev, "enable", -+ GPIOD_OUT_HIGH); -+ if (IS_ERR(hdmi->enable_gpio)) { -+ ret = PTR_ERR(hdmi->enable_gpio); -+ drm_err(hdmi, "Failed to request enable GPIO: %d\n", ret); -+ return ret; -+ } -+ -+ hdmi->phy = devm_phy_get(dev, "hdmi"); -+ if (IS_ERR(hdmi->phy)) { -+ ret = PTR_ERR(hdmi->phy); -+ if (ret != -EPROBE_DEFER) -+ drm_err(hdmi, "failed to get phy: %d\n", ret); -+ return ret; -+ } -+ -+ val = HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) | -+ HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) | -+ HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) | -+ HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK); -+ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val); -+ -+ val = HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK, -+ RK3588_SET_HPD_PATH_MASK); -+ regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val); -+ -+ val = HIWORD_UPDATE(RK3588_HDMI0_GRANT_SEL, -+ RK3588_HDMI0_GRANT_SEL); -+ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON9, val); -+ -+ val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_MSK, RK3588_HDMI0_HPD_INT_MSK); -+ regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); -+ -+ INIT_DELAYED_WORK(&hdmi->hpd_work, dw_hdmi_qp_rk3588_hpd_work); -+ -+ irq = platform_get_irq_byname(pdev, "hpd"); -+ if (irq < 0) -+ return irq; -+ -+ ret = devm_request_threaded_irq(hdmi->dev, irq, -+ dw_hdmi_qp_rk3588_hardirq, -+ dw_hdmi_qp_rk3588_irq, -+ IRQF_SHARED, "dw-hdmi-qp-hpd", -+ hdmi); -+ if (ret) -+ return ret; -+ -+ drm_encoder_helper_add(encoder, &dw_hdmi_qp_rockchip_encoder_helper_funcs); -+ drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); -+ -+ platform_set_drvdata(pdev, hdmi); -+ -+ hdmi->hdmi = dw_hdmi_qp_bind(pdev, encoder, &plat_data); -+ if (IS_ERR(hdmi->hdmi)) { -+ ret = PTR_ERR(hdmi->hdmi); -+ drm_encoder_cleanup(encoder); -+ return ret; -+ } -+ -+ connector = drm_bridge_connector_init(drm, encoder); -+ if (IS_ERR(connector)) { -+ ret = PTR_ERR(connector); -+ drm_err(hdmi, "failed to init bridge connector: %d\n", ret); -+ return ret; -+ } -+ -+ return drm_connector_attach_encoder(connector, encoder); -+} -+ -+static void dw_hdmi_qp_rockchip_unbind(struct device *dev, -+ struct device *master, -+ void *data) -+{ -+ struct rockchip_hdmi_qp *hdmi = dev_get_drvdata(dev); -+ -+ cancel_delayed_work_sync(&hdmi->hpd_work); -+ dw_hdmi_qp_unbind(hdmi->hdmi); -+ -+ drm_encoder_cleanup(&hdmi->encoder.encoder); -+} -+ -+static const struct component_ops dw_hdmi_qp_rockchip_ops = { -+ .bind = dw_hdmi_qp_rockchip_bind, -+ .unbind = dw_hdmi_qp_rockchip_unbind, -+}; -+ -+static int dw_hdmi_qp_rockchip_probe(struct platform_device *pdev) -+{ -+ return component_add(&pdev->dev, &dw_hdmi_qp_rockchip_ops); -+} -+ -+static void dw_hdmi_qp_rockchip_remove(struct platform_device *pdev) -+{ -+ component_del(&pdev->dev, &dw_hdmi_qp_rockchip_ops); -+} -+ -+static int __maybe_unused dw_hdmi_qp_rockchip_resume(struct device *dev) -+{ -+ struct rockchip_hdmi_qp *hdmi = dev_get_drvdata(dev); -+ u32 val; -+ -+ val = HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) | -+ HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) | -+ HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) | -+ HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK); -+ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON3, val); -+ -+ val = HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK, -+ RK3588_SET_HPD_PATH_MASK); -+ regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val); -+ -+ val = HIWORD_UPDATE(RK3588_HDMI0_GRANT_SEL, -+ RK3588_HDMI0_GRANT_SEL); -+ regmap_write(hdmi->vo1_regmap, RK3588_GRF_VO1_CON9, val); -+ -+ dw_hdmi_qp_resume(dev, hdmi->hdmi); -+ -+ if (hdmi->encoder.encoder.dev) -+ drm_helper_hpd_irq_event(hdmi->encoder.encoder.dev); -+ -+ return 0; -+} -+ -+static const struct dev_pm_ops dw_hdmi_qp_rockchip_pm = { -+ SET_SYSTEM_SLEEP_PM_OPS(NULL, dw_hdmi_qp_rockchip_resume) -+}; -+ -+struct platform_driver dw_hdmi_qp_rockchip_pltfm_driver = { -+ .probe = dw_hdmi_qp_rockchip_probe, -+ .remove_new = dw_hdmi_qp_rockchip_remove, -+ .driver = { -+ .name = "dwhdmiqp-rockchip", -+ .pm = &dw_hdmi_qp_rockchip_pm, -+ .of_match_table = dw_hdmi_qp_rockchip_dt_ids, -+ }, -+}; -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -index 111111111111..222222222222 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -@@ -507,6 +507,8 @@ static int __init rockchip_drm_init(void) - ADD_ROCKCHIP_SUB_DRIVER(cdn_dp_driver, CONFIG_ROCKCHIP_CDN_DP); - ADD_ROCKCHIP_SUB_DRIVER(dw_hdmi_rockchip_pltfm_driver, - CONFIG_ROCKCHIP_DW_HDMI); -+ ADD_ROCKCHIP_SUB_DRIVER(dw_hdmi_qp_rockchip_pltfm_driver, -+ CONFIG_ROCKCHIP_DW_HDMI_QP); - ADD_ROCKCHIP_SUB_DRIVER(dw_mipi_dsi_rockchip_driver, - CONFIG_ROCKCHIP_DW_MIPI_DSI); - ADD_ROCKCHIP_SUB_DRIVER(inno_hdmi_driver, CONFIG_ROCKCHIP_INNO_HDMI); -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -index 111111111111..222222222222 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h -@@ -88,6 +88,7 @@ int rockchip_drm_encoder_set_crtc_endpoint_id(struct rockchip_encoder *rencoder, - int rockchip_drm_endpoint_is_subdriver(struct device_node *ep); - extern struct platform_driver cdn_dp_driver; - extern struct platform_driver dw_hdmi_rockchip_pltfm_driver; -+extern struct platform_driver dw_hdmi_qp_rockchip_pltfm_driver; - extern struct platform_driver dw_mipi_dsi_rockchip_driver; - extern struct platform_driver inno_hdmi_driver; - extern struct platform_driver rockchip_dp_driver; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Cristian Ciocaltea -Date: Thu, 11 Jul 2024 14:48:43 +0300 -Subject: arm64: defconfig: Enable Rockchip extensions for Synopsys DW HDMI QP - -Enable Rockchip specific extensions for the Synopsys DesignWare HDMI QP -driver. - -This is needed for the HDMI output support on RK3588 SoC based boards. - -Signed-off-by: Cristian Ciocaltea ---- - arch/arm64/configs/defconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig -index 111111111111..222222222222 100644 ---- a/arch/arm64/configs/defconfig -+++ b/arch/arm64/configs/defconfig -@@ -865,6 +865,7 @@ CONFIG_ROCKCHIP_VOP2=y - CONFIG_ROCKCHIP_ANALOGIX_DP=y - CONFIG_ROCKCHIP_CDN_DP=y - CONFIG_ROCKCHIP_DW_HDMI=y -+CONFIG_ROCKCHIP_DW_HDMI_QP=y - CONFIG_ROCKCHIP_DW_MIPI_DSI=y - CONFIG_ROCKCHIP_INNO_HDMI=y - CONFIG_ROCKCHIP_LVDS=y --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.12/1023-arm64-dts-rockchip-add-PCIe-for-M.2-E-Key-to-rock-5a.patch b/patch/kernel/archive/rockchip-rk3588-6.12/1023-arm64-dts-rockchip-add-PCIe-for-M.2-E-Key-to-rock-5a.patch deleted file mode 100644 index bd33b5976c..0000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.12/1023-arm64-dts-rockchip-add-PCIe-for-M.2-E-Key-to-rock-5a.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: amazingfate -Date: Thu, 28 Mar 2024 16:07:18 +0800 -Subject: arm64: dts: rockchip: add PCIe for M.2 E-Key to rock-5a - ---- - arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts -@@ -115,6 +115,10 @@ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { - }; - }; - -+&combphy0_ps { -+ status = "okay"; -+}; -+ - &combphy2_psu { - status = "okay"; - }; -@@ -299,6 +303,11 @@ rgmii_phy1: ethernet-phy@1 { - }; - }; - -+&pcie2x1l2 { -+ status = "okay"; -+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; -+}; -+ - &pinctrl { - leds { - io_led: io-led { --- -Armbian - diff --git a/patch/kernel/archive/rockchip-rk3588-6.12/1051-arm64-dts-rockchip-nanopct6-lts-and-fixes-v6.patch b/patch/kernel/archive/rockchip-rk3588-6.12/1051-arm64-dts-rockchip-nanopct6-lts-and-fixes-v6.patch deleted file mode 100644 index eb1dce1ab3..0000000000 --- a/patch/kernel/archive/rockchip-rk3588-6.12/1051-arm64-dts-rockchip-nanopct6-lts-and-fixes-v6.patch +++ /dev/null @@ -1,2540 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Marcin Juszkiewicz -Date: Thu, 29 Aug 2024 14:26:53 +0200 -Subject: arm64: dts: rockchip: prepare NanoPC-T6 for LTS board - -FriendlyELEC introduced a second version of NanoPC-T6 SBC. - -Create common include file and make NanoPC-T6 use it. Following -patches will add LTS version. - -Signed-off-by: Marcin Juszkiewicz ---- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 932 +-------- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 945 ++++++++++ - 2 files changed, 947 insertions(+), 930 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -@@ -2,944 +2,16 @@ - /* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - * Copyright (c) 2023 Thomas McKahan -+ * Copyright (c) 2024 Linaro Ltd. - * - */ - - /dts-v1/; - --#include --#include --#include --#include "rk3588.dtsi" -+#include "rk3588-nanopc-t6.dtsi" - - / { - model = "FriendlyElec NanoPC-T6"; - compatible = "friendlyarm,nanopc-t6", "rockchip,rk3588"; - -- aliases { -- mmc0 = &sdhci; -- mmc1 = &sdmmc; -- }; -- -- chosen { -- stdout-path = "serial2:1500000n8"; -- }; -- -- leds { -- compatible = "gpio-leds"; -- -- sys_led: led-0 { -- gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; -- label = "system-led"; -- linux,default-trigger = "heartbeat"; -- pinctrl-names = "default"; -- pinctrl-0 = <&sys_led_pin>; -- }; -- -- usr_led: led-1 { -- gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; -- label = "user-led"; -- pinctrl-names = "default"; -- pinctrl-0 = <&usr_led_pin>; -- }; -- }; -- -- sound { -- compatible = "simple-audio-card"; -- pinctrl-names = "default"; -- pinctrl-0 = <&hp_det>; -- -- simple-audio-card,name = "realtek,rt5616-codec"; -- simple-audio-card,format = "i2s"; -- simple-audio-card,mclk-fs = <256>; -- -- simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; -- simple-audio-card,hp-pin-name = "Headphones"; -- -- simple-audio-card,widgets = -- "Headphone", "Headphones", -- "Microphone", "Microphone Jack"; -- simple-audio-card,routing = -- "Headphones", "HPOL", -- "Headphones", "HPOR", -- "MIC1", "Microphone Jack", -- "Microphone Jack", "micbias1"; -- -- simple-audio-card,cpu { -- sound-dai = <&i2s0_8ch>; -- }; -- simple-audio-card,codec { -- sound-dai = <&rt5616>; -- }; -- }; -- -- vcc12v_dcin: vcc12v-dcin-regulator { -- compatible = "regulator-fixed"; -- regulator-name = "vcc12v_dcin"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <12000000>; -- regulator-max-microvolt = <12000000>; -- }; -- -- /* vcc5v0_sys powers peripherals */ -- vcc5v0_sys: vcc5v0-sys-regulator { -- compatible = "regulator-fixed"; -- regulator-name = "vcc5v0_sys"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <5000000>; -- regulator-max-microvolt = <5000000>; -- vin-supply = <&vcc12v_dcin>; -- }; -- -- /* vcc4v0_sys powers the RK806, RK860's */ -- vcc4v0_sys: vcc4v0-sys-regulator { -- compatible = "regulator-fixed"; -- regulator-name = "vcc4v0_sys"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <4000000>; -- regulator-max-microvolt = <4000000>; -- vin-supply = <&vcc12v_dcin>; -- }; -- -- vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { -- compatible = "regulator-fixed"; -- regulator-name = "vcc-1v1-nldo-s3"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1100000>; -- regulator-max-microvolt = <1100000>; -- vin-supply = <&vcc4v0_sys>; -- }; -- -- vcc_3v3_pcie20: vcc3v3-pcie20-regulator { -- compatible = "regulator-fixed"; -- regulator-name = "vcc_3v3_pcie20"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- vin-supply = <&vcc_3v3_s3>; -- }; -- -- vbus5v0_typec: vbus5v0-typec-regulator { -- compatible = "regulator-fixed"; -- enable-active-high; -- gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; -- pinctrl-names = "default"; -- pinctrl-0 = <&typec5v_pwren>; -- regulator-name = "vbus5v0_typec"; -- regulator-min-microvolt = <5000000>; -- regulator-max-microvolt = <5000000>; -- vin-supply = <&vcc5v0_sys>; -- }; -- -- vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { -- compatible = "regulator-fixed"; -- enable-active-high; -- gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie_m2_1_pwren>; -- regulator-name = "vcc3v3_pcie2x1l0"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- vin-supply = <&vcc5v0_sys>; -- }; -- -- vcc3v3_pcie30: vcc3v3-pcie30-regulator { -- compatible = "regulator-fixed"; -- enable-active-high; -- gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie_m2_0_pwren>; -- regulator-name = "vcc3v3_pcie30"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- vin-supply = <&vcc5v0_sys>; -- }; -- -- vcc3v3_sd_s0: vcc3v3-sd-s0-regulator { -- compatible = "regulator-fixed"; -- enable-active-low; -- gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_LOW>; -- regulator-boot-on; -- regulator-max-microvolt = <3300000>; -- regulator-min-microvolt = <3300000>; -- regulator-name = "vcc3v3_sd_s0"; -- vin-supply = <&vcc_3v3_s3>; -- }; -- -- vdd_4g_3v3: vdd-4g-3v3-regulator { -- compatible = "regulator-fixed"; -- enable-active-high; -- gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pin_4g_lte_pwren>; -- regulator-name = "vdd_4g_3v3"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- vin-supply = <&vcc5v0_sys>; -- }; --}; -- --&combphy0_ps { -- status = "okay"; --}; -- --&combphy1_ps { -- status = "okay"; --}; -- --&combphy2_psu { -- status = "okay"; --}; -- --&cpu_l0 { -- cpu-supply = <&vdd_cpu_lit_s0>; --}; -- --&cpu_l1 { -- cpu-supply = <&vdd_cpu_lit_s0>; --}; -- --&cpu_l2 { -- cpu-supply = <&vdd_cpu_lit_s0>; --}; -- --&cpu_l3 { -- cpu-supply = <&vdd_cpu_lit_s0>; --}; -- --&cpu_b0 { -- cpu-supply = <&vdd_cpu_big0_s0>; --}; -- --&cpu_b1 { -- cpu-supply = <&vdd_cpu_big0_s0>; --}; -- --&cpu_b2 { -- cpu-supply = <&vdd_cpu_big1_s0>; --}; -- --&cpu_b3 { -- cpu-supply = <&vdd_cpu_big1_s0>; --}; -- --&gpio0 { -- gpio-line-names = /* GPIO0 A0-A7 */ -- "", "", "", "", -- "", "", "", "", -- /* GPIO0 B0-B7 */ -- "", "", "", "", -- "", "", "", "", -- /* GPIO0 C0-C7 */ -- "", "", "", "", -- "HEADER_10", "HEADER_08", "HEADER_32", "", -- /* GPIO0 D0-D7 */ -- "", "", "", "", -- "", "", "", ""; --}; -- --&gpio1 { -- gpio-line-names = /* GPIO1 A0-A7 */ -- "HEADER_27", "HEADER_28", "", "", -- "", "", "", "HEADER_15", -- /* GPIO1 B0-B7 */ -- "HEADER_26", "HEADER_21", "HEADER_19", "HEADER_23", -- "HEADER_24", "HEADER_22", "", "", -- /* GPIO1 C0-C7 */ -- "", "", "", "", -- "", "", "", "", -- /* GPIO1 D0-D7 */ -- "", "", "", "", -- "", "", "HEADER_05", "HEADER_03"; --}; -- --&gpio2 { -- gpio-line-names = /* GPIO2 A0-A7 */ -- "", "", "", "", -- "", "", "", "", -- /* GPIO2 B0-B7 */ -- "", "", "", "", -- "", "", "", "", -- /* GPIO2 C0-C7 */ -- "", "CSI1_11", "CSI1_12", "", -- "", "", "", "", -- /* GPIO2 D0-D7 */ -- "", "", "", "", -- "", "", "", ""; --}; -- --&gpio3 { -- gpio-line-names = /* GPIO3 A0-A7 */ -- "HEADER_35", "HEADER_38", "HEADER_40", "HEADER_36", -- "HEADER_37", "", "DSI0_12", "", -- /* GPIO3 B0-B7 */ -- "HEADER_33", "DSI0_10", "HEADER_07", "HEADER_16", -- "HEADER_18", "HEADER_29", "HEADER_31", "HEADER_12", -- /* GPIO3 C0-C7 */ -- "DSI0_08", "DSI0_14", "HEADER_11", "HEADER_13", -- "", "", "", "", -- /* GPIO3 D0-D7 */ -- "", "", "", "", -- "", "DSI1_10", "", ""; --}; -- --&gpio4 { -- gpio-line-names = /* GPIO4 A0-A7 */ -- "DSI1_08", "DSI1_14", "", "DSI1_12", -- "", "", "", "", -- /* GPIO4 B0-B7 */ -- "", "", "", "", -- "", "", "", "", -- /* GPIO4 C0-C7 */ -- "", "", "", "", -- "CSI0_11", "CSI0_12", "", "", -- /* GPIO4 D0-D7 */ -- "", "", "", "", -- "", "", "", ""; --}; -- --&i2c0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c0m2_xfer>; -- status = "okay"; -- -- vdd_cpu_big0_s0: regulator@42 { -- compatible = "rockchip,rk8602"; -- reg = <0x42>; -- fcs,suspend-voltage-selector = <1>; -- regulator-name = "vdd_cpu_big0_s0"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <550000>; -- regulator-max-microvolt = <1050000>; -- regulator-ramp-delay = <2300>; -- vin-supply = <&vcc4v0_sys>; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vdd_cpu_big1_s0: regulator@43 { -- compatible = "rockchip,rk8603", "rockchip,rk8602"; -- reg = <0x43>; -- fcs,suspend-voltage-selector = <1>; -- regulator-name = "vdd_cpu_big1_s0"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <550000>; -- regulator-max-microvolt = <1050000>; -- regulator-ramp-delay = <2300>; -- vin-supply = <&vcc4v0_sys>; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; --}; -- --&i2c2 { -- status = "okay"; -- -- vdd_npu_s0: regulator@42 { -- compatible = "rockchip,rk8602"; -- reg = <0x42>; -- rockchip,suspend-voltage-selector = <1>; -- regulator-name = "vdd_npu_s0"; -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <550000>; -- regulator-max-microvolt = <950000>; -- regulator-ramp-delay = <2300>; -- vin-supply = <&vcc4v0_sys>; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; --}; -- --&i2c6 { -- clock-frequency = <200000>; -- status = "okay"; -- -- fusb302: typec-portc@22 { -- compatible = "fcs,fusb302"; -- reg = <0x22>; -- interrupt-parent = <&gpio0>; -- interrupts = ; -- pinctrl-0 = <&usbc0_int>; -- pinctrl-names = "default"; -- vbus-supply = <&vbus5v0_typec>; -- -- connector { -- compatible = "usb-c-connector"; -- data-role = "dual"; -- label = "USB-C"; -- power-role = "dual"; -- try-power-role = "sink"; -- source-pdos = ; -- sink-pdos = ; -- op-sink-microwatt = <1000000>; -- }; -- }; -- -- hym8563: rtc@51 { -- compatible = "haoyu,hym8563"; -- reg = <0x51>; -- #clock-cells = <0>; -- clock-output-names = "hym8563"; -- pinctrl-names = "default"; -- pinctrl-0 = <&hym8563_int>; -- interrupt-parent = <&gpio0>; -- interrupts = ; -- wakeup-source; -- }; --}; -- --&i2c7 { -- clock-frequency = <200000>; -- status = "okay"; -- -- rt5616: codec@1b { -- compatible = "realtek,rt5616"; -- reg = <0x1b>; -- clocks = <&cru I2S0_8CH_MCLKOUT>; -- clock-names = "mclk"; -- #sound-dai-cells = <0>; -- assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; -- assigned-clock-rates = <12288000>; -- -- port { -- rt5616_p0_0: endpoint { -- remote-endpoint = <&i2s0_8ch_p0_0>; -- }; -- }; -- }; -- -- /* connected with MIPI-CSI1 */ --}; -- --&i2c8 { -- pinctrl-0 = <&i2c8m2_xfer>; --}; -- --&i2s0_8ch { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2s0_lrck -- &i2s0_mclk -- &i2s0_sclk -- &i2s0_sdi0 -- &i2s0_sdo0>; -- status = "okay"; -- -- i2s0_8ch_p0: port { -- i2s0_8ch_p0_0: endpoint { -- dai-format = "i2s"; -- mclk-fs = <256>; -- remote-endpoint = <&rt5616_p0_0>; -- }; -- }; --}; -- --&pcie2x1l0 { -- reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; -- vpcie3v3-supply = <&vcc_3v3_pcie20>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie2_0_rst>; -- status = "okay"; --}; -- --&pcie2x1l1 { -- reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; -- vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie2_1_rst>; -- status = "okay"; --}; -- --&pcie2x1l2 { -- reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; -- vpcie3v3-supply = <&vcc_3v3_pcie20>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pcie2_2_rst>; -- status = "okay"; --}; -- --&pcie30phy { -- status = "okay"; --}; -- --&pcie3x4 { -- reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; -- vpcie3v3-supply = <&vcc3v3_pcie30>; -- status = "okay"; --}; -- --&pinctrl { -- gpio-leds { -- sys_led_pin: sys-led-pin { -- rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- -- usr_led_pin: usr-led-pin { -- rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- }; -- -- headphone { -- hp_det: hp-det { -- rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- }; -- -- hym8563 { -- hym8563_int: hym8563-int { -- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; -- }; -- }; -- -- pcie { -- pcie2_0_rst: pcie2-0-rst { -- rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- -- pcie2_1_rst: pcie2-1-rst { -- rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- -- pcie2_2_rst: pcie2-2-rst { -- rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- -- pcie_m2_0_pwren: pcie-m20-pwren { -- rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- -- pcie_m2_1_pwren: pcie-m21-pwren { -- rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- }; -- -- usb { -- pin_4g_lte_pwren: 4g-lte-pwren { -- rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- -- typec5v_pwren: typec5v-pwren { -- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- -- usbc0_int: usbc0-int { -- rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; -- }; -- }; --}; -- --&pwm1 { -- pinctrl-0 = <&pwm1m1_pins>; -- status = "okay"; --}; -- --&saradc { -- vref-supply = <&avcc_1v8_s0>; -- status = "okay"; --}; -- --&sdhci { -- bus-width = <8>; -- no-sdio; -- no-sd; -- non-removable; -- max-frequency = <200000000>; -- mmc-hs400-1_8v; -- mmc-hs400-enhanced-strobe; -- status = "okay"; --}; -- --&sdmmc { -- bus-width = <4>; -- cap-mmc-highspeed; -- cap-sd-highspeed; -- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; -- disable-wp; -- no-mmc; -- no-sdio; -- sd-uhs-sdr104; -- vmmc-supply = <&vcc3v3_sd_s0>; -- vqmmc-supply = <&vccio_sd_s0>; -- status = "okay"; --}; -- --&spi2 { -- status = "okay"; -- assigned-clocks = <&cru CLK_SPI2>; -- assigned-clock-rates = <200000000>; -- pinctrl-names = "default"; -- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; -- num-cs = <1>; -- -- pmic@0 { -- compatible = "rockchip,rk806"; -- spi-max-frequency = <1000000>; -- reg = <0x0>; -- -- interrupt-parent = <&gpio0>; -- interrupts = <7 IRQ_TYPE_LEVEL_LOW>; -- -- pinctrl-names = "default"; -- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, -- <&rk806_dvs2_null>, <&rk806_dvs3_null>; -- -- system-power-controller; -- -- vcc1-supply = <&vcc4v0_sys>; -- vcc2-supply = <&vcc4v0_sys>; -- vcc3-supply = <&vcc4v0_sys>; -- vcc4-supply = <&vcc4v0_sys>; -- vcc5-supply = <&vcc4v0_sys>; -- vcc6-supply = <&vcc4v0_sys>; -- vcc7-supply = <&vcc4v0_sys>; -- vcc8-supply = <&vcc4v0_sys>; -- vcc9-supply = <&vcc4v0_sys>; -- vcc10-supply = <&vcc4v0_sys>; -- vcc11-supply = <&vcc_2v0_pldo_s3>; -- vcc12-supply = <&vcc4v0_sys>; -- vcc13-supply = <&vcc_1v1_nldo_s3>; -- vcc14-supply = <&vcc_1v1_nldo_s3>; -- vcca-supply = <&vcc4v0_sys>; -- -- gpio-controller; -- #gpio-cells = <2>; -- -- rk806_dvs1_null: dvs1-null-pins { -- pins = "gpio_pwrctrl1"; -- function = "pin_fun0"; -- }; -- -- rk806_dvs2_null: dvs2-null-pins { -- pins = "gpio_pwrctrl2"; -- function = "pin_fun0"; -- }; -- -- rk806_dvs3_null: dvs3-null-pins { -- pins = "gpio_pwrctrl3"; -- function = "pin_fun0"; -- }; -- -- regulators { -- vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { -- regulator-boot-on; -- regulator-min-microvolt = <550000>; -- regulator-max-microvolt = <950000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vdd_gpu_s0"; -- regulator-enable-ramp-delay = <400>; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <550000>; -- regulator-max-microvolt = <950000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vdd_cpu_lit_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vdd_log_s0: dcdc-reg3 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <675000>; -- regulator-max-microvolt = <750000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vdd_log_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- regulator-suspend-microvolt = <750000>; -- }; -- }; -- -- vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <550000>; -- regulator-max-microvolt = <950000>; -- regulator-init-microvolt = <750000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vdd_vdenc_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vdd_ddr_s0: dcdc-reg5 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <675000>; -- regulator-max-microvolt = <900000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vdd_ddr_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- regulator-suspend-microvolt = <850000>; -- }; -- }; -- -- vdd2_ddr_s3: dcdc-reg6 { -- regulator-always-on; -- regulator-boot-on; -- regulator-name = "vdd2_ddr_s3"; -- -- regulator-state-mem { -- regulator-on-in-suspend; -- }; -- }; -- -- vcc_2v0_pldo_s3: dcdc-reg7 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <2000000>; -- regulator-max-microvolt = <2000000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vdd_2v0_pldo_s3"; -- -- regulator-state-mem { -- regulator-on-in-suspend; -- regulator-suspend-microvolt = <2000000>; -- }; -- }; -- -- vcc_3v3_s3: dcdc-reg8 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- regulator-name = "vcc_3v3_s3"; -- -- regulator-state-mem { -- regulator-on-in-suspend; -- regulator-suspend-microvolt = <3300000>; -- }; -- }; -- -- vddq_ddr_s0: dcdc-reg9 { -- regulator-always-on; -- regulator-boot-on; -- regulator-name = "vddq_ddr_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vcc_1v8_s3: dcdc-reg10 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- regulator-name = "vcc_1v8_s3"; -- -- regulator-state-mem { -- regulator-on-in-suspend; -- regulator-suspend-microvolt = <1800000>; -- }; -- }; -- -- avcc_1v8_s0: pldo-reg1 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- regulator-name = "avcc_1v8_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vcc_1v8_s0: pldo-reg2 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- regulator-name = "vcc_1v8_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- regulator-suspend-microvolt = <1800000>; -- }; -- }; -- -- avdd_1v2_s0: pldo-reg3 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1200000>; -- regulator-max-microvolt = <1200000>; -- regulator-name = "avdd_1v2_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vcc_3v3_s0: pldo-reg4 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vcc_3v3_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vccio_sd_s0: pldo-reg5 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <3300000>; -- regulator-ramp-delay = <12500>; -- regulator-name = "vccio_sd_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- pldo6_s3: pldo-reg6 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <1800000>; -- regulator-max-microvolt = <1800000>; -- regulator-name = "pldo6_s3"; -- -- regulator-state-mem { -- regulator-on-in-suspend; -- regulator-suspend-microvolt = <1800000>; -- }; -- }; -- -- vdd_0v75_s3: nldo-reg1 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <750000>; -- regulator-max-microvolt = <750000>; -- regulator-name = "vdd_0v75_s3"; -- -- regulator-state-mem { -- regulator-on-in-suspend; -- regulator-suspend-microvolt = <750000>; -- }; -- }; -- -- vdd_ddr_pll_s0: nldo-reg2 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <850000>; -- regulator-max-microvolt = <850000>; -- regulator-name = "vdd_ddr_pll_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- regulator-suspend-microvolt = <850000>; -- }; -- }; -- -- avdd_0v75_s0: nldo-reg3 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <750000>; -- regulator-max-microvolt = <750000>; -- regulator-name = "avdd_0v75_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vdd_0v85_s0: nldo-reg4 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <850000>; -- regulator-max-microvolt = <850000>; -- regulator-name = "vdd_0v85_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- -- vdd_0v75_s0: nldo-reg5 { -- regulator-always-on; -- regulator-boot-on; -- regulator-min-microvolt = <750000>; -- regulator-max-microvolt = <750000>; -- regulator-name = "vdd_0v75_s0"; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; -- }; -- }; -- }; --}; -- --&tsadc { -- status = "okay"; --}; -- --&uart2 { -- pinctrl-0 = <&uart2m0_xfer>; -- status = "okay"; --}; -- --&u2phy2_host { -- phy-supply = <&vdd_4g_3v3>; -- status = "okay"; --}; -- --&u2phy3_host { -- status = "okay"; --}; -- --&u2phy2 { -- status = "okay"; --}; -- --&u2phy3 { -- status = "okay"; --}; -- --&usb_host0_ehci { -- status = "okay"; --}; -- --&usb_host0_ohci { -- status = "okay"; --}; -- --&usb_host1_ehci { -- status = "okay"; --}; -- --&usb_host1_ohci { -- status = "okay"; - }; -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -@@ -0,0 +1,945 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. -+ * Copyright (c) 2023 Thomas McKahan -+ * -+ */ -+ -+/dts-v1/; -+ -+#include -+#include -+#include -+#include "rk3588.dtsi" -+ -+/ { -+ model = "FriendlyElec NanoPC-T6"; -+ compatible = "friendlyarm,nanopc-t6", "rockchip,rk3588"; -+ -+ aliases { -+ mmc0 = &sdhci; -+ mmc1 = &sdmmc; -+ }; -+ -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ sys_led: led-0 { -+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; -+ label = "system-led"; -+ linux,default-trigger = "heartbeat"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sys_led_pin>; -+ }; -+ -+ usr_led: led-1 { -+ gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; -+ label = "user-led"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&usr_led_pin>; -+ }; -+ }; -+ -+ sound { -+ compatible = "simple-audio-card"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hp_det>; -+ -+ simple-audio-card,name = "realtek,rt5616-codec"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,mclk-fs = <256>; -+ -+ simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; -+ simple-audio-card,hp-pin-name = "Headphones"; -+ -+ simple-audio-card,widgets = -+ "Headphone", "Headphones", -+ "Microphone", "Microphone Jack"; -+ simple-audio-card,routing = -+ "Headphones", "HPOL", -+ "Headphones", "HPOR", -+ "MIC1", "Microphone Jack", -+ "Microphone Jack", "micbias1"; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&i2s0_8ch>; -+ }; -+ simple-audio-card,codec { -+ sound-dai = <&rt5616>; -+ }; -+ }; -+ -+ vcc12v_dcin: vcc12v-dcin-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc12v_dcin"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ }; -+ -+ /* vcc5v0_sys powers peripherals */ -+ vcc5v0_sys: vcc5v0-sys-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc12v_dcin>; -+ }; -+ -+ /* vcc4v0_sys powers the RK806, RK860's */ -+ vcc4v0_sys: vcc4v0-sys-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc4v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <4000000>; -+ regulator-max-microvolt = <4000000>; -+ vin-supply = <&vcc12v_dcin>; -+ }; -+ -+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc-1v1-nldo-s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1100000>; -+ vin-supply = <&vcc4v0_sys>; -+ }; -+ -+ vcc_3v3_pcie20: vcc3v3-pcie20-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_3v3_pcie20"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_3v3_s3>; -+ }; -+ -+ vbus5v0_typec: vbus5v0-typec-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&typec5v_pwren>; -+ regulator-name = "vbus5v0_typec"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_m2_1_pwren>; -+ regulator-name = "vcc3v3_pcie2x1l0"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc3v3_pcie30: vcc3v3-pcie30-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_m2_0_pwren>; -+ regulator-name = "vcc3v3_pcie30"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc3v3_sd_s0: vcc3v3-sd-s0-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-low; -+ gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_LOW>; -+ regulator-boot-on; -+ regulator-max-microvolt = <3300000>; -+ regulator-min-microvolt = <3300000>; -+ regulator-name = "vcc3v3_sd_s0"; -+ vin-supply = <&vcc_3v3_s3>; -+ }; -+ -+ vdd_4g_3v3: vdd-4g-3v3-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pin_4g_lte_pwren>; -+ regulator-name = "vdd_4g_3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+}; -+ -+&combphy0_ps { -+ status = "okay"; -+}; -+ -+&combphy1_ps { -+ status = "okay"; -+}; -+ -+&combphy2_psu { -+ status = "okay"; -+}; -+ -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_lit_s0>; -+}; -+ -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_big0_s0>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_big0_s0>; -+}; -+ -+&cpu_b2 { -+ cpu-supply = <&vdd_cpu_big1_s0>; -+}; -+ -+&cpu_b3 { -+ cpu-supply = <&vdd_cpu_big1_s0>; -+}; -+ -+&gpio0 { -+ gpio-line-names = /* GPIO0 A0-A7 */ -+ "", "", "", "", -+ "", "", "", "", -+ /* GPIO0 B0-B7 */ -+ "", "", "", "", -+ "", "", "", "", -+ /* GPIO0 C0-C7 */ -+ "", "", "", "", -+ "HEADER_10", "HEADER_08", "HEADER_32", "", -+ /* GPIO0 D0-D7 */ -+ "", "", "", "", -+ "", "", "", ""; -+}; -+ -+&gpio1 { -+ gpio-line-names = /* GPIO1 A0-A7 */ -+ "HEADER_27", "HEADER_28", "", "", -+ "", "", "", "HEADER_15", -+ /* GPIO1 B0-B7 */ -+ "HEADER_26", "HEADER_21", "HEADER_19", "HEADER_23", -+ "HEADER_24", "HEADER_22", "", "", -+ /* GPIO1 C0-C7 */ -+ "", "", "", "", -+ "", "", "", "", -+ /* GPIO1 D0-D7 */ -+ "", "", "", "", -+ "", "", "HEADER_05", "HEADER_03"; -+}; -+ -+&gpio2 { -+ gpio-line-names = /* GPIO2 A0-A7 */ -+ "", "", "", "", -+ "", "", "", "", -+ /* GPIO2 B0-B7 */ -+ "", "", "", "", -+ "", "", "", "", -+ /* GPIO2 C0-C7 */ -+ "", "CSI1_11", "CSI1_12", "", -+ "", "", "", "", -+ /* GPIO2 D0-D7 */ -+ "", "", "", "", -+ "", "", "", ""; -+}; -+ -+&gpio3 { -+ gpio-line-names = /* GPIO3 A0-A7 */ -+ "HEADER_35", "HEADER_38", "HEADER_40", "HEADER_36", -+ "HEADER_37", "", "DSI0_12", "", -+ /* GPIO3 B0-B7 */ -+ "HEADER_33", "DSI0_10", "HEADER_07", "HEADER_16", -+ "HEADER_18", "HEADER_29", "HEADER_31", "HEADER_12", -+ /* GPIO3 C0-C7 */ -+ "DSI0_08", "DSI0_14", "HEADER_11", "HEADER_13", -+ "", "", "", "", -+ /* GPIO3 D0-D7 */ -+ "", "", "", "", -+ "", "DSI1_10", "", ""; -+}; -+ -+&gpio4 { -+ gpio-line-names = /* GPIO4 A0-A7 */ -+ "DSI1_08", "DSI1_14", "", "DSI1_12", -+ "", "", "", "", -+ /* GPIO4 B0-B7 */ -+ "", "", "", "", -+ "", "", "", "", -+ /* GPIO4 C0-C7 */ -+ "", "", "", "", -+ "CSI0_11", "CSI0_12", "", "", -+ /* GPIO4 D0-D7 */ -+ "", "", "", "", -+ "", "", "", ""; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0m2_xfer>; -+ status = "okay"; -+ -+ vdd_cpu_big0_s0: regulator@42 { -+ compatible = "rockchip,rk8602"; -+ reg = <0x42>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu_big0_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc4v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_big1_s0: regulator@43 { -+ compatible = "rockchip,rk8603", "rockchip,rk8602"; -+ reg = <0x43>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu_big1_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc4v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ status = "okay"; -+ -+ vdd_npu_s0: regulator@42 { -+ compatible = "rockchip,rk8602"; -+ reg = <0x42>; -+ rockchip,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_npu_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc4v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&i2c6 { -+ clock-frequency = <200000>; -+ status = "okay"; -+ -+ fusb302: typec-portc@22 { -+ compatible = "fcs,fusb302"; -+ reg = <0x22>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ pinctrl-0 = <&usbc0_int>; -+ pinctrl-names = "default"; -+ vbus-supply = <&vbus5v0_typec>; -+ -+ connector { -+ compatible = "usb-c-connector"; -+ data-role = "dual"; -+ label = "USB-C"; -+ power-role = "dual"; -+ try-power-role = "sink"; -+ source-pdos = ; -+ sink-pdos = ; -+ op-sink-microwatt = <1000000>; -+ }; -+ }; -+ -+ hym8563: rtc@51 { -+ compatible = "haoyu,hym8563"; -+ reg = <0x51>; -+ #clock-cells = <0>; -+ clock-output-names = "hym8563"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hym8563_int>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ wakeup-source; -+ }; -+}; -+ -+&i2c7 { -+ clock-frequency = <200000>; -+ status = "okay"; -+ -+ rt5616: codec@1b { -+ compatible = "realtek,rt5616"; -+ reg = <0x1b>; -+ clocks = <&cru I2S0_8CH_MCLKOUT>; -+ clock-names = "mclk"; -+ #sound-dai-cells = <0>; -+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; -+ assigned-clock-rates = <12288000>; -+ -+ port { -+ rt5616_p0_0: endpoint { -+ remote-endpoint = <&i2s0_8ch_p0_0>; -+ }; -+ }; -+ }; -+ -+ /* connected with MIPI-CSI1 */ -+}; -+ -+&i2c8 { -+ pinctrl-0 = <&i2c8m2_xfer>; -+}; -+ -+&i2s0_8ch { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s0_lrck -+ &i2s0_mclk -+ &i2s0_sclk -+ &i2s0_sdi0 -+ &i2s0_sdo0>; -+ status = "okay"; -+ -+ i2s0_8ch_p0: port { -+ i2s0_8ch_p0_0: endpoint { -+ dai-format = "i2s"; -+ mclk-fs = <256>; -+ remote-endpoint = <&rt5616_p0_0>; -+ }; -+ }; -+}; -+ -+&pcie2x1l0 { -+ reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc_3v3_pcie20>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_0_rst>; -+ status = "okay"; -+}; -+ -+&pcie2x1l1 { -+ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_1_rst>; -+ status = "okay"; -+}; -+ -+&pcie2x1l2 { -+ reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc_3v3_pcie20>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie2_2_rst>; -+ status = "okay"; -+}; -+ -+&pcie30phy { -+ status = "okay"; -+}; -+ -+&pcie3x4 { -+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie30>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ gpio-leds { -+ sys_led_pin: sys-led-pin { -+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ usr_led_pin: usr-led-pin { -+ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ headphone { -+ hp_det: hp-det { -+ rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ hym8563 { -+ hym8563_int: hym8563-int { -+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ pcie { -+ pcie2_0_rst: pcie2-0-rst { -+ rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie2_1_rst: pcie2-1-rst { -+ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie2_2_rst: pcie2-2-rst { -+ rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie_m2_0_pwren: pcie-m20-pwren { -+ rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie_m2_1_pwren: pcie-m21-pwren { -+ rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ usb { -+ pin_4g_lte_pwren: 4g-lte-pwren { -+ rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ typec5v_pwren: typec5v-pwren { -+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ usbc0_int: usbc0-int { -+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; -+ -+&pwm1 { -+ pinctrl-0 = <&pwm1m1_pins>; -+ status = "okay"; -+}; -+ -+&saradc { -+ vref-supply = <&avcc_1v8_s0>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ no-sdio; -+ no-sd; -+ non-removable; -+ max-frequency = <200000000>; -+ mmc-hs400-1_8v; -+ mmc-hs400-enhanced-strobe; -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-mmc-highspeed; -+ cap-sd-highspeed; -+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; -+ disable-wp; -+ no-mmc; -+ no-sdio; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc3v3_sd_s0>; -+ vqmmc-supply = <&vccio_sd_s0>; -+ status = "okay"; -+}; -+ -+&spi2 { -+ status = "okay"; -+ assigned-clocks = <&cru CLK_SPI2>; -+ assigned-clock-rates = <200000000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; -+ num-cs = <1>; -+ -+ pmic@0 { -+ compatible = "rockchip,rk806"; -+ spi-max-frequency = <1000000>; -+ reg = <0x0>; -+ -+ interrupt-parent = <&gpio0>; -+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, -+ <&rk806_dvs2_null>, <&rk806_dvs3_null>; -+ -+ system-power-controller; -+ -+ vcc1-supply = <&vcc4v0_sys>; -+ vcc2-supply = <&vcc4v0_sys>; -+ vcc3-supply = <&vcc4v0_sys>; -+ vcc4-supply = <&vcc4v0_sys>; -+ vcc5-supply = <&vcc4v0_sys>; -+ vcc6-supply = <&vcc4v0_sys>; -+ vcc7-supply = <&vcc4v0_sys>; -+ vcc8-supply = <&vcc4v0_sys>; -+ vcc9-supply = <&vcc4v0_sys>; -+ vcc10-supply = <&vcc4v0_sys>; -+ vcc11-supply = <&vcc_2v0_pldo_s3>; -+ vcc12-supply = <&vcc4v0_sys>; -+ vcc13-supply = <&vcc_1v1_nldo_s3>; -+ vcc14-supply = <&vcc_1v1_nldo_s3>; -+ vcca-supply = <&vcc4v0_sys>; -+ -+ gpio-controller; -+ #gpio-cells = <2>; -+ -+ rk806_dvs1_null: dvs1-null-pins { -+ pins = "gpio_pwrctrl1"; -+ function = "pin_fun0"; -+ }; -+ -+ rk806_dvs2_null: dvs2-null-pins { -+ pins = "gpio_pwrctrl2"; -+ function = "pin_fun0"; -+ }; -+ -+ rk806_dvs3_null: dvs3-null-pins { -+ pins = "gpio_pwrctrl3"; -+ function = "pin_fun0"; -+ }; -+ -+ regulators { -+ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_gpu_s0"; -+ regulator-enable-ramp-delay = <400>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_cpu_lit_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_log_s0: dcdc-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <750000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_log_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <750000>; -+ }; -+ }; -+ -+ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <550000>; -+ regulator-max-microvolt = <950000>; -+ regulator-init-microvolt = <750000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_vdenc_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_ddr_s0: dcdc-reg5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <675000>; -+ regulator-max-microvolt = <900000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_ddr_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <850000>; -+ }; -+ }; -+ -+ vdd2_ddr_s3: dcdc-reg6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vdd2_ddr_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_2v0_pldo_s3: dcdc-reg7 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <2000000>; -+ regulator-max-microvolt = <2000000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vdd_2v0_pldo_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <2000000>; -+ }; -+ }; -+ -+ vcc_3v3_s3: dcdc-reg8 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc_3v3_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vddq_ddr_s0: dcdc-reg9 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vddq_ddr_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8_s3: dcdc-reg10 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc_1v8_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ avcc_1v8_s0: pldo-reg1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "avcc_1v8_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8_s0: pldo-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc_1v8_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ avdd_1v2_s0: pldo-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1200000>; -+ regulator-name = "avdd_1v2_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v3_s0: pldo-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vcc_3v3_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd_s0: pldo-reg5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-ramp-delay = <12500>; -+ regulator-name = "vccio_sd_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ pldo6_s3: pldo-reg6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "pldo6_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdd_0v75_s3: nldo-reg1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ regulator-name = "vdd_0v75_s3"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <750000>; -+ }; -+ }; -+ -+ vdd_ddr_pll_s0: nldo-reg2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ regulator-name = "vdd_ddr_pll_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <850000>; -+ }; -+ }; -+ -+ avdd_0v75_s0: nldo-reg3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ regulator-name = "avdd_0v75_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_0v85_s0: nldo-reg4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <850000>; -+ regulator-max-microvolt = <850000>; -+ regulator-name = "vdd_0v85_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_0v75_s0: nldo-reg5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <750000>; -+ regulator-name = "vdd_0v75_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&tsadc { -+ status = "okay"; -+}; -+ -+&uart2 { -+ pinctrl-0 = <&uart2m0_xfer>; -+ status = "okay"; -+}; -+ -+&u2phy2_host { -+ phy-supply = <&vdd_4g_3v3>; -+ status = "okay"; -+}; -+ -+&u2phy3_host { -+ status = "okay"; -+}; -+ -+&u2phy2 { -+ status = "okay"; -+}; -+ -+&u2phy3 { -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Marcin Juszkiewicz -Date: Thu, 29 Aug 2024 14:26:54 +0200 -Subject: arm64: dts: rockchip: move NanoPC-T6 parts to DTS - -MiniPCIe slot is present only in first version of NanoPC-T6 (2301). - -Signed-off-by: Marcin Juszkiewicz ---- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts | 24 ++++++++++ - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 17 ------- - 2 files changed, 24 insertions(+), 17 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts -@@ -14,4 +14,28 @@ / { - model = "FriendlyElec NanoPC-T6"; - compatible = "friendlyarm,nanopc-t6", "rockchip,rk3588"; - -+ vdd_4g_3v3: vdd-4g-3v3-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pin_4g_lte_pwren>; -+ regulator-name = "vdd_4g_3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+}; -+ -+&pinctrl { -+ usb { -+ pin_4g_lte_pwren: 4g-lte-pwren { -+ rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&u2phy2_host { -+ phy-supply = <&vdd_4g_3v3>; -+ status = "okay"; - }; -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -@@ -170,18 +170,6 @@ vcc3v3_sd_s0: vcc3v3-sd-s0-regulator { - regulator-name = "vcc3v3_sd_s0"; - vin-supply = <&vcc_3v3_s3>; - }; -- -- vdd_4g_3v3: vdd-4g-3v3-regulator { -- compatible = "regulator-fixed"; -- enable-active-high; -- gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; -- pinctrl-names = "default"; -- pinctrl-0 = <&pin_4g_lte_pwren>; -- regulator-name = "vdd_4g_3v3"; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; -- vin-supply = <&vcc5v0_sys>; -- }; - }; - - &combphy0_ps { -@@ -527,10 +515,6 @@ pcie_m2_1_pwren: pcie-m21-pwren { - }; - - usb { -- pin_4g_lte_pwren: 4g-lte-pwren { -- rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -- }; -- - typec5v_pwren: typec5v-pwren { - rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; -@@ -912,7 +896,6 @@ &uart2 { - }; - - &u2phy2_host { -- phy-supply = <&vdd_4g_3v3>; - status = "okay"; - }; - --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Marcin Juszkiewicz -Date: Thu, 29 Aug 2024 14:26:55 +0200 -Subject: arm64: dts: rockchip: add NanoPC-T6 LTS - -In the LTS (2310) version the miniPCIe slot got removed and USB 2.0 -setup has changed. There are two external accessible ports and two ports -on the internal header. - -There is an on-board USB hub which provides: -- one external connector (bottom one) -- two internal ports on pin header -- one port for m.2 E connector - -The top USB 2.0 connector comes directly from the SoC. - -Signed-off-by: Marcin Juszkiewicz ---- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6-lts.dts | 61 ++++++++++ - 1 file changed, 61 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6-lts.dts b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6-lts.dts -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6-lts.dts -@@ -0,0 +1,61 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. -+ * Copyright (c) 2023 Thomas McKahan -+ * Copyright (c) 2024 Linaro Ltd. -+ * -+ */ -+ -+/dts-v1/; -+ -+#include "rk3588-nanopc-t6.dtsi" -+ -+/ { -+ model = "FriendlyElec NanoPC-T6 LTS"; -+ compatible = "friendlyarm,nanopc-t6-lts", "rockchip,rk3588"; -+ -+ /* provide power for on-board USB 2.0 hub */ -+ vcc5v0_usb20_host: vcc5v0-usb20-host-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; -+ pinctrl-0 = <&usb20_host_pwren>; -+ pinctrl-names = "default"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-max-microvolt = <5000000>; -+ regulator-min-microvolt = <5000000>; -+ regulator-name = "vcc5v0_usb20_host"; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+}; -+ -+&pinctrl { -+ usb { -+ usb20_host_pwren: usb20-host-pwren { -+ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&u2phy1 { -+ status = "okay"; -+}; -+ -+&u2phy1_otg { -+ status = "okay"; -+}; -+ -+&u2phy2_host { -+ phy-supply = <&vcc5v0_usb20_host>; -+ status = "okay"; -+}; -+ -+&usbdp_phy1 { -+ status = "okay"; -+}; -+ -+&usb_host1_xhci { -+ dr_mode = "host"; -+ status = "okay"; -+}; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Marcin Juszkiewicz -Date: Thu, 29 Aug 2024 14:26:56 +0200 -Subject: arm64: dts: rockchip: add SPI flash on NanoPC-T6 - -FriendlyELEC NanoPC-T6 has optional SPI flash chip on-board. -It is populated with 32MB one on LTS version. - -Signed-off-by: Marcin Juszkiewicz -Reviewed-by: Jonas Karlman ---- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 15 ++++++++++ - 1 file changed, 15 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -@@ -560,6 +560,21 @@ &sdmmc { - status = "okay"; - }; - -+/* optional on non-LTS, populated on LTS version */ -+&sfc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&fspim1_pins>; -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <104000000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <1>; -+ }; -+}; -+ - &spi2 { - status = "okay"; - assigned-clocks = <&cru CLK_SPI2>; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Marcin Juszkiewicz -Date: Thu, 29 Aug 2024 14:26:57 +0200 -Subject: arm64: dts: rockchip: add IR-receiver to NanoPC-T6 - -FriendlyELEC NanoPC-T6 has IR receiver connected to PWM3_IR_M0 line -which ends as GPIO0_D4. - -Signed-off-by: Marcin Juszkiewicz ---- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 15 +++++++++- - 1 file changed, 14 insertions(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -@@ -25,6 +25,13 @@ chosen { - stdout-path = "serial2:1500000n8"; - }; - -+ ir-receiver { -+ compatible = "gpio-ir-receiver"; -+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ir_receiver_pin>; -+ }; -+ - leds { - compatible = "gpio-leds"; - -@@ -228,7 +235,7 @@ &gpio0 { - "HEADER_10", "HEADER_08", "HEADER_32", "", - /* GPIO0 D0-D7 */ - "", "", "", "", -- "", "", "", ""; -+ "IR receiver [PWM3_IR_M0]", "", "", ""; - }; - - &gpio1 { -@@ -492,6 +499,12 @@ hym8563_int: hym8563-int { - }; - }; - -+ ir-receiver { -+ ir_receiver_pin: ir-receiver-pin { -+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - pcie { - pcie2_0_rst: pcie2-0-rst { - rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Marcin Juszkiewicz -Date: Thu, 29 Aug 2024 14:26:58 +0200 -Subject: arm64: dts: rockchip: enable GPU on NanoPC-T6 - -Enable the Mali GPU on FriendlyELEC NanoPC-T6 - -Signed-off-by: Marcin Juszkiewicz ---- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -@@ -298,6 +298,11 @@ &gpio4 { - "", "", "", ""; - }; - -+&gpu { -+ mali-supply = <&vdd_gpu_s0>; -+ status = "okay"; -+}; -+ - &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0m2_xfer>; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Marcin Juszkiewicz -Date: Thu, 29 Aug 2024 14:26:59 +0200 -Subject: arm64: dts: rockchip: enable USB-C on NanoPC-T6 - -Enable the USB-C port on FriendlyELEC NanoPC-T6. - -Works one way so far but still better than before. - -Signed-off-by: Marcin Juszkiewicz ---- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 76 +++++++++- - 1 file changed, 72 insertions(+), 4 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -@@ -137,6 +137,8 @@ vbus5v0_typec: vbus5v0-typec-regulator { - gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&typec5v_pwren>; -+ regulator-always-on; -+ regulator-boot-on; - regulator-name = "vbus5v0_typec"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; -@@ -381,11 +383,34 @@ connector { - compatible = "usb-c-connector"; - data-role = "dual"; - label = "USB-C"; -- power-role = "dual"; -- try-power-role = "sink"; -+ power-role = "source"; - source-pdos = ; -- sink-pdos = ; -- op-sink-microwatt = <1000000>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ usbc0_hs: endpoint { -+ remote-endpoint = <&usb_host0_xhci_drd_sw>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ usbc0_ss: endpoint { -+ remote-endpoint = <&usbdp_phy0_typec_ss>; -+ }; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ usbc0_sbu: endpoint { -+ remote-endpoint = <&usbdp_phy0_typec_sbu>; -+ }; -+ }; -+ }; - }; - }; - -@@ -928,6 +953,14 @@ &uart2 { - status = "okay"; - }; - -+&u2phy0 { -+ status = "okay"; -+}; -+ -+&u2phy0_otg { -+ status = "okay"; -+}; -+ - &u2phy2_host { - status = "okay"; - }; -@@ -944,6 +977,29 @@ &u2phy3 { - status = "okay"; - }; - -+&usbdp_phy0 { -+ mode-switch; -+ orientation-switch; -+ sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; -+ sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ -+ port { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ usbdp_phy0_typec_ss: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&usbc0_ss>; -+ }; -+ -+ usbdp_phy0_typec_sbu: endpoint@1 { -+ reg = <1>; -+ remote-endpoint = <&usbc0_sbu>; -+ }; -+ }; -+}; -+ - &usb_host0_ehci { - status = "okay"; - }; -@@ -952,6 +1008,18 @@ &usb_host0_ohci { - status = "okay"; - }; - -+&usb_host0_xhci { -+ dr_mode = "host"; -+ status = "okay"; -+ usb-role-switch; -+ -+ port { -+ usb_host0_xhci_drd_sw: endpoint { -+ remote-endpoint = <&usbc0_hs>; -+ }; -+ }; -+}; -+ - &usb_host1_ehci { - status = "okay"; - }; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Marcin Juszkiewicz -Date: Thu, 29 Aug 2024 14:27:00 +0200 -Subject: arm64: dts: rockchip: add Mask Rom key on NanoPC-T6 - -Mask Rom key is connected to SARADC and can be read from OS. - -Signed-off-by: Marcin Juszkiewicz ---- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 15 ++++++++++ - 1 file changed, 15 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -@@ -8,6 +8,7 @@ - /dts-v1/; - - #include -+#include - #include - #include - #include "rk3588.dtsi" -@@ -21,6 +22,20 @@ aliases { - mmc1 = &sdmmc; - }; - -+ adc-keys-0 { -+ compatible = "adc-keys"; -+ io-channels = <&saradc 0>; -+ io-channel-names = "buttons"; -+ keyup-threshold-microvolt = <1800000>; -+ poll-interval = <100>; -+ -+ button-maskrom { -+ label = "Mask Rom"; -+ linux,code = ; -+ press-threshold-microvolt = <2000>; -+ }; -+ }; -+ - chosen { - stdout-path = "serial2:1500000n8"; - }; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: SuperKali -Date: Mon, 21 Oct 2024 13:21:03 +0000 -Subject: Add Missing parameters for USB3.0 and FAN - -Signed-off-by: SuperKali ---- - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6-lts.dts | 4 - - arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 58 ++++++++++ - 2 files changed, 58 insertions(+), 4 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6-lts.dts b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6-lts.dts -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6-lts.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6-lts.dts -@@ -42,10 +42,6 @@ &u2phy1 { - status = "okay"; - }; - --&u2phy1_otg { -- status = "okay"; --}; -- - &u2phy2_host { - phy-supply = <&vcc5v0_usb20_host>; - status = "okay"; -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi -@@ -66,6 +66,15 @@ usr_led: led-1 { - }; - }; - -+ /* FAN */ -+ fan0: pwm-fan { -+ compatible = "pwm-fan"; -+ #cooling-cells = <2>; -+ cooling-levels = <100 160 190 200 215 235 255>; -+ pwms = <&pwm1 0 50000 0>; -+ fan-supply = <&vcc5v0_sys>; -+ }; -+ - sound { - compatible = "simple-audio-card"; - pinctrl-names = "default"; -@@ -172,6 +181,18 @@ vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { - vin-supply = <&vcc5v0_sys>; - }; - -+ vcc5v0_host_30: vcc5v0-host-30 { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_host30_en>; -+ regulator-name = "vcc5v0_host_30"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ - vcc3v3_pcie30: vcc3v3-pcie30-regulator { - compatible = "regulator-fixed"; - enable-active-high; -@@ -487,6 +508,34 @@ i2s0_8ch_p0_0: endpoint { - }; - }; - -+&package_thermal { -+ polling-delay = <1000>; -+ -+ trips { -+ package_fan0: package-fan0 { -+ temperature = <55000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ package_fan1: package-fan1 { -+ temperature = <65000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ }; -+ -+ cooling-maps { -+ map1 { -+ trip = <&package_fan0>; -+ cooling-device = <&fan0 THERMAL_NO_LIMIT 1>; -+ }; -+ map2 { -+ trip = <&package_fan1>; -+ cooling-device = <&fan0 2 THERMAL_NO_LIMIT>; -+ }; -+ }; -+}; -+ - &pcie2x1l0 { - reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc_3v3_pcie20>; -@@ -577,6 +626,10 @@ typec5v_pwren: typec5v-pwren { - rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - -+ vcc5v0_host30_en: vcc5v0-host30-en { -+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ - usbc0_int: usbc0-int { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; -@@ -976,6 +1029,11 @@ &u2phy0_otg { - status = "okay"; - }; - -+&u2phy1_otg { -+ phy-supply = <&vcc5v0_host_30>; -+ status = "okay"; -+}; -+ - &u2phy2_host { - status = "okay"; - }; --- -Armbian -